CMSIS-Core (Cortex-A): Reference

| CMSIS-Core (Cortex-A) Version 1.0.0 CMSIS-Core support for Cortex-A processor-based devices

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Reference
Here is a list of all modules:
[detail level 1 2 3]

System and Clock Configuration | Functions for system and clock setup available in system_device.c
Core Register Access | Functions to access the Cortex-A core registers
Auxiliary Control Register (ACTLR) | The ACTLR provides IMPLEMENTATION DEFINED configuration and control options
ACTLR Bits | Bit position and mask macros
Cache and branch predictor maintenance operations | This section describes the cache and branch predictor maintenance operations
Configuration Base Address Register (CBAR) | Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13]
CBAR Bits | Bit position and mask macros
Coprocessor Access Control Register (CPACR) | The CPACR controls access to coprocessors CP0 to CP13
CPACR Bits | Bit position and mask macros
CPACR CP field values | Valid values for CPACR CP field
Current Program Status Register (CPSR) | The Current Program Status Register (CPSR) holds processor status and control information
CPSR Bits | Bit position and mask macros
CPSR M field values | Valid values for CPSR M field
Data Fault Status Register (DFSR) | The DFSR holds status information about the last data fault
ACTLR Bits | Bit position and mask macros
Domain Access Control Register (DACR) | DACR defines the access permission for each of the sixteen memory domains
DACR Bits | Bit position and mask macros
DACR Dn field values | Valid values for DACR Dn field
Floating-Point Exception Control register (FPEXC) | Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded
Floating-point Status and Control Register (FPSCR) | Provides floating-point system status information and control
FPSCR Bits | Bit position and mask macros
Instruction Fault Status Register (IFSR) | The IFSR holds status information about the last instruction fault
IFSR Bits | Bit position and mask macros
Interrupt Status Register (ISR) | The ISR shows whether an IRQ, FIQ, or external abort is pending
ISR Bits | Bit position and mask macros
Multiprocessor Affinity Register (MPIDR) | In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions
PL1 Physical Timer Control register (CNTP_CTL) | The control register for the physical timer
PL1 Physical Timer Value register (CNTP_TVAL) | Holds the timer value for the PL1 physical timer
Stack Pointer (SP/R13) | The processor uses SP as a pointer to the active stack
System Control Register (SCTLR) | The SCTLR provides the top level control of the system, including its memory system
SCTLR Bits | Bit position and mask macros
TLB maintenance operations | This section describes the TLB operations that are implemented on all ARMv7-A implementations
Translation Table Base Registers (TTBR0/TTBR1) | TTBRn holds the base address of translation table n, and information about the memory it occupies
Vector Base Address Register (VBAR) | When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode
Peripheral Access | Naming conventions and optional features for accessing peripherals
Version Control | Version symbols for CMSIS release specific C/C++ source code
Core Peripherals |
Generic Interrupt Controller Functions | The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC)
L1 Cache Functions | L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache
L2C-310 Cache Controller Functions | L2C-310 Cache Controller gives access to functions for level 2 cache maintenance. Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual
Generic Physical Timer Functions | Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices. Reference: Cortex-A7 MPCore Technical Reference Manual
Private Timer Functions | Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices. References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual
Memory Management Unit Functions | MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map. Reference: Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition
MMU Defines and Structs | Defines and structures that relate to the Memory Management Unit
Floating Point Unit Functions | FPU Functions enable the use of Floating Point instructions and extensions. Reference: Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition
Compiler Control | Compiler agnostic #define symbols for generic C/C++ source code
Intrinsic Functions | Functions that generate specific Cortex-A CPU Instructions
Interrupts and Exceptions | Generic functions to access the Interrupt Controller
IRQ Mode Bit-Masks | Configure interrupt line mode
IRQ Priority Bit-Masks | Definitions used by interrupt priority functions