CMSIS-Core (Cortex-M): Cache Functions (only Cortex-M7)

| CMSIS-Core (Cortex-M) Version 5.0.2 CMSIS-Core support for Cortex-M processor-based devices

- Main Page
- Usage and Description
- Reference

All Data Structures Files Functions Variables Enumerations Enumerator Groups Pages
Content
Cache Functions (only Cortex-M7)

Functions for Instruction and Data Cache. More...

## Content
| I-Cache Functions
| Functions for the instruction cache.
| D-Cache Functions
| Functions for the data cache.

## Description

Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of [0;4;8;16;32;64]KB. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.

All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.

Note
  After reset, you must invalidate each cache before enabling it.

The functions are grouped for:

- I-Cache Functions
- D-Cache Functions