| CMSIS-Core (Cortex-M) CMSIS-Core support for Cortex-M processor-based devices |

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Device Header File <Device.h>

The Device Header File contains the following functionalities that are device-specific:

- Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
- Configuration of the Processor and Core Peripherals reflect the features of the device.
- Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
- Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.

API Reference describes the standard features and functions of the Device Header File <Device.h> in details.

# Interrupt Number Definition

Device Header File <Device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

- Negative IRQn values represent processor core exceptions (internal interrupts).
- Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<Device>.c.

Example:

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
SVCall_IRQn = -5,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
WAKEUP0_IRQn = 0,
WAKEUP1_IRQn = 1,
WAKEUP2_IRQn = 2,
: :
: :
EINT1_IRQn = 30,
EINT0_IRQn = 31,
} IRQn_Type;
IRQn_Type
IRQn_Type
Definition of IRQn numbers.
Definition: ref_nvic.txt:385
PendSV_IRQn
@ PendSV_IRQn
Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].
Definition: ref_nvic.txt:397
SVCall_IRQn
@ SVCall_IRQn
Exception 11: SVC Interrupt.
Definition: ref_nvic.txt:395
SysTick_IRQn
@ SysTick_IRQn
Exception 15: System Tick Interrupt.
Definition: ref_nvic.txt:398
HardFault_IRQn
@ HardFault_IRQn
Exception 3: Hard Fault Interrupt.
Definition: ref_nvic.txt:388
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Exception 2: Non Maskable Interrupt.
Definition: ref_nvic.txt:387

# Configuration of the Processor and Core Peripherals

The Device Header File <Device.h> configures the Cortex-M or SecurCore processors and the core peripherals with `#define` directives that are set prior to including the file `core_<cpu>.h`.

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

Cortex-M0 core (core_cm0.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM0_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M0+ core (core_cm0plus.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM0PLUS_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT | 0 .. 1 | 0 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M3 core (core_cm3.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM3_REV | 0x0101 | 0x0200 | 0x0200 | Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT | 0 .. 1 | 1 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M4 core (core_cm4.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM4_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT | 0 .. 1 | 1 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M7 core (core_cm7.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM7_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__VTOR_PRESENT | 0 .. 1 | 1 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not.
__FPU_DP | 0 .. 1 | 0 | The combination of the defines __FPU_PRESENT and __FPU_DP determine whether the FPU is with single or double precision.
__ICACHE_PRESENT | 0 .. 1 | 1 | Instruction Chache present or not
__DCACHE_PRESENT | 0 .. 1 | 1 | Data Chache present or not
__DTCM_PRESENT | 0 .. 1 | 1 | Data Tightly Coupled Memory is present or not

SecurCore SC000 core (core_sc000.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__SC000_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT | 0 .. 1 | 0 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

SecurCore SC300 core (core_sc300.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__SC300_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT | 0 .. 1 | 1 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M23 core, Armv8-M Baseline core (core_cm23.h , core_armv8mbl.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__ARMv8MBL_REV or __CM23_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__SAUREGION_PRESENT | 0 .. 1 | 0 | Defines if SAU regions are present or not
__VTOR_PRESENT | 0 .. 1 | 0 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M33, Cortex-M35P, Armv8-M Mainline core (core_cm33.h, core_cm35p.h, core_armv8mml.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__ARMv8MML_REV or __CM33_REV or __CM35P_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__SAUREGION_PRESENT | 0 .. 1 | 0 | Defines if SAU regions are present or not
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not
__VTOR_PRESENT | 0 .. 1 | 1 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 3 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M55 core, Armv8.1-M Mainline core (core_cm55.h, core_armv81mml.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__ARMv81MML_REV or __CM55_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__SAUREGION_PRESENT | 0 .. 1 | 0 | Defines if SAU regions are present or not
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not
__FPU_DP | 0 .. 1 | 0 | The combination of the defines __FPU_PRESENT and __FPU_DP determine whether the FPU is with single or double precision.
__ICACHE_PRESENT | 0 .. 1 | 1 | Instruction Chache present or not
__DCACHE_PRESENT | 0 .. 1 | 1 | Data Chache present or not
__VTOR_PRESENT | 0 .. 1 | 1 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 3 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Cortex-M85 core (core_cm85.h)

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM85_REV | 0x0001 | 0x0001 | Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__SAUREGION_PRESENT | 0 .. 1 | 0 | Defines if SAU regions are present or not
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not
__FPU_DP | 0 .. 1 | 0 | The combination of the defines __FPU_PRESENT and __FPU_DP determine whether the FPU is with single or double precision.
__ICACHE_PRESENT | 0 .. 1 | 1 | Instruction Chache present or not
__DCACHE_PRESENT | 0 .. 1 | 1 | Data Chache present or not
__VTOR_PRESENT | 0 .. 1 | 1 | Defines if a VTOR register is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 3 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | Vendor defined SysTick_Config function.

Example

The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

#define __CM4_REV 0x0001U /* Core revision r0p1 */
#define __MPU_PRESENT 1U /* MPU present or not */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /* FPU present or not */
.
.
#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
#include "system_<Device>.h" /* Device System Header */

# Device Peripheral Access Layer

The Device Header File <Device.h> contains for each peripheral:

- Register Layout Typedef
- Base Address
- Access Definitions

The section Peripheral Access shows examples for peripheral definitions.

# Device.h Template File

CMSIS-Core Device Template Files include `Device.h` file that can be used as a starting point for chip vendors to implement the device-specific features required in a Device header file as described above. But the may also contain other functions to access device-specific peripherals.