| CMSIS-Core (Cortex-A) CMSIS-Core support for Cortex-A processor-based devices |

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Revision History

CMSIS-Core(A) component is maintaned with own versioning that gets incremented together with the CMSIS Software Pack releases.

The table below provides information about the changes delivered with specific versions of CMSIS-Core(A) updates.

Version | Description
--- | ---
V6.1.0 | Added support for Cortex-M52 Added deprecated CoreDebug symbols for CMSIS 5 compatibility Added define CMSIS_DISABLE_DEPRECATED to hide deprecated symbols
V6.0.0 | Core(M) and Core(A) joined into single Core component Core header files reworked, aligned with TRMs Previously deprecated features removed Dropped support for Arm Compiler 5
V1.2.1 | Bugfixes for Cortex-A32
V1.2.0 | Fixed GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR for compliance with all GIC specification versions. Added missing DSP intrinsics. Reworked assembly intrinsics: volatile, barriers and clobbers.
V1.1.4 | Fixed __FPU_Enable().
V1.1.3 | Fixed __get_SP_usr() / __set_SP_usr() for ArmClang. Fixed zero argument handling in __CLZ() .
V1.1.2 | Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings. Fixed co-processor register access macros for Arm Compiler 5.
V1.1.1 | Refactored L1 cache maintenance to be compiler agnostic.
V1.1.0 | Added compiler_iccarm.h for IAR compiler. Added missing core access functions for Arm Compiler 5. Aligned access function to coprocessor 15. Additional generic Timer functions. Bug fixes and minor enhancements.
V1.0.0 | Initial Release for Cortex-A5/A7/A9 processors.