| CMSIS-Core (Cortex-M) CMSIS-Core support for Cortex-M processor-based devices |

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Data Fields
SCB_Type Struct Reference

Structure type to access the System Control Block (SCB). More...

## Data Fields
__IOM uint32_t | AFSR
| Offset: 0x03C (R/W) Auxiliary Fault Status Register.
__IOM uint32_t | AIRCR
| Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.
__IOM uint32_t | BFAR
| Offset: 0x038 (R/W) BusFault Address Register.
__IOM uint32_t | CCR
| Offset: 0x014 (R/W) Configuration Control Register.
__IOM uint32_t | CFSR
| Offset: 0x028 (R/W) Configurable Fault Status Register.
__IOM uint32_t | CPACR
| Offset: 0x088 (R/W) Coprocessor Access Control Register.
__IM uint32_t | CPUID
| Offset: 0x000 (R/ ) CPUID Base Register.
__IOM uint32_t | DFSR
| Offset: 0x030 (R/W) Debug Fault Status Register.
__IOM uint32_t | HFSR
| Offset: 0x02C (R/W) HardFault Status Register.
__IOM uint32_t | ICSR
| Offset: 0x004 (R/W) Interrupt Control and State Register.
__IM uint32_t | ID_AFR
| Offset: 0x04C (R/ ) Auxiliary Feature Register.
__IM uint32_t | ID_DFR
| Offset: 0x048 (R/ ) Debug Feature Register.
__IM uint32_t | ID_ISAR [5U]
| Offset: 0x060 (R/ ) Instruction Set Attributes Register.
__IM uint32_t | ID_MMFR [4U]
| Offset: 0x050 (R/ ) Memory Model Feature Register.
__IM uint32_t | ID_PFR [2U]
| Offset: 0x040 (R/ ) Processor Feature Register.
__IOM uint32_t | MMFAR
| Offset: 0x034 (R/W) MemManage Fault Address Register.
__IOM uint32_t | SCR
| Offset: 0x010 (R/W) System Control Register.
__IOM uint32_t | SHCSR
| Offset: 0x024 (R/W) System Handler Control and State Register.
__IOM uint8_t | SHPR [12U]
| Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
__OM uint32_t | STIR
| Offset: 0x200 ( /W) Software Triggered Interrupt Register.
__IOM uint32_t | VTOR
| Offset: 0x008 (R/W) Vector Table Offset Register.

## Description

Structure type to access the System Control Block (SCB).

## Field Documentation

## ◆ AFSR

__IOM uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register.

## ◆ AIRCR

__IOM uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.

## ◆ BFAR

__IOM uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register.

## ◆ CCR

__IOM uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register.

## ◆ CFSR

__IOM uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register.

## ◆ CPACR

__IOM uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register.

## ◆ CPUID

__IM uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register.

## ◆ DFSR

__IOM uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register.

## ◆ HFSR

__IOM uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register.

## ◆ ICSR

__IOM uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register.

## ◆ ID_AFR

__IM uint32_t SCB_Type::ID_AFR

Offset: 0x04C (R/ ) Auxiliary Feature Register.

## ◆ ID_DFR

__IM uint32_t SCB_Type::ID_DFR

Offset: 0x048 (R/ ) Debug Feature Register.

## ◆ ID_ISAR

__IM uint32_t SCB_Type::ID_ISAR[5U]

Offset: 0x060 (R/ ) Instruction Set Attributes Register.

## ◆ ID_MMFR

__IM uint32_t SCB_Type::ID_MMFR[4U]

Offset: 0x050 (R/ ) Memory Model Feature Register.

## ◆ ID_PFR

__IM uint32_t SCB_Type::ID_PFR[2U]

Offset: 0x040 (R/ ) Processor Feature Register.

## ◆ MMFAR

__IOM uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register.

## ◆ SCR

__IOM uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register.

## ◆ SHCSR

__IOM uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register.

## ◆ SHPR

__IOM uint8_t SCB_Type::SHPR[12U]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

## ◆ STIR

__OM uint32_t SCB_Type::STIR

Offset: 0x200 ( /W) Software Triggered Interrupt Register.

## ◆ VTOR

__IOM uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register.