| CMSIS-Core (Cortex-A) CMSIS-Core support for Cortex-A processor-based devices |

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Macros
ISR Bits
Core Register Access » Interrupt Status Register (ISR)

Bit position and mask macros. More...

## Macros
#define | ISR_A_Pos 13U
| ISR: A Position.
#define | ISR_A_Msk (1UL << ISR_A_Pos)
| ISR: A Mask.
#define | ISR_I_Pos 12U
| ISR: I Position.
#define | ISR_I_Msk (1UL << ISR_I_Pos)
| ISR: I Mask.
#define | ISR_F_Pos 11U
| ISR: F Position.
#define | ISR_F_Msk (1UL << ISR_F_Pos)
| ISR: F Mask.

## Description

Bit position and mask macros.

## Macro Definition Documentation

## ◆ ISR_A_Msk

#define ISR_A_Msk (1UL << ISR_A_Pos)

ISR: A Mask.

## ◆ ISR_A_Pos

#define ISR_A_Pos 13U

ISR: A Position.

## ◆ ISR_F_Msk

#define ISR_F_Msk (1UL << ISR_F_Pos)

ISR: F Mask.

## ◆ ISR_F_Pos

#define ISR_F_Pos 11U

ISR: F Position.

## ◆ ISR_I_Msk

#define ISR_I_Msk (1UL << ISR_I_Pos)

ISR: I Mask.

## ◆ ISR_I_Pos

#define ISR_I_Pos 12U

ISR: I Position.