| CMSIS-Core (Cortex-M) CMSIS-Core support for Cortex-M processor-based devices |

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Content | Data Structures | Macros | Functions
PMU Functions for Armv8.1-M

Functions that relate to the Performance Monitoring Unit. More...

## Content
| PMU Events for Armv8.1-M
| IDs for Armv8.1-M architecture defined events.
| PMU Events for Cortex-M55
| IDs for additional events defined for Cortex-M55.
| PMU Events for Cortex-M85
| IDs for additional events defined for Cortex-M85.

## Data Structures
struct | PMU_Type
| Structure type to access the Performance Monitoring Unit (PMU). More...

## Macros
#define | PMU
| PMU configuration struct.

## Functions
__STATIC_INLINE void | ARM_PMU_CNTR_Disable (uint32_t mask)
| Disable counters.
__STATIC_INLINE void | ARM_PMU_CNTR_Enable (uint32_t mask)
| Enable counters.
__STATIC_INLINE void | ARM_PMU_CNTR_Increment (uint32_t mask)
| Software increment event counter.
__STATIC_INLINE void | ARM_PMU_CYCCNT_Reset (void)
| Reset cycle counter.
__STATIC_INLINE void | ARM_PMU_Disable (void)
| Disable the PMU.
__STATIC_INLINE void | ARM_PMU_Enable (void)
| Enable the PMU.
__STATIC_INLINE void | ARM_PMU_EVCNTR_ALL_Reset (void)
| Reset all event counters.
__STATIC_INLINE uint32_t | ARM_PMU_Get_CCNTR (void)
| Read cycle counter.
__STATIC_INLINE uint32_t | ARM_PMU_Get_CNTR_OVS (void)
| Read counter overflow status.
__STATIC_INLINE uint32_t | ARM_PMU_Get_EVCNTR (uint32_t num)
| Read event counter.
__STATIC_INLINE void | ARM_PMU_Set_CNTR_IRQ_Disable (uint32_t mask)
| Disable counter overflow interrupt request.
__STATIC_INLINE void | ARM_PMU_Set_CNTR_IRQ_Enable (uint32_t mask)
| Enable counter overflow interrupt request.
__STATIC_INLINE void | ARM_PMU_Set_CNTR_OVS (uint32_t mask)
| Clear counter overflow status.
__STATIC_INLINE void | ARM_PMU_Set_EVTYPER (uint32_t num, uint32_t type)
| Set event to count for PMU event counter.

## Description

Functions that relate to the Performance Monitoring Unit.

The following functions support the Performance Monitoring Unit (PMU) that is available on the Cortex-M55/M85 processors.

The PMU is used to monitor events that occur during run-time of an application.

Example:

// Initialize counter variables
unsigned int cycle_count = 0;
unsigned int l1_dcache_miss_count = 0;
unsigned int instructions_retired_count = 0;
// Enable the PMU
// Note: Before using the PMU, software needs to ensure
// that trace is enabled via the Debug Exception Monitor Control Register, DEMCR:
// CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
ARM_PMU_Enable();
// Configure Event Counter Register 0 to count instructions retired
// Configure Event Counter Register 1 to count L1 D-Cache misses
ARM_PMU_Set_EVTYPER(0, ARM_PMU_INST_RETIRED);
ARM_PMU_Set_EVTYPER(1, ARM_PMU_L1D_CACHE_MISS_RD);
// Reset Event Counters and Cycle Counter
ARM_PMU_EVCNTR_ALL_Reset();
ARM_PMU_CYCCNT_Reset();
// Start incrementing Cycle Count Register and Event Counter Registers 0 & 1
ARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk|PMU_CNTENSET_CNT0_ENABLE_Msk|PMU_CNTENSET_CNT1_ENABLE_Msk);
// Code you want to measure here
// Stop incrementing Cycle Count Register and Event Counter Registers 0 & 1
ARM_PMU_CNTR_Disable(PMU_CNTENCLR_CCNTR_ENABLE_Msk|PMU_CNTENCLR_CNT0_ENABLE_Msk|PMU_CNTENCLR_CNT1_ENABLE_Msk);
// Get cycle count, number of instructions retired and number of L1 D-Cache misses (on read)
cycle_count = cycle_count + ARM_PMU_Get_CCNTR();
instructions_retired_count = instructions_retired_count + ARM_PMU_Get_EVCNTR(0);
l1_dcache_miss_count = l1_dcache_miss_count + ARM_PMU_Get_EVCNTR(1); // Note: D-Cache must be enabled using
// SCB_EnableDCache() for meaningful result.
ARM_PMU_L1D_CACHE_MISS_RD
#define ARM_PMU_L1D_CACHE_MISS_RD
Level 1 data cache read miss.
Definition: ref_pmu8.txt:106
ARM_PMU_INST_RETIRED
#define ARM_PMU_INST_RETIRED
Instruction architecturally executed.
Definition: ref_pmu8.txt:71
ARM_PMU_CNTR_Enable
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
Enable counters.
ARM_PMU_CYCCNT_Reset
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
Reset cycle counter.
ARM_PMU_Enable
__STATIC_INLINE void ARM_PMU_Enable(void)
Enable the PMU.
ARM_PMU_CNTR_Disable
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
Disable counters.
ARM_PMU_Set_EVTYPER
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
Set event to count for PMU event counter.
ARM_PMU_EVCNTR_ALL_Reset
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
Reset all event counters.
ARM_PMU_Get_EVCNTR
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
Read event counter.
ARM_PMU_Get_CCNTR
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
Read cycle counter.

## Macro Definition Documentation

## ◆ PMU

#define PMU

PMU configuration struct.

This macro can be used to access the PMU registers, directly. For the common tasks one should prefer using the control functions.

Example: Example:

PMU->CTRL |= PMU_CTRL_ENABLE_Msk; // Enable PMU
PMU
#define PMU
PMU configuration struct.
Definition: ref_pmu8.txt:326

## Function Documentation

## ◆ ARM_PMU_CNTR_Disable()

__STATIC_INLINE void ARM_PMU_CNTR_Disable | ( | uint32_t | mask | ) |

Disable counters.

Parameters

  [in] | mask | Counters to enable

Note
  Disables one or more of the following:
  - event counters (0-30)
  - cycle counter

## ◆ ARM_PMU_CNTR_Enable()

__STATIC_INLINE void ARM_PMU_CNTR_Enable | ( | uint32_t | mask | ) |

Enable counters.

Parameters

  [in] | mask | Counters to enable

Note
  Enables one or more of the following:
  - event counters (0-30)
  - cycle counter

## ◆ ARM_PMU_CNTR_Increment()

__STATIC_INLINE void ARM_PMU_CNTR_Increment | ( | uint32_t | mask | ) |

Software increment event counter.

Parameters

  [in] | mask | Counters to increment

Note
  Software increment bits for one or more event counters (0-30)

## ◆ ARM_PMU_CYCCNT_Reset()

__STATIC_INLINE void ARM_PMU_CYCCNT_Reset | ( | void |  | ) |

Reset cycle counter.

## ◆ ARM_PMU_Disable()

__STATIC_INLINE void ARM_PMU_Disable | ( | void |  | ) |

Disable the PMU.

## ◆ ARM_PMU_Enable()

__STATIC_INLINE void ARM_PMU_Enable | ( | void |  | ) |

Enable the PMU.

## ◆ ARM_PMU_EVCNTR_ALL_Reset()

__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset | ( | void |  | ) |

Reset all event counters.

## ◆ ARM_PMU_Get_CCNTR()

__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR | ( | void |  | ) |

Read cycle counter.

Returns
  Cycle count

## ◆ ARM_PMU_Get_CNTR_OVS()

__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS | ( | void |  | ) |

Read counter overflow status.

Returns
  Counter overflow status bits for the following:
  - event counters (0-30)
  - cycle counter

## ◆ ARM_PMU_Get_EVCNTR()

__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR | ( | uint32_t | num | ) |

Read event counter.

Parameters

  [in] | num | Event counter (0-30) to read

Returns
  Event count

## ◆ ARM_PMU_Set_CNTR_IRQ_Disable()

__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable | ( | uint32_t | mask | ) |

Disable counter overflow interrupt request.

Parameters

  [in] | mask | Counter overflow interrupt request bits to clear

Note
  Clears overflow interrupt request bits for one or more of the following:
  - event counters (0-30)
  - cycle counter

## ◆ ARM_PMU_Set_CNTR_IRQ_Enable()

__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable | ( | uint32_t | mask | ) |

Enable counter overflow interrupt request.

Parameters

  [in] | mask | Counter overflow interrupt request bits to set

Note
  Sets overflow interrupt request bits for one or more of the following:
  - event counters (0-30)
  - cycle counter

## ◆ ARM_PMU_Set_CNTR_OVS()

__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS | ( | uint32_t | mask | ) |

Clear counter overflow status.

Parameters

  [in] | mask | Counter overflow status bits to clear

Note
  Clears overflow status bits for one or more of the following:
  - event counters (0-30)
  - cycle counter

## ◆ ARM_PMU_Set_EVTYPER()

__STATIC_INLINE void ARM_PMU_Set_EVTYPER | ( | uint32_t | num,
|  | uint32_t | type
| ) |  |

Set event to count for PMU event counter.

Parameters

  [in] | num | Event counter (0-30) to configure
  [in] | type | Event to count