| CMSIS-Core (Cortex-A) CMSIS-Core support for Cortex-A processor-based devices |

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Macros
IRQ Mode Bit-Masks
Interrupts and Exceptions

Configure interrupt line mode. More...

## Macros
#define | IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: level triggered interrupt.
#define | IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: low level triggered interrupt.
#define | IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: high level triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: edge triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: rising edge triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: falling edge triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: rising and falling edge triggered interrupt.
#define | IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos)
| Type: interrupt source triggers CPU IRQ line.
#define | IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos)
| Type: interrupt source triggers CPU FIQ line.
#define | IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos)
| Domain: interrupt is targeting non-secure domain.
#define | IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos)
| Domain: interrupt is targeting secure domain.
#define | IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets all CPUs.
#define | IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 0.
#define | IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 1.
#define | IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 2.
#define | IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 3.
#define | IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 4.
#define | IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 5.
#define | IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 6.
#define | IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 7.
#define | IRQ_MODE_ERROR (0x80000000UL)
| Bit indicating mode value error.

## Description

Configure interrupt line mode.

The following codes are used as values for the parameter mode of the function IRQ_SetMode to configure interrupt line mode. They are also returned by the function IRQ_GetMode when retrieving interrupt line mode.

The values of IRQ_MODE_TRIG_x definitions specify The values of IRQ_MODE_TYPE_x definitions specify The values of IRQ_MODE_DOMAIN_x definitions specify The values of IRQ_MODE_CPU_x definitions specify

Interrupt mode bit-masks

## Macro Definition Documentation

## ◆ IRQ_MODE_CPU_0

#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 0.

## ◆ IRQ_MODE_CPU_1

#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 1.

## ◆ IRQ_MODE_CPU_2

#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 2.

## ◆ IRQ_MODE_CPU_3

#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 3.

## ◆ IRQ_MODE_CPU_4

#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 4.

## ◆ IRQ_MODE_CPU_5

#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 5.

## ◆ IRQ_MODE_CPU_6

#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 6.

## ◆ IRQ_MODE_CPU_7

#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets CPU 7.

## ◆ IRQ_MODE_CPU_ALL

#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos)

CPU: interrupt targets all CPUs.

## ◆ IRQ_MODE_DOMAIN_NONSECURE

#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos)

Domain: interrupt is targeting non-secure domain.

## ◆ IRQ_MODE_DOMAIN_SECURE

#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos)

Domain: interrupt is targeting secure domain.

## ◆ IRQ_MODE_ERROR

#define IRQ_MODE_ERROR (0x80000000UL)

Bit indicating mode value error.

## ◆ IRQ_MODE_TRIG_EDGE

#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)

Trigger: edge triggered interrupt.

## ◆ IRQ_MODE_TRIG_EDGE_BOTH

#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)

Trigger: rising and falling edge triggered interrupt.

## ◆ IRQ_MODE_TRIG_EDGE_FALLING

#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)

Trigger: falling edge triggered interrupt.

## ◆ IRQ_MODE_TRIG_EDGE_RISING

#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)

Trigger: rising edge triggered interrupt.

## ◆ IRQ_MODE_TRIG_LEVEL

#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)

Trigger: level triggered interrupt.

## ◆ IRQ_MODE_TRIG_LEVEL_HIGH

#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)

Trigger: high level triggered interrupt.

## ◆ IRQ_MODE_TRIG_LEVEL_LOW

#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)

Trigger: low level triggered interrupt.

## ◆ IRQ_MODE_TYPE_FIQ

#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos)

Type: interrupt source triggers CPU FIQ line.

## ◆ IRQ_MODE_TYPE_IRQ

#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos)

Type: interrupt source triggers CPU IRQ line.