| CMSIS-Core (Cortex-M) CMSIS-Core support for Cortex-M processor-based devices |

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Data Structures | Macros | Functions
MPU Functions for Armv8-M

Functions that relate to the Memory Protection Unit. More...

## Data Structures
struct | ARM_MPU_Region_t
| Setup information of a single MPU Region. More...

## Macros
#define | ARM_MPU_AP_(RO, NP)
| Memory access permissions.
#define | ARM_MPU_AP_NP
| Normal memory, any privilege level.
#define | ARM_MPU_AP_PO
| Normal memory, privileged access only.
#define | ARM_MPU_AP_RO
| Normal memory, read-only.
#define | ARM_MPU_AP_RW
| Normal memory, read/write.
#define | ARM_MPU_ATTR(O, I)
| Memory Attribute.
#define | ARM_MPU_ATTR_DEVICE ( 0U )
| Attribute for device memory (outer only)
#define | ARM_MPU_ATTR_DEVICE_GRE
| Device memory type Gathering, Re-ordering, Early Write Acknowledgement.
#define | ARM_MPU_ATTR_DEVICE_nGnRE
| Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement.
#define | ARM_MPU_ATTR_DEVICE_nGnRnE
| Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement.
#define | ARM_MPU_ATTR_DEVICE_nGRE
| Device memory type non Gathering, Re-ordering, Early Write Acknowledgement.
#define | ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)
| Attribute for Normal memory, Outer and Inner cacheability.
#define | ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
| Attribute for non-cacheable, normal memory.
#define | ARM_MPU_EX
| Normal memory, Execution only permitted if read permitted.
#define | ARM_MPU_RBAR(BASE, SH, RO, NP, XN)
| Region Base Address Register value.
#define | ARM_MPU_RLAR(LIMIT, IDX)
| Region Limit Address Register value.
#define | ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX)
| Region Limit Address Register with PXN value.
#define | ARM_MPU_SH_INNER
| Normal memory inner shareable
#define | ARM_MPU_SH_NON
| Normal memory non-shareable
#define | ARM_MPU_SH_OUTER
| Normal memory outer shareable
#define | ARM_MPU_XN
| Normal memory, Execution only permitted if read permitted.
#define | MPU_ATTR_NORMAL_INNER_NON_CACHEABLE
#define | MPU_ATTR_NORMAL_INNER_WB_RA
#define | MPU_ATTR_NORMAL_INNER_WB_RA_WA
#define | MPU_ATTR_NORMAL_INNER_WB_TR_RA
#define | MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA
#define | MPU_ATTR_NORMAL_INNER_WB_TR_WA
#define | MPU_ATTR_NORMAL_INNER_WB_WA
#define | MPU_ATTR_NORMAL_INNER_WT_RA
#define | MPU_ATTR_NORMAL_INNER_WT_RA_WA
#define | MPU_ATTR_NORMAL_INNER_WT_TR_RA
#define | MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA
#define | MPU_ATTR_NORMAL_INNER_WT_TR_WA
#define | MPU_ATTR_NORMAL_INNER_WT_WA
#define | MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE
| Normal memory outer-cacheable and inner-cacheable attributes WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate.
#define | MPU_ATTR_NORMAL_OUTER_WB_RA
#define | MPU_ATTR_NORMAL_OUTER_WB_RA_WA
#define | MPU_ATTR_NORMAL_OUTER_WB_TR_RA
#define | MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA
#define | MPU_ATTR_NORMAL_OUTER_WB_TR_WA
#define | MPU_ATTR_NORMAL_OUTER_WB_WA
#define | MPU_ATTR_NORMAL_OUTER_WT_RA
#define | MPU_ATTR_NORMAL_OUTER_WT_RA_WA
#define | MPU_ATTR_NORMAL_OUTER_WT_TR_RA
#define | MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA
#define | MPU_ATTR_NORMAL_OUTER_WT_TR_WA
#define | MPU_ATTR_NORMAL_OUTER_WT_WA

## Functions
__STATIC_INLINE void | ARM_MPU_ClrRegion (uint32_t rnr)
__STATIC_INLINE void | ARM_MPU_ClrRegion_NS (uint32_t rnr)
__STATIC_INLINE void | ARM_MPU_ClrRegionEx (MPU_Type *mpu, uint32_t rnr)
__STATIC_INLINE void | ARM_MPU_Disable (void)
__STATIC_INLINE void | ARM_MPU_Disable_NS (void)
__STATIC_INLINE void | ARM_MPU_Enable (uint32_t MPU_Control)
| Enable the MPU.
__STATIC_INLINE | ARM_MPU_Enable_NS (uint32_t MPU_Control)
__STATIC_INLINE void | ARM_MPU_Load (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
__STATIC_INLINE void | ARM_MPU_Load_NS (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
__STATIC_INLINE void | ARM_MPU_LoadEx (MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
__STATIC_INLINE void | ARM_MPU_OrderedMemcpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
__STATIC_INLINE void | ARM_MPU_SetMemAttr (uint8_t idx, uint8_t attr)
__STATIC_INLINE void | ARM_MPU_SetMemAttr_NS (uint8_t idx, uint8_t attr)
__STATIC_INLINE void | ARM_MPU_SetMemAttrEx (MPU_Type *mpu, uint8_t idx, uint8_t attr)
__STATIC_INLINE void | ARM_MPU_SetRegion (uint32_t rnr, uint32_t rbar, uint32_t rlar)
__STATIC_INLINE void | ARM_MPU_SetRegion_NS (uint32_t rnr, uint32_t rbar, uint32_t rlar)
__STATIC_INLINE void | ARM_MPU_SetRegionEx (MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
__STATIC_INLINE uint32_t | ARM_MPU_TYPE ()
| Read MPU Type Register.

## Description

Functions that relate to the Memory Protection Unit.

The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.

The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.

Example:

int main()
{
// Set Region 0 using Attr 0
ARM_MPU_SetMemAttr(0UL, ARM_MPU_ATTR( /* Normal memory */
MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA, /* Outer Write-Back transient with read and write allocate */
MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA /* Inner Write-Through transient with read and write allocate */
));
ARM_MPU_SetRegion(0UL,
ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RW, ARM_MPU_AP_NP, ARM_MPU_XN), /* Non-shareable, read/write, non-privileged, execute-never */
ARM_MPU_RLAR(0x080FFFFFUL, MAIR_ATTR(0)) /* 1MB memory block using Attr 0 */
);
ARM_MPU_Enable(0);
// Execute application code that is access protected by the MPU
ARM_MPU_Disable();
}
ARM_MPU_AP_RW
#define ARM_MPU_AP_RW
Normal memory, read/write.
Definition: ref_mpu8.txt:114
ARM_MPU_ATTR
#define ARM_MPU_ATTR(O, I)
Memory Attribute.
Definition: ref_mpu8.txt:95
ARM_MPU_SH_NON
#define ARM_MPU_SH_NON
Normal memory non-shareable
Definition: ref_mpu8.txt:101
ARM_MPU_XN
#define ARM_MPU_XN
Normal memory, Execution only permitted if read permitted.
Definition: ref_mpu8.txt:130
MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA
Definition: ref_mpu8.txt:67
ARM_MPU_SetMemAttr
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA
Definition: ref_mpu8.txt:80
ARM_MPU_AP_NP
#define ARM_MPU_AP_NP
Normal memory, any privilege level.
Definition: ref_mpu8.txt:120
ARM_MPU_RLAR
#define ARM_MPU_RLAR(LIMIT, IDX)
Region Limit Address Register value.
Definition: ref_mpu8.txt:154
ARM_MPU_SetRegion
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
ARM_MPU_Enable
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_CTRL)
Enable the memory protection unit (MPU) and.
ARM_MPU_RBAR
#define ARM_MPU_RBAR(Region, BaseAddress)
MPU Region Base Address Register Value.
Definition: ref_mpu.txt:41
ARM_MPU_Disable
__STATIC_INLINE void ARM_MPU_Disable()

## Macro Definition Documentation

## ◆ ARM_MPU_AP_

#define ARM_MPU_AP_ | ( |  | RO,
|  |  | NP
| ) |  |

Memory access permissions.

Parameters

  RO | Read-Only: Set to 1 for read-only memory.
  NP | Non-Privileged: Set to 1 for non-privileged memory.

## ◆ ARM_MPU_AP_NP

#define ARM_MPU_AP_NP

Normal memory, any privilege level.

## ◆ ARM_MPU_AP_PO

#define ARM_MPU_AP_PO

Normal memory, privileged access only.

## ◆ ARM_MPU_AP_RO

#define ARM_MPU_AP_RO

Normal memory, read-only.

## ◆ ARM_MPU_AP_RW

#define ARM_MPU_AP_RW

Normal memory, read/write.

Access permissions AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only

## ◆ ARM_MPU_ATTR

#define ARM_MPU_ATTR | ( |  | O,
|  |  | I
| ) |  |

Memory Attribute.

Parameters

  O | Outer memory attributes
  I | O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes

## ◆ ARM_MPU_ATTR_DEVICE

#define ARM_MPU_ATTR_DEVICE ( 0U )

Attribute for device memory (outer only)

## ◆ ARM_MPU_ATTR_DEVICE_GRE

#define ARM_MPU_ATTR_DEVICE_GRE

Device memory type Gathering, Re-ordering, Early Write Acknowledgement.

## ◆ ARM_MPU_ATTR_DEVICE_nGnRE

#define ARM_MPU_ATTR_DEVICE_nGnRE

Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement.

## ◆ ARM_MPU_ATTR_DEVICE_nGnRnE

#define ARM_MPU_ATTR_DEVICE_nGnRnE

Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement.

## ◆ ARM_MPU_ATTR_DEVICE_nGRE

#define ARM_MPU_ATTR_DEVICE_nGRE

Device memory type non Gathering, Re-ordering, Early Write Acknowledgement.

## ◆ ARM_MPU_ATTR_MEMORY_

#define ARM_MPU_ATTR_MEMORY_ | ( |  | NT,
|  |  | WB,
|  |  | RA,
|  |  | WA
| ) |  |

Attribute for Normal memory, Outer and Inner cacheability.

Parameters

  NT | Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
  WB | Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
  RA | Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
  WA | Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.

## ◆ ARM_MPU_ATTR_NON_CACHEABLE

#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )

Attribute for non-cacheable, normal memory.

## ◆ ARM_MPU_EX

#define ARM_MPU_EX

Normal memory, Execution only permitted if read permitted.

## ◆ ARM_MPU_RBAR

#define ARM_MPU_RBAR | ( |  | BASE,
|  |  | SH,
|  |  | RO,
|  |  | NP,
|  |  | XN
| ) |  |

Region Base Address Register value.

Parameters

  BASE | The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
  SH | Defines the Shareability domain for this memory region.
  RO | Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
  NP | Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
  XN | eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.

## ◆ ARM_MPU_RLAR

#define ARM_MPU_RLAR | ( |  | LIMIT,
|  |  | IDX
| ) |  |

Region Limit Address Register value.

Parameters

  LIMIT | The limit address bits [31:5] for this memory region. The value is one extended.
  IDX | The attribute index to be associated with this memory region.

## ◆ ARM_MPU_RLAR_PXN

#define ARM_MPU_RLAR_PXN | ( |  | LIMIT,
|  |  | PXN,
|  |  | IDX
| ) |  |

Region Limit Address Register with PXN value.

Parameters

  LIMIT | The limit address bits [31:5] for this memory region. The value is one extended.
  PXN | Privileged execute never. Defines whether code can be executed from this privileged region.
  IDX | The attribute index to be associated with this memory region.

## ◆ ARM_MPU_SH_INNER

#define ARM_MPU_SH_INNER

Normal memory inner shareable

## ◆ ARM_MPU_SH_NON

#define ARM_MPU_SH_NON

Normal memory non-shareable

Shareability

## ◆ ARM_MPU_SH_OUTER

#define ARM_MPU_SH_OUTER

Normal memory outer shareable

## ◆ ARM_MPU_XN

#define ARM_MPU_XN

Normal memory, Execution only permitted if read permitted.

## ◆ MPU_ATTR_NORMAL_INNER_NON_CACHEABLE

#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE

## ◆ MPU_ATTR_NORMAL_INNER_WB_RA

#define MPU_ATTR_NORMAL_INNER_WB_RA

## ◆ MPU_ATTR_NORMAL_INNER_WB_RA_WA

#define MPU_ATTR_NORMAL_INNER_WB_RA_WA

## ◆ MPU_ATTR_NORMAL_INNER_WB_TR_RA

#define MPU_ATTR_NORMAL_INNER_WB_TR_RA

## ◆ MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA

#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA

## ◆ MPU_ATTR_NORMAL_INNER_WB_TR_WA

#define MPU_ATTR_NORMAL_INNER_WB_TR_WA

## ◆ MPU_ATTR_NORMAL_INNER_WB_WA

#define MPU_ATTR_NORMAL_INNER_WB_WA

## ◆ MPU_ATTR_NORMAL_INNER_WT_RA

#define MPU_ATTR_NORMAL_INNER_WT_RA

## ◆ MPU_ATTR_NORMAL_INNER_WT_RA_WA

#define MPU_ATTR_NORMAL_INNER_WT_RA_WA

## ◆ MPU_ATTR_NORMAL_INNER_WT_TR_RA

#define MPU_ATTR_NORMAL_INNER_WT_TR_RA

## ◆ MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA

#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA

## ◆ MPU_ATTR_NORMAL_INNER_WT_TR_WA

#define MPU_ATTR_NORMAL_INNER_WT_TR_WA

## ◆ MPU_ATTR_NORMAL_INNER_WT_WA

#define MPU_ATTR_NORMAL_INNER_WT_WA

## ◆ MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE

#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE

Normal memory outer-cacheable and inner-cacheable attributes WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate.

## ◆ MPU_ATTR_NORMAL_OUTER_WB_RA

#define MPU_ATTR_NORMAL_OUTER_WB_RA

## ◆ MPU_ATTR_NORMAL_OUTER_WB_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA

## ◆ MPU_ATTR_NORMAL_OUTER_WB_TR_RA

#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA

## ◆ MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA

## ◆ MPU_ATTR_NORMAL_OUTER_WB_TR_WA

#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA

## ◆ MPU_ATTR_NORMAL_OUTER_WB_WA

#define MPU_ATTR_NORMAL_OUTER_WB_WA

## ◆ MPU_ATTR_NORMAL_OUTER_WT_RA

#define MPU_ATTR_NORMAL_OUTER_WT_RA

## ◆ MPU_ATTR_NORMAL_OUTER_WT_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA

## ◆ MPU_ATTR_NORMAL_OUTER_WT_TR_RA

#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA

## ◆ MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA

## ◆ MPU_ATTR_NORMAL_OUTER_WT_TR_WA

#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA

## ◆ MPU_ATTR_NORMAL_OUTER_WT_WA

#define MPU_ATTR_NORMAL_OUTER_WT_WA

## Function Documentation

## ◆ ARM_MPU_ClrRegion()

__STATIC_INLINE void ARM_MPU_ClrRegion | ( | uint32_t | rnr | ) |

Clear and disable the given MPU region.

Parameters

  rnr | Region number to be cleared.

## ◆ ARM_MPU_ClrRegion_NS()

__STATIC_INLINE void ARM_MPU_ClrRegion_NS | ( | uint32_t | rnr | ) |

Clear and disable the given Non-secure MPU region.

Parameters

  rnr | Region number to be cleared.

## ◆ ARM_MPU_ClrRegionEx()

__STATIC_INLINE void ARM_MPU_ClrRegionEx | ( | MPU_Type * | mpu,
|  | uint32_t | rnr
| ) |  |

Clear and disable the given MPU region of the given MPU.

Parameters

  mpu | Pointer to MPU to be used.
  rnr | Region number to be cleared.

## ◆ ARM_MPU_Disable()

__STATIC_INLINE void ARM_MPU_Disable | ( | void |  | ) |

Disable the MPU.

## ◆ ARM_MPU_Disable_NS()

__STATIC_INLINE void ARM_MPU_Disable_NS | ( | void |  | ) |

Disable the Non-secure MPU.

## ◆ ARM_MPU_Enable()

__STATIC_INLINE void ARM_MPU_Enable | ( | uint32_t | MPU_Control | ) |

Enable the MPU.

Parameters

  MPU_Control | Default access permissions for unconfigured regions.

## ◆ ARM_MPU_Enable_NS()

__STATIC_INLINE ARM_MPU_Enable_NS | ( | uint32_t | MPU_Control | ) |

Enable the Non-secure MPU.

Parameters

  MPU_Control | Default access permissions for unconfigured regions.

## ◆ ARM_MPU_Load()

__STATIC_INLINE void ARM_MPU_Load | ( | uint32_t | rnr,
|  | ARM_MPU_Region_t const * | table,
|  | uint32_t | cnt
| ) |  |

Load the given number of MPU regions from a table.

Parameters

  rnr | First region number to be configured.
  table | Pointer to the MPU configuration table.
  cnt | Amount of regions to be configured.

Example:

const ARM_MPU_Region_t mpuTable[1][4] = {
{
// BASE SH RO NP XN LIMIT ATTR
{ .RBAR = ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x080FFFFFUL, MAIR_ATTR(0)) },
{ .RBAR = ARM_MPU_RBAR(0x20000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x20007FFFUL, MAIR_ATTR(0)) },
{ .RBAR = ARM_MPU_RBAR(0x40020000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x40021FFFUL, MAIR_ATTR(1)) },
{ .RBAR = ARM_MPU_RBAR(0x40022000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x40022FFFUL, MAIR_ATTR(1)) }
}
};
void UpdateMpu(uint32_t idx)
{
ARM_MPU_Load(0, mpuTable[idx], 4);
}
ARM_MPU_AP_RO
#define ARM_MPU_AP_RO
Normal memory, read-only.
Definition: ref_mpu8.txt:117
ARM_MPU_Load
__STATIC_INLINE void ARM_MPU_Load(MPU_Region_t const *table, uint32_t cnt)
ARM_MPU_Region_t
Setup information of a single MPU Region.
Definition: ref_mpu.txt:84
ARM_MPU_Region_t::RBAR
uint32_t RBAR
The region base address register value (RBAR)
Definition: ref_mpu.txt:85

## ◆ ARM_MPU_Load_NS()

__STATIC_INLINE void ARM_MPU_Load_NS | ( | uint32_t | rnr,
|  | ARM_MPU_Region_t const * | table,
|  | uint32_t | cnt
| ) |  |

Load the given number of MPU regions from a table to the Non-secure MPU.

Parameters

  rnr | First region number to be configured.
  table | Pointer to the MPU configuration table.
  cnt | Amount of regions to be configured.

## ◆ ARM_MPU_LoadEx()

__STATIC_INLINE void ARM_MPU_LoadEx | ( | MPU_Type * | mpu,
|  | uint32_t | rnr,
|  | ARM_MPU_Region_t const * | table,
|  | uint32_t | cnt
| ) |  |

Load the given number of MPU regions from a table to the given MPU.

Parameters

  mpu | Pointer to the MPU registers to be used.
  rnr | First region number to be configured.
  table | Pointer to the MPU configuration table.
  cnt | Amount of regions to be configured.

## ◆ ARM_MPU_OrderedMemcpy()

__STATIC_INLINE void ARM_MPU_OrderedMemcpy | ( | volatile uint32_t * | dst,
|  | const uint32_t *__RESTRICT | src,
|  | uint32_t | len
| ) |  |

Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx.

Parameters

  dst | Destination data is copied to.
  src | Source data is copied from.
  len | Amount of data words to be copied.

## ◆ ARM_MPU_SetMemAttr()

__STATIC_INLINE void ARM_MPU_SetMemAttr | ( | uint8_t | idx,
|  | uint8_t | attr
| ) |  |

Set the memory attribute encoding.

Parameters

  idx | The attribute index to be set [0-7]
  attr | The attribute value to be set.

## ◆ ARM_MPU_SetMemAttr_NS()

__STATIC_INLINE void ARM_MPU_SetMemAttr_NS | ( | uint8_t | idx,
|  | uint8_t | attr
| ) |  |

Set the memory attribute encoding to the Non-secure MPU.

Parameters

  idx | The attribute index to be set [0-7]
  attr | The attribute value to be set.

## ◆ ARM_MPU_SetMemAttrEx()

__STATIC_INLINE void ARM_MPU_SetMemAttrEx | ( | MPU_Type * | mpu,
|  | uint8_t | idx,
|  | uint8_t | attr
| ) |  |

Set the memory attribute encoding to the given MPU.

Parameters

  mpu | Pointer to the MPU to be configured.
  idx | The attribute index to be set [0-7]
  attr | The attribute value to be set.

## ◆ ARM_MPU_SetRegion()

__STATIC_INLINE void ARM_MPU_SetRegion | ( | uint32_t | rnr,
|  | uint32_t | rbar,
|  | uint32_t | rlar
| ) |  |

Configure the given MPU region.

Parameters

  rnr | Region number to be configured.
  rbar | Value for RBAR register.
  rlar | Value for RLAR register.

## ◆ ARM_MPU_SetRegion_NS()

__STATIC_INLINE void ARM_MPU_SetRegion_NS | ( | uint32_t | rnr,
|  | uint32_t | rbar,
|  | uint32_t | rlar
| ) |  |

Configure the given Non-secure MPU region.

Parameters

  rnr | Region number to be configured.
  rbar | Value for RBAR register.
  rlar | Value for RLAR register.

## ◆ ARM_MPU_SetRegionEx()

__STATIC_INLINE void ARM_MPU_SetRegionEx | ( | MPU_Type * | mpu,
|  | uint32_t | rnr,
|  | uint32_t | rbar,
|  | uint32_t | rlar
| ) |  |

Configure the given MPU region of the given MPU.

Parameters

  mpu | Pointer to MPU to be used.
  rnr | Region number to be configured.
  rbar | Value for RBAR register.
  rlar | Value for RLAR register.

## ◆ ARM_MPU_TYPE()

__STATIC_INLINE uint32_t ARM_MPU_TYPE | ( |  | ) |

Read MPU Type Register.

Returns
  Number of MPU regions