| CMSIS-Core (Cortex-A) CMSIS-Core support for Cortex-A processor-based devices |

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Data Fields
CNTP_CTL_Type Union Reference
Core Peripherals » Generic Physical Timer Functions

Physical Timer Control register. More...

`#include <core_ca.h>`

## Data Fields
struct {
uint32_t ENABLE:1
| bit: 0 Enables the timer. More...
uint32_t IMASK:1
| bit: 1 Timer output signal mask bit. More...
uint32_t ISTATUS:1
| bit: 2 The status of the timer. More...
} | b
| Structure used for bit access.
uint32_t | w
| Type used for word access.
struct {
uint32_t ENABLE:1
| bit: 0 Enables the timer. More...
uint32_t IMASK:1
| bit: 1 Timer output signal mask bit. More...
uint32_t ISTATUS:1
| bit: 2 The status of the timer. More...
uint32_t _reserved0:29
| bit: 3..31 Reserved More...
} | b
| Structure used for bit access.

## Description

Physical Timer Control register.

## Field Documentation

## ◆ _reserved0

uint32_t CNTP_CTL_Type::_reserved0

bit: 3..31 Reserved

## ◆ [1/2]

struct { ... } CNTP_CTL_Type::b

Structure used for bit access.

## ◆ [2/2]

struct { ... } CNTP_CTL_Type::b

Structure used for bit access.

## ◆ ENABLE

uint32_t CNTP_CTL_Type::ENABLE

bit: 0 Enables the timer.

Enables the timer.

Permitted values are:

- 0 - Timer disabled.
- 1 - Timer enabled.

## ◆ IMASK

uint32_t CNTP_CTL_Type::IMASK

bit: 1 Timer output signal mask bit.

Timer output signal mask bit.

Permitted values are:

- 0 - Timer output signal is not masked.
- 1 - Timer output signal is masked.

## ◆ ISTATUS

uint32_t CNTP_CTL_Type::ISTATUS

bit: 2 The status of the timer.

The status of the timer.

This bit indicates whether the timer condition is asserted:

- 0 - Timer condition is not asserted.
- 1 - Timer condition is asserted.

## ◆ w

uint32_t CNTP_CTL_Type::w

Type used for word access.