| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

Modules | Macros
NUC472/NUC442 Peripheral Memory Base
Collaboration diagram for NUC472/NUC442 Peripheral Memory Base:

## Modules
| NUC472/NUC442 Peripheral Pointer

## Macros
#define | FLASH_BASE ((uint32_t)0x00000000)
#define | SRAM_BASE ((uint32_t)0x20000000)
#define | PERIPH_BASE ((uint32_t)0x40000000)
#define | AHBPERIPH_BASE PERIPH_BASE
#define | APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
#define | SYS_BASE (AHBPERIPH_BASE + 0x00000)
#define | CLK_BASE (AHBPERIPH_BASE + 0x00200)
#define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
#define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
#define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
#define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
#define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
#define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
#define | GPIOG_BASE (AHBPERIPH_BASE + 0x04180)
#define | GPIOH_BASE (AHBPERIPH_BASE + 0x041C0)
#define | GPIOI_BASE (AHBPERIPH_BASE + 0x04200)
#define | GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
#define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
#define | PDMA_BASE (AHBPERIPH_BASE + 0x08000)
#define | USBH_BASE (AHBPERIPH_BASE + 0x09000)
#define | EMAC_BASE (AHBPERIPH_BASE + 0x0B000)
#define | FMC_BASE (AHBPERIPH_BASE + 0x0C000)
#define | SD_BASE (AHBPERIPH_BASE + 0x0D000)
#define | EBI_BASE (AHBPERIPH_BASE + 0x10000)
#define | UDC20_BASE (AHBPERIPH_BASE + 0x19000)
#define | CAP_BASE (AHBPERIPH_BASE + 0x30000)
#define | CRC_BASE (AHBPERIPH_BASE + 0x31000)
#define | WDT_BASE (APBPERIPH_BASE + 0x00000)
#define | WWDT_BASE (APBPERIPH_BASE + 0x00100)
#define | OPA_BASE (APBPERIPH_BASE + 0x06000)
#define | I2S0_BASE (APBPERIPH_BASE + 0x08000)
#define | TIMER0_BASE (APBPERIPH_BASE + 0x10000)
#define | TIMER1_BASE (APBPERIPH_BASE + 0x10020)
#define | PWM0_BASE (APBPERIPH_BASE + 0x18000)
#define | EPWM0_BASE (APBPERIPH_BASE + 0x1C000)
#define | SPI0_BASE (APBPERIPH_BASE + 0x20000)
#define | SPI2_BASE (APBPERIPH_BASE + 0x22000)
#define | UART0_BASE (APBPERIPH_BASE + 0x30000)
#define | UART2_BASE (APBPERIPH_BASE + 0x32000)
#define | UART4_BASE (APBPERIPH_BASE + 0x34000)
#define | I2C0_BASE (APBPERIPH_BASE + 0x40000)
#define | I2C2_BASE (APBPERIPH_BASE + 0x42000)
#define | I2C4_BASE (APBPERIPH_BASE + 0x44000)
#define | SC0_BASE (APBPERIPH_BASE + 0x50000)
#define | SC2_BASE (APBPERIPH_BASE + 0x52000)
#define | SC4_BASE (APBPERIPH_BASE + 0x54000)
#define | CAN0_BASE (APBPERIPH_BASE + 0x60000)
#define | QEI0_BASE (APBPERIPH_BASE + 0x70000)
#define | ECAP0_BASE (APBPERIPH_BASE + 0x74000)
#define | PS2D_BASE (APBPERIPH_BASE + 0xA0000)
#define | RTC_BASE (APBPERIPH_BASE + 0x01000)
#define | ADC_BASE (APBPERIPH_BASE + 0x03000)
#define | EADC_BASE (APBPERIPH_BASE + 0x04000)
#define | ACMP_BASE (APBPERIPH_BASE + 0x05000)
#define | I2S1_BASE (APBPERIPH_BASE + 0x09000)
#define | OTG_BASE (APBPERIPH_BASE + 0x0D000)
#define | TIMER2_BASE (APBPERIPH_BASE + 0x11000)
#define | TIMER3_BASE (APBPERIPH_BASE + 0x11020)
#define | PWM1_BASE (APBPERIPH_BASE + 0x19000)
#define | EPWM1_BASE (APBPERIPH_BASE + 0x1D000)
#define | SPI1_BASE (APBPERIPH_BASE + 0x21000)
#define | SPI3_BASE (APBPERIPH_BASE + 0x23000)
#define | UART1_BASE (APBPERIPH_BASE + 0x31000)
#define | UART3_BASE (APBPERIPH_BASE + 0x33000)
#define | UART5_BASE (APBPERIPH_BASE + 0x35000)
#define | I2C1_BASE (APBPERIPH_BASE + 0x41000)
#define | I2C3_BASE (APBPERIPH_BASE + 0x43000)
#define | SC1_BASE (APBPERIPH_BASE + 0x51000)
#define | SC3_BASE (APBPERIPH_BASE + 0x53000)
#define | SC5_BASE (APBPERIPH_BASE + 0x55000)
#define | CAN1_BASE (APBPERIPH_BASE + 0x61000)
#define | QEI1_BASE (APBPERIPH_BASE + 0x71000)
#define | ECAP1_BASE (APBPERIPH_BASE + 0x75000)
#define | CRPT_BASE (0x50080000UL)

## Detailed Description

Memory Mapped Structure for NUC472/NUC442 Peripheral

## Macro Definition Documentation

## ◆ ACMP_BASE

#define ACMP_BASE (APBPERIPH_BASE + 0x05000)

Definition at line 28767 of file NUC472_442.h.

## ◆ ADC_BASE

#define ADC_BASE (APBPERIPH_BASE + 0x03000)

Definition at line 28765 of file NUC472_442.h.

## ◆ AHBPERIPH_BASE

#define AHBPERIPH_BASE PERIPH_BASE

AHB Base Address

Definition at line 28711 of file NUC472_442.h.

## ◆ APBPERIPH_BASE

#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)

APB Base Address AHB peripherals

Definition at line 28714 of file NUC472_442.h.

## ◆ CAN0_BASE

#define CAN0_BASE (APBPERIPH_BASE + 0x60000)

Definition at line 28758 of file NUC472_442.h.

## ◆ CAN1_BASE

#define CAN1_BASE (APBPERIPH_BASE + 0x61000)

Definition at line 28784 of file NUC472_442.h.

## ◆ CAP_BASE

#define CAP_BASE (AHBPERIPH_BASE + 0x30000)

Definition at line 28735 of file NUC472_442.h.

## ◆ CLK_BASE

#define CLK_BASE (AHBPERIPH_BASE + 0x00200)

Definition at line 28716 of file NUC472_442.h.

## ◆ CRC_BASE

#define CRC_BASE (AHBPERIPH_BASE + 0x31000)

APB2 peripherals

Definition at line 28738 of file NUC472_442.h.

## ◆ CRPT_BASE

#define CRPT_BASE (0x50080000UL)

Definition at line 28787 of file NUC472_442.h.

## ◆ EADC_BASE

#define EADC_BASE (APBPERIPH_BASE + 0x04000)

Definition at line 28766 of file NUC472_442.h.

## ◆ EBI_BASE

#define EBI_BASE (AHBPERIPH_BASE + 0x10000)

Definition at line 28733 of file NUC472_442.h.

## ◆ ECAP0_BASE

#define ECAP0_BASE (APBPERIPH_BASE + 0x74000)

Definition at line 28760 of file NUC472_442.h.

## ◆ ECAP1_BASE

#define ECAP1_BASE (APBPERIPH_BASE + 0x75000)

Definition at line 28786 of file NUC472_442.h.

## ◆ EMAC_BASE

#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000)

Definition at line 28730 of file NUC472_442.h.

## ◆ EPWM0_BASE

#define EPWM0_BASE (APBPERIPH_BASE + 0x1C000)

Definition at line 28746 of file NUC472_442.h.

## ◆ EPWM1_BASE

#define EPWM1_BASE (APBPERIPH_BASE + 0x1D000)

Definition at line 28773 of file NUC472_442.h.

## ◆ FLASH_BASE

#define FLASH_BASE ((uint32_t)0x00000000)

Flash base address

Definition at line 28708 of file NUC472_442.h.

## ◆ FMC_BASE

#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)

Definition at line 28731 of file NUC472_442.h.

## ◆ GPIO_DBCTL_BASE

#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)

Definition at line 28726 of file NUC472_442.h.

## ◆ GPIO_PIN_DATA_BASE

#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)

Definition at line 28727 of file NUC472_442.h.

## ◆ GPIOA_BASE

#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)

Definition at line 28717 of file NUC472_442.h.

## ◆ GPIOB_BASE

#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)

Definition at line 28718 of file NUC472_442.h.

## ◆ GPIOC_BASE

#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)

Definition at line 28719 of file NUC472_442.h.

## ◆ GPIOD_BASE

#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)

Definition at line 28720 of file NUC472_442.h.

## ◆ GPIOE_BASE

#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)

Definition at line 28721 of file NUC472_442.h.

## ◆ GPIOF_BASE

#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)

Definition at line 28722 of file NUC472_442.h.

## ◆ GPIOG_BASE

#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180)

Definition at line 28723 of file NUC472_442.h.

## ◆ GPIOH_BASE

#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0)

Definition at line 28724 of file NUC472_442.h.

## ◆ GPIOI_BASE

#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200)

Definition at line 28725 of file NUC472_442.h.

## ◆ I2C0_BASE

#define I2C0_BASE (APBPERIPH_BASE + 0x40000)

Definition at line 28752 of file NUC472_442.h.

## ◆ I2C1_BASE

#define I2C1_BASE (APBPERIPH_BASE + 0x41000)

Definition at line 28779 of file NUC472_442.h.

## ◆ I2C2_BASE

#define I2C2_BASE (APBPERIPH_BASE + 0x42000)

Definition at line 28753 of file NUC472_442.h.

## ◆ I2C3_BASE

#define I2C3_BASE (APBPERIPH_BASE + 0x43000)

Definition at line 28780 of file NUC472_442.h.

## ◆ I2C4_BASE

#define I2C4_BASE (APBPERIPH_BASE + 0x44000)

Definition at line 28754 of file NUC472_442.h.

## ◆ I2S0_BASE

#define I2S0_BASE (APBPERIPH_BASE + 0x08000)

Definition at line 28742 of file NUC472_442.h.

## ◆ I2S1_BASE

#define I2S1_BASE (APBPERIPH_BASE + 0x09000)

Definition at line 28768 of file NUC472_442.h.

## ◆ OPA_BASE

#define OPA_BASE (APBPERIPH_BASE + 0x06000)

Definition at line 28741 of file NUC472_442.h.

## ◆ OTG_BASE

#define OTG_BASE (APBPERIPH_BASE + 0x0D000)

Definition at line 28769 of file NUC472_442.h.

## ◆ PDMA_BASE

#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)

Definition at line 28728 of file NUC472_442.h.

## ◆ PERIPH_BASE

#define PERIPH_BASE ((uint32_t)0x40000000)

Peripheral Base Address

Definition at line 28710 of file NUC472_442.h.

## ◆ PS2D_BASE

#define PS2D_BASE (APBPERIPH_BASE + 0xA0000)

APB1 peripherals

Definition at line 28763 of file NUC472_442.h.

## ◆ PWM0_BASE

#define PWM0_BASE (APBPERIPH_BASE + 0x18000)

Definition at line 28745 of file NUC472_442.h.

## ◆ PWM1_BASE

#define PWM1_BASE (APBPERIPH_BASE + 0x19000)

Definition at line 28772 of file NUC472_442.h.

## ◆ QEI0_BASE

#define QEI0_BASE (APBPERIPH_BASE + 0x70000)

Definition at line 28759 of file NUC472_442.h.

## ◆ QEI1_BASE

#define QEI1_BASE (APBPERIPH_BASE + 0x71000)

Definition at line 28785 of file NUC472_442.h.

## ◆ RTC_BASE

#define RTC_BASE (APBPERIPH_BASE + 0x01000)

Definition at line 28764 of file NUC472_442.h.

## ◆ SC0_BASE

#define SC0_BASE (APBPERIPH_BASE + 0x50000)

Definition at line 28755 of file NUC472_442.h.

## ◆ SC1_BASE

#define SC1_BASE (APBPERIPH_BASE + 0x51000)

Definition at line 28781 of file NUC472_442.h.

## ◆ SC2_BASE

#define SC2_BASE (APBPERIPH_BASE + 0x52000)

Definition at line 28756 of file NUC472_442.h.

## ◆ SC3_BASE

#define SC3_BASE (APBPERIPH_BASE + 0x53000)

Definition at line 28782 of file NUC472_442.h.

## ◆ SC4_BASE

#define SC4_BASE (APBPERIPH_BASE + 0x54000)

Definition at line 28757 of file NUC472_442.h.

## ◆ SC5_BASE

#define SC5_BASE (APBPERIPH_BASE + 0x55000)

Definition at line 28783 of file NUC472_442.h.

## ◆ SD_BASE

#define SD_BASE (AHBPERIPH_BASE + 0x0D000)

Definition at line 28732 of file NUC472_442.h.

## ◆ SPI0_BASE

#define SPI0_BASE (APBPERIPH_BASE + 0x20000)

Definition at line 28747 of file NUC472_442.h.

## ◆ SPI1_BASE

#define SPI1_BASE (APBPERIPH_BASE + 0x21000)

Definition at line 28774 of file NUC472_442.h.

## ◆ SPI2_BASE

#define SPI2_BASE (APBPERIPH_BASE + 0x22000)

Definition at line 28748 of file NUC472_442.h.

## ◆ SPI3_BASE

#define SPI3_BASE (APBPERIPH_BASE + 0x23000)

Definition at line 28775 of file NUC472_442.h.

## ◆ SRAM_BASE

#define SRAM_BASE ((uint32_t)0x20000000)

SRAM Base Address

Definition at line 28709 of file NUC472_442.h.

## ◆ SYS_BASE

#define SYS_BASE (AHBPERIPH_BASE + 0x00000)

Definition at line 28715 of file NUC472_442.h.

## ◆ TIMER0_BASE

#define TIMER0_BASE (APBPERIPH_BASE + 0x10000)

Definition at line 28743 of file NUC472_442.h.

## ◆ TIMER1_BASE

#define TIMER1_BASE (APBPERIPH_BASE + 0x10020)

Definition at line 28744 of file NUC472_442.h.

## ◆ TIMER2_BASE

#define TIMER2_BASE (APBPERIPH_BASE + 0x11000)

Definition at line 28770 of file NUC472_442.h.

## ◆ TIMER3_BASE

#define TIMER3_BASE (APBPERIPH_BASE + 0x11020)

Definition at line 28771 of file NUC472_442.h.

## ◆ UART0_BASE

#define UART0_BASE (APBPERIPH_BASE + 0x30000)

Definition at line 28749 of file NUC472_442.h.

## ◆ UART1_BASE

#define UART1_BASE (APBPERIPH_BASE + 0x31000)

Definition at line 28776 of file NUC472_442.h.

## ◆ UART2_BASE

#define UART2_BASE (APBPERIPH_BASE + 0x32000)

Definition at line 28750 of file NUC472_442.h.

## ◆ UART3_BASE

#define UART3_BASE (APBPERIPH_BASE + 0x33000)

Definition at line 28777 of file NUC472_442.h.

## ◆ UART4_BASE

#define UART4_BASE (APBPERIPH_BASE + 0x34000)

Definition at line 28751 of file NUC472_442.h.

## ◆ UART5_BASE

#define UART5_BASE (APBPERIPH_BASE + 0x35000)

Definition at line 28778 of file NUC472_442.h.

## ◆ UDC20_BASE

#define UDC20_BASE (AHBPERIPH_BASE + 0x19000)

Definition at line 28734 of file NUC472_442.h.

## ◆ USBH_BASE

#define USBH_BASE (AHBPERIPH_BASE + 0x09000)

Definition at line 28729 of file NUC472_442.h.

## ◆ WDT_BASE

#define WDT_BASE (APBPERIPH_BASE + 0x00000)

Definition at line 28739 of file NUC472_442.h.

## ◆ WWDT_BASE

#define WWDT_BASE (APBPERIPH_BASE + 0x00100)

Definition at line 28740 of file NUC472_442.h.