| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

epwm.c
Go to the documentation of this file.
1/**************************************************************************/
12#include "NUC472_442.h"
13
35uint32_t EPWM_ConfigOutputChannel (EPWM_T *pwm,
36 uint32_t u32ChannelNum,
37 uint32_t u32Frequency,
38 uint32_t u32DutyCycle)
39{
40 uint32_t i;
41 uint32_t u32PWM_CLock;
42 uint8_t u8Divider = 1;
43 uint16_t u16CNR = 0xFFFF;
44
45 u32PWM_CLock = SystemCoreClock;
46
47 for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 16
48 {
49 // clk divider not support 8
50 if (u8Divider == 8)
51 continue;
52
53 i = (u32PWM_CLock / u32Frequency) / u8Divider;
54 // If target value is larger than CNR, need to use a larger divider
55 if(i > 0x10000)
56 continue;
57
58 // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
59
60 if(i <= 0x10000)
61 {
62 if(i == 1)
63 u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
64 else
65 u16CNR = i;
66 break;
67 }
68
69 }
70 // Store return value here 'cos we're gonna change u8Divider & u16CNR to the real value to fill into register
71 i = u32PWM_CLock / (u8Divider * u16CNR);
72
73 u16CNR -= 1;
74 // convert to real register value
75 if(u8Divider == 1)
76 u8Divider = 0;
77 else if (u8Divider == 2)
78 u8Divider = 1;
79 else if (u8Divider == 4)
80 u8Divider = 2;
81 else // 16
82 u8Divider = 3;
83
84 pwm->CTL = (pwm->CTL & ~EPWM_CTL_CLKDIV_Msk) | ( u8Divider << EPWM_CTL_CLKDIV_Pos);
85
86 if(u32DutyCycle == 0)
87 pwm->CMPDAT[u32ChannelNum >> 1] = 0;
88 else
89 pwm->CMPDAT[u32ChannelNum >> 1] = u32DutyCycle * (u16CNR + 1) / 100 - 1;
90
91 pwm->PERIOD = u16CNR;
92
93 return(i);
94}
95
96
104 void EPWM_Start (EPWM_T *pwm, uint32_t u32ChannelMask)
105{
106 pwm->CTL |= EPWM_CTL_CNTEN_Msk;
107}
108
116 void EPWM_Stop (EPWM_T *pwm, uint32_t u32ChannelMask)
117{
118 pwm->CTL &= ~EPWM_CTL_CNTEN_Msk;
119}
120
128 void EPWM_ForceStop (EPWM_T *pwm, uint32_t u32ChannelMask)
129{
130 pwm->CTL &= ~EPWM_CTL_CNTEN_Msk;
131}
132
152 void EPWM_EnableFaultBrake (EPWM_T *pwm,
153 uint32_t u32ChannelMask,
154 uint32_t u32LevelMask,
155 uint32_t u32BrakeSource)
156{
157 if ((u32BrakeSource == EPWM_BRK0_BKP0)||(u32BrakeSource == EPWM_BRK0_CPO0)||(u32BrakeSource == EPWM_BRK0_CPO1)||(u32BrakeSource == EPWM_BRK0_CPO2))
158 pwm->CTL |= (u32BrakeSource | EPWM_CTL_BRKP0EN_Msk);
159 else if (u32BrakeSource == EPWM_BRK1_LVDBKEN)
160 pwm->CTL |= EPWM_BRK1_LVDBKEN;
161 else
162 pwm->CTL = (pwm->CTL & ~EPWM_CTL_BRK1SEL_Msk) | u32BrakeSource | EPWM_CTL_BRKP1EN_Msk;
163
164 pwm->BRKOUT = (pwm->BRKOUT & ~EPWM_BRKOUT_BRKOUT_Msk) | u32LevelMask;
165}
166
174 void EPWM_ClearFaultBrakeFlag (EPWM_T *pwm, uint32_t u32BrakeSource)
175{
176 pwm->STATUS = EPWM_STATUS_BRK0LOCK_Msk | EPWM_STATUS_BRKIF0_Msk;
177}
178
179
187 void EPWM_EnableOutput (EPWM_T *pwm, uint32_t u32ChannelMask)
188{
189 if (u32ChannelMask & 0x15)
190 pwm->OUTEN0 |= EPWM_OUTEN0_EVENOUTEN_Msk;
191 if (u32ChannelMask & 0x2A)
192 pwm->OUTEN0 |= EPWM_OUTEN0_ODDOUTEN_Msk;
193}
194
202 void EPWM_DisableOutput (EPWM_T *pwm, uint32_t u32ChannelMask)
203{
204 if (u32ChannelMask & 0x15)
205 pwm->OUTEN0 &= ~EPWM_OUTEN0_EVENOUTEN_Msk;
206 if (u32ChannelMask & 0x2A)
207 pwm->OUTEN0 &= ~EPWM_OUTEN0_ODDOUTEN_Msk;
208
209}
210
218 void EPWM_EnableDeadZone (EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
219{
220 // every two channels shares the same setting
221 u32ChannelNum >>= 1;
222 // set duration
223 pwm->DTCTL = (pwm->DTCTL & ~EPWM_DTCTL_DTCNT_Msk) | u32Duration;
224 // enable dead zone
225 pwm->DTCTL |= (EPWM_DTCTL_DTEN0_Msk << u32ChannelNum);
226}
227
234 void EPWM_DisableDeadZone (EPWM_T *pwm, uint32_t u32ChannelNum)
235{
236 // every two channels shares the same setting
237 u32ChannelNum >>= 1;
238 // enable dead zone
239 pwm->DTCTL &= ~(EPWM_DTCTL_DTEN0_Msk << u32ChannelNum);
240}
241
249 void EPWM_EnableDutyInt (EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
250{
251 // every two channels shares the same setting
252 u32ChannelNum >>= 1;
253 // set duty interrupt type
254 pwm->CTL = (pwm->CTL & ~EPWM_CTL_INTTYPE_Msk) | EPWM_CTL_PWMIEN_Msk;
255
256 pwm->EINTCTL |= ((EPWM_EINTCTL_EINTTYPE0_Msk << u32ChannelNum) | (EPWM_EINTCTL_EDGEIEN0_Msk << u32ChannelNum));
257}
258
265 void EPWM_DisableDutyInt (EPWM_T *pwm, uint32_t u32ChannelNum)
266{
267 // every two channels shares the same setting
268 u32ChannelNum >>= 1;
269 pwm->CTL &= ~(EPWM_EINTCTL_EDGEIEN0_Msk << u32ChannelNum);
270}
271
278 void EPWM_ClearDutyIntFlag (EPWM_T *pwm, uint32_t u32ChannelNum)
279{
280 // every two channels shares the same setting
281 u32ChannelNum >>= 1;
282 // write 1 clear
283 pwm->STATUS = (EPWM_STATUS_EIF0_Msk << u32ChannelNum);
284}
285
294uint32_t EPWM_GetDutyIntFlag (EPWM_T *pwm, uint32_t u32ChannelNum)
295{
296 return((pwm->STATUS & (EPWM_STATUS_EIF0_Msk << u32ChannelNum)) ? 1 : 0);
297}
298
305 void EPWM_EnableFaultBrakeInt (EPWM_T *pwm, uint32_t u32BrakeSource)
306{
307 pwm->CTL |= EPWM_CTL_BRKIEN_Msk;
308}
309
316 void EPWM_DisableFaultBrakeInt (EPWM_T *pwm, uint32_t u32BrakeSource)
317{
318 pwm->CTL &= ~EPWM_CTL_BRKIEN_Msk;
319}
320
329 void EPWM_ClearFaultBrakeIntFlag (EPWM_T *pwm, uint32_t u32BrakeSource)
330{
331 pwm->STATUS = u32BrakeSource;
332}
333
344uint32_t EPWM_GetFaultBrakeIntFlag (EPWM_T *pwm, uint32_t u32BrakeSource)
345{
346 return (pwm->STATUS & u32BrakeSource ? 1 : 0);
347}
348
357 void EPWM_EnablePeriodInt (EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
358{
359 // set period interrupt type and enable period interrupt
360 pwm->CTL |= (EPWM_CTL_INTTYPE_Msk | EPWM_CTL_PWMIEN_Msk);
361}
362
369 void EPWM_DisablePeriodInt (EPWM_T *pwm, uint32_t u32ChannelNum)
370{
371 pwm->CTL &= ~EPWM_CTL_PWMIEN_Msk;
372}
373
380 void EPWM_ClearPeriodIntFlag (EPWM_T *pwm, uint32_t u32ChannelNum)
381{
382 // write 1 clear
383 pwm->STATUS = EPWM_STATUS_PIF_Msk;
384}
385
394uint32_t EPWM_GetPeriodIntFlag (EPWM_T *pwm, uint32_t u32ChannelNum)
395{
396 return(pwm->STATUS & EPWM_STATUS_PIF_Msk ? 1 : 0);
397}
398
399
400 /* end of group NUC472_442_EPWM_EXPORTED_FUNCTIONS */
402 /* end of group NUC472_442_EPWM_Driver */
404 /* end of group NUC472_442_Device_Driver */
406
407/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
NUC472_442.h
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's d...
EPWM_CTL_BRKIEN_Msk
#define EPWM_CTL_BRKIEN_Msk
Definition: NUC472_442.h:14404
EPWM_OUTEN0_ODDOUTEN_Msk
#define EPWM_OUTEN0_ODDOUTEN_Msk
Definition: NUC472_442.h:14578
EPWM_CTL_PWMIEN_Msk
#define EPWM_CTL_PWMIEN_Msk
Definition: NUC472_442.h:14401
EPWM_CTL_BRKP1EN_Msk
#define EPWM_CTL_BRKP1EN_Msk
Definition: NUC472_442.h:14437
EPWM_STATUS_EIF0_Msk
#define EPWM_STATUS_EIF0_Msk
Definition: NUC472_442.h:14479
EPWM_STATUS_PIF_Msk
#define EPWM_STATUS_PIF_Msk
Definition: NUC472_442.h:14476
EPWM_CTL_INTTYPE_Msk
#define EPWM_CTL_INTTYPE_Msk
Definition: NUC472_442.h:14413
EPWM_DTCTL_DTEN0_Msk
#define EPWM_DTCTL_DTEN0_Msk
Definition: NUC472_442.h:14527
EPWM_STATUS_BRKIF0_Msk
#define EPWM_STATUS_BRKIF0_Msk
Definition: NUC472_442.h:14470
EPWM_OUTEN0_EVENOUTEN_Msk
#define EPWM_OUTEN0_EVENOUTEN_Msk
Definition: NUC472_442.h:14575
EPWM_EINTCTL_EDGEIEN0_Msk
#define EPWM_EINTCTL_EDGEIEN0_Msk
Definition: NUC472_442.h:14557
EPWM_CTL_CLKDIV_Pos
#define EPWM_CTL_CLKDIV_Pos
Definition: NUC472_442.h:14397
EPWM_EINTCTL_EINTTYPE0_Msk
#define EPWM_EINTCTL_EINTTYPE0_Msk
Definition: NUC472_442.h:14566
EPWM_CTL_CNTEN_Msk
#define EPWM_CTL_CNTEN_Msk
Definition: NUC472_442.h:14410
EPWM_STATUS_BRK0LOCK_Msk
#define EPWM_STATUS_BRK0LOCK_Msk
Definition: NUC472_442.h:14488
EPWM_CTL_BRKP0EN_Msk
#define EPWM_CTL_BRKP0EN_Msk
Definition: NUC472_442.h:14434
EPWM_BRK0_CPO1
#define EPWM_BRK0_CPO1
Definition: epwm.h:54
EPWM_BRK0_BKP0
#define EPWM_BRK0_BKP0
Definition: epwm.h:52
EPWM_BRK0_CPO2
#define EPWM_BRK0_CPO2
Definition: epwm.h:55
EPWM_BRK1_LVDBKEN
#define EPWM_BRK1_LVDBKEN
Definition: epwm.h:56
EPWM_BRK0_CPO0
#define EPWM_BRK0_CPO0
Definition: epwm.h:53
EPWM_GetPeriodIntFlag
uint32_t EPWM_GetPeriodIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum)
This function get period interrupt of selected channel.
Definition: epwm.c:394
EPWM_DisableDutyInt
void EPWM_DisableDutyInt(EPWM_T *pwm, uint32_t u32ChannelNum)
This function disable duty interrupt of selected channel.
Definition: epwm.c:265
EPWM_GetDutyIntFlag
uint32_t EPWM_GetDutyIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum)
This function get duty interrupt flag of selected channel.
Definition: epwm.c:294
EPWM_DisableFaultBrakeInt
void EPWM_DisableFaultBrakeInt(EPWM_T *pwm, uint32_t u32BrakeSource)
This function disable fault brake interrupt.
Definition: epwm.c:316
EPWM_Stop
void EPWM_Stop(EPWM_T *pwm, uint32_t u32ChannelMask)
This function stop PWM module.
Definition: epwm.c:116
EPWM_DisableDeadZone
void EPWM_DisableDeadZone(EPWM_T *pwm, uint32_t u32ChannelNum)
This function disable Dead zone of selected channel.
Definition: epwm.c:234
EPWM_DisableOutput
void EPWM_DisableOutput(EPWM_T *pwm, uint32_t u32ChannelMask)
This function disables PWM output generation of selected channels.
Definition: epwm.c:202
EPWM_ClearDutyIntFlag
void EPWM_ClearDutyIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum)
This function clears duty interrupt flag of selected channel.
Definition: epwm.c:278
EPWM_DisablePeriodInt
void EPWM_DisablePeriodInt(EPWM_T *pwm, uint32_t u32ChannelNum)
This function disable period interrupt of selected channel.
Definition: epwm.c:369
EPWM_EnableFaultBrake
void EPWM_EnableFaultBrake(EPWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
This function enable fault brake of selected channels.
Definition: epwm.c:152
EPWM_ForceStop
void EPWM_ForceStop(EPWM_T *pwm, uint32_t u32ChannelMask)
This function stop PWM generation immediately by clear channel enable bit.
Definition: epwm.c:128
EPWM_ClearFaultBrakeFlag
void EPWM_ClearFaultBrakeFlag(EPWM_T *pwm, uint32_t u32BrakeSource)
This function clear fault brake flag.
Definition: epwm.c:174
EPWM_EnableFaultBrakeInt
void EPWM_EnableFaultBrakeInt(EPWM_T *pwm, uint32_t u32BrakeSource)
This function enable fault brake interrupt.
Definition: epwm.c:305
EPWM_Start
void EPWM_Start(EPWM_T *pwm, uint32_t u32ChannelMask)
This function start PWM module.
Definition: epwm.c:104
EPWM_EnablePeriodInt
void EPWM_EnablePeriodInt(EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
This function enable period interrupt of selected channel.
Definition: epwm.c:357
EPWM_EnableOutput
void EPWM_EnableOutput(EPWM_T *pwm, uint32_t u32ChannelMask)
This function enables PWM output generation of selected channels.
Definition: epwm.c:187
EPWM_EnableDutyInt
void EPWM_EnableDutyInt(EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
This function enable duty interrupt of selected channel.
Definition: epwm.c:249
EPWM_EnableDeadZone
void EPWM_EnableDeadZone(EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
This function enable Dead zone of selected channel.
Definition: epwm.c:218
EPWM_ClearFaultBrakeIntFlag
void EPWM_ClearFaultBrakeIntFlag(EPWM_T *pwm, uint32_t u32BrakeSource)
This function clear fault brake interrupt of selected source.
Definition: epwm.c:329
EPWM_ClearPeriodIntFlag
void EPWM_ClearPeriodIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum)
This function clear period interrupt of selected channel.
Definition: epwm.c:380
EPWM_ConfigOutputChannel
uint32_t EPWM_ConfigOutputChannel(EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode.
Definition: epwm.c:35
EPWM_GetFaultBrakeIntFlag
uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *pwm, uint32_t u32BrakeSource)
This function get fault brake interrupt of selected source.
Definition: epwm.c:344
EPWM_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:14036
EPWM_T::EINTCTL
__IO uint32_t EINTCTL
Definition: NUC472_442.h:14369
EPWM_T::CMPDAT
__IO uint32_t CMPDAT[3]
Definition: NUC472_442.h:14120
EPWM_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:14086
EPWM_T::OUTEN0
__IO uint32_t OUTEN0
Definition: NUC472_442.h:14385
EPWM_T::PERIOD
__IO uint32_t PERIOD
Definition: NUC472_442.h:14103
EPWM_T::BRKOUT
__IO uint32_t BRKOUT
Definition: NUC472_442.h:14233
EPWM_T::DTCTL
__IO uint32_t DTCTL
Definition: NUC472_442.h:14218
EPWM_T
Definition: NUC472_442.h:13932
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_NUC472_442.c:17