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NUC472_NUC442_BSP V3.03.004
The Board Support Package for NUC472/NUC442
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Macros | |
#define | EADC_POWER_DOWN(eadc) |
Power down EADC module. More... | |
#define | EADC_POWER_ON(eadc) |
Power on EADC module. More... | |
#define | EADC_CONV_RESET(eadc) |
A/D Converter Control Circuits Reset. More... | |
#define | EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) |
Enable double buffer mode. More... | |
#define | EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) |
Disable double buffer mode. More... | |
#define | EADC_ENABLE_INT(eadc, u32Mask) |
Enable the interrupt. More... | |
#define | EADC_DISABLE_INT(eadc, u32Mask) |
Disable the interrupt. More... | |
#define | EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) |
Enable the sample module interrupt. More... | |
#define | EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) |
Disable the sample module interrupt. More... | |
#define | EADC_START_CONV(eadc, u32ModuleMask) |
Start the A/D conversion. More... | |
#define | EADC_GET_PENDING_CONV(eadc) |
Get the conversion pending flag. More... | |
#define | EADC_GET_CONV_DATA(eadc, u32ModuleNum) |
Get the conversion data of the user-specified sample module. More... | |
#define | EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) |
Get the data overrun flag of the user-specified sample module. More... | |
#define | EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) |
Get the data valid flag of the user-specified sample module. More... | |
#define | EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) |
Get the double data of the user-specified sample module. More... | |
#define | EADC_GET_INT_FLAG(eadc, u32Mask) |
Get the user-specified interrupt flags. More... | |
#define | EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) |
Get the user-specified sample module overrun flags. More... | |
#define | EADC_CLR_INT_FLAG(eadc, u32Mask) |
Clear the selected interrupt status bits. More... | |
#define | EADC_IS_DATA_OV(eadc) |
Check all sample module A/D result data register overrun flags. More... | |
#define | EADC_IS_DATA_VALID(eadc) |
Check all sample module A/D result data register valid flags. More... | |
#define | EADC_IS_SAMPLE_MODULE_OV(eadc) |
Check all A/D sample module start of conversion overrun flags. More... | |
#define | EADC_IS_INT_FLAG_OV(eadc) |
Check all A/D interrupt flag overrun bits. More... | |
#define | EADC_IS_BUSY(eadc, converter) |
Get the busy state of EADC. More... | |
#define | EADC_ENABLE_CMP0(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount) |
Configure the comparator 0 and enable it. More... | |
#define | EADC_ENABLE_CMP1(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount) |
Configure the comparator 1 and enable it. More... | |
#define | EADC_ENABLE_CMP_INT(eadc, u32CMP) |
Enable the compare interrupt. More... | |
#define | EADC_DISABLE_CMP_INT(eadc, u32CMP) |
Disable the compare interrupt. More... | |
#define | EADC_DISABLE_CMP0(eadc) |
Disable comparator 0. More... | |
#define | EADC_DISABLE_CMP1(eadc) |
Disable comparator 1. More... | |
#define | EADC_ENABLE_SIMULTANEOUS(eadc, u32ModuleMask) |
Enable simultaneous mode. More... | |
#define | EADC_DISABLE_SIMULTANEOUS(eadc, u32ModuleMask) |
Disable simultaneous mode. More... | |
#define | EADC_EnablePWMTriggerCondition(eadc, u32ADTriggerModuleNum, u32TriggerMask) (*(__IO uint32_t *)(&(eadc)->AD0TRGEN0 + (u32ADTriggerModuleNum)) |= (u32TriggerMask)) |
Enable PWM and EPWM trigger trigger EADC condition. More... | |
#define | EADC_DisablePWMTriggerCondition(eadc, u32ADTriggerModuleNum, u32TriggerMask) (*(__IO uint32_t *)(&(eadc)->AD0TRGEN0 + (u32ADTriggerModuleNum)) |= (u32TriggerMask)) |
Disable PWM and EPWM trigger trigger EADC condition. More... | |
Functions | |
void | EADC_Open (EADC_T *eadc, uint32_t u32InputMode) |
This function make EADC_module be ready to convert. More... | |
void | EADC_Close (EADC_T *eadc) |
Disable EADC_module. More... | |
void | EADC_ConfigSampleModule (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel) |
Configure the sample control logic module. More... | |
void | EADC_SetTriggerDelayTime (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider) |
Set trigger delay time. More... | |
void | EADC_SetExtendSampleTime (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) |
Set EADC extend sample time. More... | |
#define EADC_CLR_INT_FLAG | ( | eadc, | |
u32Mask | |||
) |
Clear the selected interrupt status bits.
[in] | eadc | Base address of EADC module. |
[in] | u32Mask | The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. Bit 4 is ADCMPO0, bit 5 is ADCMPO1, bit 6 is ADCMPF0, bit 7 is ADCMPF1. |
This macro is used to clear clear the selected interrupt status bits.
#define EADC_CONV_RESET | ( | eadc | ) |
#define EADC_DISABLE_CMP0 | ( | eadc | ) |
#define EADC_DISABLE_CMP1 | ( | eadc | ) |
#define EADC_DISABLE_CMP_INT | ( | eadc, | |
u32CMP | |||
) |
#define EADC_DISABLE_DOUBLE_BUFFER | ( | eadc, | |
u32ModuleNum | |||
) |
Disable double buffer mode.
[in] | eadc | Base address of EADC module.. |
[in] | u32ModuleNum | Decides the sample module number, valid values are:
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Sample has one sample result register.
#define EADC_DISABLE_INT | ( | eadc, | |
u32Mask | |||
) |
Disable the interrupt.
[in] | eadc | Base address of EADC module. |
[in] | u32Mask | Decides the combination of interrupt enable bits. Each bit corresponds to a interrupt enable. This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. |
Specific sample module A/D ADINT0 interrupt function Disabled.
#define EADC_DISABLE_SAMPLE_MODULE_INT | ( | eadc, | |
u32IntSel, | |||
u32ModuleMask | |||
) |
Disable the sample module interrupt.
[in] | eadc | Base address of EADC module. |
[in] | u32IntSel | Decides which interrupt source will be used, valid value are from 0 to 3. |
[in] | u32ModuleMask | the combination of sample module interrupt enable bits. Each bit corresponds to a sample module interrupt enable. This parameter decides which sample module interrupts will be disabled, valid range are between 1~0xFFFF. |
There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
#define EADC_DISABLE_SIMULTANEOUS | ( | eadc, | |
u32ModuleMask | |||
) |
Disable simultaneous mode.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleMask | The combination of sample module. Each bit corresponds to a sample module. This parameter decides which sample module will be set to disable simultaneous mode, valid range are between 1~0xFF. Bit 0 is sample module 0, bit 1 is sample module 1..., bit 7 is sample module 7. |
This macro is used to set selected sample modules to disable simultaneous mode.
#define EADC_DisablePWMTriggerCondition | ( | eadc, | |
u32ADTriggerModuleNum, | |||
u32TriggerMask | |||
) | (*(__IO uint32_t *)(&(eadc)->AD0TRGEN0 + (u32ADTriggerModuleNum)) |= (u32TriggerMask)) |
Disable PWM and EPWM trigger trigger EADC condition.
[in] | eadc | Base address of EADC module. |
[in] | u32ADTriggerModuleNum | Decides the sample module number, valid values are:
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[in] | u32TriggerMask | Decides the PWM and EPWM trigger EADC condition, valid range are between 0~0xFFFFFFFF. |
This macro is used to disable PWM and EPWM trigger EADC condition.
#define EADC_ENABLE_CMP0 | ( | eadc, | |
u32ModuleNum, | |||
u32Condition, | |||
u16CMPData, | |||
u32MatchCount | |||
) |
Configure the comparator 0 and enable it.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | specifies the compare sample module, valid values are:
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[in] | u32Condition | specifies the compare condition. Valid values are:
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[in] | u16CMPData | specifies the compare value, valid range are between 0~0xFFF. |
[in] | u32MatchCount | specifies the match count setting, valid range are between 0~0xF. |
For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
#define EADC_ENABLE_CMP1 | ( | eadc, | |
u32ModuleNum, | |||
u32Condition, | |||
u16CMPData, | |||
u32MatchCount | |||
) |
Configure the comparator 1 and enable it.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | specifies the compare sample module, valid values are:
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[in] | u32Condition | specifies the compare condition. Valid values are:
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[in] | u16CMPData | specifies the compare value, valid range are between 0~0xFFF. |
[in] | u32MatchCount | specifies the match count setting, valid range are between 0~0xF. |
For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
#define EADC_ENABLE_CMP_INT | ( | eadc, | |
u32CMP | |||
) |
Enable the compare interrupt.
[in] | eadc | Base address of EADC module. |
[in] | u32CMP | Specifies the compare register, valid value are 0 and 1. |
If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~1) and CMPMCNT (EADC_CMPn[11:8], n=0~1), ADCMPFn (EADC_STATUS1[7:6], n=0~1) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
#define EADC_ENABLE_DOUBLE_BUFFER | ( | eadc, | |
u32ModuleNum | |||
) |
Enable double buffer mode.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid values are:
|
The EADC controller supports a double buffer mode in eadc0/1 sample module 0~3.
#define EADC_ENABLE_INT | ( | eadc, | |
u32Mask | |||
) |
Enable the interrupt.
[in] | eadc | Base address of EADC module. |
[in] | u32Mask | Decides the combination of interrupt enable bits. Each bit corresponds to a interrupt enable. This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. |
The A/D converter generates a conversion end ADIFn (EADC_STATUS1[n]) upon the end of specific sample module A/D conversion. If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
#define EADC_ENABLE_SAMPLE_MODULE_INT | ( | eadc, | |
u32IntSel, | |||
u32ModuleMask | |||
) |
Enable the sample module interrupt.
[in] | eadc | Base address of EADC module. |
[in] | u32IntSel | Decides which interrupt source will be used, valid value are from 0 to 3. |
[in] | u32ModuleMask | the combination of sample module interrupt enable bits. Each bit corresponds to a sample module interrupt enable. This parameter decides which sample module interrupts will be enabled, valid range are between 1~0xFFFF. |
There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
#define EADC_ENABLE_SIMULTANEOUS | ( | eadc, | |
u32ModuleMask | |||
) |
Enable simultaneous mode.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleMask | The combination of sample module. Each bit corresponds to a sample module. This parameter decides which sample module will be set to simultaneous mode, valid range are between 1~0xFF. Bit 0 is sample module 0, bit 1 is sample module 1..., bit 7 is sample module 7. |
This macro is used to set selected sample modules to be simultaneous mode.
#define EADC_EnablePWMTriggerCondition | ( | eadc, | |
u32ADTriggerModuleNum, | |||
u32TriggerMask | |||
) | (*(__IO uint32_t *)(&(eadc)->AD0TRGEN0 + (u32ADTriggerModuleNum)) |= (u32TriggerMask)) |
Enable PWM and EPWM trigger trigger EADC condition.
[in] | eadc | Base address of EADC module. |
[in] | u32ADTriggerModuleNum | Decides the sample module number, valid values are:
|
[in] | u32TriggerMask | Decides the PWM and EPWM trigger EADC condition, valid range are between 0~0xFFFFFFFF. |
This macro is used to enable PWM and EPWM trigger EADC condition.
#define EADC_GET_CONV_DATA | ( | eadc, | |
u32ModuleNum | |||
) |
Get the conversion data of the user-specified sample module.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid values are:
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This macro is used to read RESULT bit (EADC_ADxDATn[11:0], x=0~1, n=0~7) field to get conversion data.
#define EADC_GET_DATA_OVERRUN_FLAG | ( | eadc, | |
u32ModuleMask | |||
) |
Get the data overrun flag of the user-specified sample module.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleMask | The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. |
This macro is used to read OV bit (EADC_STATUS0[31:16]) field to get data overrun status.
#define EADC_GET_DATA_VALID_FLAG | ( | eadc, | |
u32ModuleMask | |||
) |
Get the data valid flag of the user-specified sample module.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleMask | The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. |
This macro is used to read VALID bit of EADC_STATUS0[15:0] to get data valid status.
#define EADC_GET_DOUBLE_DATA | ( | eadc, | |
u32ModuleNum | |||
) |
Get the double data of the user-specified sample module.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid values are:
|
This macro is used to read RESULT bit (EADC_ADxDDATn[11:0], x=0~1, n=0~3) field to get conversion data.
#define EADC_GET_INT_FLAG | ( | eadc, | |
u32Mask | |||
) |
Get the user-specified interrupt flags.
[in] | eadc | Base address of EADC module. |
[in] | u32Mask | The combination of interrupt status bits. Each bit corresponds to a interrupt status. Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. Bit 4 is ADCMPO0, bit 5 is ADCMPO1, bit 6 is ADCMPF0, bit 7 is ADCMPF1. |
This macro is used to get the user-specified interrupt flags.
#define EADC_GET_PENDING_CONV | ( | eadc | ) |
Get the conversion pending flag.
[in] | eadc | Base address of EADC module. |
This STPFn(EADC_PENDSTS[15:0]) bit remains 1 during pending state, when the respective EADC conversion is end, the STPFn (n=0~15) bit is automatically cleared to 0.
#define EADC_GET_SAMPLE_MODULE_OV_FLAG | ( | eadc, | |
u32ModuleMask | |||
) |
Get the user-specified sample module overrun flags.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleMask | The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0xFFFF. |
This macro is used to get the user-specified sample module overrun flags.
#define EADC_IS_BUSY | ( | eadc, | |
converter | |||
) |
Get the busy state of EADC.
[in] | eadc | Base address of EADC module. |
[in] | converter | Which converter, it should be 0 or 1. |
0 | Idle state. |
1 | Busy state. |
This macro is used to read BUSY0(EADC_STATUS1[8]) or BUSY1(EADC_STATUS1[16]) to get busy state.
#define EADC_IS_DATA_OV | ( | eadc | ) |
Check all sample module A/D result data register overrun flags.
[in] | eadc | Base address of EADC module. |
0 | None of sample module data register overrun flag is set to 1. |
1 | Any one of sample module data register overrun flag is set to 1. |
The AOV bit (EADC_STATUS1[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_ADxDATn[16]) is set to 1.
#define EADC_IS_DATA_VALID | ( | eadc | ) |
Check all sample module A/D result data register valid flags.
[in] | eadc | Base address of EADC module. |
0 | None of sample module data register valid flag is set to 1. |
1 | Any one of sample module data register valid flag is set to 1. |
The AVALID bit (EADC_STATUS1[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_ADxDATn[17]) is set to 1.
#define EADC_IS_INT_FLAG_OV | ( | eadc | ) |
Check all A/D interrupt flag overrun bits.
[in] | eadc | Base address of EADC module. |
0 | None of ADINT interrupt flag is overwritten to 1. |
1 | Any one of ADINT interrupt flag is overwritten to 1. |
The ADOVIF bit (EADC_STATUS1[24]) will keep 1 when any one of ADINT interrupt flag ADFOVn (EADC_ADIFOV[3:0]) is overwritten to 1.
#define EADC_IS_SAMPLE_MODULE_OV | ( | eadc | ) |
Check all A/D sample module start of conversion overrun flags.
[in] | eadc | Base address of EADC module. |
0 | None of sample module event overrun flag is set to 1. |
1 | Any one of sample module event overrun flag is set to 1. |
The STOVF bit (EADC_STATUS1[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
#define EADC_POWER_DOWN | ( | eadc | ) |
#define EADC_POWER_ON | ( | eadc | ) |
#define EADC_START_CONV | ( | eadc, | |
u32ModuleMask | |||
) |
Start the A/D conversion.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleMask | The combination of sample module. Each bit corresponds to a sample module. This parameter decides which sample module will be conversion, valid range are between 1~0xFFFF. Bit 0 is sample module 0, bit 1 is sample module 1..., bit 15 is sample module 15. |
After write EADC_SWTRG register to start EADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
void EADC_Close | ( | EADC_T * | eadc | ) |
void EADC_ConfigSampleModule | ( | EADC_T * | eadc, |
uint32_t | u32ModuleNum, | ||
uint32_t | u32TriggerSrc, | ||
uint32_t | u32Channel | ||
) |
Configure the sample control logic module.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid values are:
|
[in] | u32TriggerSrc | Decides the trigger source. Valid values are:
|
[in] | u32Channel | Specifies the sample module channel, valid value are:
|
Each of EADC control logic modules 0~15 which is configurable for EADC converter channel and trigger source.
void EADC_Open | ( | EADC_T * | eadc, |
uint32_t | u32InputMode | ||
) |
This function make EADC_module be ready to convert.
[in] | eadc | Base address of EADC module. |
[in] | u32InputMode | This parameter is not used. |
This function is used to set analog input mode and enable A/D Converter. Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
void EADC_SetExtendSampleTime | ( | EADC_T * | eadc, |
uint32_t | u32ModuleNum, | ||
uint32_t | u32ExtendSampleTime | ||
) |
Set EADC extend sample time.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid values are:
|
[in] | u32ExtendSampleTime | Decides the extend sampling time, the range is from 0~255 EADC clock. Valid value are from 0 to 0xFF. |
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
void EADC_SetTriggerDelayTime | ( | EADC_T * | eadc, |
uint32_t | u32ModuleNum, | ||
uint32_t | u32TriggerDelayTime, | ||
uint32_t | u32DelayClockDivider | ||
) |
Set trigger delay time.
[in] | eadc | Base address of EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid values are:
|
[in] | u32TriggerDelayTime | Decides the trigger delay time, valid range are between 0~0xFF. |
[in] | u32DelayClockDivider | Decides the trigger delay clock divider. Valid values are:
|
User can configure the trigger delay time by setting TRGDLYCNT (EADC_ADxSPCTLn[15:8], x=0~1, n=0~7) and TRGDLYDIV (EADC_ADxSPCTLn[17:16], x=0~1, n=0~7). Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.