| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

NUC472_442.h
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1/**************************************************************************/
53#ifndef __NUC472_442_H__
54#define __NUC472_442_H__
55
56#ifdef __cplusplus
57extern "C" {
58#endif
59
60/******************************************************************************/
61/* Processor and Core Peripherals */
62/******************************************************************************/
71 typedef enum IRQn {
72 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
73 NonMaskableInt_IRQn = -14,
74 MemoryManagement_IRQn = -12,
75 BusFault_IRQn = -11,
76 UsageFault_IRQn = -10,
77 SVCall_IRQn = -5,
78 DebugMonitor_IRQn = -4,
79 PendSV_IRQn = -2,
80 SysTick_IRQn = -1,
82 /****** NUC472/NUC442 Specific Interrupt Numbers ********************************************************/
83
84 BOD_IRQn = 0,
85 IRC_IRQn = 1,
86 PWRWU_IRQn = 2,
87 SRAMF_IRQn = 3,
88 CLKF_IRQn = 4,
89 RTC_IRQn = 6,
90 TAMPER_IRQn = 7,
91 EINT0_IRQn = 8,
92 EINT1_IRQn = 9,
93 EINT2_IRQn = 10,
94 EINT3_IRQn = 11,
95 EINT4_IRQn = 12,
96 EINT5_IRQn = 13,
97 EINT6_IRQn = 14,
98 EINT7_IRQn = 15,
99 GPA_IRQn = 16,
100 GPB_IRQn = 17,
101 GPC_IRQn = 18,
102 GPD_IRQn = 19,
103 GPE_IRQn = 20,
104 GPF_IRQn = 21,
105 GPG_IRQn = 22,
106 GPH_IRQn = 23,
107 GPI_IRQn = 24,
108 TMR0_IRQn = 32,
109 TMR1_IRQn = 33,
110 TMR2_IRQn = 34,
111 TMR3_IRQn = 35,
112 PDMA_IRQn = 40,
113 ADC_IRQn = 42,
114 WDT_IRQn = 46,
115 WWDT_IRQn = 47,
116 EADC0_IRQn = 48,
117 EADC1_IRQn = 49,
118 EADC2_IRQn = 50,
119 EADC3_IRQn = 51,
120 ACMP_IRQn = 56,
121 OPA0_IRQn = 60,
122 OPA1_IRQn = 61,
123 ICAP0_IRQn = 62,
124 ICAP1_IRQn = 63,
125 PWM0CH0_IRQn = 64,
126 PWM0CH1_IRQn = 65,
127 PWM0CH2_IRQn = 66,
128 PWM0CH3_IRQn = 67,
129 PWM0CH4_IRQn = 68,
130 PWM0CH5_IRQn = 69,
131 PWM0_BRK_IRQn = 70,
132 QEI0_IRQn = 71,
133 PWM1CH0_IRQn = 72,
134 PWM1CH1_IRQn = 73,
135 PWM1CH2_IRQn = 74,
136 PWM1CH3_IRQn = 75,
137 PWM1CH4_IRQn = 76,
138 PWM1CH5_IRQn = 77,
139 PWM1BRK_IRQn = 78,
140 QEI1_IRQn = 79,
141 EPWM0_IRQn = 80,
142 EPWM0BRK_IRQn = 81,
143 EPWM1_IRQn = 82,
144 EPWM1BRK_IRQn = 83,
145 USBD_IRQn = 88,
146 USBH_IRQn = 89,
147 USB_OTG_IRQn = 90,
148 EMAC_TX_IRQn = 92,
149 EMAC_RX_IRQn = 93,
150 SPI0_IRQn = 96,
151 SPI1_IRQn = 97,
152 SPI2_IRQn = 98,
153 SPI3_IRQn = 99,
154 UART0_IRQn = 104,
155 UART1_IRQn = 105,
156 UART2_IRQn = 106,
157 UART3_IRQn = 107,
158 UART4_IRQn = 108,
159 UART5_IRQn = 109,
160 I2C0_IRQn = 112,
161 I2C1_IRQn = 113,
162 I2C2_IRQn = 114,
163 I2C3_IRQn = 115,
164 I2C4_IRQn = 116,
165 SC0_IRQn = 120,
166 SC1_IRQn = 121,
167 SC2_IRQn = 122,
168 SC3_IRQn = 123,
169 SC4_IRQn = 124,
170 SC5_IRQn = 125,
171 CAN0_IRQn = 128,
172 CAN1_IRQn = 129,
173 I2S0_IRQn = 132,
174 I2S1_IRQn = 133,
175 SD_IRQn = 136,
176 PS2D_IRQn = 138,
177 CAP_IRQn = 139,
178 CRPT_IRQn = 140,
179 CRC_IRQn = 141,
180}
181IRQn_Type;
182
183
184/*
185 * ==========================================================================
186 * ----------- Processor and Core Peripheral Section ------------------------
187 * ==========================================================================
188 */
189
190/* Configuration of the Cortex-M# Processor and Core Peripherals */
191#define __CM4_REV 0x0201
192#define __NVIC_PRIO_BITS 4
193#define __Vendor_SysTickConfig 0
194#define __MPU_PRESENT 1
195#define __FPU_PRESENT 1 /* end of group NUC472_442_CMSIS */
198
199
200#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
201#include "system_NUC472_442.h" /* NUC472/NUC442 System include file */
202#include <stdint.h>
203
204/******************************************************************************/
205/* Device Specific Peripheral registers structures */
206/******************************************************************************/
212#if defined ( __CC_ARM )
213#pragma anon_unions
214#endif
215
216
217/*---------------------- Analog Comparator Controller -------------------------*/
223 typedef struct {
224
225
257 __IO uint32_t CTL[3];
258
288 __IO uint32_t STATUS;
289
306 __IO uint32_t VREF;
307
308} ACMP_T;
309
315#define ACMP_CTL_ACMPEN_Pos (0)
316#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
318#define ACMP_CTL_ACMPIE_Pos (1)
319#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
321#define ACMP_CTL_HYSEN_Pos (2)
322#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos)
324#define ACMP_CTL_ACMPOINV_Pos (3)
325#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos)
327#define ACMP_CTL_NEGSEL_Pos (4)
328#define ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
330#define ACMP_CTL_POSSEL_Pos (5)
331#define ACMP_CTL_POSSEL_Msk (0x7ul << ACMP_CTL_POSSEL_Pos)
333#define ACMP_STATUS_ACMPIF0_Pos (0)
334#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
336#define ACMP_STATUS_ACMPIF1_Pos (1)
337#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
339#define ACMP_STATUS_ACMPIF2_Pos (2)
340#define ACMP_STATUS_ACMPIF2_Msk (0x1ul << ACMP_STATUS_ACMPIF2_Pos)
342#define ACMP_STATUS_ACMPO0_Pos (3)
343#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
345#define ACMP_STATUS_ACMPO1_Pos (4)
346#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
348#define ACMP_STATUS_ACMPO2_Pos (5)
349#define ACMP_STATUS_ACMPO2_Msk (0x1ul << ACMP_STATUS_ACMPO2_Pos)
351#define ACMP_VREF_CRVCTL_Pos (0)
352#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
354#define ACMP_VREF_CRVSSEL_Pos (6)
355#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos)
357#define ACMP_VREF_IREFSEL_Pos (7)
358#define ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos) /* ACMP_CONST */ /* end of ACMP register group */
362
363
364/*---------------------- Analog to Digital Converter -------------------------*/
370 typedef struct {
371
372
394 __I uint32_t DAT[14];
395
397 uint32_t RESERVE0[2];
399
400
470 __IO uint32_t CTL;
471
493 __IO uint32_t CHEN;
494
539 __IO uint32_t CMP[2];
540
572 __IO uint32_t STATUS0;
573
586 __I uint32_t STATUS1;
588 uint32_t RESERVE1[2];
590
591
602 __I uint32_t CURDAT;
603
604} ADC_T;
605
611#define ADC_DAT0_RESULT_Pos (0)
612#define ADC_DAT0_RESULT_Msk (0xfffful << ADC_DAT0_RESULT_Pos)
614#define ADC_DAT0_OV_Pos (16)
615#define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos)
617#define ADC_DAT0_VALID_Pos (17)
618#define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos)
620#define ADC_DAT1_RESULT_Pos (0)
621#define ADC_DAT1_RESULT_Msk (0xfffful << ADC_DAT1_RESULT_Pos)
623#define ADC_DAT1_OV_Pos (16)
624#define ADC_DAT1_OV_Msk (0x1ul << ADC_DAT1_OV_Pos)
626#define ADC_DAT1_VALID_Pos (17)
627#define ADC_DAT1_VALID_Msk (0x1ul << ADC_DAT1_VALID_Pos)
629#define ADC_DAT2_RESULT_Pos (0)
630#define ADC_DAT2_RESULT_Msk (0xfffful << ADC_DAT2_RESULT_Pos)
632#define ADC_DAT2_OV_Pos (16)
633#define ADC_DAT2_OV_Msk (0x1ul << ADC_DAT2_OV_Pos)
635#define ADC_DAT2_VALID_Pos (17)
636#define ADC_DAT2_VALID_Msk (0x1ul << ADC_DAT2_VALID_Pos)
638#define ADC_DAT3_RESULT_Pos (0)
639#define ADC_DAT3_RESULT_Msk (0xfffful << ADC_DAT3_RESULT_Pos)
641#define ADC_DAT3_OV_Pos (16)
642#define ADC_DAT3_OV_Msk (0x1ul << ADC_DAT3_OV_Pos)
644#define ADC_DAT3_VALID_Pos (17)
645#define ADC_DAT3_VALID_Msk (0x1ul << ADC_DAT3_VALID_Pos)
647#define ADC_DAT4_RESULT_Pos (0)
648#define ADC_DAT4_RESULT_Msk (0xfffful << ADC_DAT4_RESULT_Pos)
650#define ADC_DAT4_OV_Pos (16)
651#define ADC_DAT4_OV_Msk (0x1ul << ADC_DAT4_OV_Pos)
653#define ADC_DAT4_VALID_Pos (17)
654#define ADC_DAT4_VALID_Msk (0x1ul << ADC_DAT4_VALID_Pos)
656#define ADC_DAT5_RESULT_Pos (0)
657#define ADC_DAT5_RESULT_Msk (0xfffful << ADC_DAT5_RESULT_Pos)
659#define ADC_DAT5_OV_Pos (16)
660#define ADC_DAT5_OV_Msk (0x1ul << ADC_DAT5_OV_Pos)
662#define ADC_DAT5_VALID_Pos (17)
663#define ADC_DAT5_VALID_Msk (0x1ul << ADC_DAT5_VALID_Pos)
665#define ADC_DAT6_RESULT_Pos (0)
666#define ADC_DAT6_RESULT_Msk (0xfffful << ADC_DAT6_RESULT_Pos)
668#define ADC_DAT6_OV_Pos (16)
669#define ADC_DAT6_OV_Msk (0x1ul << ADC_DAT6_OV_Pos)
671#define ADC_DAT6_VALID_Pos (17)
672#define ADC_DAT6_VALID_Msk (0x1ul << ADC_DAT6_VALID_Pos)
674#define ADC_DAT7_RESULT_Pos (0)
675#define ADC_DAT7_RESULT_Msk (0xfffful << ADC_DAT7_RESULT_Pos)
677#define ADC_DAT7_OV_Pos (16)
678#define ADC_DAT7_OV_Msk (0x1ul << ADC_DAT7_OV_Pos)
680#define ADC_DAT7_VALID_Pos (17)
681#define ADC_DAT7_VALID_Msk (0x1ul << ADC_DAT7_VALID_Pos)
683#define ADC_DAT8_RESULT_Pos (0)
684#define ADC_DAT8_RESULT_Msk (0xfffful << ADC_DAT8_RESULT_Pos)
686#define ADC_DAT8_OV_Pos (16)
687#define ADC_DAT8_OV_Msk (0x1ul << ADC_DAT8_OV_Pos)
689#define ADC_DAT8_VALID_Pos (17)
690#define ADC_DAT8_VALID_Msk (0x1ul << ADC_DAT8_VALID_Pos)
692#define ADC_DAT9_RESULT_Pos (0)
693#define ADC_DAT9_RESULT_Msk (0xfffful << ADC_DAT9_RESULT_Pos)
695#define ADC_DAT9_OV_Pos (16)
696#define ADC_DAT9_OV_Msk (0x1ul << ADC_DAT9_OV_Pos)
698#define ADC_DAT9_VALID_Pos (17)
699#define ADC_DAT9_VALID_Msk (0x1ul << ADC_DAT9_VALID_Pos)
701#define ADC_DAT10_RESULT_Pos (0)
702#define ADC_DAT10_RESULT_Msk (0xfffful << ADC_DAT10_RESULT_Pos)
704#define ADC_DAT10_OV_Pos (16)
705#define ADC_DAT10_OV_Msk (0x1ul << ADC_DAT10_OV_Pos)
707#define ADC_DAT10_VALID_Pos (17)
708#define ADC_DAT10_VALID_Msk (0x1ul << ADC_DAT10_VALID_Pos)
710#define ADC_DAT11_RESULT_Pos (0)
711#define ADC_DAT11_RESULT_Msk (0xfffful << ADC_DAT11_RESULT_Pos)
713#define ADC_DAT11_OV_Pos (16)
714#define ADC_DAT11_OV_Msk (0x1ul << ADC_DAT11_OV_Pos)
716#define ADC_DAT11_VALID_Pos (17)
717#define ADC_DAT11_VALID_Msk (0x1ul << ADC_DAT11_VALID_Pos)
719#define ADC_DAT12_RESULT_Pos (0)
720#define ADC_DAT12_RESULT_Msk (0xfffful << ADC_DAT12_RESULT_Pos)
722#define ADC_DAT12_OV_Pos (16)
723#define ADC_DAT12_OV_Msk (0x1ul << ADC_DAT12_OV_Pos)
725#define ADC_DAT12_VALID_Pos (17)
726#define ADC_DAT12_VALID_Msk (0x1ul << ADC_DAT12_VALID_Pos)
728#define ADC_DAT13_RESULT_Pos (0)
729#define ADC_DAT13_RESULT_Msk (0xfffful << ADC_DAT13_RESULT_Pos)
731#define ADC_DAT13_OV_Pos (16)
732#define ADC_DAT13_OV_Msk (0x1ul << ADC_DAT13_OV_Pos)
734#define ADC_DAT13_VALID_Pos (17)
735#define ADC_DAT13_VALID_Msk (0x1ul << ADC_DAT13_VALID_Pos)
737#define ADC_CTL_ADCEN_Pos (0)
738#define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
740#define ADC_CTL_ADCIEN_Pos (1)
741#define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
743#define ADC_CTL_OPMODE_Pos (2)
744#define ADC_CTL_OPMODE_Msk (0x3ul << ADC_CTL_OPMODE_Pos)
746#define ADC_CTL_HWTRGSEL_Pos (4)
747#define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
749#define ADC_CTL_HWTRGCOND_Pos (6)
750#define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos)
752#define ADC_CTL_HWTRGEN_Pos (8)
753#define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
755#define ADC_CTL_PDMAEN_Pos (9)
756#define ADC_CTL_PDMAEN_Msk (0x1ul << ADC_CTL_PDMAEN_Pos)
758#define ADC_CTL_DIFFEN_Pos (10)
759#define ADC_CTL_DIFFEN_Msk (0x1ul << ADC_CTL_DIFFEN_Pos)
761#define ADC_CTL_SWTRG_Pos (11)
762#define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
764#define ADC_CTL_PWMTRGDLY_Pos (16)
765#define ADC_CTL_PWMTRGDLY_Msk (0xfful << ADC_CTL_PWMTRGDLY_Pos)
767#define ADC_CTL_DMOF_Pos (31)
768#define ADC_CTL_DMOF_Msk (0x1ul << ADC_CTL_DMOF_Pos)
770#define ADC_CHEN_CHEN_Pos (0)
771#define ADC_CHEN_CHEN_Msk (0xffful << ADC_CHEN_CHEN_Pos)
773#define ADC_CHEN_ADTSEN_Pos (16)
774#define ADC_CHEN_ADTSEN_Msk (0x1ul << ADC_CHEN_ADTSEN_Pos)
776#define ADC_CHEN_ADBGEN_Pos (17)
777#define ADC_CHEN_ADBGEN_Msk (0x1ul << ADC_CHEN_ADBGEN_Pos)
779#define ADC_CMP0_ADCMPEN_Pos (0)
780#define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
782#define ADC_CMP0_ADCMPIE_Pos (1)
783#define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
785#define ADC_CMP0_CMPCOND_Pos (2)
786#define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
788#define ADC_CMP0_CMPCH_Pos (3)
789#define ADC_CMP0_CMPCH_Msk (0xful << ADC_CMP0_CMPCH_Pos)
791#define ADC_CMP0_CMPMCNT_Pos (8)
792#define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
794#define ADC_CMP0_CMPDAT_Pos (16)
795#define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos)
797#define ADC_CMP1_ADCMPEN_Pos (0)
798#define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
800#define ADC_CMP1_ADCMPIE_Pos (1)
801#define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
803#define ADC_CMP1_CMPCOND_Pos (2)
804#define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
806#define ADC_CMP1_CMPCH_Pos (3)
807#define ADC_CMP1_CMPCH_Msk (0xful << ADC_CMP1_CMPCH_Pos)
809#define ADC_CMP1_CMPMCNT_Pos (8)
810#define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
812#define ADC_CMP1_CMPDAT_Pos (16)
813#define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos)
815#define ADC_STATUS0_ADIF_Pos (0)
816#define ADC_STATUS0_ADIF_Msk (0x1ul << ADC_STATUS0_ADIF_Pos)
818#define ADC_STATUS0_ADCMPF0_Pos (1)
819#define ADC_STATUS0_ADCMPF0_Msk (0x1ul << ADC_STATUS0_ADCMPF0_Pos)
821#define ADC_STATUS0_ADCMPF1_Pos (2)
822#define ADC_STATUS0_ADCMPF1_Msk (0x1ul << ADC_STATUS0_ADCMPF1_Pos)
824#define ADC_STATUS0_BUSY_Pos (3)
825#define ADC_STATUS0_BUSY_Msk (0x1ul << ADC_STATUS0_BUSY_Pos)
827#define ADC_STATUS0_CHANNEL_Pos (4)
828#define ADC_STATUS0_CHANNEL_Msk (0xful << ADC_STATUS0_CHANNEL_Pos)
830#define ADC_STATUS1_VALID_Pos (0)
831#define ADC_STATUS1_VALID_Msk (0x3ffful << ADC_STATUS1_VALID_Pos)
833#define ADC_STATUS1_OV_Pos (16)
834#define ADC_STATUS1_OV_Msk (0x3ffful << ADC_STATUS1_OV_Pos)
836#define ADC_CURDAT_CURDAT_Pos (0)
837#define ADC_CURDAT_CURDAT_Msk (0x3fffful << ADC_CURDAT_CURDAT_Pos) /* ADC_CONST */ /* end of ADC register group */
841
842
843/*---------------------- Controller Area Network Controller -------------------------*/
849 typedef struct {
850
868 __IO uint32_t CREQ;
869
931 __IO uint32_t CMASK;
932
944 __IO uint32_t MASK1;
945
965 __IO uint32_t MASK2;
966
978 __IO uint32_t ARB1;
979
1006 __IO uint32_t ARB2;
1007
1063 __IO uint32_t MCON;
1064
1077 __IO uint32_t DAT_A1;
1078
1091 __IO uint32_t DAT_A2;
1092
1105 __IO uint32_t DAT_B1;
1106
1119 __IO uint32_t DAT_B2;
1121 __I uint32_t RESERVE0[13];
1123} CAN_IF_T;
1124
1125 typedef struct {
1126
1156 __IO uint32_t CON;
1157
1188 __IO uint32_t STATUS;
1189
1205 __IO uint32_t ERR;
1206
1229 __IO uint32_t BTIME;
1230
1248 __IO uint32_t IIDR;
1249
1278 __IO uint32_t TEST;
1279
1291 __IO uint32_t BRPE;
1292
1293 __I uint32_t RESERVE0[1];
1294
1295 __IO CAN_IF_T IF[2];
1296
1297 __I uint32_t RESERVE1[8];
1298
1311 __IO uint32_t TXREQ1;
1312
1325 __IO uint32_t TXREQ2;
1326
1327 __I uint32_t RESERVE2[6];
1328
1340 __IO uint32_t NDAT1;
1341
1353 __IO uint32_t NDAT2;
1354
1355 __I uint32_t RESERVE3[6];
1356
1368 __IO uint32_t IPND1;
1369
1381 __IO uint32_t IPND2;
1382
1383 __I uint32_t RESERVE4[6];
1384
1399 __IO uint32_t MVLD1;
1400
1414 __IO uint32_t MVLD2;
1415
1428 __IO uint32_t WU_EN;
1429
1442 __IO uint32_t WU_STATUS;
1443} CAN_T;
1444
1450#define CAN_CON_TEST_Pos 7
1451#define CAN_CON_TEST_Msk (1ul << CAN_CON_TEST_Pos)
1453#define CAN_CON_CCE_Pos 6
1454#define CAN_CON_CCE_Msk (1ul << CAN_CON_CCE_Pos)
1456#define CAN_CON_DAR_Pos 5
1457#define CAN_CON_DAR_Msk (1ul << CAN_CON_DAR_Pos)
1459#define CAN_CON_EIE_Pos 3
1460#define CAN_CON_EIE_Msk (1ul << CAN_CON_EIE_Pos)
1462#define CAN_CON_SIE_Pos 2
1463#define CAN_CON_SIE_Msk (1ul << CAN_CON_SIE_Pos)
1465#define CAN_CON_IE_Pos 1
1466#define CAN_CON_IE_Msk (1ul << CAN_CON_IE_Pos)
1468#define CAN_CON_INIT_Pos 0
1469#define CAN_CON_INIT_Msk (1ul << CAN_CON_INIT_Pos)
1471#define CAN_STATUS_BOFF_Pos 7
1472#define CAN_STATUS_BOFF_Msk (1ul << CAN_STATUS_BOFF_Pos)
1474#define CAN_STATUS_EWARN_Pos 6
1475#define CAN_STATUS_EWARN_Msk (1ul << CAN_STATUS_EWARN_Pos)
1477#define CAN_STATUS_EPASS_Pos 5
1478#define CAN_STATUS_EPASS_Msk (1ul << CAN_STATUS_EPASS_Pos)
1480#define CAN_STATUS_RXOK_Pos 4
1481#define CAN_STATUS_RXOK_Msk (1ul << CAN_STATUS_RXOK_Pos)
1483#define CAN_STATUS_TXOK_Pos 3
1484#define CAN_STATUS_TXOK_Msk (1ul << CAN_STATUS_TXOK_Pos)
1486#define CAN_STATUS_LEC_Pos 0
1487#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos)
1489#define CAN_ERR_RP_Pos 15
1490#define CAN_ERR_RP_Msk (1ul << CAN_ERR_RP_Pos)
1492#define CAN_ERR_REC_Pos 8
1493#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos)
1495#define CAN_ERR_TEC_Pos 0
1496#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos)
1498#define CAN_BTIME_TSEG2_Pos 12
1499#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos)
1501#define CAN_BTIME_TSEG1_Pos 8
1502#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos)
1504#define CAN_BTIME_SJW_Pos 6
1505#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos)
1507#define CAN_BTIME_BRP_Pos 0
1508#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos)
1510#define CAN_IIDR_INTID_Pos 0
1511#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos)
1513#define CAN_TEST_RX_Pos 7
1514#define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos)
1516#define CAN_TEST_TX_Pos 5
1517#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos)
1519#define CAN_TEST_LBACK_Pos 4
1520#define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos)
1522#define CAN_TEST_SILENT_Pos 3
1523#define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos)
1525#define CAN_TEST_BASIC_Pos 2
1526#define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos)
1528#define CAN_BRPE_BRPE_Pos 0
1529#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos)
1531#define CAN_IF_CREQ_BUSY_Pos 15
1532#define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos)
1534#define CAN_IF_CREQ_MSGNUM_Pos 0
1535#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos)
1537#define CAN_IF_CMASK_WRRD_Pos 7
1538#define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos)
1540#define CAN_IF_CMASK_MASK_Pos 6
1541#define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos)
1543#define CAN_IF_CMASK_ARB_Pos 5
1544#define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos)
1546#define CAN_IF_CMASK_CONTROL_Pos 4
1547#define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos)
1549#define CAN_IF_CMASK_CLRINTPND_Pos 3
1550#define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos)
1552#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2
1553#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos)
1555#define CAN_IF_CMASK_DATAA_Pos 1
1556#define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos)
1558#define CAN_IF_CMASK_DATAB_Pos 0
1559#define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos)
1561#define CAN_IF_MASK1_MSK_Pos 0
1562#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos)
1564#define CAN_IF_MASK2_MXTD_Pos 15
1565#define CAN_IF_MASK2_MXTD_Msk (1ul << CAN_IF_MASK2_MXTD_Pos)
1567#define CAN_IF_MASK2_MDIR_Pos 14
1568#define CAN_IF_MASK2_MDIR_Msk (1ul << CAN_IF_MASK2_MDIR_Pos)
1570#define CAN_IF_MASK2_MSK_Pos 0
1571#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos)
1573#define CAN_IF_ARB1_ID_Pos 0
1574#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos)
1576#define CAN_IF_ARB2_MSGVAL_Pos 15
1577#define CAN_IF_ARB2_MSGVAL_Msk (1ul << CAN_IF_ARB2_MSGVAL_Pos)
1579#define CAN_IF_ARB2_XTD_Pos 14
1580#define CAN_IF_ARB2_XTD_Msk (1ul << CAN_IF_ARB2_XTD_Pos)
1582#define CAN_IF_ARB2_DIR_Pos 13
1583#define CAN_IF_ARB2_DIR_Msk (1ul << CAN_IF_ARB2_DIR_Pos)
1585#define CAN_IF_ARB2_ID_Pos 0
1586#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos)
1588#define CAN_IF_MCON_NEWDAT_Pos 15
1589#define CAN_IF_MCON_NEWDAT_Msk (1ul << CAN_IF_MCON_NEWDAT_Pos)
1591#define CAN_IF_MCON_MSGLST_Pos 14
1592#define CAN_IF_MCON_MSGLST_Msk (1ul << CAN_IF_MCON_MSGLST_Pos)
1594#define CAN_IF_MCON_INTPND_Pos 13
1595#define CAN_IF_MCON_INTPND_Msk (1ul << CAN_IF_MCON_INTPND_Pos)
1597#define CAN_IF_MCON_UMASK_Pos 12
1598#define CAN_IF_MCON_UMASK_Msk (1ul << CAN_IF_MCON_UMASK_Pos)
1600#define CAN_IF_MCON_TXIE_Pos 11
1601#define CAN_IF_MCON_TXIE_Msk (1ul << CAN_IF_MCON_TXIE_Pos)
1603#define CAN_IF_MCON_RXIE_Pos 10
1604#define CAN_IF_MCON_RXIE_Msk (1ul << CAN_IF_MCON_RXIE_Pos)
1606#define CAN_IF_MCON_RMTEN_Pos 9
1607#define CAN_IF_MCON_RMTEN_Msk (1ul << CAN_IF_MCON_RMTEN_Pos)
1609#define CAN_IF_MCON_TXRQST_Pos 8
1610#define CAN_IF_MCON_TXRQST_Msk (1ul << CAN_IF_MCON_TXRQST_Pos)
1612#define CAN_IF_MCON_EOB_Pos 7
1613#define CAN_IF_MCON_EOB_Msk (1ul << CAN_IF_MCON_EOB_Pos)
1615#define CAN_IF_MCON_DLC_Pos 0
1616#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos)
1618#define CAN_IF_DAT_A1_DATA1_Pos 8
1619#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos)
1621#define CAN_IF_DAT_A1_DATA0_Pos 0
1622#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos)
1624#define CAN_IF_DAT_A2_DATA3_Pos 8
1625#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos)
1627#define CAN_IF_DAT_A2_DATA2_Pos 0
1628#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos)
1630#define CAN_IF_DAT_B1_DATA5_Pos 8
1631#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos)
1633#define CAN_IF_DAT_B1_DATA4_Pos 0
1634#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos)
1636#define CAN_IF_DAT_B2_DATA7_Pos 8
1637#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos)
1639#define CAN_IF_DAT_B2_DATA6_Pos 0
1640#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos)
1642#define CAN_IF_TXRQST1_TXRQST_Pos 0
1643#define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos)
1645#define CAN_IF_TXRQST2_TXRQST_Pos 0
1646#define CAN_IF_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST2_TXRQST_Pos)
1648#define CAN_IF_NDAT1_NEWDATA_Pos 0
1649#define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos)
1651#define CAN_IF_NDAT2_NEWDATA_Pos 0
1652#define CAN_IF_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT2_NEWDATA_Pos)
1654#define CAN_IF_IPND1_INTPND_Pos 0
1655#define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos)
1657#define CAN_IF_IPND2_INTPND_Pos 0
1658#define CAN_IF_IPND2_INTPND_Msk (0xFFFFul << CAN_IF_IPND2_INTPND_Pos)
1660#define CAN_IF_MVLD1_MSGVAL_Pos 0
1661#define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos)
1663#define CAN_IF_MVLD2_MSGVAL_Pos 0
1664#define CAN_IF_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD2_MSGVAL_Pos)
1666#define CAN_WUEN_WAKUP_EN_Pos 0
1667#define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos)
1669#define CAN_WUSTATUS_WAKUP_STS_Pos 0
1670#define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /* CAN_CONST */ /* end of CAN register group */
1674
1675
1676/*---------------------- Capture Engine -------------------------*/
1682 typedef struct {
1683
1684
1714 __IO uint32_t CTL;
1715
1771 __IO uint32_t PAR;
1772
1804 __IO uint32_t INT;
1805
1820 __IO uint32_t POSTERIZE;
1821
1845 __IO uint32_t MD;
1846
1856 __IO uint32_t MDADDR;
1857
1867 __IO uint32_t MDYADDR;
1868
1879 __IO uint32_t SEPIA;
1880
1891 __IO uint32_t CWSP;
1892
1903 __IO uint32_t CWS;
1904
1929 __IO uint32_t PKTSL;
1930
1955 __IO uint32_t PLNSL;
1956
1971 __IO uint32_t FRCTL;
1972
1985 __IO uint32_t STRIDE;
1987 uint32_t RESERVE0[1];
1989
1990
2004 __IO uint32_t FIFOTH;
2005
2016 __IO uint32_t CMPADDR;
2018 uint32_t RESERVE1[1];
2020
2021
2042 __IO uint32_t PKTSM;
2043
2064 __IO uint32_t PLNSM;
2065
2075 __I uint32_t CURADDRP;
2076
2086 __I uint32_t CURADDRY;
2087
2097 __I uint32_t CURADDRU;
2098
2108 __I uint32_t CURVADDR;
2109
2120 __IO uint32_t PKTBA0;
2121
2132 __IO uint32_t PKTBA1;
2134 uint32_t RESERVE2[6];
2136
2137
2148 __IO uint32_t YBA;
2149
2160 __IO uint32_t UBA;
2161
2172 __IO uint32_t VBA;
2173
2174} CAP_T;
2175
2181#define CAP_CTL_CAPEN_Pos (0)
2182#define CAP_CTL_CAPEN_Msk (0x1ul << CAP_CTL_CAPEN_Pos)
2184#define CAP_CTL_ADDRSW_Pos (3)
2185#define CAP_CTL_ADDRSW_Msk (0x1ul << CAP_CTL_ADDRSW_Pos)
2187#define CAP_CTL_PLNEN_Pos (5)
2188#define CAP_CTL_PLNEN_Msk (0x1ul << CAP_CTL_PLNEN_Pos)
2190#define CAP_CTL_PKTEN_Pos (6)
2191#define CAP_CTL_PKTEN_Msk (0x1ul << CAP_CTL_PKTEN_Pos)
2193#define CAP_CTL_SHUTTER_Pos (16)
2194#define CAP_CTL_SHUTTER_Msk (0x1ul << CAP_CTL_SHUTTER_Pos)
2196#define CAP_CTL_UPDATE_Pos (20)
2197#define CAP_CTL_UPDATE_Msk (0x1ul << CAP_CTL_UPDATE_Pos)
2199#define CAP_CTL_VPRST_Pos (24)
2200#define CAP_CTL_VPRST_Msk (0x1ul << CAP_CTL_VPRST_Pos)
2202#define CAP_PAR_INFMT_Pos (0)
2203#define CAP_PAR_INFMT_Msk (0x1ul << CAP_PAR_INFMT_Pos)
2205#define CAP_PAR_SENTYPE_Pos (1)
2206#define CAP_PAR_SENTYPE_Msk (0x1ul << CAP_PAR_SENTYPE_Pos)
2208#define CAP_PAR_INDATORD_Pos (2)
2209#define CAP_PAR_INDATORD_Msk (0x3ul << CAP_PAR_INDATORD_Pos)
2211#define CAP_PAR_OUTFMT_Pos (4)
2212#define CAP_PAR_OUTFMT_Msk (0x3ul << CAP_PAR_OUTFMT_Pos)
2214#define CAP_PAR_RANGE_Pos (6)
2215#define CAP_PAR_RANGE_Msk (0x1ul << CAP_PAR_RANGE_Pos)
2217#define CAP_PAR_PLNFMT_Pos (7)
2218#define CAP_PAR_PLNFMT_Msk (0x1ul << CAP_PAR_PLNFMT_Pos)
2220#define CAP_PAR_PCLKP_Pos (8)
2221#define CAP_PAR_PCLKP_Msk (0x1ul << CAP_PAR_PCLKP_Pos)
2223#define CAP_PAR_HSP_Pos (9)
2224#define CAP_PAR_HSP_Msk (0x1ul << CAP_PAR_HSP_Pos)
2226#define CAP_PAR_VSP_Pos (10)
2227#define CAP_PAR_VSP_Msk (0x1ul << CAP_PAR_VSP_Pos)
2229#define CAP_PAR_COLORCTL_Pos (11)
2230#define CAP_PAR_COLORCTL_Msk (0x3ul << CAP_PAR_COLORCTL_Pos)
2232#define CAP_PAR_FBB_Pos (18)
2233#define CAP_PAR_FBB_Msk (0x1ul << CAP_PAR_FBB_Pos)
2235#define CAP_INT_VINTF_Pos (0)
2236#define CAP_INT_VINTF_Msk (0x1ul << CAP_INT_VINTF_Pos)
2238#define CAP_INT_MEINTF_Pos (1)
2239#define CAP_INT_MEINTF_Msk (0x1ul << CAP_INT_MEINTF_Pos)
2241#define CAP_INT_ADDRMINTF_Pos (3)
2242#define CAP_INT_ADDRMINTF_Msk (0x1ul << CAP_INT_ADDRMINTF_Pos)
2244#define CAP_INT_MDINTF_Pos (4)
2245#define CAP_INT_MDINTF_Msk (0x1ul << CAP_INT_MDINTF_Pos)
2247#define CAP_INT_VIEN_Pos (16)
2248#define CAP_INT_VIEN_Msk (0x1ul << CAP_INT_VIEN_Pos)
2250#define CAP_INT_MEIEN_Pos (17)
2251#define CAP_INT_MEIEN_Msk (0x1ul << CAP_INT_MEIEN_Pos)
2253#define CAP_INT_ADDRMIEN_Pos (19)
2254#define CAP_INT_ADDRMIEN_Msk (0x1ul << CAP_INT_ADDRMIEN_Pos)
2256#define CAP_INT_MDIEN_Pos (20)
2257#define CAP_INT_MDIEN_Msk (0x1ul << CAP_INT_MDIEN_Pos)
2259#define CAP_POSTERIZE_VCOMP_Pos (0)
2260#define CAP_POSTERIZE_VCOMP_Msk (0xfful << CAP_POSTERIZE_VCOMP_Pos)
2262#define CAP_POSTERIZE_UCOMP_Pos (8)
2263#define CAP_POSTERIZE_UCOMP_Msk (0xfful << CAP_POSTERIZE_UCOMP_Pos)
2265#define CAP_POSTERIZE_YCOMP_Pos (16)
2266#define CAP_POSTERIZE_YCOMP_Msk (0xfful << CAP_POSTERIZE_YCOMP_Pos)
2268#define CAP_MD_MDEN_Pos (0)
2269#define CAP_MD_MDEN_Msk (0x1ul << CAP_MD_MDEN_Pos)
2271#define CAP_MD_MDBS_Pos (8)
2272#define CAP_MD_MDBS_Msk (0x1ul << CAP_MD_MDBS_Pos)
2274#define CAP_MD_MDSM_Pos (9)
2275#define CAP_MD_MDSM_Msk (0x1ul << CAP_MD_MDSM_Pos)
2277#define CAP_MD_MDDF_Pos (10)
2278#define CAP_MD_MDDF_Msk (0x3ul << CAP_MD_MDDF_Pos)
2280#define CAP_MD_MDTHR_Pos (16)
2281#define CAP_MD_MDTHR_Msk (0x1ful << CAP_MD_MDTHR_Pos)
2283#define CAP_MDADDR_MDADDR_Pos (0)
2284#define CAP_MDADDR_MDADDR_Msk (0xfffffffful << CAP_MDADDR_MDADDR_Pos)
2286#define CAP_MDYADDR_MDYADDR_Pos (0)
2287#define CAP_MDYADDR_MDYADDR_Msk (0xfffffffful << CAP_MDYADDR_MDYADDR_Pos)
2289#define CAP_SEPIA_VCOMP_Pos (0)
2290#define CAP_SEPIA_VCOMP_Msk (0xfful << CAP_SEPIA_VCOMP_Pos)
2292#define CAP_SEPIA_UCOMP_Pos (8)
2293#define CAP_SEPIA_UCOMP_Msk (0xfful << CAP_SEPIA_UCOMP_Pos)
2295#define CAP_CWSP_CWSADDRH_Pos (0)
2296#define CAP_CWSP_CWSADDRH_Msk (0xffful << CAP_CWSP_CWSADDRH_Pos)
2298#define CAP_CWSP_CWSADDRV_Pos (16)
2299#define CAP_CWSP_CWSADDRV_Msk (0x7fful << CAP_CWSP_CWSADDRV_Pos)
2301#define CAP_CWS_CWW_Pos (0)
2302#define CAP_CWS_CWW_Msk (0xffful << CAP_CWS_CWW_Pos)
2304#define CAP_CWS_CWH_Pos (16)
2305#define CAP_CWS_CWH_Msk (0x7fful << CAP_CWS_CWH_Pos)
2307#define CAP_PKTSL_PKTSHML_Pos (0)
2308#define CAP_PKTSL_PKTSHML_Msk (0xfful << CAP_PKTSL_PKTSHML_Pos)
2310#define CAP_PKTSL_PKTSHNL_Pos (8)
2311#define CAP_PKTSL_PKTSHNL_Msk (0xfful << CAP_PKTSL_PKTSHNL_Pos)
2313#define CAP_PKTSL_PKTSVML_Pos (16)
2314#define CAP_PKTSL_PKTSVML_Msk (0xfful << CAP_PKTSL_PKTSVML_Pos)
2316#define CAP_PKTSL_PKTSVNL_Pos (24)
2317#define CAP_PKTSL_PKTSVNL_Msk (0xfful << CAP_PKTSL_PKTSVNL_Pos)
2319#define CAP_PLNSL_PLNSHML_Pos (0)
2320#define CAP_PLNSL_PLNSHML_Msk (0xfful << CAP_PLNSL_PLNSHML_Pos)
2322#define CAP_PLNSL_PLNSHNL_Pos (8)
2323#define CAP_PLNSL_PLNSHNL_Msk (0xfful << CAP_PLNSL_PLNSHNL_Pos)
2325#define CAP_PLNSL_PLNSVML_Pos (16)
2326#define CAP_PLNSL_PLNSVML_Msk (0xfful << CAP_PLNSL_PLNSVML_Pos)
2328#define CAP_PLNSL_PLNSVNL_Pos (24)
2329#define CAP_PLNSL_PLNSVNL_Msk (0xfful << CAP_PLNSL_PLNSVNL_Pos)
2331#define CAP_FRCTL_FRM_Pos (0)
2332#define CAP_FRCTL_FRM_Msk (0x3ful << CAP_FRCTL_FRM_Pos)
2334#define CAP_FRCTL_FRN_Pos (8)
2335#define CAP_FRCTL_FRN_Msk (0x3ful << CAP_FRCTL_FRN_Pos)
2337#define CAP_STRIDE_PKTSTRIDE_Pos (0)
2338#define CAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CAP_STRIDE_PKTSTRIDE_Pos)
2340#define CAP_STRIDE_PLNSTRIDE_Pos (16)
2341#define CAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CAP_STRIDE_PLNSTRIDE_Pos)
2343#define CAP_FIFOTH_PLNVFTH_Pos (0)
2344#define CAP_FIFOTH_PLNVFTH_Msk (0xful << CAP_FIFOTH_PLNVFTH_Pos)
2346#define CAP_FIFOTH_PLNUFTH_Pos (8)
2347#define CAP_FIFOTH_PLNUFTH_Msk (0xful << CAP_FIFOTH_PLNUFTH_Pos)
2349#define CAP_FIFOTH_PLNYFTH_Pos (16)
2350#define CAP_FIFOTH_PLNYFTH_Msk (0x1ful << CAP_FIFOTH_PLNYFTH_Pos)
2352#define CAP_FIFOTH_PKTFTH_Pos (24)
2353#define CAP_FIFOTH_PKTFTH_Msk (0x1ful << CAP_FIFOTH_PKTFTH_Pos)
2355#define CAP_FIFOTH_OVF_Pos (31)
2356#define CAP_FIFOTH_OVF_Msk (0x1ul << CAP_FIFOTH_OVF_Pos)
2358#define CAP_CMPADDR_CMPADDR_Pos (0)
2359#define CAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CAP_CMPADDR_CMPADDR_Pos)
2361#define CAP_PKTSM_PKTSHMH_Pos (0)
2362#define CAP_PKTSM_PKTSHMH_Msk (0xfful << CAP_PKTSM_PKTSHMH_Pos)
2364#define CAP_PKTSM_PKTSHNH_Pos (8)
2365#define CAP_PKTSM_PKTSHNH_Msk (0xfful << CAP_PKTSM_PKTSHNH_Pos)
2367#define CAP_PKTSM_PKTSVMH_Pos (16)
2368#define CAP_PKTSM_PKTSVMH_Msk (0xfful << CAP_PKTSM_PKTSVMH_Pos)
2370#define CAP_PKTSM_PKTSVNH_Pos (24)
2371#define CAP_PKTSM_PKTSVNH_Msk (0xfful << CAP_PKTSM_PKTSVNH_Pos)
2373#define CAP_PLNSM_PLNSHMH_Pos (0)
2374#define CAP_PLNSM_PLNSHMH_Msk (0xfful << CAP_PLNSM_PLNSHMH_Pos)
2376#define CAP_PLNSM_PLNSHNH_Pos (8)
2377#define CAP_PLNSM_PLNSHNH_Msk (0xfful << CAP_PLNSM_PLNSHNH_Pos)
2379#define CAP_PLNSM_PLNSVMH_Pos (16)
2380#define CAP_PLNSM_PLNSVMH_Msk (0xfful << CAP_PLNSM_PLNSVMH_Pos)
2382#define CAP_PLNSM_PLNSVNH_Pos (24)
2383#define CAP_PLNSM_PLNSVNH_Msk (0xfful << CAP_PLNSM_PLNSVNH_Pos)
2385#define CAP_CURADDRP_CURADDR_Pos (0)
2386#define CAP_CURADDRP_CURADDR_Msk (0xfffffffful << CAP_CURADDRP_CURADDR_Pos)
2388#define CAP_CURADDRY_CURADDR_Pos (0)
2389#define CAP_CURADDRY_CURADDR_Msk (0xfffffffful << CAP_CURADDRY_CURADDR_Pos)
2391#define CAP_CURADDRU_CURADDR_Pos (0)
2392#define CAP_CURADDRU_CURADDR_Msk (0xfffffffful << CAP_CURADDRU_CURADDR_Pos)
2394#define CAP_CURVADDR_CURADDR_Pos (0)
2395#define CAP_CURVADDR_CURADDR_Msk (0xfffffffful << CAP_CURVADDR_CURADDR_Pos)
2397#define CAP_PKTBA0_BASEADDR_Pos (0)
2398#define CAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CAP_PKTBA0_BASEADDR_Pos)
2400#define CAP_PKTBA1_BASEADDR_Pos (0)
2401#define CAP_PKTBA1_BASEADDR_Msk (0xfffffffful << CAP_PKTBA1_BASEADDR_Pos)
2403#define CAP_YBA_BASEADDR_Pos (0)
2404#define CAP_YBA_BASEADDR_Msk (0xfffffffful << CAP_YBA_BASEADDR_Pos)
2406#define CAP_UBA_BASEADDR_Pos (0)
2407#define CAP_UBA_BASEADDR_Msk (0xfffffffful << CAP_UBA_BASEADDR_Pos)
2409#define CAP_VBA_BASEADDR_Pos (0)
2410#define CAP_VBA_BASEADDR_Msk (0xfffffffful << CAP_VBA_BASEADDR_Pos) /* CAP_CONST */ /* end of CAP register group */
2414
2415
2416/*---------------------- Enhanced Input Capture Timer -------------------------*/
2422 typedef struct {
2423
2424
2436 __IO uint32_t CNT;
2437
2449 __IO uint32_t HOLD0;
2450
2462 __IO uint32_t HOLD1;
2463
2475 __IO uint32_t HOLD2;
2476
2488 __IO uint32_t CNTCMP;
2489
2573 __IO uint32_t CTL0;
2574
2622 __IO uint32_t CTL1;
2623
2657 __IO uint32_t STATUS;
2658
2659} ECAP_T;
2660
2666#define ECAP_CNT_VAL_Pos (0)
2667#define ECAP_CNT_VAL_Msk (0xfffffful << ECAP_CNT_VAL_Pos)
2669#define ECAP_HOLD0_VAL_Pos (0)
2670#define ECAP_HOLD0_VAL_Msk (0xfffffful << ECAP_HOLD0_VAL_Pos)
2672#define ECAP_HOLD1_VAL_Pos (0)
2673#define ECAP_HOLD1_VAL_Msk (0xfffffful << ECAP_HOLD1_VAL_Pos)
2675#define ECAP_HOLD2_VAL_Pos (0)
2676#define ECAP_HOLD2_VAL_Msk (0xfffffful << ECAP_HOLD2_VAL_Pos)
2678#define ECAP_CNTCMP_VAL_Pos (0)
2679#define ECAP_CNTCMP_VAL_Msk (0xfffffful << ECAP_CNTCMP_VAL_Pos)
2681#define ECAP_CTL0_NFDIS_Pos (0)
2682#define ECAP_CTL0_NFDIS_Msk (0x3ul << ECAP_CTL0_NFDIS_Pos)
2684#define ECAP_CTL0_CAPNF_DIS_Pos (3)
2685#define ECAP_CTL0_CAPNF_DIS_Msk (0x1ul << ECAP_CTL0_CAPNF_DIS_Pos)
2687#define ECAP_CTL0_CAPEN0_Pos (4)
2688#define ECAP_CTL0_CAPEN0_Msk (0x1ul << ECAP_CTL0_CAPEN0_Pos)
2690#define ECAP_CTL0_CAPEN1_Pos (5)
2691#define ECAP_CTL0_CAPEN1_Msk (0x1ul << ECAP_CTL0_CAPEN1_Pos)
2693#define ECAP_CTL0_CAPEN2_Pos (6)
2694#define ECAP_CTL0_CAPEN2_Msk (0x1ul << ECAP_CTL0_CAPEN2_Pos)
2696#define ECAP_CTL0_CAPSEL0_Pos (8)
2697#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos)
2699#define ECAP_CTL0_CAPSEL1_Pos (10)
2700#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos)
2702#define ECAP_CTL0_CAPSEL2_Pos (12)
2703#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos)
2705#define ECAP_CTL0_CAPIEN0_Pos (16)
2706#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos)
2708#define ECAP_CTL0_CAPIEN1_Pos (17)
2709#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos)
2711#define ECAP_CTL0_CAPIEN2_Pos (18)
2712#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos)
2714#define ECAP_CTL0_OVIEN_Pos (20)
2715#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos)
2717#define ECAP_CTL0_CMPIEN_Pos (21)
2718#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos)
2720#define ECAP_CTL0_CNTEN_Pos (24)
2721#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos)
2723#define ECAP_CTL0_CMPCLR_Pos (25)
2724#define ECAP_CTL0_CMPCLR_Msk (0x1ul << ECAP_CTL0_CMPCLR_Pos)
2726#define ECAP_CTL0_CPTCLR_Pos (26)
2727#define ECAP_CTL0_CPTCLR_Msk (0x1ul << ECAP_CTL0_CPTCLR_Pos)
2729#define ECAP_CTL0_RLDEN_Pos (27)
2730#define ECAP_CTL0_RLDEN_Msk (0x1ul << ECAP_CTL0_RLDEN_Pos)
2732#define ECAP_CTL0_CMPEN_Pos (28)
2733#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos)
2735#define ECAP_CTL0_CAPEN_Pos (29)
2736#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos)
2738#define ECAP_CTL1_EDGESEL0_Pos (0)
2739#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos)
2741#define ECAP_CTL1_EDGESEL1_Pos (2)
2742#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos)
2744#define ECAP_CTL1_EDGESEL2_Pos (4)
2745#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos)
2747#define ECAP_CTL1_RLDSEL_Pos (8)
2748#define ECAP_CTL1_RLDSEL_Msk (0x7ul << ECAP_CTL1_RLDSEL_Pos)
2750#define ECAP_CTL1_CLKSEL_Pos (12)
2751#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos)
2753#define ECAP_CTL1_SRCSEL_Pos (16)
2754#define ECAP_CTL1_SRCSEL_Msk (0x3ul << ECAP_CTL1_SRCSEL_Pos)
2756#define ECAP_STATUS_CAPF0_Pos (0)
2757#define ECAP_STATUS_CAPF0_Msk (0x1ul << ECAP_STATUS_CAPF0_Pos)
2759#define ECAP_STATUS_CAPF1_Pos (1)
2760#define ECAP_STATUS_CAPF1_Msk (0x1ul << ECAP_STATUS_CAPF1_Pos)
2762#define ECAP_STATUS_CAPF2_Pos (2)
2763#define ECAP_STATUS_CAPF2_Msk (0x1ul << ECAP_STATUS_CAPF2_Pos)
2765#define ECAP_STATUS_CMPF_Pos (4)
2766#define ECAP_STATUS_CMPF_Msk (0x1ul << ECAP_STATUS_CMPF_Pos)
2768#define ECAP_STATUS_OVF_Pos (5)
2769#define ECAP_STATUS_OVF_Msk (0x1ul << ECAP_STATUS_OVF_Pos) /* ECAP_CONST */ /* end of ECAP register group */
2773
2774
2775/*---------------------- System Clock Controller -------------------------*/
2781 typedef struct {
2782
2783
2841 __IO uint32_t PWRCTL;
2842
2884 __IO uint32_t AHBCLK;
2885
2984 __IO uint32_t APBCLK0;
2985
3057 __IO uint32_t APBCLK1;
3058
3120 __IO uint32_t CLKSEL0;
3121
3200 __IO uint32_t CLKSEL1;
3201
3264 __IO uint32_t CLKSEL2;
3265
3314 __IO uint32_t CLKSEL3;
3315
3334 __IO uint32_t CLKDIV0;
3335
3352 __IO uint32_t CLKDIV1;
3353
3366 __IO uint32_t CLKDIV2;
3367
3382 __IO uint32_t CLKDIV3;
3384 uint32_t RESERVE0[4];
3386
3387
3418 __IO uint32_t PLLCTL;
3419
3435 __IO uint32_t PLL2CTL;
3437 uint32_t RESERVE1[2];
3439
3440
3480 __IO uint32_t STATUS;
3482 uint32_t RESERVE2[3];
3484
3485
3506 __IO uint32_t CLKOCTL;
3508 uint32_t RESERVE3[3];
3510
3511
3538 __IO uint32_t CLKDCTL;
3539
3540} CLK_T;
3541
3547#define CLK_PWRCTL_HXTEN_Pos (0)
3548#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos)
3550#define CLK_PWRCTL_LXTEN_Pos (1)
3551#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos)
3553#define CLK_PWRCTL_HIRCEN_Pos (2)
3554#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos)
3556#define CLK_PWRCTL_LIRCEN_Pos (3)
3557#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
3559#define CLK_PWRCTL_PDWKDLY_Pos (4)
3560#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
3562#define CLK_PWRCTL_PDWKIEN_Pos (5)
3563#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
3565#define CLK_PWRCTL_PDWKIF_Pos (6)
3566#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos)
3568#define CLK_PWRCTL_PDEN_Pos (7)
3569#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
3571#define CLK_PWRCTL_PDWTCPU_Pos (8)
3572#define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos)
3574#define CLK_PWRCTL_DBPDEN_Pos (9)
3575#define CLK_PWRCTL_DBPDEN_Msk (0x1ul << CLK_PWRCTL_DBPDEN_Pos)
3577#define CLK_AHBCLK_PDMACKEN_Pos (1)
3578#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)
3580#define CLK_AHBCLK_ISPCKEN_Pos (2)
3581#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
3583#define CLK_AHBCLK_EBICKEN_Pos (3)
3584#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos)
3586#define CLK_AHBCLK_USBHCKEN_Pos (4)
3587#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)
3589#define CLK_AHBCLK_EMACCKEN_Pos (5)
3590#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos)
3592#define CLK_AHBCLK_SDHCKEN_Pos (6)
3593#define CLK_AHBCLK_SDHCKEN_Msk (0x1ul << CLK_AHBCLK_SDHCKEN_Pos)
3595#define CLK_AHBCLK_CRCCKEN_Pos (7)
3596#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)
3598#define CLK_AHBCLK_CAPCKEN_Pos (8)
3599#define CLK_AHBCLK_CAPCKEN_Msk (0x1ul << CLK_AHBCLK_CAPCKEN_Pos)
3601#define CLK_AHBCLK_SENCKEN_Pos (9)
3602#define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos)
3604#define CLK_AHBCLK_USBDCKEN_Pos (10)
3605#define CLK_AHBCLK_USBDCKEN_Msk (0x1ul << CLK_AHBCLK_USBDCKEN_Pos)
3607#define CLK_AHBCLK_CRPTCKEN_Pos (12)
3608#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos)
3610#define CLK_APBCLK0_WDTCKEN_Pos (0)
3611#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)
3613#define CLK_APBCLK0_RTCCKEN_Pos (1)
3614#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)
3616#define CLK_APBCLK0_TMR0CKEN_Pos (2)
3617#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)
3619#define CLK_APBCLK0_TMR1CKEN_Pos (3)
3620#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)
3622#define CLK_APBCLK0_TMR2CKEN_Pos (4)
3623#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)
3625#define CLK_APBCLK0_TMR3CKEN_Pos (5)
3626#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)
3628#define CLK_APBCLK0_CLKOCKEN_Pos (6)
3629#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)
3631#define CLK_APBCLK0_ACMPCKEN_Pos (7)
3632#define CLK_APBCLK0_ACMPCKEN_Msk (0x1ul << CLK_APBCLK0_ACMPCKEN_Pos)
3634#define CLK_APBCLK0_I2C0CKEN_Pos (8)
3635#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)
3637#define CLK_APBCLK0_I2C1CKEN_Pos (9)
3638#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)
3640#define CLK_APBCLK0_I2C2CKEN_Pos (10)
3641#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos)
3643#define CLK_APBCLK0_I2C3CKEN_Pos (11)
3644#define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos)
3646#define CLK_APBCLK0_SPI0CKEN_Pos (12)
3647#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)
3649#define CLK_APBCLK0_SPI1CKEN_Pos (13)
3650#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)
3652#define CLK_APBCLK0_SPI2CKEN_Pos (14)
3653#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos)
3655#define CLK_APBCLK0_SPI3CKEN_Pos (15)
3656#define CLK_APBCLK0_SPI3CKEN_Msk (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos)
3658#define CLK_APBCLK0_UART0CKEN_Pos (16)
3659#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)
3661#define CLK_APBCLK0_UART1CKEN_Pos (17)
3662#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)
3664#define CLK_APBCLK0_UART2CKEN_Pos (18)
3665#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)
3667#define CLK_APBCLK0_UART3CKEN_Pos (19)
3668#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)
3670#define CLK_APBCLK0_UART4CKEN_Pos (20)
3671#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos)
3673#define CLK_APBCLK0_UART5CKEN_Pos (21)
3674#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos)
3676#define CLK_APBCLK0_CAN0CKEN_Pos (24)
3677#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos)
3679#define CLK_APBCLK0_CAN1CKEN_Pos (25)
3680#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos)
3682#define CLK_APBCLK0_OTGCKEN_Pos (26)
3683#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos)
3685#define CLK_APBCLK0_ADCCKEN_Pos (28)
3686#define CLK_APBCLK0_ADCCKEN_Msk (0x1ul << CLK_APBCLK0_ADCCKEN_Pos)
3688#define CLK_APBCLK0_I2S0CKEN_Pos (29)
3689#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos)
3691#define CLK_APBCLK0_I2S1CKEN_Pos (30)
3692#define CLK_APBCLK0_I2S1CKEN_Msk (0x1ul << CLK_APBCLK0_I2S1CKEN_Pos)
3694#define CLK_APBCLK0_PS2CKEN_Pos (31)
3695#define CLK_APBCLK0_PS2CKEN_Msk (0x1ul << CLK_APBCLK0_PS2CKEN_Pos)
3697#define CLK_APBCLK1_SC0CKEN_Pos (0)
3698#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)
3700#define CLK_APBCLK1_SC1CKEN_Pos (1)
3701#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos)
3703#define CLK_APBCLK1_SC2CKEN_Pos (2)
3704#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos)
3706#define CLK_APBCLK1_SC3CKEN_Pos (3)
3707#define CLK_APBCLK1_SC3CKEN_Msk (0x1ul << CLK_APBCLK1_SC3CKEN_Pos)
3709#define CLK_APBCLK1_SC4CKEN_Pos (4)
3710#define CLK_APBCLK1_SC4CKEN_Msk (0x1ul << CLK_APBCLK1_SC4CKEN_Pos)
3712#define CLK_APBCLK1_SC5CKEN_Pos (5)
3713#define CLK_APBCLK1_SC5CKEN_Msk (0x1ul << CLK_APBCLK1_SC5CKEN_Pos)
3715#define CLK_APBCLK1_I2C4CKEN_Pos (8)
3716#define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos)
3718#define CLK_APBCLK1_PWM0CH01CKEN_Pos (16)
3719#define CLK_APBCLK1_PWM0CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH01CKEN_Pos)
3721#define CLK_APBCLK1_PWM0CH23CKEN_Pos (17)
3722#define CLK_APBCLK1_PWM0CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH23CKEN_Pos)
3724#define CLK_APBCLK1_PWM0CH45CKEN_Pos (18)
3725#define CLK_APBCLK1_PWM0CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH45CKEN_Pos)
3727#define CLK_APBCLK1_PWM1CH01CKEN_Pos (19)
3728#define CLK_APBCLK1_PWM1CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH01CKEN_Pos)
3730#define CLK_APBCLK1_PWM1CH23CKEN_Pos (20)
3731#define CLK_APBCLK1_PWM1CH23CKEN_Msk (0x3ul << CLK_APBCLK1_PWM1CH23CKEN_Pos)
3733#define CLK_APBCLK1_PWM1CH45CKEN_Pos (21)
3734#define CLK_APBCLK1_PWM1CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH45CKEN_Pos)
3736#define CLK_APBCLK1_QEI0CKEN_Pos (22)
3737#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos)
3739#define CLK_APBCLK1_QEI1CKEN_Pos (23)
3740#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos)
3742#define CLK_APBCLK1_ECAP0CKEN_Pos (26)
3743#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos)
3745#define CLK_APBCLK1_ECAP1CKEN_Pos (27)
3746#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos)
3748#define CLK_APBCLK1_EPWM0CKEN_Pos (28)
3749#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos)
3751#define CLK_APBCLK1_EPWM1CKEN_Pos (29)
3752#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos)
3754#define CLK_APBCLK1_OPACKEN_Pos (30)
3755#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos)
3757#define CLK_APBCLK1_EADCCKEN_Pos (31)
3758#define CLK_APBCLK1_EADCCKEN_Msk (0x1ul << CLK_APBCLK1_EADCCKEN_Pos)
3760#define CLK_CLKSEL0_HCLKSEL_Pos (0)
3761#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
3763#define CLK_CLKSEL0_STCLKSEL_Pos (3)
3764#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)
3766#define CLK_CLKSEL0_PCLKSEL_Pos (6)
3767#define CLK_CLKSEL0_PCLKSEL_Msk (0x1ul << CLK_CLKSEL0_PCLKSEL_Pos)
3769#define CLK_CLKSEL0_USBHSEL_Pos (8)
3770#define CLK_CLKSEL0_USBHSEL_Msk (0x1ul << CLK_CLKSEL0_USBHSEL_Pos)
3772#define CLK_CLKSEL0_CAPSEL_Pos (16)
3773#define CLK_CLKSEL0_CAPSEL_Msk (0x3ul << CLK_CLKSEL0_CAPSEL_Pos)
3775#define CLK_CLKSEL0_SDHSEL_Pos (20)
3776#define CLK_CLKSEL0_SDHSEL_Msk (0x3ul << CLK_CLKSEL0_SDHSEL_Pos)
3778#define CLK_CLKSEL1_WDTSEL_Pos (0)
3779#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
3781#define CLK_CLKSEL1_ADCSEL_Pos (2)
3782#define CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos)
3784#define CLK_CLKSEL1_SPI0SEL_Pos (4)
3785#define CLK_CLKSEL1_SPI0SEL_Msk (0x1ul << CLK_CLKSEL1_SPI0SEL_Pos)
3787#define CLK_CLKSEL1_SPI1SEL_Pos (5)
3788#define CLK_CLKSEL1_SPI1SEL_Msk (0x1ul << CLK_CLKSEL1_SPI1SEL_Pos)
3790#define CLK_CLKSEL1_SPI2SEL_Pos (6)
3791#define CLK_CLKSEL1_SPI2SEL_Msk (0x1ul << CLK_CLKSEL1_SPI2SEL_Pos)
3793#define CLK_CLKSEL1_SPI3SEL_Pos (7)
3794#define CLK_CLKSEL1_SPI3SEL_Msk (0x1ul << CLK_CLKSEL1_SPI3SEL_Pos)
3796#define CLK_CLKSEL1_TMR0SEL_Pos (8)
3797#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
3799#define CLK_CLKSEL1_TMR1SEL_Pos (12)
3800#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
3802#define CLK_CLKSEL1_TMR2SEL_Pos (16)
3803#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)
3805#define CLK_CLKSEL1_TMR3SEL_Pos (20)
3806#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)
3808#define CLK_CLKSEL1_UARTSEL_Pos (24)
3809#define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos)
3811#define CLK_CLKSEL1_CLKOSEL_Pos (28)
3812#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)
3814#define CLK_CLKSEL1_WWDTSEL_Pos (30)
3815#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)
3817#define CLK_CLKSEL2_PWM0CH01SEL_Pos (0)
3818#define CLK_CLKSEL2_PWM0CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH01SEL_Pos)
3820#define CLK_CLKSEL2_PWM0CH23SEL_Pos (4)
3821#define CLK_CLKSEL2_PWM0CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH23SEL_Pos)
3823#define CLK_CLKSEL2_PWM0CH45SEL_Pos (8)
3824#define CLK_CLKSEL2_PWM0CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH45SEL_Pos)
3826#define CLK_CLKSEL2_PWM1CH01SEL_Pos (12)
3827#define CLK_CLKSEL2_PWM1CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH01SEL_Pos)
3829#define CLK_CLKSEL2_PWM1CH23SEL_Pos (16)
3830#define CLK_CLKSEL2_PWM1CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH23SEL_Pos)
3832#define CLK_CLKSEL2_PWM1CH45SEL_Pos (20)
3833#define CLK_CLKSEL2_PWM1CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH45SEL_Pos)
3835#define CLK_CLKSEL3_SC0SEL_Pos (0)
3836#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)
3838#define CLK_CLKSEL3_SC1SEL_Pos (2)
3839#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos)
3841#define CLK_CLKSEL3_SC2SEL_Pos (4)
3842#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos)
3844#define CLK_CLKSEL3_SC3SEL_Pos (6)
3845#define CLK_CLKSEL3_SC3SEL_Msk (0x3ul << CLK_CLKSEL3_SC3SEL_Pos)
3847#define CLK_CLKSEL3_SC4SEL_Pos (8)
3848#define CLK_CLKSEL3_SC4SEL_Msk (0x3ul << CLK_CLKSEL3_SC4SEL_Pos)
3850#define CLK_CLKSEL3_SC5SEL_Pos (10)
3851#define CLK_CLKSEL3_SC5SEL_Msk (0x3ul << CLK_CLKSEL3_SC5SEL_Pos)
3853#define CLK_CLKSEL3_I2S0SEL_Pos (16)
3854#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos)
3856#define CLK_CLKSEL3_I2S1SEL_Pos (18)
3857#define CLK_CLKSEL3_I2S1SEL_Msk (0x3ul << CLK_CLKSEL3_I2S1SEL_Pos)
3859#define CLK_CLKDIV0_HCLKDIV_Pos (0)
3860#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos)
3862#define CLK_CLKDIV0_USBHDIV_Pos (4)
3863#define CLK_CLKDIV0_USBHDIV_Msk (0xful << CLK_CLKDIV0_USBHDIV_Pos)
3865#define CLK_CLKDIV0_UARTDIV_Pos (8)
3866#define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos)
3868#define CLK_CLKDIV0_ADCDIV_Pos (16)
3869#define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos)
3871#define CLK_CLKDIV0_SDHDIV_Pos (24)
3872#define CLK_CLKDIV0_SDHDIV_Msk (0xfful << CLK_CLKDIV0_SDHDIV_Pos)
3874#define CLK_CLKDIV1_SC0DIV_Pos (0)
3875#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos)
3877#define CLK_CLKDIV1_SC1DIV_Pos (8)
3878#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos)
3880#define CLK_CLKDIV1_SC2DIV_Pos (16)
3881#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos)
3883#define CLK_CLKDIV1_SC3DIV_Pos (24)
3884#define CLK_CLKDIV1_SC3DIV_Msk (0xfful << CLK_CLKDIV1_SC3DIV_Pos)
3886#define CLK_CLKDIV2_SC4DIV_Pos (0)
3887#define CLK_CLKDIV2_SC4DIV_Msk (0xfful << CLK_CLKDIV2_SC4DIV_Pos)
3889#define CLK_CLKDIV2_SC5DIV_Pos (8)
3890#define CLK_CLKDIV2_SC5DIV_Msk (0xfful << CLK_CLKDIV2_SC5DIV_Pos)
3892#define CLK_CLKDIV3_CAPDIV_Pos (0)
3893#define CLK_CLKDIV3_CAPDIV_Msk (0xfful << CLK_CLKDIV3_CAPDIV_Pos)
3895#define CLK_CLKDIV3_VSENSEDIV_Pos (8)
3896#define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos)
3898#define CLK_CLKDIV3_EMACDIV_Pos (16)
3899#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos)
3901#define CLK_PLLCTL_FBDIV_Pos (0)
3902#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
3904#define CLK_PLLCTL_INDIV_Pos (9)
3905#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
3907#define CLK_PLLCTL_OUTDV_Pos (14)
3908#define CLK_PLLCTL_OUTDV_Msk (0x3ul << CLK_PLLCTL_OUTDV_Pos)
3910#define CLK_PLLCTL_PD_Pos (16)
3911#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
3913#define CLK_PLLCTL_BP_Pos (17)
3914#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
3916#define CLK_PLLCTL_OE_Pos (18)
3917#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
3919#define CLK_PLLCTL_PLLSRC_Pos (19)
3920#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
3922#define CLK_PLLCTL_PLLREMAP_Pos (20)
3923#define CLK_PLLCTL_PLLREMAP_Msk (0x1ul << CLK_PLLCTL_PLLREMAP_Pos)
3925#define CLK_PLL2CTL_PLL2DIV_Pos (0)
3926#define CLK_PLL2CTL_PLL2DIV_Msk (0xfful << CLK_PLL2CTL_PLL2DIV_Pos)
3928#define CLK_PLL2CTL_PLL2CKEN_Pos (8)
3929#define CLK_PLL2CTL_PLL2CKEN_Msk (0x1ul << CLK_PLL2CTL_PLL2CKEN_Pos)
3931#define CLK_STATUS_HXTSTB_Pos (0)
3932#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos)
3934#define CLK_STATUS_LXTSTB_Pos (1)
3935#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos)
3937#define CLK_STATUS_PLLSTB_Pos (2)
3938#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos)
3940#define CLK_STATUS_LIRCSTB_Pos (3)
3941#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
3943#define CLK_STATUS_HIRCSTB_Pos (4)
3944#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos)
3946#define CLK_STATUS_PLL2STB_Pos (5)
3947#define CLK_STATUS_PLL2STB_Msk (0x1ul << CLK_STATUS_PLL2STB_Pos)
3949#define CLK_STATUS_CLKSFAIL_Pos (7)
3950#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
3952#define CLK_CLKOCTL_FSEL_Pos (0)
3953#define CLK_CLKOCTL_FSEL_Msk (0xful << CLK_CLKOCTL_FSEL_Pos)
3955#define CLK_CLKOCTL_CLKOEN_Pos (4)
3956#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
3958#define CLK_CLKOCTL_DIV1EN_Pos (5)
3959#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
3961#define CLK_CLKDCTL_SYSFDEN_Pos (0)
3962#define CLK_CLKDCTL_SYSFDEN_Msk (0x1ul << CLK_CLKDCTL_SYSFDEN_Pos)
3964#define CLK_CLKDCTL_SYSFIEN_Pos (1)
3965#define CLK_CLKDCTL_SYSFIEN_Msk (0x1ul << CLK_CLKDCTL_SYSFIEN_Pos)
3967#define CLK_CLKDCTL_SYSFIF_Pos (2)
3968#define CLK_CLKDCTL_SYSFIF_Msk (0x1ul << CLK_CLKDCTL_SYSFIF_Pos)
3970#define CLK_CLKDCTL_IRCDEN_Pos (8)
3971#define CLK_CLKDCTL_IRCDEN_Msk (0x1ul << CLK_CLKDCTL_IRCDEN_Pos)
3973#define CLK_CLKDCTL_IRCFIEN_Pos (9)
3974#define CLK_CLKDCTL_IRCFIEN_Msk (0x1ul << CLK_CLKDCTL_IRCFIEN_Pos)
3976#define CLK_CLKDCTL_IRCFIF_Pos (10)
3977#define CLK_CLKDCTL_IRCFIF_Msk (0x1ul << CLK_CLKDCTL_IRCFIF_Pos) /* CLK_CONST */ /* end of CLK register group */
3981
3982
3983/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
3989 typedef struct {
3990
3991
4034 __IO uint32_t CTL;
4035
4047 __IO uint32_t DAT;
4048
4059 __IO uint32_t SEED;
4060
4071 __I uint32_t CHECKSUM;
4072
4073} CRC_T;
4074
4080#define CRC_CTL_CRCEN_Pos (0)
4081#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos)
4083#define CRC_CTL_CRCRST_Pos (1)
4084#define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos)
4086#define CRC_CTL_DATREV_Pos (24)
4087#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos)
4089#define CRC_CTL_CHKSREV_Pos (25)
4090#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos)
4092#define CRC_CTL_DATFMT_Pos (26)
4093#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos)
4095#define CRC_CTL_CHKSFMT_Pos (27)
4096#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos)
4098#define CRC_CTL_DATLEN_Pos (28)
4099#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos)
4101#define CRC_CTL_CRCMODE_Pos (30)
4102#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos)
4104#define CRC_DAT_DATA_Pos (0)
4105#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos)
4107#define CRC_SEED_SEED_Pos (0)
4108#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos)
4110#define CRC_CHECKSUM_CHECKSUM_Pos (0)
4111#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /* CRC_CONST */ /* end of CRC register group */
4115
4116
4117/*---------------------- Cryptographic Accelerator -------------------------*/
4123 typedef struct {
4159 __IO uint32_t INTEN;
4160
4201 __IO uint32_t INTSTS;
4202
4225 __IO uint32_t PRNG_CTL;
4226
4237 __O uint32_t PRNG_SEED;
4238
4249 __I uint32_t PRNG_KEY0;
4250
4261 __I uint32_t PRNG_KEY1;
4262
4273 __I uint32_t PRNG_KEY2;
4274
4285 __I uint32_t PRNG_KEY3;
4286
4297 __I uint32_t PRNG_KEY4;
4298
4309 __I uint32_t PRNG_KEY5;
4310
4321 __I uint32_t PRNG_KEY6;
4322
4333 __I uint32_t PRNG_KEY7;
4335 uint32_t RESERVE0[8];
4337
4338
4354 __I uint32_t AES_FDBCK0;
4355
4371 __I uint32_t AES_FDBCK1;
4372
4388 __I uint32_t AES_FDBCK2;
4389
4405 __I uint32_t AES_FDBCK3;
4406
4424 __I uint32_t TDES_FDBCKH;
4425
4443 __I uint32_t TDES_FDBCKL;
4445 uint32_t RESERVE1[38];
4447
4448
4518 __IO uint32_t AES_CTL;
4519
4562 __I uint32_t AES_STS;
4563
4574 __IO uint32_t AES_DATIN;
4575
4587 __I uint32_t AES_DATOUT;
4588
4605 __IO uint32_t AES0_KEY0;
4606
4623 __IO uint32_t AES0_KEY1;
4624
4641 __IO uint32_t AES0_KEY2;
4642
4659 __IO uint32_t AES0_KEY3;
4660
4677 __IO uint32_t AES0_KEY4;
4678
4695 __IO uint32_t AES0_KEY5;
4696
4713 __IO uint32_t AES0_KEY6;
4714
4731 __IO uint32_t AES0_KEY7;
4732
4746 __IO uint32_t AES0_IV0;
4747
4761 __IO uint32_t AES0_IV1;
4762
4776 __IO uint32_t AES0_IV2;
4777
4791 __IO uint32_t AES0_IV3;
4792
4813 __IO uint32_t AES0_SADDR;
4814
4835 __IO uint32_t AES0_DADDR;
4836
4856 __IO uint32_t AES0_CNT;
4857
4874 __IO uint32_t AES1_KEY0;
4875
4892 __IO uint32_t AES1_KEY1;
4893
4910 __IO uint32_t AES1_KEY2;
4911
4928 __IO uint32_t AES1_KEY3;
4929
4946 __IO uint32_t AES1_KEY4;
4947
4964 __IO uint32_t AES1_KEY5;
4965
4982 __IO uint32_t AES1_KEY6;
4983
5000 __IO uint32_t AES1_KEY7;
5001
5015 __IO uint32_t AES1_IV0;
5016
5030 __IO uint32_t AES1_IV1;
5031
5045 __IO uint32_t AES1_IV2;
5046
5060 __IO uint32_t AES1_IV3;
5061
5082 __IO uint32_t AES1_SADDR;
5083
5104 __IO uint32_t AES1_DADDR;
5105
5125 __IO uint32_t AES1_CNT;
5126
5143 __IO uint32_t AES2_KEY0;
5144
5161 __IO uint32_t AES2_KEY1;
5162
5179 __IO uint32_t AES2_KEY2;
5180
5197 __IO uint32_t AES2_KEY3;
5198
5215 __IO uint32_t AES2_KEY4;
5216
5233 __IO uint32_t AES2_KEY5;
5234
5251 __IO uint32_t AES2_KEY6;
5252
5269 __IO uint32_t AES2_KEY7;
5270
5284 __IO uint32_t AES2_IV0;
5285
5299 __IO uint32_t AES2_IV1;
5300
5314 __IO uint32_t AES2_IV2;
5315
5329 __IO uint32_t AES2_IV3;
5330
5351 __IO uint32_t AES2_SADDR;
5352
5373 __IO uint32_t AES2_DADDR;
5374
5394 __IO uint32_t AES2_CNT;
5395
5412 __IO uint32_t AES3_KEY0;
5413
5430 __IO uint32_t AES3_KEY1;
5431
5448 __IO uint32_t AES3_KEY2;
5449
5466 __IO uint32_t AES3_KEY3;
5467
5484 __IO uint32_t AES3_KEY4;
5485
5502 __IO uint32_t AES3_KEY5;
5503
5520 __IO uint32_t AES3_KEY6;
5521
5538 __IO uint32_t AES3_KEY7;
5539
5553 __IO uint32_t AES3_IV0;
5554
5568 __IO uint32_t AES3_IV1;
5569
5583 __IO uint32_t AES3_IV2;
5584
5598 __IO uint32_t AES3_IV3;
5599
5620 __IO uint32_t AES3_SADDR;
5621
5642 __IO uint32_t AES3_DADDR;
5643
5663 __IO uint32_t AES3_CNT;
5664
5733 __IO uint32_t TDES_CTL;
5734
5773 __I uint32_t TDES_STS;
5774
5788 __IO uint32_t TDES0_KEY1H;
5789
5803 __IO uint32_t TDES0_KEY1L;
5804
5818 __IO uint32_t TDES0_KEY2H;
5819
5833 __IO uint32_t TDES0_KEY2L;
5834
5848 __IO uint32_t TDES0_KEY3H;
5849
5863 __IO uint32_t TDES0_KEY3L;
5864
5876 __IO uint32_t TDES0_IVH;
5877
5889 __IO uint32_t TDES0_IVL;
5890
5911 __IO uint32_t TDES0_SADDR;
5912
5933 __IO uint32_t TDES0_DADDR;
5934
5951 __IO uint32_t TDES0_CNT;
5952
5964 __IO uint32_t TDES_DATIN;
5965
5977 __I uint32_t TDES_DATOUT;
5979 uint32_t RESERVE2[3];
5981
5982
5996 __IO uint32_t TDES1_KEY1H;
5997
6011 __IO uint32_t TDES1_KEY1L;
6012
6026 __IO uint32_t TDES1_KEY2H;
6027
6041 __IO uint32_t TDES1_KEY2L;
6042
6056 __IO uint32_t TDES1_KEY3H;
6057
6071 __IO uint32_t TDES1_KEY3L;
6072
6084 __IO uint32_t TDES1_IVH;
6085
6097 __IO uint32_t TDES1_IVL;
6098
6119 __IO uint32_t TDES1_SADDR;
6120
6141 __IO uint32_t TDES1_DADDR;
6142
6159 __IO uint32_t TDES1_CNT;
6161 uint32_t RESERVE3[5];
6163
6164
6178 __IO uint32_t TDES2_KEY1H;
6179
6193 __IO uint32_t TDES2_KEY1L;
6194
6208 __IO uint32_t TDES2_KEY2H;
6209
6223 __IO uint32_t TDES2_KEY2L;
6224
6238 __IO uint32_t TDES2_KEY3H;
6239
6253 __IO uint32_t TDES2_KEY3L;
6254
6266 __IO uint32_t TDES2_IVH;
6267
6279 __IO uint32_t TDES2_IVL;
6280
6301 __IO uint32_t TDES2_SADDR;
6302
6323 __IO uint32_t TDES2_DADDR;
6324
6341 __IO uint32_t TDES2_CNT;
6343 uint32_t RESERVE4[5];
6345
6346
6360 __IO uint32_t TDES3_KEY1H;
6361
6375 __IO uint32_t TDES3_KEY1L;
6376
6390 __IO uint32_t TDES3_KEY2H;
6391
6405 __IO uint32_t TDES3_KEY2L;
6406
6420 __IO uint32_t TDES3_KEY3H;
6421
6435 __IO uint32_t TDES3_KEY3L;
6436
6448 __IO uint32_t TDES3_IVH;
6449
6461 __IO uint32_t TDES3_IVL;
6462
6483 __IO uint32_t TDES3_SADDR;
6484
6505 __IO uint32_t TDES3_DADDR;
6506
6523 __IO uint32_t TDES3_CNT;
6525 uint32_t RESERVE5[3];
6527
6528
6564 __IO uint32_t SHA_CTL;
6565
6586 __I uint32_t SHA_STS;
6587
6600 __I uint32_t SHA_DGST0;
6601
6614 __I uint32_t SHA_DGST1;
6615
6628 __I uint32_t SHA_DGST2;
6629
6642 __I uint32_t SHA_DGST3;
6643
6656 __I uint32_t SHA_DGST4;
6657
6670 __I uint32_t SHA_DGST5;
6671
6684 __I uint32_t SHA_DGST6;
6685
6698 __I uint32_t SHA_DGST7;
6700 uint32_t RESERVE6[8];
6702
6703
6719 __IO uint32_t SHA_KEYCNT;
6720
6741 __IO uint32_t SHA_SADDR;
6742
6759 __IO uint32_t SHA_DMACNT;
6760
6771 __IO uint32_t SHA_DATIN;
6772
6773} CRPT_T;
6774
6780#define CRPT_INTEN_AESIEN_Pos (0)
6781#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos)
6783#define CRPT_INTEN_AESERRIEN_Pos (1)
6784#define CRPT_INTEN_AESERRIEN_Msk (0x1ul << CRPT_INTEN_AESERRIEN_Pos)
6786#define CRPT_INTEN_TDESIEN_Pos (8)
6787#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos)
6789#define CRPT_INTEN_TDESERRIEN_Pos (9)
6790#define CRPT_INTEN_TDESERRIEN_Msk (0x1ul << CRPT_INTEN_TDESERRIEN_Pos)
6792#define CRPT_INTEN_PRNGIEN_Pos (16)
6793#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos)
6795#define CRPT_INTEN_SHAIEN_Pos (24)
6796#define CRPT_INTEN_SHAIEN_Msk (0x1ul << CRPT_INTEN_SHAIEN_Pos)
6798#define CRPT_INTEN_SHAERRIEN_Pos (25)
6799#define CRPT_INTEN_SHAERRIEN_Msk (0x1ul << CRPT_INTEN_SHAERRIEN_Pos)
6801#define CRPT_INTSTS_AESIF_Pos (0)
6802#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos)
6804#define CRPT_INTSTS_AESERRIF_Pos (1)
6805#define CRPT_INTSTS_AESERRIF_Msk (0x1ul << CRPT_INTSTS_AESERRIF_Pos)
6807#define CRPT_INTSTS_TDESIF_Pos (8)
6808#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos)
6810#define CRPT_INTSTS_TDESERRIF_Pos (9)
6811#define CRPT_INTSTS_TDESERRIF_Msk (0x1ul << CRPT_INTSTS_TDESERRIF_Pos)
6813#define CRPT_INTSTS_PRNGIF_Pos (16)
6814#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos)
6816#define CRPT_INTSTS_SHAIF_Pos (24)
6817#define CRPT_INTSTS_SHAIF_Msk (0x1ul << CRPT_INTSTS_SHAIF_Pos)
6819#define CRPT_INTSTS_SHAERRIF_Pos (25)
6820#define CRPT_INTSTS_SHAERRIF_Msk (0x1ul << CRPT_INTSTS_SHAERRIF_Pos)
6822#define CRPT_PRNG_CTL_START_Pos (0)
6823#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos)
6825#define CRPT_PRNG_CTL_SEEDRLD_Pos (1)
6826#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos)
6828#define CRPT_PRNG_CTL_KEYSZ_Pos (2)
6829#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos)
6831#define CRPT_PRNG_CTL_BUSY_Pos (8)
6832#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos)
6834#define CRPT_PRNG_SEED_SEED_Pos (0)
6835#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos)
6837#define CRPT_PRNG_KEY0_KEY_Pos (0)
6838#define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos)
6840#define CRPT_PRNG_KEY1_KEY_Pos (0)
6841#define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos)
6843#define CRPT_PRNG_KEY2_KEY_Pos (0)
6844#define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos)
6846#define CRPT_PRNG_KEY3_KEY_Pos (0)
6847#define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos)
6849#define CRPT_PRNG_KEY4_KEY_Pos (0)
6850#define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos)
6852#define CRPT_PRNG_KEY5_KEY_Pos (0)
6853#define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos)
6855#define CRPT_PRNG_KEY6_KEY_Pos (0)
6856#define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos)
6858#define CRPT_PRNG_KEY7_KEY_Pos (0)
6859#define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos)
6861#define CRPT_AES_FDBCK0_FDBCK_Pos (0)
6862#define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos)
6864#define CRPT_AES_FDBCK1_FDBCK_Pos (0)
6865#define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos)
6867#define CRPT_AES_FDBCK2_FDBCK_Pos (0)
6868#define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos)
6870#define CRPT_AES_FDBCK3_FDBCK_Pos (0)
6871#define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos)
6873#define CRPT_TDES_FDBCKH_FDBCK_Pos (0)
6874#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos)
6876#define CRPT_TDES_FDBCKL_FDBCK_Pos (0)
6877#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos)
6879#define CRPT_AES_CTL_START_Pos (0)
6880#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos)
6882#define CRPT_AES_CTL_STOP_Pos (1)
6883#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos)
6885#define CRPT_AES_CTL_KEYSZ_Pos (2)
6886#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos)
6888#define CRPT_AES_CTL_DMALAST_Pos (5)
6889#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos)
6891#define CRPT_AES_CTL_DMACSCAD_Pos (6)
6892#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos)
6894#define CRPT_AES_CTL_DMAEN_Pos (7)
6895#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos)
6897#define CRPT_AES_CTL_OPMODE_Pos (8)
6898#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos)
6900#define CRPT_AES_CTL_ENCRPT_Pos (16)
6901#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos)
6903#define CRPT_AES_CTL_OUTSWAP_Pos (22)
6904#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos)
6906#define CRPT_AES_CTL_INSWAP_Pos (23)
6907#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos)
6909#define CRPT_AES_CTL_CHANNEL_Pos (24)
6910#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos)
6912#define CRPT_AES_CTL_KEYUNPRT_Pos (26)
6913#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos)
6915#define CRPT_AES_CTL_KEYPRT_Pos (31)
6916#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos)
6918#define CRPT_AES_STS_BUSY_Pos (0)
6919#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos)
6921#define CRPT_AES_STS_INBUFEMPTY_Pos (8)
6922#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos)
6924#define CRPT_AES_STS_INBUFFULL_Pos (9)
6925#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos)
6927#define CRPT_AES_STS_INBUFERR_Pos (10)
6928#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos)
6930#define CRPT_AES_STS_CNTERR_Pos (12)
6931#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos)
6933#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16)
6934#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos)
6936#define CRPT_AES_STS_OUTBUFFULL_Pos (17)
6937#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos)
6939#define CRPT_AES_STS_OUTBUFERR_Pos (18)
6940#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos)
6942#define CRPT_AES_STS_BUSERR_Pos (20)
6943#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos)
6945#define CRPT_AES_DATIN_DATIN_Pos (0)
6946#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos)
6948#define CRPT_AES_DATOUT_DATOUT_Pos (0)
6949#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos)
6951#define CRPT_AES0_KEY0_KEY_Pos (0)
6952#define CRPT_AES0_KEY0_KEY_Msk (0xfffffffful << CRPT_AES0_KEY0_KEY_Pos)
6954#define CRPT_AES0_KEY1_KEY_Pos (0)
6955#define CRPT_AES0_KEY1_KEY_Msk (0xfffffffful << CRPT_AES0_KEY1_KEY_Pos)
6957#define CRPT_AES0_KEY2_KEY_Pos (0)
6958#define CRPT_AES0_KEY2_KEY_Msk (0xfffffffful << CRPT_AES0_KEY2_KEY_Pos)
6960#define CRPT_AES0_KEY3_KEY_Pos (0)
6961#define CRPT_AES0_KEY3_KEY_Msk (0xfffffffful << CRPT_AES0_KEY3_KEY_Pos)
6963#define CRPT_AES0_KEY4_KEY_Pos (0)
6964#define CRPT_AES0_KEY4_KEY_Msk (0xfffffffful << CRPT_AES0_KEY4_KEY_Pos)
6966#define CRPT_AES0_KEY5_KEY_Pos (0)
6967#define CRPT_AES0_KEY5_KEY_Msk (0xfffffffful << CRPT_AES0_KEY5_KEY_Pos)
6969#define CRPT_AES0_KEY6_KEY_Pos (0)
6970#define CRPT_AES0_KEY6_KEY_Msk (0xfffffffful << CRPT_AES0_KEY6_KEY_Pos)
6972#define CRPT_AES0_KEY7_KEY_Pos (0)
6973#define CRPT_AES0_KEY7_KEY_Msk (0xfffffffful << CRPT_AES0_KEY7_KEY_Pos)
6975#define CRPT_AES0_IV0_IV_Pos (0)
6976#define CRPT_AES0_IV0_IV_Msk (0xfffffffful << CRPT_AES0_IV0_IV_Pos)
6978#define CRPT_AES0_IV1_IV_Pos (0)
6979#define CRPT_AES0_IV1_IV_Msk (0xfffffffful << CRPT_AES0_IV1_IV_Pos)
6981#define CRPT_AES0_IV2_IV_Pos (0)
6982#define CRPT_AES0_IV2_IV_Msk (0xfffffffful << CRPT_AES0_IV2_IV_Pos)
6984#define CRPT_AES0_IV3_IV_Pos (0)
6985#define CRPT_AES0_IV3_IV_Msk (0xfffffffful << CRPT_AES0_IV3_IV_Pos)
6987#define CRPT_AES0_SADDR_SADDR_Pos (0)
6988#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos)
6990#define CRPT_AES0_DADDR_DADDR_Pos (0)
6991#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos)
6993#define CRPT_AES0_CNT_CNT_Pos (0)
6994#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos)
6996#define CRPT_AES1_KEY0_KEY_Pos (0)
6997#define CRPT_AES1_KEY0_KEY_Msk (0xfffffffful << CRPT_AES1_KEY0_KEY_Pos)
6999#define CRPT_AES1_KEY1_KEY_Pos (0)
7000#define CRPT_AES1_KEY1_KEY_Msk (0xfffffffful << CRPT_AES1_KEY1_KEY_Pos)
7002#define CRPT_AES1_KEY2_KEY_Pos (0)
7003#define CRPT_AES1_KEY2_KEY_Msk (0xfffffffful << CRPT_AES1_KEY2_KEY_Pos)
7005#define CRPT_AES1_KEY3_KEY_Pos (0)
7006#define CRPT_AES1_KEY3_KEY_Msk (0xfffffffful << CRPT_AES1_KEY3_KEY_Pos)
7008#define CRPT_AES1_KEY4_KEY_Pos (0)
7009#define CRPT_AES1_KEY4_KEY_Msk (0xfffffffful << CRPT_AES1_KEY4_KEY_Pos)
7011#define CRPT_AES1_KEY5_KEY_Pos (0)
7012#define CRPT_AES1_KEY5_KEY_Msk (0xfffffffful << CRPT_AES1_KEY5_KEY_Pos)
7014#define CRPT_AES1_KEY6_KEY_Pos (0)
7015#define CRPT_AES1_KEY6_KEY_Msk (0xfffffffful << CRPT_AES1_KEY6_KEY_Pos)
7017#define CRPT_AES1_KEY7_KEY_Pos (0)
7018#define CRPT_AES1_KEY7_KEY_Msk (0xfffffffful << CRPT_AES1_KEY7_KEY_Pos)
7020#define CRPT_AES1_IV0_IV_Pos (0)
7021#define CRPT_AES1_IV0_IV_Msk (0xfffffffful << CRPT_AES1_IV0_IV_Pos)
7023#define CRPT_AES1_IV1_IV_Pos (0)
7024#define CRPT_AES1_IV1_IV_Msk (0xfffffffful << CRPT_AES1_IV1_IV_Pos)
7026#define CRPT_AES1_IV2_IV_Pos (0)
7027#define CRPT_AES1_IV2_IV_Msk (0xfffffffful << CRPT_AES1_IV2_IV_Pos)
7029#define CRPT_AES1_IV3_IV_Pos (0)
7030#define CRPT_AES1_IV3_IV_Msk (0xfffffffful << CRPT_AES1_IV3_IV_Pos)
7032#define CRPT_AES1_SADDR_SADDR_Pos (0)
7033#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos)
7035#define CRPT_AES1_DADDR_DADDR_Pos (0)
7036#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos)
7038#define CRPT_AES1_CNT_CNT_Pos (0)
7039#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos)
7041#define CRPT_AES2_KEY0_KEY_Pos (0)
7042#define CRPT_AES2_KEY0_KEY_Msk (0xfffffffful << CRPT_AES2_KEY0_KEY_Pos)
7044#define CRPT_AES2_KEY1_KEY_Pos (0)
7045#define CRPT_AES2_KEY1_KEY_Msk (0xfffffffful << CRPT_AES2_KEY1_KEY_Pos)
7047#define CRPT_AES2_KEY2_KEY_Pos (0)
7048#define CRPT_AES2_KEY2_KEY_Msk (0xfffffffful << CRPT_AES2_KEY2_KEY_Pos)
7050#define CRPT_AES2_KEY3_KEY_Pos (0)
7051#define CRPT_AES2_KEY3_KEY_Msk (0xfffffffful << CRPT_AES2_KEY3_KEY_Pos)
7053#define CRPT_AES2_KEY4_KEY_Pos (0)
7054#define CRPT_AES2_KEY4_KEY_Msk (0xfffffffful << CRPT_AES2_KEY4_KEY_Pos)
7056#define CRPT_AES2_KEY5_KEY_Pos (0)
7057#define CRPT_AES2_KEY5_KEY_Msk (0xfffffffful << CRPT_AES2_KEY5_KEY_Pos)
7059#define CRPT_AES2_KEY6_KEY_Pos (0)
7060#define CRPT_AES2_KEY6_KEY_Msk (0xfffffffful << CRPT_AES2_KEY6_KEY_Pos)
7062#define CRPT_AES2_KEY7_KEY_Pos (0)
7063#define CRPT_AES2_KEY7_KEY_Msk (0xfffffffful << CRPT_AES2_KEY7_KEY_Pos)
7065#define CRPT_AES2_IV0_IV_Pos (0)
7066#define CRPT_AES2_IV0_IV_Msk (0xfffffffful << CRPT_AES2_IV0_IV_Pos)
7068#define CRPT_AES2_IV1_IV_Pos (0)
7069#define CRPT_AES2_IV1_IV_Msk (0xfffffffful << CRPT_AES2_IV1_IV_Pos)
7071#define CRPT_AES2_IV2_IV_Pos (0)
7072#define CRPT_AES2_IV2_IV_Msk (0xfffffffful << CRPT_AES2_IV2_IV_Pos)
7074#define CRPT_AES2_IV3_IV_Pos (0)
7075#define CRPT_AES2_IV3_IV_Msk (0xfffffffful << CRPT_AES2_IV3_IV_Pos)
7077#define CRPT_AES2_SADDR_SADDR_Pos (0)
7078#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos)
7080#define CRPT_AES2_DADDR_DADDR_Pos (0)
7081#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos)
7083#define CRPT_AES2_CNT_CNT_Pos (0)
7084#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos)
7086#define CRPT_AES3_KEY0_KEY_Pos (0)
7087#define CRPT_AES3_KEY0_KEY_Msk (0xfffffffful << CRPT_AES3_KEY0_KEY_Pos)
7089#define CRPT_AES3_KEY1_KEY_Pos (0)
7090#define CRPT_AES3_KEY1_KEY_Msk (0xfffffffful << CRPT_AES3_KEY1_KEY_Pos)
7092#define CRPT_AES3_KEY2_KEY_Pos (0)
7093#define CRPT_AES3_KEY2_KEY_Msk (0xfffffffful << CRPT_AES3_KEY2_KEY_Pos)
7095#define CRPT_AES3_KEY3_KEY_Pos (0)
7096#define CRPT_AES3_KEY3_KEY_Msk (0xfffffffful << CRPT_AES3_KEY3_KEY_Pos)
7098#define CRPT_AES3_KEY4_KEY_Pos (0)
7099#define CRPT_AES3_KEY4_KEY_Msk (0xfffffffful << CRPT_AES3_KEY4_KEY_Pos)
7101#define CRPT_AES3_KEY5_KEY_Pos (0)
7102#define CRPT_AES3_KEY5_KEY_Msk (0xfffffffful << CRPT_AES3_KEY5_KEY_Pos)
7104#define CRPT_AES3_KEY6_KEY_Pos (0)
7105#define CRPT_AES3_KEY6_KEY_Msk (0xfffffffful << CRPT_AES3_KEY6_KEY_Pos)
7107#define CRPT_AES3_KEY7_KEY_Pos (0)
7108#define CRPT_AES3_KEY7_KEY_Msk (0xfffffffful << CRPT_AES3_KEY7_KEY_Pos)
7110#define CRPT_AES3_IV0_IV_Pos (0)
7111#define CRPT_AES3_IV0_IV_Msk (0xfffffffful << CRPT_AES3_IV0_IV_Pos)
7113#define CRPT_AES3_IV1_IV_Pos (0)
7114#define CRPT_AES3_IV1_IV_Msk (0xfffffffful << CRPT_AES3_IV1_IV_Pos)
7116#define CRPT_AES3_IV2_IV_Pos (0)
7117#define CRPT_AES3_IV2_IV_Msk (0xfffffffful << CRPT_AES3_IV2_IV_Pos)
7119#define CRPT_AES3_IV3_IV_Pos (0)
7120#define CRPT_AES3_IV3_IV_Msk (0xfffffffful << CRPT_AES3_IV3_IV_Pos)
7122#define CRPT_AES3_SADDR_SADDR_Pos (0)
7123#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos)
7125#define CRPT_AES3_DADDR_DADDR_Pos (0)
7126#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos)
7128#define CRPT_AES3_CNT_CNT_Pos (0)
7129#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos)
7131#define CRPT_TDES_CTL_START_Pos (0)
7132#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos)
7134#define CRPT_TDES_CTL_STOP_Pos (1)
7135#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos)
7137#define CRPT_TDES_CTL_TMODE_Pos (2)
7138#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos)
7140#define CRPT_TDES_CTL_3KEYS_Pos (3)
7141#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos)
7143#define CRPT_TDES_CTL_DMALAST_Pos (5)
7144#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos)
7146#define CRPT_TDES_CTL_DMACSCAD_Pos (6)
7147#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos)
7149#define CRPT_TDES_CTL_DMAEN_Pos (7)
7150#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos)
7152#define CRPT_TDES_CTL_OPMODE_Pos (8)
7153#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos)
7155#define CRPT_TDES_CTL_ENCRPT_Pos (16)
7156#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos)
7158#define CRPT_TDES_CTL_BLKSWAP_Pos (21)
7159#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos)
7161#define CRPT_TDES_CTL_OUTSWAP_Pos (22)
7162#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos)
7164#define CRPT_TDES_CTL_INSWAP_Pos (23)
7165#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos)
7167#define CRPT_TDES_CTL_CHANNEL_Pos (24)
7168#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos)
7170#define CRPT_TDES_CTL_KEYUNPRT_Pos (26)
7171#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos)
7173#define CRPT_TDES_CTL_KEYPRT_Pos (31)
7174#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos)
7176#define CRPT_TDES_STS_BUSY_Pos (0)
7177#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos)
7179#define CRPT_TDES_STS_INBUFEMPTY_Pos (8)
7180#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos)
7182#define CRPT_TDES_STS_INBUFFULL_Pos (9)
7183#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos)
7185#define CRPT_TDES_STS_INBUFERR_Pos (10)
7186#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos)
7188#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16)
7189#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos)
7191#define CRPT_TDES_STS_OUTBUFFULL_Pos (17)
7192#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos)
7194#define CRPT_TDES_STS_OUTBUFERR_Pos (18)
7195#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos)
7197#define CRPT_TDES_STS_BUSERR_Pos (20)
7198#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos)
7200#define CRPT_TDES0_KEY1H_KEY_Pos (0)
7201#define CRPT_TDES0_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1H_KEY_Pos)
7203#define CRPT_TDES0_KEY1L_KEY_Pos (0)
7204#define CRPT_TDES0_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1L_KEY_Pos)
7206#define CRPT_TDES0_KEY2H_KEY_Pos (0)
7207#define CRPT_TDES0_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2H_KEY_Pos)
7209#define CRPT_TDES0_KEY2L_KEY_Pos (0)
7210#define CRPT_TDES0_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2L_KEY_Pos)
7212#define CRPT_TDES0_KEY3H_KEY_Pos (0)
7213#define CRPT_TDES0_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3H_KEY_Pos)
7215#define CRPT_TDES0_KEY3L_KEY_Pos (0)
7216#define CRPT_TDES0_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3L_KEY_Pos)
7218#define CRPT_TDES0_IVH_IV_Pos (0)
7219#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos)
7221#define CRPT_TDES0_IVL_IV_Pos (0)
7222#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos)
7224#define CRPT_TDES0_SADDR_SADDR_Pos (0)
7225#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos)
7227#define CRPT_TDES0_DADDR_DADDR_Pos (0)
7228#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos)
7230#define CRPT_TDES0_CNT_CNT_Pos (0)
7231#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos)
7233#define CRPT_TDES_DATIN_DATIN_Pos (0)
7234#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos)
7236#define CRPT_TDES_DATOUT_DATOUT_Pos (0)
7237#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos)
7239#define CRPT_TDES1_KEY1H_KEY_Pos (0)
7240#define CRPT_TDES1_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1H_KEY_Pos)
7242#define CRPT_TDES1_KEY1L_KEYL_Pos (0)
7243#define CRPT_TDES1_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos)
7245#define CRPT_TDES1_KEY2H_KEY_Pos (0)
7246#define CRPT_TDES1_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2H_KEY_Pos)
7248#define CRPT_TDES1_KEY2L_KEY_Pos (0)
7249#define CRPT_TDES1_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2L_KEY_Pos)
7251#define CRPT_TDES1_KEY3H_KEY_Pos (0)
7252#define CRPT_TDES1_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3H_KEY_Pos)
7254#define CRPT_TDES1_KEY3L_KEY_Pos (0)
7255#define CRPT_TDES1_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3L_KEY_Pos)
7257#define CRPT_TDES1_IVH_IV_Pos (0)
7258#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos)
7260#define CRPT_TDES1_IVL_IV_Pos (0)
7261#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos)
7263#define CRPT_TDES1_SADDR_SADDR_Pos (0)
7264#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos)
7266#define CRPT_TDES1_DADDR_DADDR_Pos (0)
7267#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos)
7269#define CRPT_TDES1_CNT_CNT_Pos (0)
7270#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos)
7272#define CRPT_TDES2_KEY1H_KEY_Pos (0)
7273#define CRPT_TDES2_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1H_KEY_Pos)
7275#define CRPT_TDES2_KEY1L_KEY_Pos (0)
7276#define CRPT_TDES2_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1L_KEY_Pos)
7278#define CRPT_TDES2_KEY2H_KEY_Pos (0)
7279#define CRPT_TDES2_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2H_KEY_Pos)
7281#define CRPT_TDES2_KEY2L_KEY_Pos (0)
7282#define CRPT_TDES2_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2L_KEY_Pos)
7284#define CRPT_TDES2_KEY3H_KEY_Pos (0)
7285#define CRPT_TDES2_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3H_KEY_Pos)
7287#define CRPT_TDES2_KEY3L_KEY_Pos (0)
7288#define CRPT_TDES2_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3L_KEY_Pos)
7290#define CRPT_TDES2_IVH_IV_Pos (0)
7291#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos)
7293#define CRPT_TDES2_IVL_IV_Pos (0)
7294#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos)
7296#define CRPT_TDES2_SADDR_SADDR_Pos (0)
7297#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos)
7299#define CRPT_TDES2_DADDR_DADDR_Pos (0)
7300#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos)
7302#define CRPT_TDES2_CNT_CNT_Pos (0)
7303#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos)
7305#define CRPT_TDES3_KEY1H_KEY_Pos (0)
7306#define CRPT_TDES3_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1H_KEY_Pos)
7308#define CRPT_TDES3_KEY1L_KEY_Pos (0)
7309#define CRPT_TDES3_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1L_KEY_Pos)
7311#define CRPT_TDES3_KEY2H_KEY_Pos (0)
7312#define CRPT_TDES3_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2H_KEY_Pos)
7314#define CRPT_TDES3_KEY2L_KEY_Pos (0)
7315#define CRPT_TDES3_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2L_KEY_Pos)
7317#define CRPT_TDES3_KEY3H_KEY_Pos (0)
7318#define CRPT_TDES3_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3H_KEY_Pos)
7320#define CRPT_TDES3_KEY3L_KEY_Pos (0)
7321#define CRPT_TDES3_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3L_KEY_Pos)
7323#define CRPT_TDES3_IVH_IV_Pos (0)
7324#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos)
7326#define CRPT_TDES3_IVL_IV_Pos (0)
7327#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos)
7329#define CRPT_TDES3_SADDR_SADDR_Pos (0)
7330#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos)
7332#define CRPT_TDES3_DADDR_DADDR_Pos (0)
7333#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos)
7335#define CRPT_TDES3_CNT_CNT_Pos (0)
7336#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos)
7338#define CRPT_SHA_CTL_START_Pos (0)
7339#define CRPT_SHA_CTL_START_Msk (0x1ul << CRPT_SHA_CTL_START_Pos)
7341#define CRPT_SHA_CTL_STOP_Pos (1)
7342#define CRPT_SHA_CTL_STOP_Msk (0x1ul << CRPT_SHA_CTL_STOP_Pos)
7344#define CRPT_SHA_CTL_DMALAST_Pos (5)
7345#define CRPT_SHA_CTL_DMALAST_Msk (0x1ul << CRPT_SHA_CTL_DMALAST_Pos)
7347#define CRPT_SHA_CTL_DMAEN_Pos (7)
7348#define CRPT_SHA_CTL_DMAEN_Msk (0x1ul << CRPT_SHA_CTL_DMAEN_Pos)
7350#define CRPT_SHA_CTL_OPMODE_Pos (8)
7351#define CRPT_SHA_CTL_OPMODE_Msk (0x7ul << CRPT_SHA_CTL_OPMODE_Pos)
7353#define CRPT_SHA_CTL_OUTSWAP_Pos (22)
7354#define CRPT_SHA_CTL_OUTSWAP_Msk (0x1ul << CRPT_SHA_CTL_OUTSWAP_Pos)
7356#define CRPT_SHA_CTL_INSWAP_Pos (23)
7357#define CRPT_SHA_CTL_INSWAP_Msk (0x1ul << CRPT_SHA_CTL_INSWAP_Pos)
7359#define CRPT_SHA_STS_BUSY_Pos (0)
7360#define CRPT_SHA_STS_BUSY_Msk (0x1ul << CRPT_SHA_STS_BUSY_Pos)
7362#define CRPT_SHA_STS_DMABUSY_Pos (1)
7363#define CRPT_SHA_STS_DMABUSY_Msk (0x1ul << CRPT_SHA_STS_DMABUSY_Pos)
7365#define CRPT_SHA_STS_DMAERR_Pos (8)
7366#define CRPT_SHA_STS_DMAERR_Msk (0x1ul << CRPT_SHA_STS_DMAERR_Pos)
7368#define CRPT_SHA_STS_DATINREQ_Pos (16)
7369#define CRPT_SHA_STS_DATINREQ_Msk (0x1ul << CRPT_SHA_STS_DATINREQ_Pos)
7371#define CRPT_SHA_DGST0_DGST_Pos (0)
7372#define CRPT_SHA_DGST0_DGST_Msk (0xfffffffful << CRPT_SHA_DGST0_DGST_Pos)
7374#define CRPT_SHA_DGST1_DGST_Pos (0)
7375#define CRPT_SHA_DGST1_DGST_Msk (0xfffffffful << CRPT_SHA_DGST1_DGST_Pos)
7377#define CRPT_SHA_DGST2_DGST_Pos (0)
7378#define CRPT_SHA_DGST2_DGST_Msk (0xfffffffful << CRPT_SHA_DGST2_DGST_Pos)
7380#define CRPT_SHA_DGST3_DGST_Pos (0)
7381#define CRPT_SHA_DGST3_DGST_Msk (0xfffffffful << CRPT_SHA_DGST3_DGST_Pos)
7383#define CRPT_SHA_DGST4_DGST_Pos (0)
7384#define CRPT_SHA_DGST4_DGST_Msk (0xfffffffful << CRPT_SHA_DGST4_DGST_Pos)
7386#define CRPT_SHA_DGST5_DGST_Pos (0)
7387#define CRPT_SHA_DGST5_DGST_Msk (0xfffffffful << CRPT_SHA_DGST5_DGST_Pos)
7389#define CRPT_SHA_DGST6_DGST_Pos (0)
7390#define CRPT_SHA_DGST6_DGST_Msk (0xfffffffful << CRPT_SHA_DGST6_DGST_Pos)
7392#define CRPT_SHA_DGST7_DGST_Pos (0)
7393#define CRPT_SHA_DGST7_DGST_Msk (0xfffffffful << CRPT_SHA_DGST7_DGST_Pos)
7395#define CRPT_SHA_KEYCNT_KEYCNT_Pos (0)
7396#define CRPT_SHA_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_SHA_KEYCNT_KEYCNT_Pos)
7398#define CRPT_SHA_SADDR_SADDR_Pos (0)
7399#define CRPT_SHA_SADDR_SADDR_Msk (0xfffffffful << CRPT_SHA_SADDR_SADDR_Pos)
7401#define CRPT_SHA_DMACNT_DMACNT_Pos (0)
7402#define CRPT_SHA_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_SHA_DMACNT_DMACNT_Pos)
7404#define CRPT_SHA_DATIN_DATIN_Pos (0)
7405#define CRPT_SHA_DATIN_DATIN_Msk (0xfffffffful << CRPT_SHA_DATIN_DATIN_Pos) /* CRPT_CONST */ /* end of CRPT register group */
7409
7410
7411/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
7417 typedef struct {
7418
7419
7439 __I uint32_t AD0DAT0;
7440
7460 __I uint32_t AD0DAT1;
7461
7481 __I uint32_t AD0DAT2;
7482
7502 __I uint32_t AD0DAT3;
7503
7523 __I uint32_t AD0DAT4;
7524
7544 __I uint32_t AD0DAT5;
7545
7565 __I uint32_t AD0DAT6;
7566
7586 __I uint32_t AD0DAT7;
7587
7607 __I uint32_t AD1DAT0;
7608
7628 __I uint32_t AD1DAT1;
7629
7649 __I uint32_t AD1DAT2;
7650
7670 __I uint32_t AD1DAT3;
7671
7691 __I uint32_t AD1DAT4;
7692
7712 __I uint32_t AD1DAT5;
7713
7733 __I uint32_t AD1DAT6;
7734
7754 __I uint32_t AD1DAT7;
7755
7793 __IO uint32_t CTL;
7795 uint32_t RESERVE0[1];
7797
7798
7815 __O uint32_t SWTRG;
7816
7835 __I uint32_t PENDSTS;
7836
7861 __IO uint32_t ADIFOV;
7862
7883 __IO uint32_t OVSTS;
7884
7940 __IO uint32_t AD0SPCTL0;
7941
7997 __IO uint32_t AD0SPCTL1;
7998
8054 __IO uint32_t AD0SPCTL2;
8055
8111 __IO uint32_t AD0SPCTL3;
8112
8152 __IO uint32_t AD0SPCTL4;
8153
8193 __IO uint32_t AD0SPCTL5;
8194
8234 __IO uint32_t AD0SPCTL6;
8235
8275 __IO uint32_t AD0SPCTL7;
8276
8332 __IO uint32_t AD1SPCTL0;
8333
8389 __IO uint32_t AD1SPCTL1;
8390
8446 __IO uint32_t AD1SPCTL2;
8447
8503 __IO uint32_t AD1SPCTL3;
8504
8544 __IO uint32_t AD1SPCTL4;
8545
8585 __IO uint32_t AD1SPCTL5;
8586
8626 __IO uint32_t AD1SPCTL6;
8627
8667 __IO uint32_t AD1SPCTL7;
8669 uint32_t RESERVE1[3];
8671
8672
8713 __IO uint32_t SIMUSEL;
8714
8751 __IO uint32_t CMP[2];
8752
8773 __I uint32_t STATUS0;
8774
8874 __IO uint32_t STATUS1;
8875
8890 __IO uint32_t EXTSMPT;
8892 uint32_t RESERVE2[17];
8894
8895
8910 __I uint32_t AD0DDAT0;
8911
8926 __I uint32_t AD0DDAT1;
8927
8942 __I uint32_t AD0DDAT2;
8943
8958 __I uint32_t AD0DDAT3;
8960 uint32_t RESERVE3[4];
8962
8963
8978 __I uint32_t AD1DDAT0;
8979
8994 __I uint32_t AD1DDAT1;
8995
9010 __I uint32_t AD1DDAT2;
9011
9026 __I uint32_t AD1DDAT3;
9027
9060 __IO uint32_t DBMEN;
9061
9118 __IO uint32_t INTSRC[4];
9119
9224 __IO uint32_t AD0TRGEN0;
9225
9330 __IO uint32_t AD0TRGEN1;
9331
9436 __IO uint32_t AD0TRGEN2;
9437
9542 __IO uint32_t AD0TRGEN3;
9543
9648 __IO uint32_t AD1TRGEN0;
9649
9754 __IO uint32_t AD1TRGEN1;
9755
9860 __IO uint32_t AD1TRGEN2;
9861
9966 __IO uint32_t AD1TRGEN3;
9967
9968} EADC_T;
9969
9975#define EADC_AD0DAT0_RESULT_Pos (0)
9976#define EADC_AD0DAT0_RESULT_Msk (0xffful << EADC_AD0DAT0_RESULT_Pos)
9978#define EADC_AD0DAT0_OV_Pos (16)
9979#define EADC_AD0DAT0_OV_Msk (0x1ul << EADC_AD0DAT0_OV_Pos)
9981#define EADC_AD0DAT0_VALID_Pos (17)
9982#define EADC_AD0DAT0_VALID_Msk (0x1ul << EADC_AD0DAT0_VALID_Pos)
9984#define EADC_AD0DAT1_RESULT_Pos (0)
9985#define EADC_AD0DAT1_RESULT_Msk (0xffful << EADC_AD0DAT1_RESULT_Pos)
9987#define EADC_AD0DAT1_OV_Pos (16)
9988#define EADC_AD0DAT1_OV_Msk (0x1ul << EADC_AD0DAT1_OV_Pos)
9990#define EADC_AD0DAT1_VALID_Pos (17)
9991#define EADC_AD0DAT1_VALID_Msk (0x1ul << EADC_AD0DAT1_VALID_Pos)
9993#define EADC_AD0DAT2_RESULT_Pos (0)
9994#define EADC_AD0DAT2_RESULT_Msk (0xffful << EADC_AD0DAT2_RESULT_Pos)
9996#define EADC_AD0DAT2_OV_Pos (16)
9997#define EADC_AD0DAT2_OV_Msk (0x1ul << EADC_AD0DAT2_OV_Pos)
9999#define EADC_AD0DAT2_VALID_Pos (17)
10000#define EADC_AD0DAT2_VALID_Msk (0x1ul << EADC_AD0DAT2_VALID_Pos)
10002#define EADC_AD0DAT3_RESULT_Pos (0)
10003#define EADC_AD0DAT3_RESULT_Msk (0xffful << EADC_AD0DAT3_RESULT_Pos)
10005#define EADC_AD0DAT3_OV_Pos (16)
10006#define EADC_AD0DAT3_OV_Msk (0x1ul << EADC_AD0DAT3_OV_Pos)
10008#define EADC_AD0DAT3_VALID_Pos (17)
10009#define EADC_AD0DAT3_VALID_Msk (0x1ul << EADC_AD0DAT3_VALID_Pos)
10011#define EADC_AD0DAT4_RESULT_Pos (0)
10012#define EADC_AD0DAT4_RESULT_Msk (0xffful << EADC_AD0DAT4_RESULT_Pos)
10014#define EADC_AD0DAT4_OV_Pos (16)
10015#define EADC_AD0DAT4_OV_Msk (0x1ul << EADC_AD0DAT4_OV_Pos)
10017#define EADC_AD0DAT4_VALID_Pos (17)
10018#define EADC_AD0DAT4_VALID_Msk (0x1ul << EADC_AD0DAT4_VALID_Pos)
10020#define EADC_AD0DAT5_RESULT_Pos (0)
10021#define EADC_AD0DAT5_RESULT_Msk (0xffful << EADC_AD0DAT5_RESULT_Pos)
10023#define EADC_AD0DAT5_OV_Pos (16)
10024#define EADC_AD0DAT5_OV_Msk (0x1ul << EADC_AD0DAT5_OV_Pos)
10026#define EADC_AD0DAT5_VALID_Pos (17)
10027#define EADC_AD0DAT5_VALID_Msk (0x1ul << EADC_AD0DAT5_VALID_Pos)
10029#define EADC_AD0DAT6_RESULT_Pos (0)
10030#define EADC_AD0DAT6_RESULT_Msk (0xffful << EADC_AD0DAT6_RESULT_Pos)
10032#define EADC_AD0DAT6_OV_Pos (16)
10033#define EADC_AD0DAT6_OV_Msk (0x1ul << EADC_AD0DAT6_OV_Pos)
10035#define EADC_AD0DAT6_VALID_Pos (17)
10036#define EADC_AD0DAT6_VALID_Msk (0x1ul << EADC_AD0DAT6_VALID_Pos)
10038#define EADC_AD0DAT7_RESULT_Pos (0)
10039#define EADC_AD0DAT7_RESULT_Msk (0xffful << EADC_AD0DAT7_RESULT_Pos)
10041#define EADC_AD0DAT7_OV_Pos (16)
10042#define EADC_AD0DAT7_OV_Msk (0x1ul << EADC_AD0DAT7_OV_Pos)
10044#define EADC_AD0DAT7_VALID_Pos (17)
10045#define EADC_AD0DAT7_VALID_Msk (0x1ul << EADC_AD0DAT7_VALID_Pos)
10047#define EADC_AD1DAT0_RESULT_Pos (0)
10048#define EADC_AD1DAT0_RESULT_Msk (0xffful << EADC_AD1DAT0_RESULT_Pos)
10050#define EADC_AD1DAT0_OV_Pos (16)
10051#define EADC_AD1DAT0_OV_Msk (0x1ul << EADC_AD1DAT0_OV_Pos)
10053#define EADC_AD1DAT0_VALID_Pos (17)
10054#define EADC_AD1DAT0_VALID_Msk (0x1ul << EADC_AD1DAT0_VALID_Pos)
10056#define EADC_AD1DAT1_RESULT_Pos (0)
10057#define EADC_AD1DAT1_RESULT_Msk (0xffful << EADC_AD1DAT1_RESULT_Pos)
10059#define EADC_AD1DAT1_OV_Pos (16)
10060#define EADC_AD1DAT1_OV_Msk (0x1ul << EADC_AD1DAT1_OV_Pos)
10062#define EADC_AD1DAT1_VALID_Pos (17)
10063#define EADC_AD1DAT1_VALID_Msk (0x1ul << EADC_AD1DAT1_VALID_Pos)
10065#define EADC_AD1DAT2_RESULT_Pos (0)
10066#define EADC_AD1DAT2_RESULT_Msk (0xffful << EADC_AD1DAT2_RESULT_Pos)
10068#define EADC_AD1DAT2_OV_Pos (16)
10069#define EADC_AD1DAT2_OV_Msk (0x1ul << EADC_AD1DAT2_OV_Pos)
10071#define EADC_AD1DAT2_VALID_Pos (17)
10072#define EADC_AD1DAT2_VALID_Msk (0x1ul << EADC_AD1DAT2_VALID_Pos)
10074#define EADC_AD1DAT3_RESULT_Pos (0)
10075#define EADC_AD1DAT3_RESULT_Msk (0xffful << EADC_AD1DAT3_RESULT_Pos)
10077#define EADC_AD1DAT3_OV_Pos (16)
10078#define EADC_AD1DAT3_OV_Msk (0x1ul << EADC_AD1DAT3_OV_Pos)
10080#define EADC_AD1DAT3_VALID_Pos (17)
10081#define EADC_AD1DAT3_VALID_Msk (0x1ul << EADC_AD1DAT3_VALID_Pos)
10083#define EADC_AD1DAT4_RESULT_Pos (0)
10084#define EADC_AD1DAT4_RESULT_Msk (0xffful << EADC_AD1DAT4_RESULT_Pos)
10086#define EADC_AD1DAT4_OV_Pos (16)
10087#define EADC_AD1DAT4_OV_Msk (0x1ul << EADC_AD1DAT4_OV_Pos)
10089#define EADC_AD1DAT4_VALID_Pos (17)
10090#define EADC_AD1DAT4_VALID_Msk (0x1ul << EADC_AD1DAT4_VALID_Pos)
10092#define EADC_AD1DAT5_RESULT_Pos (0)
10093#define EADC_AD1DAT5_RESULT_Msk (0xffful << EADC_AD1DAT5_RESULT_Pos)
10095#define EADC_AD1DAT5_OV_Pos (16)
10096#define EADC_AD1DAT5_OV_Msk (0x1ul << EADC_AD1DAT5_OV_Pos)
10098#define EADC_AD1DAT5_VALID_Pos (17)
10099#define EADC_AD1DAT5_VALID_Msk (0x1ul << EADC_AD1DAT5_VALID_Pos)
10101#define EADC_AD1DAT6_RESULT_Pos (0)
10102#define EADC_AD1DAT6_RESULT_Msk (0xffful << EADC_AD1DAT6_RESULT_Pos)
10104#define EADC_AD1DAT6_OV_Pos (16)
10105#define EADC_AD1DAT6_OV_Msk (0x1ul << EADC_AD1DAT6_OV_Pos)
10107#define EADC_AD1DAT6_VALID_Pos (17)
10108#define EADC_AD1DAT6_VALID_Msk (0x1ul << EADC_AD1DAT6_VALID_Pos)
10110#define EADC_AD1DAT7_RESULT_Pos (0)
10111#define EADC_AD1DAT7_RESULT_Msk (0xffful << EADC_AD1DAT7_RESULT_Pos)
10113#define EADC_AD1DAT7_OV_Pos (16)
10114#define EADC_AD1DAT7_OV_Msk (0x1ul << EADC_AD1DAT7_OV_Pos)
10116#define EADC_AD1DAT7_VALID_Pos (17)
10117#define EADC_AD1DAT7_VALID_Msk (0x1ul << EADC_AD1DAT7_VALID_Pos)
10119#define EADC_CTL_ADCEN_Pos (0)
10120#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos)
10122#define EADC_CTL_ADCRST_Pos (1)
10123#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos)
10125#define EADC_CTL_ADCIEN0_Pos (2)
10126#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos)
10128#define EADC_CTL_ADCIEN1_Pos (3)
10129#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos)
10131#define EADC_CTL_ADCIEN2_Pos (4)
10132#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos)
10134#define EADC_CTL_ADCIEN3_Pos (5)
10135#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos)
10137#define EADC_SWTRG_SWTRG7_0_Pos (0)
10138#define EADC_SWTRG_SWTRG7_0_Msk (0xfful << EADC_SWTRG_SWTRG7_0_Pos)
10140#define EADC_SWTRG_SWTRG15_8_Pos (8)
10141#define EADC_SWTRG_SWTRG15_8_Msk (0xfful << EADC_SWTRG_SWTRG15_8_Pos)
10143#define EADC_PENDSTS_STPF7_0_Pos (0)
10144#define EADC_PENDSTS_STPF7_0_Msk (0xfful << EADC_PENDSTS_STPF7_0_Pos)
10146#define EADC_PENDSTS_STPF15_8_Pos (8)
10147#define EADC_PENDSTS_STPF15_8_Msk (0xfful << EADC_PENDSTS_STPF15_8_Pos)
10149#define EADC_ADIFOV_ADFOV0_Pos (0)
10150#define EADC_ADIFOV_ADFOV0_Msk (0x1ul << EADC_ADIFOV_ADFOV0_Pos)
10152#define EADC_ADIFOV_ADFOV1_Pos (1)
10153#define EADC_ADIFOV_ADFOV1_Msk (0x1ul << EADC_ADIFOV_ADFOV1_Pos)
10155#define EADC_ADIFOV_ADFOV2_Pos (2)
10156#define EADC_ADIFOV_ADFOV2_Msk (0x1ul << EADC_ADIFOV_ADFOV2_Pos)
10158#define EADC_ADIFOV_ADFOV3_Pos (3)
10159#define EADC_ADIFOV_ADFOV3_Msk (0x1ul << EADC_ADIFOV_ADFOV3_Pos)
10161#define EADC_OVSTS_SPOVF7_0_Pos (0)
10162#define EADC_OVSTS_SPOVF7_0_Msk (0xfful << EADC_OVSTS_SPOVF7_0_Pos)
10164#define EADC_OVSTS_SPOVF15_8_Pos (8)
10165#define EADC_OVSTS_SPOVF15_8_Msk (0xfful << EADC_OVSTS_SPOVF15_8_Pos)
10167#define EADC_AD0SPCTL0_CHSEL_Pos (0)
10168#define EADC_AD0SPCTL0_CHSEL_Msk (0xful << EADC_AD0SPCTL0_CHSEL_Pos)
10170#define EADC_AD0SPCTL0_TRGSEL_Pos (4)
10171#define EADC_AD0SPCTL0_TRGSEL_Msk (0xful << EADC_AD0SPCTL0_TRGSEL_Pos)
10173#define EADC_AD0SPCTL0_TRGDLYCNT_Pos (8)
10174#define EADC_AD0SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL0_TRGDLYCNT_Pos)
10176#define EADC_AD0SPCTL0_TRGDLYDIV_Pos (16)
10177#define EADC_AD0SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL0_TRGDLYDIV_Pos)
10179#define EADC_AD0SPCTL0_EXTREN_Pos (20)
10180#define EADC_AD0SPCTL0_EXTREN_Msk (0x1ul << EADC_AD0SPCTL0_EXTREN_Pos)
10182#define EADC_AD0SPCTL0_EXTFEN_Pos (21)
10183#define EADC_AD0SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL0_EXTFEN_Pos)
10185#define EADC_AD0SPCTL1_CHSEL_Pos (0)
10186#define EADC_AD0SPCTL1_CHSEL_Msk (0xful << EADC_AD0SPCTL1_CHSEL_Pos)
10188#define EADC_AD0SPCTL1_TRGSEL_Pos (4)
10189#define EADC_AD0SPCTL1_TRGSEL_Msk (0xful << EADC_AD0SPCTL1_TRGSEL_Pos)
10191#define EADC_AD0SPCTL1_TRGDLYCNT_Pos (8)
10192#define EADC_AD0SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL1_TRGDLYCNT_Pos)
10194#define EADC_AD0SPCTL1_TRGDLYDIV_Pos (16)
10195#define EADC_AD0SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL1_TRGDLYDIV_Pos)
10197#define EADC_AD0SPCTL1_EXTREN_Pos (20)
10198#define EADC_AD0SPCTL1_EXTREN_Msk (0x1ul << EADC_AD0SPCTL1_EXTREN_Pos)
10200#define EADC_AD0SPCTL1_EXTFEN_Pos (21)
10201#define EADC_AD0SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL1_EXTFEN_Pos)
10203#define EADC_AD0SPCTL2_CHSEL_Pos (0)
10204#define EADC_AD0SPCTL2_CHSEL_Msk (0xful << EADC_AD0SPCTL2_CHSEL_Pos)
10206#define EADC_AD0SPCTL2_TRGSEL_Pos (4)
10207#define EADC_AD0SPCTL2_TRGSEL_Msk (0xful << EADC_AD0SPCTL2_TRGSEL_Pos)
10209#define EADC_AD0SPCTL2_TRGDLYCNT_Pos (8)
10210#define EADC_AD0SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL2_TRGDLYCNT_Pos)
10212#define EADC_AD0SPCTL2_TRGDLYDIV_Pos (16)
10213#define EADC_AD0SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL2_TRGDLYDIV_Pos)
10215#define EADC_AD0SPCTL2_EXTREN_Pos (20)
10216#define EADC_AD0SPCTL2_EXTREN_Msk (0x1ul << EADC_AD0SPCTL2_EXTREN_Pos)
10218#define EADC_AD0SPCTL2_EXTFEN_Pos (21)
10219#define EADC_AD0SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL2_EXTFEN_Pos)
10221#define EADC_AD0SPCTL3_CHSEL_Pos (0)
10222#define EADC_AD0SPCTL3_CHSEL_Msk (0xful << EADC_AD0SPCTL3_CHSEL_Pos)
10224#define EADC_AD0SPCTL3_TRGSEL_Pos (4)
10225#define EADC_AD0SPCTL3_TRGSEL_Msk (0xful << EADC_AD0SPCTL3_TRGSEL_Pos)
10227#define EADC_AD0SPCTL3_TRGDLYCNT_Pos (8)
10228#define EADC_AD0SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL3_TRGDLYCNT_Pos)
10230#define EADC_AD0SPCTL3_TRGDLYDIV_Pos (16)
10231#define EADC_AD0SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL3_TRGDLYDIV_Pos)
10233#define EADC_AD0SPCTL3_EXTREN_Pos (20)
10234#define EADC_AD0SPCTL3_EXTREN_Msk (0x1ul << EADC_AD0SPCTL3_EXTREN_Pos)
10236#define EADC_AD0SPCTL3_EXTFEN_Pos (21)
10237#define EADC_AD0SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL3_EXTFEN_Pos)
10239#define EADC_AD0SPCTL4_CHSEL_Pos (0)
10240#define EADC_AD0SPCTL4_CHSEL_Msk (0xful << EADC_AD0SPCTL4_CHSEL_Pos)
10242#define EADC_AD0SPCTL4_TRGSEL_Pos (4)
10243#define EADC_AD0SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL4_TRGSEL_Pos)
10245#define EADC_AD0SPCTL4_EXTREN_Pos (20)
10246#define EADC_AD0SPCTL4_EXTREN_Msk (0x1ul << EADC_AD0SPCTL4_EXTREN_Pos)
10248#define EADC_AD0SPCTL4_EXTFEN_Pos (21)
10249#define EADC_AD0SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL4_EXTFEN_Pos)
10251#define EADC_AD0SPCTL5_CHSEL_Pos (0)
10252#define EADC_AD0SPCTL5_CHSEL_Msk (0xful << EADC_AD0SPCTL5_CHSEL_Pos)
10254#define EADC_AD0SPCTL5_TRGSEL_Pos (4)
10255#define EADC_AD0SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL5_TRGSEL_Pos)
10257#define EADC_AD0SPCTL5_EXTREN_Pos (20)
10258#define EADC_AD0SPCTL5_EXTREN_Msk (0x1ul << EADC_AD0SPCTL5_EXTREN_Pos)
10260#define EADC_AD0SPCTL5_EXTFEN_Pos (21)
10261#define EADC_AD0SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL5_EXTFEN_Pos)
10263#define EADC_AD0SPCTL6_CHSEL_Pos (0)
10264#define EADC_AD0SPCTL6_CHSEL_Msk (0xful << EADC_AD0SPCTL6_CHSEL_Pos)
10266#define EADC_AD0SPCTL6_TRGSEL_Pos (4)
10267#define EADC_AD0SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL6_TRGSEL_Pos)
10269#define EADC_AD0SPCTL6_EXTREN_Pos (20)
10270#define EADC_AD0SPCTL6_EXTREN_Msk (0x1ul << EADC_AD0SPCTL6_EXTREN_Pos)
10272#define EADC_AD0SPCTL6_EXTFEN_Pos (21)
10273#define EADC_AD0SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL6_EXTFEN_Pos)
10275#define EADC_AD0SPCTL7_CHSEL_Pos (0)
10276#define EADC_AD0SPCTL7_CHSEL_Msk (0xful << EADC_AD0SPCTL7_CHSEL_Pos)
10278#define EADC_AD0SPCTL7_TRGSEL_Pos (4)
10279#define EADC_AD0SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL7_TRGSEL_Pos)
10281#define EADC_AD0SPCTL7_EXTREN_Pos (20)
10282#define EADC_AD0SPCTL7_EXTREN_Msk (0x1ul << EADC_AD0SPCTL7_EXTREN_Pos)
10284#define EADC_AD0SPCTL7_EXTFEN_Pos (21)
10285#define EADC_AD0SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL7_EXTFEN_Pos)
10287#define EADC_AD1SPCTL0_CHSEL_Pos (0)
10288#define EADC_AD1SPCTL0_CHSEL_Msk (0xful << EADC_AD1SPCTL0_CHSEL_Pos)
10290#define EADC_AD1SPCTL0_TRGSEL_Pos (4)
10291#define EADC_AD1SPCTL0_TRGSEL_Msk (0xful << EADC_AD1SPCTL0_TRGSEL_Pos)
10293#define EADC_AD1SPCTL0_TRGDLYCNT_Pos (8)
10294#define EADC_AD1SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL0_TRGDLYCNT_Pos)
10296#define EADC_AD1SPCTL0_TRGDLYDIV_Pos (16)
10297#define EADC_AD1SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL0_TRGDLYDIV_Pos)
10299#define EADC_AD1SPCTL0_EXTREN_Pos (20)
10300#define EADC_AD1SPCTL0_EXTREN_Msk (0x1ul << EADC_AD1SPCTL0_EXTREN_Pos)
10302#define EADC_AD1SPCTL0_EXTFEN_Pos (21)
10303#define EADC_AD1SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL0_EXTFEN_Pos)
10305#define EADC_AD1SPCTL1_CHSEL_Pos (0)
10306#define EADC_AD1SPCTL1_CHSEL_Msk (0xful << EADC_AD1SPCTL1_CHSEL_Pos)
10308#define EADC_AD1SPCTL1_TRGSEL_Pos (4)
10309#define EADC_AD1SPCTL1_TRGSEL_Msk (0xful << EADC_AD1SPCTL1_TRGSEL_Pos)
10311#define EADC_AD1SPCTL1_TRGDLYCNT_Pos (8)
10312#define EADC_AD1SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL1_TRGDLYCNT_Pos)
10314#define EADC_AD1SPCTL1_TRGDLYDIV_Pos (16)
10315#define EADC_AD1SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL1_TRGDLYDIV_Pos)
10317#define EADC_AD1SPCTL1_EXTREN_Pos (20)
10318#define EADC_AD1SPCTL1_EXTREN_Msk (0x1ul << EADC_AD1SPCTL1_EXTREN_Pos)
10320#define EADC_AD1SPCTL1_EXTFEN_Pos (21)
10321#define EADC_AD1SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL1_EXTFEN_Pos)
10323#define EADC_AD1SPCTL2_CHSEL_Pos (0)
10324#define EADC_AD1SPCTL2_CHSEL_Msk (0xful << EADC_AD1SPCTL2_CHSEL_Pos)
10326#define EADC_AD1SPCTL2_TRGSEL_Pos (4)
10327#define EADC_AD1SPCTL2_TRGSEL_Msk (0xful << EADC_AD1SPCTL2_TRGSEL_Pos)
10329#define EADC_AD1SPCTL2_TRGDLYCNT_Pos (8)
10330#define EADC_AD1SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL2_TRGDLYCNT_Pos)
10332#define EADC_AD1SPCTL2_TRGDLYDIV_Pos (16)
10333#define EADC_AD1SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL2_TRGDLYDIV_Pos)
10335#define EADC_AD1SPCTL2_EXTREN_Pos (20)
10336#define EADC_AD1SPCTL2_EXTREN_Msk (0x1ul << EADC_AD1SPCTL2_EXTREN_Pos)
10338#define EADC_AD1SPCTL2_EXTFEN_Pos (21)
10339#define EADC_AD1SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL2_EXTFEN_Pos)
10341#define EADC_AD1SPCTL3_CHSEL_Pos (0)
10342#define EADC_AD1SPCTL3_CHSEL_Msk (0xful << EADC_AD1SPCTL3_CHSEL_Pos)
10344#define EADC_AD1SPCTL3_TRGSEL_Pos (4)
10345#define EADC_AD1SPCTL3_TRGSEL_Msk (0xful << EADC_AD1SPCTL3_TRGSEL_Pos)
10347#define EADC_AD1SPCTL3_TRGDLYCNT_Pos (8)
10348#define EADC_AD1SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL3_TRGDLYCNT_Pos)
10350#define EADC_AD1SPCTL3_TRGDLYDIV_Pos (16)
10351#define EADC_AD1SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL3_TRGDLYDIV_Pos)
10353#define EADC_AD1SPCTL3_EXTREN_Pos (20)
10354#define EADC_AD1SPCTL3_EXTREN_Msk (0x1ul << EADC_AD1SPCTL3_EXTREN_Pos)
10356#define EADC_AD1SPCTL3_EXTFEN_Pos (21)
10357#define EADC_AD1SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL3_EXTFEN_Pos)
10359#define EADC_AD1SPCTL4_CHSEL_Pos (0)
10360#define EADC_AD1SPCTL4_CHSEL_Msk (0xful << EADC_AD1SPCTL4_CHSEL_Pos)
10362#define EADC_AD1SPCTL4_TRGSEL_Pos (4)
10363#define EADC_AD1SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL4_TRGSEL_Pos)
10365#define EADC_AD1SPCTL4_EXTREN_Pos (20)
10366#define EADC_AD1SPCTL4_EXTREN_Msk (0x1ul << EADC_AD1SPCTL4_EXTREN_Pos)
10368#define EADC_AD1SPCTL4_EXTFEN_Pos (21)
10369#define EADC_AD1SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL4_EXTFEN_Pos)
10371#define EADC_AD1SPCTL5_CHSEL_Pos (0)
10372#define EADC_AD1SPCTL5_CHSEL_Msk (0xful << EADC_AD1SPCTL5_CHSEL_Pos)
10374#define EADC_AD1SPCTL5_TRGSEL_Pos (4)
10375#define EADC_AD1SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL5_TRGSEL_Pos)
10377#define EADC_AD1SPCTL5_EXTREN_Pos (20)
10378#define EADC_AD1SPCTL5_EXTREN_Msk (0x1ul << EADC_AD1SPCTL5_EXTREN_Pos)
10380#define EADC_AD1SPCTL5_EXTFEN_Pos (21)
10381#define EADC_AD1SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL5_EXTFEN_Pos)
10383#define EADC_AD1SPCTL6_CHSEL_Pos (0)
10384#define EADC_AD1SPCTL6_CHSEL_Msk (0xful << EADC_AD1SPCTL6_CHSEL_Pos)
10386#define EADC_AD1SPCTL6_TRGSEL_Pos (4)
10387#define EADC_AD1SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL6_TRGSEL_Pos)
10389#define EADC_AD1SPCTL6_EXTREN_Pos (20)
10390#define EADC_AD1SPCTL6_EXTREN_Msk (0x1ul << EADC_AD1SPCTL6_EXTREN_Pos)
10392#define EADC_AD1SPCTL6_EXTFEN_Pos (21)
10393#define EADC_AD1SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL6_EXTFEN_Pos)
10395#define EADC_AD1SPCTL7_CHSEL_Pos (0)
10396#define EADC_AD1SPCTL7_CHSEL_Msk (0xful << EADC_AD1SPCTL7_CHSEL_Pos)
10398#define EADC_AD1SPCTL7_TRGSEL_Pos (4)
10399#define EADC_AD1SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL7_TRGSEL_Pos)
10401#define EADC_AD1SPCTL7_EXTREN_Pos (20)
10402#define EADC_AD1SPCTL7_EXTREN_Msk (0x1ul << EADC_AD1SPCTL7_EXTREN_Pos)
10404#define EADC_AD1SPCTL7_EXTFEN_Pos (21)
10405#define EADC_AD1SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL7_EXTFEN_Pos)
10407#define EADC_SIMUSEL_SIMUSEL0_Pos (0)
10408#define EADC_SIMUSEL_SIMUSEL0_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL0_Pos)
10410#define EADC_SIMUSEL_SIMUSEL1_Pos (1)
10411#define EADC_SIMUSEL_SIMUSEL1_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL1_Pos)
10413#define EADC_SIMUSEL_SIMUSEL2_Pos (2)
10414#define EADC_SIMUSEL_SIMUSEL2_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL2_Pos)
10416#define EADC_SIMUSEL_SIMUSEL3_Pos (3)
10417#define EADC_SIMUSEL_SIMUSEL3_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL3_Pos)
10419#define EADC_SIMUSEL_SIMUSEL4_Pos (4)
10420#define EADC_SIMUSEL_SIMUSEL4_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL4_Pos)
10422#define EADC_SIMUSEL_SIMUSEL5_Pos (5)
10423#define EADC_SIMUSEL_SIMUSEL5_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL5_Pos)
10425#define EADC_SIMUSEL_SIMUSEL6_Pos (6)
10426#define EADC_SIMUSEL_SIMUSEL6_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL6_Pos)
10428#define EADC_SIMUSEL_SIMUSEL7_Pos (7)
10429#define EADC_SIMUSEL_SIMUSEL7_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL7_Pos)
10431#define EADC_CMP0_ADCMPEN_Pos (0)
10432#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos)
10434#define EADC_CMP0_ADCMPIE_Pos (1)
10435#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos)
10437#define EADC_CMP0_CMPCOND_Pos (2)
10438#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos)
10440#define EADC_CMP0_CMPSPL_Pos (3)
10441#define EADC_CMP0_CMPSPL_Msk (0x7ul << EADC_CMP0_CMPSPL_Pos)
10443#define EADC_CMP0_CMPMCNT_Pos (8)
10444#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos)
10446#define EADC_CMP0_CMPDAT_Pos (16)
10447#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos)
10449#define EADC_CMP1_ADCMPEN_Pos (0)
10450#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos)
10452#define EADC_CMP1_ADCMPIE_Pos (1)
10453#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos)
10455#define EADC_CMP1_CMPCOND_Pos (2)
10456#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos)
10458#define EADC_CMP1_CMPSPL_Pos (3)
10459#define EADC_CMP1_CMPSPL_Msk (0x7ul << EADC_CMP1_CMPSPL_Pos)
10461#define EADC_CMP1_CMPMCNT_Pos (8)
10462#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos)
10464#define EADC_CMP1_CMPDAT_Pos (16)
10465#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos)
10467#define EADC_STATUS0_VALID_Pos (0)
10468#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos)
10470#define EADC_STATUS0_OV_Pos (16)
10471#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos)
10473#define EADC_STATUS1_ADIF0_Pos (0)
10474#define EADC_STATUS1_ADIF0_Msk (0x1ul << EADC_STATUS1_ADIF0_Pos)
10476#define EADC_STATUS1_ADIF1_Pos (1)
10477#define EADC_STATUS1_ADIF1_Msk (0x1ul << EADC_STATUS1_ADIF1_Pos)
10479#define EADC_STATUS1_ADIF2_Pos (2)
10480#define EADC_STATUS1_ADIF2_Msk (0x1ul << EADC_STATUS1_ADIF2_Pos)
10482#define EADC_STATUS1_ADIF3_Pos (3)
10483#define EADC_STATUS1_ADIF3_Msk (0x1ul << EADC_STATUS1_ADIF3_Pos)
10485#define EADC_STATUS1_ADCMPO0_Pos (4)
10486#define EADC_STATUS1_ADCMPO0_Msk (0x1ul << EADC_STATUS1_ADCMPO0_Pos)
10488#define EADC_STATUS1_ADCMPO1_Pos (5)
10489#define EADC_STATUS1_ADCMPO1_Msk (0x1ul << EADC_STATUS1_ADCMPO1_Pos)
10491#define EADC_STATUS1_ADCMPF0_Pos (6)
10492#define EADC_STATUS1_ADCMPF0_Msk (0x1ul << EADC_STATUS1_ADCMPF0_Pos)
10494#define EADC_STATUS1_ADCMPF1_Pos (7)
10495#define EADC_STATUS1_ADCMPF1_Msk (0x1ul << EADC_STATUS1_ADCMPF1_Pos)
10497#define EADC_STATUS1_BUSY0_Pos (8)
10498#define EADC_STATUS1_BUSY0_Msk (0x1ul << EADC_STATUS1_BUSY0_Pos)
10500#define EADC_STATUS1_CHANNEL0_Pos (12)
10501#define EADC_STATUS1_CHANNEL0_Msk (0xful << EADC_STATUS1_CHANNEL0_Pos)
10503#define EADC_STATUS1_BUSY1_Pos (16)
10504#define EADC_STATUS1_BUSY1_Msk (0x1ul << EADC_STATUS1_BUSY1_Pos)
10506#define EADC_STATUS1_CHANNEL1_Pos (20)
10507#define EADC_STATUS1_CHANNEL1_Msk (0xful << EADC_STATUS1_CHANNEL1_Pos)
10509#define EADC_STATUS1_ADOVIF_Pos (24)
10510#define EADC_STATUS1_ADOVIF_Msk (0x1ul << EADC_STATUS1_ADOVIF_Pos)
10512#define EADC_STATUS1_STOVF_Pos (25)
10513#define EADC_STATUS1_STOVF_Msk (0x1ul << EADC_STATUS1_STOVF_Pos)
10515#define EADC_STATUS1_AVALID_Pos (26)
10516#define EADC_STATUS1_AVALID_Msk (0x1ul << EADC_STATUS1_AVALID_Pos)
10518#define EADC_STATUS1_AOV_Pos (27)
10519#define EADC_STATUS1_AOV_Msk (0x1ul << EADC_STATUS1_AOV_Pos)
10521#define EADC_EXTSMPT_EXTSMPT0_Pos (0)
10522#define EADC_EXTSMPT_EXTSMPT0_Msk (0xfful << EADC_EXTSMPT_EXTSMPT0_Pos)
10524#define EADC_EXTSMPT_EXTSMPT1_Pos (16)
10525#define EADC_EXTSMPT_EXTSMPT1_Msk (0xfful << EADC_EXTSMPT_EXTSMPT1_Pos)
10527#define EADC_AD0DDAT0_RESULT_Pos (0)
10528#define EADC_AD0DDAT0_RESULT_Msk (0xffful << EADC_AD0DDAT0_RESULT_Pos)
10530#define EADC_AD0DDAT0_VALID_Pos (16)
10531#define EADC_AD0DDAT0_VALID_Msk (0x1ul << EADC_AD0DDAT0_VALID_Pos)
10533#define EADC_AD0DDAT1_RESULT_Pos (0)
10534#define EADC_AD0DDAT1_RESULT_Msk (0xffful << EADC_AD0DDAT1_RESULT_Pos)
10536#define EADC_AD0DDAT1_VALID_Pos (16)
10537#define EADC_AD0DDAT1_VALID_Msk (0x1ul << EADC_AD0DDAT1_VALID_Pos)
10539#define EADC_AD0DDAT2_RESULT_Pos (0)
10540#define EADC_AD0DDAT2_RESULT_Msk (0xffful << EADC_AD0DDAT2_RESULT_Pos)
10542#define EADC_AD0DDAT2_VALID_Pos (16)
10543#define EADC_AD0DDAT2_VALID_Msk (0x1ul << EADC_AD0DDAT2_VALID_Pos)
10545#define EADC_AD0DDAT3_RESULT_Pos (0)
10546#define EADC_AD0DDAT3_RESULT_Msk (0xffful << EADC_AD0DDAT3_RESULT_Pos)
10548#define EADC_AD0DDAT3_VALID_Pos (16)
10549#define EADC_AD0DDAT3_VALID_Msk (0x1ul << EADC_AD0DDAT3_VALID_Pos)
10551#define EADC_AD1DDAT0_RESULT_Pos (0)
10552#define EADC_AD1DDAT0_RESULT_Msk (0xffful << EADC_AD1DDAT0_RESULT_Pos)
10554#define EADC_AD1DDAT0_VALID_Pos (16)
10555#define EADC_AD1DDAT0_VALID_Msk (0x1ul << EADC_AD1DDAT0_VALID_Pos)
10557#define EADC_AD1DDAT1_RESULT_Pos (0)
10558#define EADC_AD1DDAT1_RESULT_Msk (0xffful << EADC_AD1DDAT1_RESULT_Pos)
10560#define EADC_AD1DDAT1_VALID_Pos (16)
10561#define EADC_AD1DDAT1_VALID_Msk (0x1ul << EADC_AD1DDAT1_VALID_Pos)
10563#define EADC_AD1DDAT2_RESULT_Pos (0)
10564#define EADC_AD1DDAT2_RESULT_Msk (0xffful << EADC_AD1DDAT2_RESULT_Pos)
10566#define EADC_AD1DDAT2_VALID_Pos (16)
10567#define EADC_AD1DDAT2_VALID_Msk (0x1ul << EADC_AD1DDAT2_VALID_Pos)
10569#define EADC_AD1DDAT3_RESULT_Pos (0)
10570#define EADC_AD1DDAT3_RESULT_Msk (0xffful << EADC_AD1DDAT3_RESULT_Pos)
10572#define EADC_AD1DDAT3_VALID_Pos (16)
10573#define EADC_AD1DDAT3_VALID_Msk (0x1ul << EADC_AD1DDAT3_VALID_Pos)
10575#define EADC_DBMEN_AD0DBM0_Pos (0)
10576#define EADC_DBMEN_AD0DBM0_Msk (0x1ul << EADC_DBMEN_AD0DBM0_Pos)
10578#define EADC_DBMEN_AD0DBM1_Pos (1)
10579#define EADC_DBMEN_AD0DBM1_Msk (0x1ul << EADC_DBMEN_AD0DBM1_Pos)
10581#define EADC_DBMEN_AD0DBM2_Pos (2)
10582#define EADC_DBMEN_AD0DBM2_Msk (0x1ul << EADC_DBMEN_AD0DBM2_Pos)
10584#define EADC_DBMEN_AD0DBM3_Pos (3)
10585#define EADC_DBMEN_AD0DBM3_Msk (0x1ul << EADC_DBMEN_AD0DBM3_Pos)
10587#define EADC_DBMEN_AD1DBM0_Pos (8)
10588#define EADC_DBMEN_AD1DBM0_Msk (0x1ul << EADC_DBMEN_AD1DBM0_Pos)
10590#define EADC_DBMEN_AD1DBM1_Pos (9)
10591#define EADC_DBMEN_AD1DBM1_Msk (0x1ul << EADC_DBMEN_AD1DBM1_Pos)
10593#define EADC_DBMEN_AD1DBM2_Pos (10)
10594#define EADC_DBMEN_AD1DBM2_Msk (0x1ul << EADC_DBMEN_AD1DBM2_Pos)
10596#define EADC_DBMEN_AD1DBM3_Pos (11)
10597#define EADC_DBMEN_AD1DBM3_Msk (0x1ul << EADC_DBMEN_AD1DBM3_Pos)
10599#define EADC_INTSRC0_AD0SPIE0_Pos (0)
10600#define EADC_INTSRC0_AD0SPIE0_Msk (0x1ul << EADC_INTSRC0_AD0SPIE0_Pos)
10602#define EADC_INTSRC0_AD0SPIE1_Pos (1)
10603#define EADC_INTSRC0_AD0SPIE1_Msk (0x1ul << EADC_INTSRC0_AD0SPIE1_Pos)
10605#define EADC_INTSRC0_AD0SPIE2_Pos (2)
10606#define EADC_INTSRC0_AD0SPIE2_Msk (0x1ul << EADC_INTSRC0_AD0SPIE2_Pos)
10608#define EADC_INTSRC0_AD0SPIE3_Pos (3)
10609#define EADC_INTSRC0_AD0SPIE3_Msk (0x1ul << EADC_INTSRC0_AD0SPIE3_Pos)
10611#define EADC_INTSRC0_AD0SPIE4_Pos (4)
10612#define EADC_INTSRC0_AD0SPIE4_Msk (0x1ul << EADC_INTSRC0_AD0SPIE4_Pos)
10614#define EADC_INTSRC0_AD0SPIE5_Pos (5)
10615#define EADC_INTSRC0_AD0SPIE5_Msk (0x1ul << EADC_INTSRC0_AD0SPIE5_Pos)
10617#define EADC_INTSRC0_AD0SPIE6_Pos (6)
10618#define EADC_INTSRC0_AD0SPIE6_Msk (0x1ul << EADC_INTSRC0_AD0SPIE6_Pos)
10620#define EADC_INTSRC0_AD0SPIE7_Pos (7)
10621#define EADC_INTSRC0_AD0SPIE7_Msk (0x1ul << EADC_INTSRC0_AD0SPIE7_Pos)
10623#define EADC_INTSRC0_AD1SPIE0_Pos (8)
10624#define EADC_INTSRC0_AD1SPIE0_Msk (0x1ul << EADC_INTSRC0_AD1SPIE0_Pos)
10626#define EADC_INTSRC0_AD1SPIE1_Pos (9)
10627#define EADC_INTSRC0_AD1SPIE1_Msk (0x1ul << EADC_INTSRC0_AD1SPIE1_Pos)
10629#define EADC_INTSRC0_AD1SPIE2_Pos (10)
10630#define EADC_INTSRC0_AD1SPIE2_Msk (0x1ul << EADC_INTSRC0_AD1SPIE2_Pos)
10632#define EADC_INTSRC0_AD1SPIE3_Pos (11)
10633#define EADC_INTSRC0_AD1SPIE3_Msk (0x1ul << EADC_INTSRC0_AD1SPIE3_Pos)
10635#define EADC_INTSRC0_AD1SPIE4_Pos (12)
10636#define EADC_INTSRC0_AD1SPIE4_Msk (0x1ul << EADC_INTSRC0_AD1SPIE4_Pos)
10638#define EADC_INTSRC0_AD1SPIE5_Pos (13)
10639#define EADC_INTSRC0_AD1SPIE5_Msk (0x1ul << EADC_INTSRC0_AD1SPIE5_Pos)
10641#define EADC_INTSRC0_AD1SPIE6_Pos (14)
10642#define EADC_INTSRC0_AD1SPIE6_Msk (0x1ul << EADC_INTSRC0_AD1SPIE6_Pos)
10644#define EADC_INTSRC0_AD1SPIE7_Pos (15)
10645#define EADC_INTSRC0_AD1SPIE7_Msk (0x1ul << EADC_INTSRC0_AD1SPIE7_Pos)
10647#define EADC_INTSRC1_AD0SPIE0_Pos (0)
10648#define EADC_INTSRC1_AD0SPIE0_Msk (0x1ul << EADC_INTSRC1_AD0SPIE0_Pos)
10650#define EADC_INTSRC1_AD0SPIE1_Pos (1)
10651#define EADC_INTSRC1_AD0SPIE1_Msk (0x1ul << EADC_INTSRC1_AD0SPIE1_Pos)
10653#define EADC_INTSRC1_AD0SPIE2_Pos (2)
10654#define EADC_INTSRC1_AD0SPIE2_Msk (0x1ul << EADC_INTSRC1_AD0SPIE2_Pos)
10656#define EADC_INTSRC1_AD0SPIE3_Pos (3)
10657#define EADC_INTSRC1_AD0SPIE3_Msk (0x1ul << EADC_INTSRC1_AD0SPIE3_Pos)
10659#define EADC_INTSRC1_AD0SPIE4_Pos (4)
10660#define EADC_INTSRC1_AD0SPIE4_Msk (0x1ul << EADC_INTSRC1_AD0SPIE4_Pos)
10662#define EADC_INTSRC1_AD0SPIE5_Pos (5)
10663#define EADC_INTSRC1_AD0SPIE5_Msk (0x1ul << EADC_INTSRC1_AD0SPIE5_Pos)
10665#define EADC_INTSRC1_AD0SPIE6_Pos (6)
10666#define EADC_INTSRC1_AD0SPIE6_Msk (0x1ul << EADC_INTSRC1_AD0SPIE6_Pos)
10668#define EADC_INTSRC1_AD0SPIE7_Pos (7)
10669#define EADC_INTSRC1_AD0SPIE7_Msk (0x1ul << EADC_INTSRC1_AD0SPIE7_Pos)
10671#define EADC_INTSRC1_AD1SPIE0_Pos (8)
10672#define EADC_INTSRC1_AD1SPIE0_Msk (0x1ul << EADC_INTSRC1_AD1SPIE0_Pos)
10674#define EADC_INTSRC1_AD1SPIE1_Pos (9)
10675#define EADC_INTSRC1_AD1SPIE1_Msk (0x1ul << EADC_INTSRC1_AD1SPIE1_Pos)
10677#define EADC_INTSRC1_AD1SPIE2_Pos (10)
10678#define EADC_INTSRC1_AD1SPIE2_Msk (0x1ul << EADC_INTSRC1_AD1SPIE2_Pos)
10680#define EADC_INTSRC1_AD1SPIE3_Pos (11)
10681#define EADC_INTSRC1_AD1SPIE3_Msk (0x1ul << EADC_INTSRC1_AD1SPIE3_Pos)
10683#define EADC_INTSRC1_AD1SPIE4_Pos (12)
10684#define EADC_INTSRC1_AD1SPIE4_Msk (0x1ul << EADC_INTSRC1_AD1SPIE4_Pos)
10686#define EADC_INTSRC1_AD1SPIE5_Pos (13)
10687#define EADC_INTSRC1_AD1SPIE5_Msk (0x1ul << EADC_INTSRC1_AD1SPIE5_Pos)
10689#define EADC_INTSRC1_AD1SPIE6_Pos (14)
10690#define EADC_INTSRC1_AD1SPIE6_Msk (0x1ul << EADC_INTSRC1_AD1SPIE6_Pos)
10692#define EADC_INTSRC1_AD1SPIE7_Pos (15)
10693#define EADC_INTSRC1_AD1SPIE7_Msk (0x1ul << EADC_INTSRC1_AD1SPIE7_Pos)
10695#define EADC_INTSRC2_AD0SPIE0_Pos (0)
10696#define EADC_INTSRC2_AD0SPIE0_Msk (0x1ul << EADC_INTSRC2_AD0SPIE0_Pos)
10698#define EADC_INTSRC2_AD0SPIE1_Pos (1)
10699#define EADC_INTSRC2_AD0SPIE1_Msk (0x1ul << EADC_INTSRC2_AD0SPIE1_Pos)
10701#define EADC_INTSRC2_AD0SPIE2_Pos (2)
10702#define EADC_INTSRC2_AD0SPIE2_Msk (0x1ul << EADC_INTSRC2_AD0SPIE2_Pos)
10704#define EADC_INTSRC2_AD0SPIE3_Pos (3)
10705#define EADC_INTSRC2_AD0SPIE3_Msk (0x1ul << EADC_INTSRC2_AD0SPIE3_Pos)
10707#define EADC_INTSRC2_AD0SPIE4_Pos (4)
10708#define EADC_INTSRC2_AD0SPIE4_Msk (0x1ul << EADC_INTSRC2_AD0SPIE4_Pos)
10710#define EADC_INTSRC2_AD0SPIE5_Pos (5)
10711#define EADC_INTSRC2_AD0SPIE5_Msk (0x1ul << EADC_INTSRC2_AD0SPIE5_Pos)
10713#define EADC_INTSRC2_AD0SPIE6_Pos (6)
10714#define EADC_INTSRC2_AD0SPIE6_Msk (0x1ul << EADC_INTSRC2_AD0SPIE6_Pos)
10716#define EADC_INTSRC2_AD0SPIE7_Pos (7)
10717#define EADC_INTSRC2_AD0SPIE7_Msk (0x1ul << EADC_INTSRC2_AD0SPIE7_Pos)
10719#define EADC_INTSRC2_AD1SPIE0_Pos (8)
10720#define EADC_INTSRC2_AD1SPIE0_Msk (0x1ul << EADC_INTSRC2_AD1SPIE0_Pos)
10722#define EADC_INTSRC2_AD1SPIE1_Pos (9)
10723#define EADC_INTSRC2_AD1SPIE1_Msk (0x1ul << EADC_INTSRC2_AD1SPIE1_Pos)
10725#define EADC_INTSRC2_AD1SPIE2_Pos (10)
10726#define EADC_INTSRC2_AD1SPIE2_Msk (0x1ul << EADC_INTSRC2_AD1SPIE2_Pos)
10728#define EADC_INTSRC2_AD1SPIE3_Pos (11)
10729#define EADC_INTSRC2_AD1SPIE3_Msk (0x1ul << EADC_INTSRC2_AD1SPIE3_Pos)
10731#define EADC_INTSRC2_AD1SPIE4_Pos (12)
10732#define EADC_INTSRC2_AD1SPIE4_Msk (0x1ul << EADC_INTSRC2_AD1SPIE4_Pos)
10734#define EADC_INTSRC2_AD1SPIE5_Pos (13)
10735#define EADC_INTSRC2_AD1SPIE5_Msk (0x1ul << EADC_INTSRC2_AD1SPIE5_Pos)
10737#define EADC_INTSRC2_AD1SPIE6_Pos (14)
10738#define EADC_INTSRC2_AD1SPIE6_Msk (0x1ul << EADC_INTSRC2_AD1SPIE6_Pos)
10740#define EADC_INTSRC2_AD1SPIE7_Pos (15)
10741#define EADC_INTSRC2_AD1SPIE7_Msk (0x1ul << EADC_INTSRC2_AD1SPIE7_Pos)
10743#define EADC_INTSRC3_AD0SPIE0_Pos (0)
10744#define EADC_INTSRC3_AD0SPIE0_Msk (0x1ul << EADC_INTSRC3_AD0SPIE0_Pos)
10746#define EADC_INTSRC3_AD0SPIE1_Pos (1)
10747#define EADC_INTSRC3_AD0SPIE1_Msk (0x1ul << EADC_INTSRC3_AD0SPIE1_Pos)
10749#define EADC_INTSRC3_AD0SPIE2_Pos (2)
10750#define EADC_INTSRC3_AD0SPIE2_Msk (0x1ul << EADC_INTSRC3_AD0SPIE2_Pos)
10752#define EADC_INTSRC3_AD0SPIE3_Pos (3)
10753#define EADC_INTSRC3_AD0SPIE3_Msk (0x1ul << EADC_INTSRC3_AD0SPIE3_Pos)
10755#define EADC_INTSRC3_AD0SPIE4_Pos (4)
10756#define EADC_INTSRC3_AD0SPIE4_Msk (0x1ul << EADC_INTSRC3_AD0SPIE4_Pos)
10758#define EADC_INTSRC3_AD0SPIE5_Pos (5)
10759#define EADC_INTSRC3_AD0SPIE5_Msk (0x1ul << EADC_INTSRC3_AD0SPIE5_Pos)
10761#define EADC_INTSRC3_AD0SPIE6_Pos (6)
10762#define EADC_INTSRC3_AD0SPIE6_Msk (0x1ul << EADC_INTSRC3_AD0SPIE6_Pos)
10764#define EADC_INTSRC3_AD0SPIE7_Pos (7)
10765#define EADC_INTSRC3_AD0SPIE7_Msk (0x1ul << EADC_INTSRC3_AD0SPIE7_Pos)
10767#define EADC_INTSRC3_AD1SPIE0_Pos (8)
10768#define EADC_INTSRC3_AD1SPIE0_Msk (0x1ul << EADC_INTSRC3_AD1SPIE0_Pos)
10770#define EADC_INTSRC3_AD1SPIE1_Pos (9)
10771#define EADC_INTSRC3_AD1SPIE1_Msk (0x1ul << EADC_INTSRC3_AD1SPIE1_Pos)
10773#define EADC_INTSRC3_AD1SPIE2_Pos (10)
10774#define EADC_INTSRC3_AD1SPIE2_Msk (0x1ul << EADC_INTSRC3_AD1SPIE2_Pos)
10776#define EADC_INTSRC3_AD1SPIE3_Pos (11)
10777#define EADC_INTSRC3_AD1SPIE3_Msk (0x1ul << EADC_INTSRC3_AD1SPIE3_Pos)
10779#define EADC_INTSRC3_AD1SPIE4_Pos (12)
10780#define EADC_INTSRC3_AD1SPIE4_Msk (0x1ul << EADC_INTSRC3_AD1SPIE4_Pos)
10782#define EADC_INTSRC3_AD1SPIE5_Pos (13)
10783#define EADC_INTSRC3_AD1SPIE5_Msk (0x1ul << EADC_INTSRC3_AD1SPIE5_Pos)
10785#define EADC_INTSRC3_AD1SPIE6_Pos (14)
10786#define EADC_INTSRC3_AD1SPIE6_Msk (0x1ul << EADC_INTSRC3_AD1SPIE6_Pos)
10788#define EADC_INTSRC3_AD1SPIE7_Pos (15)
10789#define EADC_INTSRC3_AD1SPIE7_Msk (0x1ul << EADC_INTSRC3_AD1SPIE7_Pos)
10791#define EADC_AD0TRGEN0_EPWM00REN_Pos (0)
10792#define EADC_AD0TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00REN_Pos)
10794#define EADC_AD0TRGEN0_EPWM00FEN_Pos (1)
10795#define EADC_AD0TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00FEN_Pos)
10797#define EADC_AD0TRGEN0_EPWM00PEN_Pos (2)
10798#define EADC_AD0TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00PEN_Pos)
10800#define EADC_AD0TRGEN0_EPWM00CEN_Pos (3)
10801#define EADC_AD0TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00CEN_Pos)
10803#define EADC_AD0TRGEN0_EPWM02REN_Pos (4)
10804#define EADC_AD0TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02REN_Pos)
10806#define EADC_AD0TRGEN0_EPWM02FEN_Pos (5)
10807#define EADC_AD0TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02FEN_Pos)
10809#define EADC_AD0TRGEN0_EPWM02PEN_Pos (6)
10810#define EADC_AD0TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02PEN_Pos)
10812#define EADC_AD0TRGEN0_EPWM02CEN_Pos (7)
10813#define EADC_AD0TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02CEN_Pos)
10815#define EADC_AD0TRGEN0_EPWM04REN_Pos (8)
10816#define EADC_AD0TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04REN_Pos)
10818#define EADC_AD0TRGEN0_EPWM04FEN_Pos (9)
10819#define EADC_AD0TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04FEN_Pos)
10821#define EADC_AD0TRGEN0_EPWM04PEN_Pos (10)
10822#define EADC_AD0TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04PEN_Pos)
10824#define EADC_AD0TRGEN0_EPWM04CEN_Pos (11)
10825#define EADC_AD0TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04CEN_Pos)
10827#define EADC_AD0TRGEN0_EPWM10REN_Pos (12)
10828#define EADC_AD0TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10REN_Pos)
10830#define EADC_AD0TRGEN0_EPWM10FEN_Pos (13)
10831#define EADC_AD0TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10FEN_Pos)
10833#define EADC_AD0TRGEN0_EPWM10PEN_Pos (14)
10834#define EADC_AD0TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10PEN_Pos)
10836#define EADC_AD0TRGEN0_EPWM10CEN_Pos (15)
10837#define EADC_AD0TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10CEN_Pos)
10839#define EADC_AD0TRGEN0_EPWM12REN_Pos (16)
10840#define EADC_AD0TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12REN_Pos)
10842#define EADC_AD0TRGEN0_EPWM120FEN_Pos (17)
10843#define EADC_AD0TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM120FEN_Pos)
10845#define EADC_AD0TRGEN0_EPWM12PEN_Pos (18)
10846#define EADC_AD0TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12PEN_Pos)
10848#define EADC_AD0TRGEN0_EPWM12CEN_Pos (19)
10849#define EADC_AD0TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12CEN_Pos)
10851#define EADC_AD0TRGEN0_EPWM14REN_Pos (20)
10852#define EADC_AD0TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14REN_Pos)
10854#define EADC_AD0TRGEN0_EPWM14FEN_Pos (21)
10855#define EADC_AD0TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14FEN_Pos)
10857#define EADC_AD0TRGEN0_EPWM14PEN_Pos (22)
10858#define EADC_AD0TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14PEN_Pos)
10860#define EADC_AD0TRGEN0_EPWM14CEN_Pos (23)
10861#define EADC_AD0TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14CEN_Pos)
10863#define EADC_AD0TRGEN0_PWM00REN_Pos (24)
10864#define EADC_AD0TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00REN_Pos)
10866#define EADC_AD0TRGEN0_PWM00FEN_Pos (25)
10867#define EADC_AD0TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00FEN_Pos)
10869#define EADC_AD0TRGEN0_PWM00PEN_Pos (26)
10870#define EADC_AD0TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00PEN_Pos)
10872#define EADC_AD0TRGEN0_PWM00CEN_Pos (27)
10873#define EADC_AD0TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00CEN_Pos)
10875#define EADC_AD0TRGEN0_PWM01REN_Pos (28)
10876#define EADC_AD0TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01REN_Pos)
10878#define EADC_AD0TRGEN0_PWM01FEN_Pos (29)
10879#define EADC_AD0TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01FEN_Pos)
10881#define EADC_AD0TRGEN0_PWM01PEN_Pos (30)
10882#define EADC_AD0TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01PEN_Pos)
10884#define EADC_AD0TRGEN0_PWM01CEN_Pos (31)
10885#define EADC_AD0TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01CEN_Pos)
10887#define EADC_AD0TRGEN1_EPWM00REN_Pos (0)
10888#define EADC_AD0TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00REN_Pos)
10890#define EADC_AD0TRGEN1_EPWM00FEN_Pos (1)
10891#define EADC_AD0TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00FEN_Pos)
10893#define EADC_AD0TRGEN1_EPWM00PEN_Pos (2)
10894#define EADC_AD0TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00PEN_Pos)
10896#define EADC_AD0TRGEN1_EPWM00CEN_Pos (3)
10897#define EADC_AD0TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00CEN_Pos)
10899#define EADC_AD0TRGEN1_EPWM02REN_Pos (4)
10900#define EADC_AD0TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02REN_Pos)
10902#define EADC_AD0TRGEN1_EPWM02FEN_Pos (5)
10903#define EADC_AD0TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02FEN_Pos)
10905#define EADC_AD0TRGEN1_EPWM02PEN_Pos (6)
10906#define EADC_AD0TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02PEN_Pos)
10908#define EADC_AD0TRGEN1_EPWM02CEN_Pos (7)
10909#define EADC_AD0TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02CEN_Pos)
10911#define EADC_AD0TRGEN1_EPWM04REN_Pos (8)
10912#define EADC_AD0TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04REN_Pos)
10914#define EADC_AD0TRGEN1_EPWM04FEN_Pos (9)
10915#define EADC_AD0TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04FEN_Pos)
10917#define EADC_AD0TRGEN1_EPWM04PEN_Pos (10)
10918#define EADC_AD0TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04PEN_Pos)
10920#define EADC_AD0TRGEN1_EPWM04CEN_Pos (11)
10921#define EADC_AD0TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04CEN_Pos)
10923#define EADC_AD0TRGEN1_EPWM10REN_Pos (12)
10924#define EADC_AD0TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10REN_Pos)
10926#define EADC_AD0TRGEN1_EPWM10FEN_Pos (13)
10927#define EADC_AD0TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10FEN_Pos)
10929#define EADC_AD0TRGEN1_EPWM10PEN_Pos (14)
10930#define EADC_AD0TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10PEN_Pos)
10932#define EADC_AD0TRGEN1_EPWM10CEN_Pos (15)
10933#define EADC_AD0TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10CEN_Pos)
10935#define EADC_AD0TRGEN1_EPWM12REN_Pos (16)
10936#define EADC_AD0TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12REN_Pos)
10938#define EADC_AD0TRGEN1_EPWM120FEN_Pos (17)
10939#define EADC_AD0TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM120FEN_Pos)
10941#define EADC_AD0TRGEN1_EPWM12PEN_Pos (18)
10942#define EADC_AD0TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12PEN_Pos)
10944#define EADC_AD0TRGEN1_EPWM12CEN_Pos (19)
10945#define EADC_AD0TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12CEN_Pos)
10947#define EADC_AD0TRGEN1_EPWM14REN_Pos (20)
10948#define EADC_AD0TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14REN_Pos)
10950#define EADC_AD0TRGEN1_EPWM14FEN_Pos (21)
10951#define EADC_AD0TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14FEN_Pos)
10953#define EADC_AD0TRGEN1_EPWM14PEN_Pos (22)
10954#define EADC_AD0TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14PEN_Pos)
10956#define EADC_AD0TRGEN1_EPWM14CEN_Pos (23)
10957#define EADC_AD0TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14CEN_Pos)
10959#define EADC_AD0TRGEN1_PWM00REN_Pos (24)
10960#define EADC_AD0TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00REN_Pos)
10962#define EADC_AD0TRGEN1_PWM00FEN_Pos (25)
10963#define EADC_AD0TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00FEN_Pos)
10965#define EADC_AD0TRGEN1_PWM00PEN_Pos (26)
10966#define EADC_AD0TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00PEN_Pos)
10968#define EADC_AD0TRGEN1_PWM00CEN_Pos (27)
10969#define EADC_AD0TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00CEN_Pos)
10971#define EADC_AD0TRGEN1_PWM01REN_Pos (28)
10972#define EADC_AD0TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01REN_Pos)
10974#define EADC_AD0TRGEN1_PWM01FEN_Pos (29)
10975#define EADC_AD0TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01FEN_Pos)
10977#define EADC_AD0TRGEN1_PWM01PEN_Pos (30)
10978#define EADC_AD0TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01PEN_Pos)
10980#define EADC_AD0TRGEN1_PWM01CEN_Pos (31)
10981#define EADC_AD0TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01CEN_Pos)
10983#define EADC_AD0TRGEN2_EPWM00REN_Pos (0)
10984#define EADC_AD0TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00REN_Pos)
10986#define EADC_AD0TRGEN2_EPWM00FEN_Pos (1)
10987#define EADC_AD0TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00FEN_Pos)
10989#define EADC_AD0TRGEN2_EPWM00PEN_Pos (2)
10990#define EADC_AD0TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00PEN_Pos)
10992#define EADC_AD0TRGEN2_EPWM00CEN_Pos (3)
10993#define EADC_AD0TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00CEN_Pos)
10995#define EADC_AD0TRGEN2_EPWM02REN_Pos (4)
10996#define EADC_AD0TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02REN_Pos)
10998#define EADC_AD0TRGEN2_EPWM02FEN_Pos (5)
10999#define EADC_AD0TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02FEN_Pos)
11001#define EADC_AD0TRGEN2_EPWM02PEN_Pos (6)
11002#define EADC_AD0TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02PEN_Pos)
11004#define EADC_AD0TRGEN2_EPWM02CEN_Pos (7)
11005#define EADC_AD0TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02CEN_Pos)
11007#define EADC_AD0TRGEN2_EPWM04REN_Pos (8)
11008#define EADC_AD0TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04REN_Pos)
11010#define EADC_AD0TRGEN2_EPWM04FEN_Pos (9)
11011#define EADC_AD0TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04FEN_Pos)
11013#define EADC_AD0TRGEN2_EPWM04PEN_Pos (10)
11014#define EADC_AD0TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04PEN_Pos)
11016#define EADC_AD0TRGEN2_EPWM04CEN_Pos (11)
11017#define EADC_AD0TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04CEN_Pos)
11019#define EADC_AD0TRGEN2_EPWM10REN_Pos (12)
11020#define EADC_AD0TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10REN_Pos)
11022#define EADC_AD0TRGEN2_EPWM10FEN_Pos (13)
11023#define EADC_AD0TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10FEN_Pos)
11025#define EADC_AD0TRGEN2_EPWM10PEN_Pos (14)
11026#define EADC_AD0TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10PEN_Pos)
11028#define EADC_AD0TRGEN2_EPWM10CEN_Pos (15)
11029#define EADC_AD0TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10CEN_Pos)
11031#define EADC_AD0TRGEN2_EPWM12REN_Pos (16)
11032#define EADC_AD0TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12REN_Pos)
11034#define EADC_AD0TRGEN2_EPWM120FEN_Pos (17)
11035#define EADC_AD0TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM120FEN_Pos)
11037#define EADC_AD0TRGEN2_EPWM12PEN_Pos (18)
11038#define EADC_AD0TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12PEN_Pos)
11040#define EADC_AD0TRGEN2_EPWM12CEN_Pos (19)
11041#define EADC_AD0TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12CEN_Pos)
11043#define EADC_AD0TRGEN2_EPWM14REN_Pos (20)
11044#define EADC_AD0TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14REN_Pos)
11046#define EADC_AD0TRGEN2_EPWM14FEN_Pos (21)
11047#define EADC_AD0TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14FEN_Pos)
11049#define EADC_AD0TRGEN2_EPWM14PEN_Pos (22)
11050#define EADC_AD0TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14PEN_Pos)
11052#define EADC_AD0TRGEN2_EPWM14CEN_Pos (23)
11053#define EADC_AD0TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14CEN_Pos)
11055#define EADC_AD0TRGEN2_PWM00REN_Pos (24)
11056#define EADC_AD0TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00REN_Pos)
11058#define EADC_AD0TRGEN2_PWM00FEN_Pos (25)
11059#define EADC_AD0TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00FEN_Pos)
11061#define EADC_AD0TRGEN2_PWM00PEN_Pos (26)
11062#define EADC_AD0TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00PEN_Pos)
11064#define EADC_AD0TRGEN2_PWM00CEN_Pos (27)
11065#define EADC_AD0TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00CEN_Pos)
11067#define EADC_AD0TRGEN2_PWM01REN_Pos (28)
11068#define EADC_AD0TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01REN_Pos)
11070#define EADC_AD0TRGEN2_PWM01FEN_Pos (29)
11071#define EADC_AD0TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01FEN_Pos)
11073#define EADC_AD0TRGEN2_PWM01PEN_Pos (30)
11074#define EADC_AD0TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01PEN_Pos)
11076#define EADC_AD0TRGEN2_PWM01CEN_Pos (31)
11077#define EADC_AD0TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01CEN_Pos)
11079#define EADC_AD0TRGEN3_EPWM00REN_Pos (0)
11080#define EADC_AD0TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00REN_Pos)
11082#define EADC_AD0TRGEN3_EPWM00FEN_Pos (1)
11083#define EADC_AD0TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00FEN_Pos)
11085#define EADC_AD0TRGEN3_EPWM00PEN_Pos (2)
11086#define EADC_AD0TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00PEN_Pos)
11088#define EADC_AD0TRGEN3_EPWM00CEN_Pos (3)
11089#define EADC_AD0TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00CEN_Pos)
11091#define EADC_AD0TRGEN3_EPWM02REN_Pos (4)
11092#define EADC_AD0TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02REN_Pos)
11094#define EADC_AD0TRGEN3_EPWM02FEN_Pos (5)
11095#define EADC_AD0TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02FEN_Pos)
11097#define EADC_AD0TRGEN3_EPWM02PEN_Pos (6)
11098#define EADC_AD0TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02PEN_Pos)
11100#define EADC_AD0TRGEN3_EPWM02CEN_Pos (7)
11101#define EADC_AD0TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02CEN_Pos)
11103#define EADC_AD0TRGEN3_EPWM04REN_Pos (8)
11104#define EADC_AD0TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04REN_Pos)
11106#define EADC_AD0TRGEN3_EPWM04FEN_Pos (9)
11107#define EADC_AD0TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04FEN_Pos)
11109#define EADC_AD0TRGEN3_EPWM04PEN_Pos (10)
11110#define EADC_AD0TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04PEN_Pos)
11112#define EADC_AD0TRGEN3_EPWM04CEN_Pos (11)
11113#define EADC_AD0TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04CEN_Pos)
11115#define EADC_AD0TRGEN3_EPWM10REN_Pos (12)
11116#define EADC_AD0TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10REN_Pos)
11118#define EADC_AD0TRGEN3_EPWM10FEN_Pos (13)
11119#define EADC_AD0TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10FEN_Pos)
11121#define EADC_AD0TRGEN3_EPWM10PEN_Pos (14)
11122#define EADC_AD0TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10PEN_Pos)
11124#define EADC_AD0TRGEN3_EPWM10CEN_Pos (15)
11125#define EADC_AD0TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10CEN_Pos)
11127#define EADC_AD0TRGEN3_EPWM12REN_Pos (16)
11128#define EADC_AD0TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12REN_Pos)
11130#define EADC_AD0TRGEN3_EPWM120FEN_Pos (17)
11131#define EADC_AD0TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM120FEN_Pos)
11133#define EADC_AD0TRGEN3_EPWM12PEN_Pos (18)
11134#define EADC_AD0TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12PEN_Pos)
11136#define EADC_AD0TRGEN3_EPWM12CEN_Pos (19)
11137#define EADC_AD0TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12CEN_Pos)
11139#define EADC_AD0TRGEN3_EPWM14REN_Pos (20)
11140#define EADC_AD0TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14REN_Pos)
11142#define EADC_AD0TRGEN3_EPWM14FEN_Pos (21)
11143#define EADC_AD0TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14FEN_Pos)
11145#define EADC_AD0TRGEN3_EPWM14PEN_Pos (22)
11146#define EADC_AD0TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14PEN_Pos)
11148#define EADC_AD0TRGEN3_EPWM14CEN_Pos (23)
11149#define EADC_AD0TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14CEN_Pos)
11151#define EADC_AD0TRGEN3_PWM00REN_Pos (24)
11152#define EADC_AD0TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00REN_Pos)
11154#define EADC_AD0TRGEN3_PWM00FEN_Pos (25)
11155#define EADC_AD0TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00FEN_Pos)
11157#define EADC_AD0TRGEN3_PWM00PEN_Pos (26)
11158#define EADC_AD0TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00PEN_Pos)
11160#define EADC_AD0TRGEN3_PWM00CEN_Pos (27)
11161#define EADC_AD0TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00CEN_Pos)
11163#define EADC_AD0TRGEN3_PWM01REN_Pos (28)
11164#define EADC_AD0TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01REN_Pos)
11166#define EADC_AD0TRGEN3_PWM01FEN_Pos (29)
11167#define EADC_AD0TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01FEN_Pos)
11169#define EADC_AD0TRGEN3_PWM01PEN_Pos (30)
11170#define EADC_AD0TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01PEN_Pos)
11172#define EADC_AD0TRGEN3_PWM01CEN_Pos (31)
11173#define EADC_AD0TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01CEN_Pos)
11175#define EADC_AD1TRGEN0_EPWM00REN_Pos (0)
11176#define EADC_AD1TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00REN_Pos)
11178#define EADC_AD1TRGEN0_EPWM00FEN_Pos (1)
11179#define EADC_AD1TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00FEN_Pos)
11181#define EADC_AD1TRGEN0_EPWM00PEN_Pos (2)
11182#define EADC_AD1TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00PEN_Pos)
11184#define EADC_AD1TRGEN0_EPWM00CEN_Pos (3)
11185#define EADC_AD1TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00CEN_Pos)
11187#define EADC_AD1TRGEN0_EPWM02REN_Pos (4)
11188#define EADC_AD1TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02REN_Pos)
11190#define EADC_AD1TRGEN0_EPWM02FEN_Pos (5)
11191#define EADC_AD1TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02FEN_Pos)
11193#define EADC_AD1TRGEN0_EPWM02PEN_Pos (6)
11194#define EADC_AD1TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02PEN_Pos)
11196#define EADC_AD1TRGEN0_EPWM02CEN_Pos (7)
11197#define EADC_AD1TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02CEN_Pos)
11199#define EADC_AD1TRGEN0_EPWM04REN_Pos (8)
11200#define EADC_AD1TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04REN_Pos)
11202#define EADC_AD1TRGEN0_EPWM04FEN_Pos (9)
11203#define EADC_AD1TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04FEN_Pos)
11205#define EADC_AD1TRGEN0_EPWM04PEN_Pos (10)
11206#define EADC_AD1TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04PEN_Pos)
11208#define EADC_AD1TRGEN0_EPWM04CEN_Pos (11)
11209#define EADC_AD1TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04CEN_Pos)
11211#define EADC_AD1TRGEN0_EPWM10REN_Pos (12)
11212#define EADC_AD1TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10REN_Pos)
11214#define EADC_AD1TRGEN0_EPWM10FEN_Pos (13)
11215#define EADC_AD1TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10FEN_Pos)
11217#define EADC_AD1TRGEN0_EPWM10PEN_Pos (14)
11218#define EADC_AD1TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10PEN_Pos)
11220#define EADC_AD1TRGEN0_EPWM10CEN_Pos (15)
11221#define EADC_AD1TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10CEN_Pos)
11223#define EADC_AD1TRGEN0_EPWM12REN_Pos (16)
11224#define EADC_AD1TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12REN_Pos)
11226#define EADC_AD1TRGEN0_EPWM120FEN_Pos (17)
11227#define EADC_AD1TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM120FEN_Pos)
11229#define EADC_AD1TRGEN0_EPWM12PEN_Pos (18)
11230#define EADC_AD1TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12PEN_Pos)
11232#define EADC_AD1TRGEN0_EPWM12CEN_Pos (19)
11233#define EADC_AD1TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12CEN_Pos)
11235#define EADC_AD1TRGEN0_EPWM14REN_Pos (20)
11236#define EADC_AD1TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14REN_Pos)
11238#define EADC_AD1TRGEN0_EPWM14FEN_Pos (21)
11239#define EADC_AD1TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14FEN_Pos)
11241#define EADC_AD1TRGEN0_EPWM14PEN_Pos (22)
11242#define EADC_AD1TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14PEN_Pos)
11244#define EADC_AD1TRGEN0_EPWM14CEN_Pos (23)
11245#define EADC_AD1TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14CEN_Pos)
11247#define EADC_AD1TRGEN0_PWM00REN_Pos (24)
11248#define EADC_AD1TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00REN_Pos)
11250#define EADC_AD1TRGEN0_PWM00FEN_Pos (25)
11251#define EADC_AD1TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00FEN_Pos)
11253#define EADC_AD1TRGEN0_PWM00PEN_Pos (26)
11254#define EADC_AD1TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00PEN_Pos)
11256#define EADC_AD1TRGEN0_PWM00CEN_Pos (27)
11257#define EADC_AD1TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00CEN_Pos)
11259#define EADC_AD1TRGEN0_PWM01REN_Pos (28)
11260#define EADC_AD1TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01REN_Pos)
11262#define EADC_AD1TRGEN0_PWM01FEN_Pos (29)
11263#define EADC_AD1TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01FEN_Pos)
11265#define EADC_AD1TRGEN0_PWM01PEN_Pos (30)
11266#define EADC_AD1TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01PEN_Pos)
11268#define EADC_AD1TRGEN0_PWM01CEN_Pos (31)
11269#define EADC_AD1TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01CEN_Pos)
11271#define EADC_AD1TRGEN1_EPWM00REN_Pos (0)
11272#define EADC_AD1TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00REN_Pos)
11274#define EADC_AD1TRGEN1_EPWM00FEN_Pos (1)
11275#define EADC_AD1TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00FEN_Pos)
11277#define EADC_AD1TRGEN1_EPWM00PEN_Pos (2)
11278#define EADC_AD1TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00PEN_Pos)
11280#define EADC_AD1TRGEN1_EPWM00CEN_Pos (3)
11281#define EADC_AD1TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00CEN_Pos)
11283#define EADC_AD1TRGEN1_EPWM02REN_Pos (4)
11284#define EADC_AD1TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02REN_Pos)
11286#define EADC_AD1TRGEN1_EPWM02FEN_Pos (5)
11287#define EADC_AD1TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02FEN_Pos)
11289#define EADC_AD1TRGEN1_EPWM02PEN_Pos (6)
11290#define EADC_AD1TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02PEN_Pos)
11292#define EADC_AD1TRGEN1_EPWM02CEN_Pos (7)
11293#define EADC_AD1TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02CEN_Pos)
11295#define EADC_AD1TRGEN1_EPWM04REN_Pos (8)
11296#define EADC_AD1TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04REN_Pos)
11298#define EADC_AD1TRGEN1_EPWM04FEN_Pos (9)
11299#define EADC_AD1TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04FEN_Pos)
11301#define EADC_AD1TRGEN1_EPWM04PEN_Pos (10)
11302#define EADC_AD1TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04PEN_Pos)
11304#define EADC_AD1TRGEN1_EPWM04CEN_Pos (11)
11305#define EADC_AD1TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04CEN_Pos)
11307#define EADC_AD1TRGEN1_EPWM10REN_Pos (12)
11308#define EADC_AD1TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10REN_Pos)
11310#define EADC_AD1TRGEN1_EPWM10FEN_Pos (13)
11311#define EADC_AD1TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10FEN_Pos)
11313#define EADC_AD1TRGEN1_EPWM10PEN_Pos (14)
11314#define EADC_AD1TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10PEN_Pos)
11316#define EADC_AD1TRGEN1_EPWM10CEN_Pos (15)
11317#define EADC_AD1TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10CEN_Pos)
11319#define EADC_AD1TRGEN1_EPWM12REN_Pos (16)
11320#define EADC_AD1TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12REN_Pos)
11322#define EADC_AD1TRGEN1_EPWM120FEN_Pos (17)
11323#define EADC_AD1TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM120FEN_Pos)
11325#define EADC_AD1TRGEN1_EPWM12PEN_Pos (18)
11326#define EADC_AD1TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12PEN_Pos)
11328#define EADC_AD1TRGEN1_EPWM12CEN_Pos (19)
11329#define EADC_AD1TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12CEN_Pos)
11331#define EADC_AD1TRGEN1_EPWM14REN_Pos (20)
11332#define EADC_AD1TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14REN_Pos)
11334#define EADC_AD1TRGEN1_EPWM14FEN_Pos (21)
11335#define EADC_AD1TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14FEN_Pos)
11337#define EADC_AD1TRGEN1_EPWM14PEN_Pos (22)
11338#define EADC_AD1TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14PEN_Pos)
11340#define EADC_AD1TRGEN1_EPWM14CEN_Pos (23)
11341#define EADC_AD1TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14CEN_Pos)
11343#define EADC_AD1TRGEN1_PWM00REN_Pos (24)
11344#define EADC_AD1TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00REN_Pos)
11346#define EADC_AD1TRGEN1_PWM00FEN_Pos (25)
11347#define EADC_AD1TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00FEN_Pos)
11349#define EADC_AD1TRGEN1_PWM00PEN_Pos (26)
11350#define EADC_AD1TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00PEN_Pos)
11352#define EADC_AD1TRGEN1_PWM00CEN_Pos (27)
11353#define EADC_AD1TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00CEN_Pos)
11355#define EADC_AD1TRGEN1_PWM01REN_Pos (28)
11356#define EADC_AD1TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01REN_Pos)
11358#define EADC_AD1TRGEN1_PWM01FEN_Pos (29)
11359#define EADC_AD1TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01FEN_Pos)
11361#define EADC_AD1TRGEN1_PWM01PEN_Pos (30)
11362#define EADC_AD1TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01PEN_Pos)
11364#define EADC_AD1TRGEN1_PWM01CEN_Pos (31)
11365#define EADC_AD1TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01CEN_Pos)
11367#define EADC_AD1TRGEN2_EPWM00REN_Pos (0)
11368#define EADC_AD1TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00REN_Pos)
11370#define EADC_AD1TRGEN2_EPWM00FEN_Pos (1)
11371#define EADC_AD1TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00FEN_Pos)
11373#define EADC_AD1TRGEN2_EPWM00PEN_Pos (2)
11374#define EADC_AD1TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00PEN_Pos)
11376#define EADC_AD1TRGEN2_EPWM00CEN_Pos (3)
11377#define EADC_AD1TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00CEN_Pos)
11379#define EADC_AD1TRGEN2_EPWM02REN_Pos (4)
11380#define EADC_AD1TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02REN_Pos)
11382#define EADC_AD1TRGEN2_EPWM02FEN_Pos (5)
11383#define EADC_AD1TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02FEN_Pos)
11385#define EADC_AD1TRGEN2_EPWM02PEN_Pos (6)
11386#define EADC_AD1TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02PEN_Pos)
11388#define EADC_AD1TRGEN2_EPWM02CEN_Pos (7)
11389#define EADC_AD1TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02CEN_Pos)
11391#define EADC_AD1TRGEN2_EPWM04REN_Pos (8)
11392#define EADC_AD1TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04REN_Pos)
11394#define EADC_AD1TRGEN2_EPWM04FEN_Pos (9)
11395#define EADC_AD1TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04FEN_Pos)
11397#define EADC_AD1TRGEN2_EPWM04PEN_Pos (10)
11398#define EADC_AD1TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04PEN_Pos)
11400#define EADC_AD1TRGEN2_EPWM04CEN_Pos (11)
11401#define EADC_AD1TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04CEN_Pos)
11403#define EADC_AD1TRGEN2_EPWM10REN_Pos (12)
11404#define EADC_AD1TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10REN_Pos)
11406#define EADC_AD1TRGEN2_EPWM10FEN_Pos (13)
11407#define EADC_AD1TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10FEN_Pos)
11409#define EADC_AD1TRGEN2_EPWM10PEN_Pos (14)
11410#define EADC_AD1TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10PEN_Pos)
11412#define EADC_AD1TRGEN2_EPWM10CEN_Pos (15)
11413#define EADC_AD1TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10CEN_Pos)
11415#define EADC_AD1TRGEN2_EPWM12REN_Pos (16)
11416#define EADC_AD1TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12REN_Pos)
11418#define EADC_AD1TRGEN2_EPWM120FEN_Pos (17)
11419#define EADC_AD1TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM120FEN_Pos)
11421#define EADC_AD1TRGEN2_EPWM12PEN_Pos (18)
11422#define EADC_AD1TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12PEN_Pos)
11424#define EADC_AD1TRGEN2_EPWM12CEN_Pos (19)
11425#define EADC_AD1TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12CEN_Pos)
11427#define EADC_AD1TRGEN2_EPWM14REN_Pos (20)
11428#define EADC_AD1TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14REN_Pos)
11430#define EADC_AD1TRGEN2_EPWM14FEN_Pos (21)
11431#define EADC_AD1TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14FEN_Pos)
11433#define EADC_AD1TRGEN2_EPWM14PEN_Pos (22)
11434#define EADC_AD1TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14PEN_Pos)
11436#define EADC_AD1TRGEN2_EPWM14CEN_Pos (23)
11437#define EADC_AD1TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14CEN_Pos)
11439#define EADC_AD1TRGEN2_PWM00REN_Pos (24)
11440#define EADC_AD1TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00REN_Pos)
11442#define EADC_AD1TRGEN2_PWM00FEN_Pos (25)
11443#define EADC_AD1TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00FEN_Pos)
11445#define EADC_AD1TRGEN2_PWM00PEN_Pos (26)
11446#define EADC_AD1TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00PEN_Pos)
11448#define EADC_AD1TRGEN2_PWM00CEN_Pos (27)
11449#define EADC_AD1TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00CEN_Pos)
11451#define EADC_AD1TRGEN2_PWM01REN_Pos (28)
11452#define EADC_AD1TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01REN_Pos)
11454#define EADC_AD1TRGEN2_PWM01FEN_Pos (29)
11455#define EADC_AD1TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01FEN_Pos)
11457#define EADC_AD1TRGEN2_PWM01PEN_Pos (30)
11458#define EADC_AD1TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01PEN_Pos)
11460#define EADC_AD1TRGEN2_PWM01CEN_Pos (31)
11461#define EADC_AD1TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01CEN_Pos)
11463#define EADC_AD1TRGEN3_EPWM00REN_Pos (0)
11464#define EADC_AD1TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00REN_Pos)
11466#define EADC_AD1TRGEN3_EPWM00FEN_Pos (1)
11467#define EADC_AD1TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00FEN_Pos)
11469#define EADC_AD1TRGEN3_EPWM00PEN_Pos (2)
11470#define EADC_AD1TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00PEN_Pos)
11472#define EADC_AD1TRGEN3_EPWM00CEN_Pos (3)
11473#define EADC_AD1TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00CEN_Pos)
11475#define EADC_AD1TRGEN3_EPWM02REN_Pos (4)
11476#define EADC_AD1TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02REN_Pos)
11478#define EADC_AD1TRGEN3_EPWM02FEN_Pos (5)
11479#define EADC_AD1TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02FEN_Pos)
11481#define EADC_AD1TRGEN3_EPWM02PEN_Pos (6)
11482#define EADC_AD1TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02PEN_Pos)
11484#define EADC_AD1TRGEN3_EPWM02CEN_Pos (7)
11485#define EADC_AD1TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02CEN_Pos)
11487#define EADC_AD1TRGEN3_EPWM04REN_Pos (8)
11488#define EADC_AD1TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04REN_Pos)
11490#define EADC_AD1TRGEN3_EPWM04FEN_Pos (9)
11491#define EADC_AD1TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04FEN_Pos)
11493#define EADC_AD1TRGEN3_EPWM04PEN_Pos (10)
11494#define EADC_AD1TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04PEN_Pos)
11496#define EADC_AD1TRGEN3_EPWM04CEN_Pos (11)
11497#define EADC_AD1TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04CEN_Pos)
11499#define EADC_AD1TRGEN3_EPWM10REN_Pos (12)
11500#define EADC_AD1TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10REN_Pos)
11502#define EADC_AD1TRGEN3_EPWM10FEN_Pos (13)
11503#define EADC_AD1TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10FEN_Pos)
11505#define EADC_AD1TRGEN3_EPWM10PEN_Pos (14)
11506#define EADC_AD1TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10PEN_Pos)
11508#define EADC_AD1TRGEN3_EPWM10CEN_Pos (15)
11509#define EADC_AD1TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10CEN_Pos)
11511#define EADC_AD1TRGEN3_EPWM12REN_Pos (16)
11512#define EADC_AD1TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12REN_Pos)
11514#define EADC_AD1TRGEN3_EPWM120FEN_Pos (17)
11515#define EADC_AD1TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM120FEN_Pos)
11517#define EADC_AD1TRGEN3_EPWM12PEN_Pos (18)
11518#define EADC_AD1TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12PEN_Pos)
11520#define EADC_AD1TRGEN3_EPWM12CEN_Pos (19)
11521#define EADC_AD1TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12CEN_Pos)
11523#define EADC_AD1TRGEN3_EPWM14REN_Pos (20)
11524#define EADC_AD1TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14REN_Pos)
11526#define EADC_AD1TRGEN3_EPWM14FEN_Pos (21)
11527#define EADC_AD1TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14FEN_Pos)
11529#define EADC_AD1TRGEN3_EPWM14PEN_Pos (22)
11530#define EADC_AD1TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14PEN_Pos)
11532#define EADC_AD1TRGEN3_EPWM14CEN_Pos (23)
11533#define EADC_AD1TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14CEN_Pos)
11535#define EADC_AD1TRGEN3_PWM00REN_Pos (24)
11536#define EADC_AD1TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00REN_Pos)
11538#define EADC_AD1TRGEN3_PWM00FEN_Pos (25)
11539#define EADC_AD1TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00FEN_Pos)
11541#define EADC_AD1TRGEN3_PWM00PEN_Pos (26)
11542#define EADC_AD1TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00PEN_Pos)
11544#define EADC_AD1TRGEN3_PWM00CEN_Pos (27)
11545#define EADC_AD1TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00CEN_Pos)
11547#define EADC_AD1TRGEN3_PWM01REN_Pos (28)
11548#define EADC_AD1TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01REN_Pos)
11550#define EADC_AD1TRGEN3_PWM01FEN_Pos (29)
11551#define EADC_AD1TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01FEN_Pos)
11553#define EADC_AD1TRGEN3_PWM01PEN_Pos (30)
11554#define EADC_AD1TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01PEN_Pos)
11556#define EADC_AD1TRGEN3_PWM01CEN_Pos (31)
11557#define EADC_AD1TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01CEN_Pos) /* EADC_CONST */ /* end of EADC register group */
11561
11562
11563/*---------------------- External Bus Interface Controller -------------------------*/
11569 typedef struct {
11570
11571
11598 __IO uint32_t CTL;
11599
11640 __IO uint32_t TCTL[4];
11641
11651 __IO uint32_t KEY0;
11652
11662 __IO uint32_t KEY1;
11663
11673 __IO uint32_t KEY2;
11674
11684 __IO uint32_t KEY3;
11685
11686} EBI_T;
11687
11693#define EBI_CTL_MCLKDIV_Pos (8)
11694#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos)
11696#define EBI_CTL_CRYPTOEN_Pos (24)
11697#define EBI_CTL_CRYPTOEN_Msk (0xful << EBI_CTL_CRYPTOEN_Pos)
11699#define EBI_CTL_CSPOLINV_Pos (28)
11700#define EBI_CTL_CSPOLINV_Msk (0xful << EBI_CTL_CSPOLINV_Pos)
11702#define EBI_TCTL_TALE_Pos (0)
11703#define EBI_TCTL_TALE_Msk (0x7ul << EBI_TCTL_TALE_Pos)
11705#define EBI_TCTL_TACC_Pos (3)
11706#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos)
11708#define EBI_TCTL_TAHD_Pos (8)
11709#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos)
11711#define EBI_TCTL_W2X_Pos (12)
11712#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos)
11714#define EBI_TCTL_R2W_Pos (16)
11715#define EBI_TCTL_R2W_Msk (0xful << EBI_TCTL_R2W_Pos)
11717#define EBI_TCTL_R2R_Pos (24)
11718#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos)
11720#define EBI_TCTL_CSEN_Pos (28)
11721#define EBI_TCTL_CSEN_Msk (0x1ul << EBI_TCTL_CSEN_Pos)
11723#define EBI_TCTL_DW16_Pos (29)
11724#define EBI_TCTL_DW16_Msk (0x1ul << EBI_TCTL_DW16_Pos)
11726#define EBI_TCTL_SEPEN_Pos (30)
11727#define EBI_TCTL_SEPEN_Msk (0x1ul << EBI_TCTL_SEPEN_Pos)
11729#define EBI_KEY0_KEY_Pos (0)
11730#define EBI_KEY0_KEY_Msk (0xfffffffful << EBI_KEY0_KEY_Pos)
11732#define EBI_KEY1_KEY_Pos (0)
11733#define EBI_KEY1_KEY_Msk (0xfffffffful << EBI_KEY1_KEY_Pos)
11735#define EBI_KEY2_KEY_Pos (0)
11736#define EBI_KEY2_KEY_Msk (0xfffffffful << EBI_KEY2_KEY_Pos)
11738#define EBI_KEY3_KEY_Pos (0)
11739#define EBI_KEY3_KEY_Msk (0xfffffffful << EBI_KEY3_KEY_Pos) /* EBI_CONST */ /* end of EBI register group */
11743
11744
11745/*---------------------- Ethernet MAC Controller -------------------------*/
11751 typedef struct {
11752
11753
11788 __IO uint32_t CAMCTL;
11789
11804 __IO uint32_t CAMEN;
11805
11822 __IO uint32_t CAM0M;
11823
11838 __IO uint32_t CAM0L;
11839
11856 __IO uint32_t CAM1M;
11857
11872 __IO uint32_t CAM1L;
11873
11890 __IO uint32_t CAM2M;
11891
11906 __IO uint32_t CAM2L;
11907
11924 __IO uint32_t CAM3M;
11925
11940 __IO uint32_t CAM3L;
11941
11958 __IO uint32_t CAM4M;
11959
11974 __IO uint32_t CAM4L;
11975
11992 __IO uint32_t CAM5M;
11993
12008 __IO uint32_t CAM5L;
12009
12026 __IO uint32_t CAM6M;
12027
12042 __IO uint32_t CAM6L;
12043
12060 __IO uint32_t CAM7M;
12061
12076 __IO uint32_t CAM7L;
12077
12094 __IO uint32_t CAM8M;
12095
12110 __IO uint32_t CAM8L;
12111
12128 __IO uint32_t CAM9M;
12129
12144 __IO uint32_t CAM9L;
12145
12162 __IO uint32_t CAM10M;
12163
12178 __IO uint32_t CAM10L;
12179
12196 __IO uint32_t CAM11M;
12197
12212 __IO uint32_t CAM11L;
12213
12230 __IO uint32_t CAM12M;
12231
12246 __IO uint32_t CAM12L;
12247
12264 __IO uint32_t CAM13M;
12265
12280 __IO uint32_t CAM13L;
12281
12298 __IO uint32_t CAM14M;
12299
12314 __IO uint32_t CAM14L;
12315
12328 __IO uint32_t CAM15MSB;
12329
12341 __IO uint32_t CAM15LSB;
12342
12357 __IO uint32_t TXDSA;
12358
12373 __IO uint32_t RXDSA;
12374
12481 __IO uint32_t CTL;
12482
12493 __IO uint32_t MIIMDAT;
12494
12529 __IO uint32_t MIIMCTL;
12530
12568 __IO uint32_t FIFOCTL;
12569
12583 __O uint32_t TXST;
12584
12598 __O uint32_t RXST;
12599
12612 __IO uint32_t MRFL;
12613
12770 __IO uint32_t INTEN;
12771
12948 __IO uint32_t INTSTS;
12949
12998 __IO uint32_t GENSTS;
12999
13014 __IO uint32_t MPCNT;
13015
13027 __I uint32_t RPCNT;
13029 uint32_t RESERVE0[2];
13031
13032
13045 __IO uint32_t FRSTS;
13046
13058 __I uint32_t CTXDSA;
13059
13071 __I uint32_t CTXBSA;
13072
13084 __I uint32_t CRXDSA;
13085
13097 __I uint32_t CRXBSA;
13099 uint32_t RESERVE1[9];
13101
13102
13134 __IO uint32_t TSCTL;
13136 uint32_t RESERVE2[3];
13138
13139
13151 __I uint32_t TSSEC;
13152
13164 __I uint32_t TSSUBSEC;
13165
13177 __IO uint32_t TSINC;
13178
13191 __IO uint32_t TSADDEND;
13192
13205 __IO uint32_t UPDSEC;
13206
13219 __IO uint32_t UPDSUBSEC;
13220
13233 __IO uint32_t ALMSEC;
13234
13247 __IO uint32_t ALMSUBSEC;
13248
13249} EMAC_T;
13250
13256#define EMAC_CAMCTL_AUP_Pos (0)
13257#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos)
13259#define EMAC_CAMCTL_AMP_Pos (1)
13260#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos)
13262#define EMAC_CAMCTL_ABP_Pos (2)
13263#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos)
13265#define EMAC_CAMCTL_COMPEN_Pos (3)
13266#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos)
13268#define EMAC_CAMCTL_CMPEN_Pos (4)
13269#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos)
13271#define EMAC_CAMEN_CAMxEN_Pos (0)
13272#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos)
13274#define EMAC_CAM0M_MACADDR2_Pos (0)
13275#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos)
13277#define EMAC_CAM0M_MACADDR3_Pos (8)
13278#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos)
13280#define EMAC_CAM0M_MACADDR4_Pos (16)
13281#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos)
13283#define EMAC_CAM0M_MACADDR5_Pos (24)
13284#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos)
13286#define EMAC_CAM0L_Rserved_Pos (0)
13287#define EMAC_CAM0L_Rserved_Msk (0xfffful << EMAC_CAM0L_Rserved_Pos)
13289#define EMAC_CAM0L_MACADDR0_Pos (16)
13290#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos)
13292#define EMAC_CAM0L_MACADDR1_Pos (24)
13293#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos)
13295#define EMAC_CAM1M_MACADDR2_Pos (0)
13296#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos)
13298#define EMAC_CAM1M_MACADDR3_Pos (8)
13299#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos)
13301#define EMAC_CAM1M_MACADDR4_Pos (16)
13302#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos)
13304#define EMAC_CAM1M_MACADDR5_Pos (24)
13305#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos)
13307#define EMAC_CAM1L_Rserved_Pos (0)
13308#define EMAC_CAM1L_Rserved_Msk (0xfffful << EMAC_CAM1L_Rserved_Pos)
13310#define EMAC_CAM1L_MACADDR0_Pos (16)
13311#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos)
13313#define EMAC_CAM1L_MACADDR1_Pos (24)
13314#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos)
13316#define EMAC_CAM2M_MACADDR2_Pos (0)
13317#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos)
13319#define EMAC_CAM2M_MACADDR3_Pos (8)
13320#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos)
13322#define EMAC_CAM2M_MACADDR4_Pos (16)
13323#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos)
13325#define EMAC_CAM2M_MACADDR5_Pos (24)
13326#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos)
13328#define EMAC_CAM2L_Rserved_Pos (0)
13329#define EMAC_CAM2L_Rserved_Msk (0xfffful << EMAC_CAM2L_Rserved_Pos)
13331#define EMAC_CAM2L_MACADDR0_Pos (16)
13332#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos)
13334#define EMAC_CAM2L_MACADDR1_Pos (24)
13335#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos)
13337#define EMAC_CAM3M_MACADDR2_Pos (0)
13338#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos)
13340#define EMAC_CAM3M_MACADDR3_Pos (8)
13341#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos)
13343#define EMAC_CAM3M_MACADDR4_Pos (16)
13344#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos)
13346#define EMAC_CAM3M_MACADDR5_Pos (24)
13347#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos)
13349#define EMAC_CAM3L_Rserved_Pos (0)
13350#define EMAC_CAM3L_Rserved_Msk (0xfffful << EMAC_CAM3L_Rserved_Pos)
13352#define EMAC_CAM3L_MACADDR0_Pos (16)
13353#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos)
13355#define EMAC_CAM3L_MACADDR1_Pos (24)
13356#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos)
13358#define EMAC_CAM4M_MACADDR2_Pos (0)
13359#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos)
13361#define EMAC_CAM4M_MACADDR3_Pos (8)
13362#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos)
13364#define EMAC_CAM4M_MACADDR4_Pos (16)
13365#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos)
13367#define EMAC_CAM4M_MACADDR5_Pos (24)
13368#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos)
13370#define EMAC_CAM4L_Rserved_Pos (0)
13371#define EMAC_CAM4L_Rserved_Msk (0xfffful << EMAC_CAM4L_Rserved_Pos)
13373#define EMAC_CAM4L_MACADDR0_Pos (16)
13374#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos)
13376#define EMAC_CAM4L_MACADDR1_Pos (24)
13377#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos)
13379#define EMAC_CAM5M_MACADDR2_Pos (0)
13380#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos)
13382#define EMAC_CAM5M_MACADDR3_Pos (8)
13383#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos)
13385#define EMAC_CAM5M_MACADDR4_Pos (16)
13386#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos)
13388#define EMAC_CAM5M_MACADDR5_Pos (24)
13389#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos)
13391#define EMAC_CAM5L_Rserved_Pos (0)
13392#define EMAC_CAM5L_Rserved_Msk (0xfffful << EMAC_CAM5L_Rserved_Pos)
13394#define EMAC_CAM5L_MACADDR0_Pos (16)
13395#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos)
13397#define EMAC_CAM5L_MACADDR1_Pos (24)
13398#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos)
13400#define EMAC_CAM6M_MACADDR2_Pos (0)
13401#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos)
13403#define EMAC_CAM6M_MACADDR3_Pos (8)
13404#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos)
13406#define EMAC_CAM6M_MACADDR4_Pos (16)
13407#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos)
13409#define EMAC_CAM6M_MACADDR5_Pos (24)
13410#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos)
13412#define EMAC_CAM6L_Rserved_Pos (0)
13413#define EMAC_CAM6L_Rserved_Msk (0xfffful << EMAC_CAM6L_Rserved_Pos)
13415#define EMAC_CAM6L_MACADDR0_Pos (16)
13416#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos)
13418#define EMAC_CAM6L_MACADDR1_Pos (24)
13419#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos)
13421#define EMAC_CAM7M_MACADDR2_Pos (0)
13422#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos)
13424#define EMAC_CAM7M_MACADDR3_Pos (8)
13425#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos)
13427#define EMAC_CAM7M_MACADDR4_Pos (16)
13428#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos)
13430#define EMAC_CAM7M_MACADDR5_Pos (24)
13431#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos)
13433#define EMAC_CAM7L_Rserved_Pos (0)
13434#define EMAC_CAM7L_Rserved_Msk (0xfffful << EMAC_CAM7L_Rserved_Pos)
13436#define EMAC_CAM7L_MACADDR0_Pos (16)
13437#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos)
13439#define EMAC_CAM7L_MACADDR1_Pos (24)
13440#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos)
13442#define EMAC_CAM8M_MACADDR2_Pos (0)
13443#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos)
13445#define EMAC_CAM8M_MACADDR3_Pos (8)
13446#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos)
13448#define EMAC_CAM8M_MACADDR4_Pos (16)
13449#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos)
13451#define EMAC_CAM8M_MACADDR5_Pos (24)
13452#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos)
13454#define EMAC_CAM8L_Rserved_Pos (0)
13455#define EMAC_CAM8L_Rserved_Msk (0xfffful << EMAC_CAM8L_Rserved_Pos)
13457#define EMAC_CAM8L_MACADDR0_Pos (16)
13458#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos)
13460#define EMAC_CAM8L_MACADDR1_Pos (24)
13461#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos)
13463#define EMAC_CAM9M_MACADDR2_Pos (0)
13464#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos)
13466#define EMAC_CAM9M_MACADDR3_Pos (8)
13467#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos)
13469#define EMAC_CAM9M_MACADDR4_Pos (16)
13470#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos)
13472#define EMAC_CAM9M_MACADDR5_Pos (24)
13473#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos)
13475#define EMAC_CAM9L_Rserved_Pos (0)
13476#define EMAC_CAM9L_Rserved_Msk (0xfffful << EMAC_CAM9L_Rserved_Pos)
13478#define EMAC_CAM9L_MACADDR0_Pos (16)
13479#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos)
13481#define EMAC_CAM9L_MACADDR1_Pos (24)
13482#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos)
13484#define EMAC_CAM10M_MACADDR2_Pos (0)
13485#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos)
13487#define EMAC_CAM10M_MACADDR3_Pos (8)
13488#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos)
13490#define EMAC_CAM10M_MACADDR4_Pos (16)
13491#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos)
13493#define EMAC_CAM10M_MACADDR5_Pos (24)
13494#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos)
13496#define EMAC_CAM10L_Rserved_Pos (0)
13497#define EMAC_CAM10L_Rserved_Msk (0xfffful << EMAC_CAM10L_Rserved_Pos)
13499#define EMAC_CAM10L_MACADDR0_Pos (16)
13500#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos)
13502#define EMAC_CAM10L_MACADDR1_Pos (24)
13503#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos)
13505#define EMAC_CAM11M_MACADDR2_Pos (0)
13506#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos)
13508#define EMAC_CAM11M_MACADDR3_Pos (8)
13509#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos)
13511#define EMAC_CAM11M_MACADDR4_Pos (16)
13512#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos)
13514#define EMAC_CAM11M_MACADDR5_Pos (24)
13515#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos)
13517#define EMAC_CAM11L_Rserved_Pos (0)
13518#define EMAC_CAM11L_Rserved_Msk (0xfffful << EMAC_CAM11L_Rserved_Pos)
13520#define EMAC_CAM11L_MACADDR0_Pos (16)
13521#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos)
13523#define EMAC_CAM11L_MACADDR1_Pos (24)
13524#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos)
13526#define EMAC_CAM12M_MACADDR2_Pos (0)
13527#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos)
13529#define EMAC_CAM12M_MACADDR3_Pos (8)
13530#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos)
13532#define EMAC_CAM12M_MACADDR4_Pos (16)
13533#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos)
13535#define EMAC_CAM12M_MACADDR5_Pos (24)
13536#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos)
13538#define EMAC_CAM12L_Rserved_Pos (0)
13539#define EMAC_CAM12L_Rserved_Msk (0xfffful << EMAC_CAM12L_Rserved_Pos)
13541#define EMAC_CAM12L_MACADDR0_Pos (16)
13542#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos)
13544#define EMAC_CAM12L_MACADDR1_Pos (24)
13545#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos)
13547#define EMAC_CAM13M_MACADDR2_Pos (0)
13548#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos)
13550#define EMAC_CAM13M_MACADDR3_Pos (8)
13551#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos)
13553#define EMAC_CAM13M_MACADDR4_Pos (16)
13554#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos)
13556#define EMAC_CAM13M_MACADDR5_Pos (24)
13557#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos)
13559#define EMAC_CAM13L_Rserved_Pos (0)
13560#define EMAC_CAM13L_Rserved_Msk (0xfffful << EMAC_CAM13L_Rserved_Pos)
13562#define EMAC_CAM13L_MACADDR0_Pos (16)
13563#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos)
13565#define EMAC_CAM13L_MACADDR1_Pos (24)
13566#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos)
13568#define EMAC_CAM14M_MACADDR2_Pos (0)
13569#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos)
13571#define EMAC_CAM14M_MACADDR3_Pos (8)
13572#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos)
13574#define EMAC_CAM14M_MACADDR4_Pos (16)
13575#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos)
13577#define EMAC_CAM14M_MACADDR5_Pos (24)
13578#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos)
13580#define EMAC_CAM14L_Rserved_Pos (0)
13581#define EMAC_CAM14L_Rserved_Msk (0xfffful << EMAC_CAM14L_Rserved_Pos)
13583#define EMAC_CAM14L_MACADDR0_Pos (16)
13584#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos)
13586#define EMAC_CAM14L_MACADDR1_Pos (24)
13587#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos)
13589#define EMAC_CAM15MSB_OPCODE_Pos (0)
13590#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos)
13592#define EMAC_CAM15MSB_LENGTH_Pos (16)
13593#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos)
13595#define EMAC_CAM15LSB_OPERAND_Pos (24)
13596#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos)
13598#define EMAC_TXDSA_TXDSA_Pos (0)
13599#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos)
13601#define EMAC_RXDSA_RXDSA_Pos (0)
13602#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos)
13604#define EMAC_CTL_RXON_Pos (0)
13605#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos)
13607#define EMAC_CTL_ALP_Pos (1)
13608#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos)
13610#define EMAC_CTL_ARP_Pos (2)
13611#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos)
13613#define EMAC_CTL_ACP_Pos (3)
13614#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos)
13616#define EMAC_CTL_AEP_Pos (4)
13617#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos)
13619#define EMAC_CTL_STRIPCRC_Pos (5)
13620#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos)
13622#define EMAC_CTL_WOLEN_Pos (6)
13623#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos)
13625#define EMAC_CTL_TXON_Pos (8)
13626#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos)
13628#define EMAC_CTL_NODEF_Pos (9)
13629#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos)
13631#define EMAC_CTL_SDPZ_Pos (16)
13632#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos)
13634#define EMAC_CTL_SQECHKEN_Pos (17)
13635#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos)
13637#define EMAC_CTL_FUDUP_Pos (18)
13638#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos)
13640#define EMAC_CTL_RMIIRXCTL_Pos (19)
13641#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos)
13643#define EMAC_CTL_OPMODE_Pos (20)
13644#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos)
13646#define EMAC_CTL_RMIIEN_Pos (22)
13647#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos)
13649#define EMAC_CTL_RST_Pos (24)
13650#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos)
13652#define EMAC_MIIMDAT_DATA_Pos (0)
13653#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos)
13655#define EMAC_MIIMCTL_PHYREG_Pos (0)
13656#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos)
13658#define EMAC_MIIMCTL_PHYADDR_Pos (8)
13659#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos)
13661#define EMAC_MIIMCTL_WRITE_Pos (16)
13662#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos)
13664#define EMAC_MIIMCTL_BUSY_Pos (17)
13665#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos)
13667#define EMAC_MIIMCTL_PREAMSP_Pos (18)
13668#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos)
13670#define EMAC_MIIMCTL_MDCON_Pos (19)
13671#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos)
13673#define EMAC_FIFOCTL_RXFIFOTH_Pos (0)
13674#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos)
13676#define EMAC_FIFOCTL_TXFIFOTH_Pos (8)
13677#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos)
13679#define EMAC_FIFOCTL_BURSTLEN_Pos (20)
13680#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos)
13682#define EMAC_TXST_TXST_Pos (0)
13683#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos)
13685#define EMAC_RXST_RXST_Pos (0)
13686#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos)
13688#define EMAC_MRFL_MRFL_Pos (0)
13689#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos)
13691#define EMAC_INTEN_RXIEN_Pos (0)
13692#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos)
13694#define EMAC_INTEN_CRCEIEN_Pos (1)
13695#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos)
13697#define EMAC_INTEN_RXOVIEN_Pos (2)
13698#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos)
13700#define EMAC_INTEN_LPIEN_Pos (3)
13701#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos)
13703#define EMAC_INTEN_RXGDIEN_Pos (4)
13704#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos)
13706#define EMAC_INTEN_ALIEIEN_Pos (5)
13707#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos)
13709#define EMAC_INTEN_RPIEN_Pos (6)
13710#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos)
13712#define EMAC_INTEN_MPCOVIEN_Pos (7)
13713#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos)
13715#define EMAC_INTEN_MFLEIEN_Pos (8)
13716#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos)
13718#define EMAC_INTEN_DENIEN_Pos (9)
13719#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos)
13721#define EMAC_INTEN_RDUIEN_Pos (10)
13722#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos)
13724#define EMAC_INTEN_RXBEIEN_Pos (11)
13725#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos)
13727#define EMAC_INTEN_CFRIEN_Pos (14)
13728#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos)
13730#define EMAC_INTEN_WOLIEN_Pos (15)
13731#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos)
13733#define EMAC_INTEN_TXIEN_Pos (16)
13734#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos)
13736#define EMAC_INTEN_TXUDIEN_Pos (17)
13737#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos)
13739#define EMAC_INTEN_TXCPIEN_Pos (18)
13740#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos)
13742#define EMAC_INTEN_EXDEFIEN_Pos (19)
13743#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos)
13745#define EMAC_INTEN_NCSIEN_Pos (20)
13746#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos)
13748#define EMAC_INTEN_TXABTIEN_Pos (21)
13749#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos)
13751#define EMAC_INTEN_LCIEN_Pos (22)
13752#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos)
13754#define EMAC_INTEN_TDUIEN_Pos (23)
13755#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos)
13757#define EMAC_INTEN_TXBEIEN_Pos (24)
13758#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos)
13760#define EMAC_INTEN_TSALMIEN_Pos (28)
13761#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos)
13763#define EMAC_INTSTS_RXIF_Pos (0)
13764#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos)
13766#define EMAC_INTSTS_CRCEIF_Pos (1)
13767#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos)
13769#define EMAC_INTSTS_RXOVIF_Pos (2)
13770#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos)
13772#define EMAC_INTSTS_LPIF_Pos (3)
13773#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos)
13775#define EMAC_INTSTS_RXGDIF_Pos (4)
13776#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos)
13778#define EMAC_INTSTS_ALIEIF_Pos (5)
13779#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos)
13781#define EMAC_INTSTS_RPIF_Pos (6)
13782#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos)
13784#define EMAC_INTSTS_MPCOVIF_Pos (7)
13785#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos)
13787#define EMAC_INTSTS_MFLEIF_Pos (8)
13788#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos)
13790#define EMAC_INTSTS_DENIF_Pos (9)
13791#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos)
13793#define EMAC_INTSTS_RDUIF_Pos (10)
13794#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos)
13796#define EMAC_INTSTS_RXBEIF_Pos (11)
13797#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos)
13799#define EMAC_INTSTS_CFRIF_Pos (14)
13800#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos)
13802#define EMAC_INTSTS_WOLIF_Pos (15)
13803#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos)
13805#define EMAC_INTSTS_TXIF_Pos (16)
13806#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos)
13808#define EMAC_INTSTS_TXUDIF_Pos (17)
13809#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos)
13811#define EMAC_INTSTS_TXCPIF_Pos (18)
13812#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos)
13814#define EMAC_INTSTS_EXDEFIF_Pos (19)
13815#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos)
13817#define EMAC_INTSTS_NCSIF_Pos (20)
13818#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos)
13820#define EMAC_INTSTS_TXABTIF_Pos (21)
13821#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos)
13823#define EMAC_INTSTS_LCIF_Pos (22)
13824#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos)
13826#define EMAC_INTSTS_TDUIF_Pos (23)
13827#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos)
13829#define EMAC_INTSTS_TXBEIF_Pos (24)
13830#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos)
13832#define EMAC_INTSTS_TSALMIF_Pos (28)
13833#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos)
13835#define EMAC_GENSTS_CFRIF_Pos (0)
13836#define EMAC_GENSTS_CFRIF_Msk (0x1ul << EMAC_GENSTS_CFRIF_Pos)
13838#define EMAC_GENSTS_RXHALT_Pos (1)
13839#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos)
13841#define EMAC_GENSTS_RXFFULL_Pos (2)
13842#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos)
13844#define EMAC_GENSTS_COLCNT_Pos (4)
13845#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos)
13847#define EMAC_GENSTS_DEF_Pos (8)
13848#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos)
13850#define EMAC_GENSTS_TXPAUSED_Pos (9)
13851#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos)
13853#define EMAC_GENSTS_SQE_Pos (10)
13854#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos)
13856#define EMAC_GENSTS_TXHALT_Pos (11)
13857#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos)
13859#define EMAC_GENSTS_RPSTS_Pos (12)
13860#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos)
13862#define EMAC_MPCNT_MPCNT_Pos (0)
13863#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos)
13865#define EMAC_RPCNT_RPCNT_Pos (0)
13866#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos)
13868#define EMAC_FRSTS_RXFLT_Pos (0)
13869#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos)
13871#define EMAC_CTXDSA_CTXDSA_Pos (0)
13872#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos)
13874#define EMAC_CTXBSA_CTXBSA_Pos (0)
13875#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos)
13877#define EMAC_CRXDSA_CRXDSA_Pos (0)
13878#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos)
13880#define EMAC_CRXBSA_CRXBSA_Pos (0)
13881#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos)
13883#define EMAC_TSCTL_TSEN_Pos (0)
13884#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos)
13886#define EMAC_TSCTL_TSIEN_Pos (1)
13887#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos)
13889#define EMAC_TSCTL_TSMODE_Pos (2)
13890#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos)
13892#define EMAC_TSCTL_TSUPDATE_Pos (3)
13893#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos)
13895#define EMAC_TSCTL_TSALMEN_Pos (5)
13896#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos)
13898#define EMAC_TSSEC_SEC_Pos (0)
13899#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos)
13901#define EMAC_TSSUBSEC_SUBSEC_Pos (0)
13902#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos)
13904#define EMAC_TSINC_CNTINC_Pos (0)
13905#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos)
13907#define EMAC_TSADDEND_ADDEND_Pos (0)
13908#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos)
13910#define EMAC_UPDSEC_SEC_Pos (0)
13911#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos)
13913#define EMAC_UPDSUBSEC_SUBSEC_Pos (0)
13914#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos)
13916#define EMAC_ALMSEC_SEC_Pos (0)
13917#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos)
13919#define EMAC_ALMSUBSEC_SUBSEC_Pos (0)
13920#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /* EMAC_CONST */ /* end of EMAC register group */
13924
13925
13926/*---------------------- Enhanced PWM Generator -------------------------*/
13932 typedef struct {
13933
13934
14036 __IO uint32_t CTL;
14037
14086 __IO uint32_t STATUS;
14087
14103 __IO uint32_t PERIOD;
14104
14120 __IO uint32_t CMPDAT[3];
14121
14136 __IO uint32_t MSKEN;
14137
14151 __IO uint32_t MSK;
14152
14163 __IO uint32_t ASYMCMP0;
14164
14175 __IO uint32_t ASYMCMP2;
14176
14187 __IO uint32_t ASYMCMP4;
14188
14218 __IO uint32_t DTCTL;
14219
14233 __IO uint32_t BRKOUT;
14234
14248 __IO uint32_t NPCTL;
14249
14328 __IO uint32_t ASYMCTL;
14329
14341 __IO uint32_t PERIODCNT;
14342
14369 __IO uint32_t EINTCTL;
14370
14385 __IO uint32_t OUTEN0;
14386
14387} EPWM_T;
14388
14394#define EPWM_CTL_MODE_Pos (0)
14395#define EPWM_CTL_MODE_Msk (0x3ul << EPWM_CTL_MODE_Pos)
14397#define EPWM_CTL_CLKDIV_Pos (2)
14398#define EPWM_CTL_CLKDIV_Msk (0x3ul << EPWM_CTL_CLKDIV_Pos)
14400#define EPWM_CTL_PWMIEN_Pos (4)
14401#define EPWM_CTL_PWMIEN_Msk (0x1ul << EPWM_CTL_PWMIEN_Pos)
14403#define EPWM_CTL_BRKIEN_Pos (5)
14404#define EPWM_CTL_BRKIEN_Msk (0x1ul << EPWM_CTL_BRKIEN_Pos)
14406#define EPWM_CTL_LOAD_Pos (6)
14407#define EPWM_CTL_LOAD_Msk (0x1ul << EPWM_CTL_LOAD_Pos)
14409#define EPWM_CTL_CNTEN_Pos (7)
14410#define EPWM_CTL_CNTEN_Msk (0x1ul << EPWM_CTL_CNTEN_Pos)
14412#define EPWM_CTL_INTTYPE_Pos (8)
14413#define EPWM_CTL_INTTYPE_Msk (0x1ul << EPWM_CTL_INTTYPE_Pos)
14415#define EPWM_CTL_PINV_Pos (9)
14416#define EPWM_CTL_PINV_Msk (0x1ul << EPWM_CTL_PINV_Pos)
14418#define EPWM_CTL_CNTCLR_Pos (11)
14419#define EPWM_CTL_CNTCLR_Msk (0x1ul << EPWM_CTL_CNTCLR_Pos)
14421#define EPWM_CTL_CNTTYPE_Pos (12)
14422#define EPWM_CTL_CNTTYPE_Msk (0x1ul << EPWM_CTL_CNTTYPE_Pos)
14424#define EPWM_CTL_GROUPEN_Pos (13)
14425#define EPWM_CTL_GROUPEN_Msk (0x1ul << EPWM_CTL_GROUPEN_Pos)
14427#define EPWM_CTL_BRKP0INV_Pos (14)
14428#define EPWM_CTL_BRKP0INV_Msk (0x1ul << EPWM_CTL_BRKP0INV_Pos)
14430#define EPWM_CTL_BRKP1INV_Pos (15)
14431#define EPWM_CTL_BRKP1INV_Msk (0x1ul << EPWM_CTL_BRKP1INV_Pos)
14433#define EPWM_CTL_BRKP0EN_Pos (16)
14434#define EPWM_CTL_BRKP0EN_Msk (0x1ul << EPWM_CTL_BRKP0EN_Pos)
14436#define EPWM_CTL_BRKP1EN_Pos (17)
14437#define EPWM_CTL_BRKP1EN_Msk (0x1ul << EPWM_CTL_BRKP1EN_Pos)
14439#define EPWM_CTL_BRK1SEL_Pos (18)
14440#define EPWM_CTL_BRK1SEL_Msk (0x3ul << EPWM_CTL_BRK1SEL_Pos)
14442#define EPWM_CTL_BRK0NFSEL_Pos (20)
14443#define EPWM_CTL_BRK0NFSEL_Msk (0x3ul << EPWM_CTL_BRK0NFSEL_Pos)
14445#define EPWM_CTL_BRK1NFSEL_Pos (22)
14446#define EPWM_CTL_BRK1NFSEL_Msk (0x3ul << EPWM_CTL_BRK1NFSEL_Pos)
14448#define EPWM_CTL_CPO0BKEN_Pos (24)
14449#define EPWM_CTL_CPO0BKEN_Msk (0x1ul << EPWM_CTL_CPO0BKEN_Pos)
14451#define EPWM_CTL_CPO1BKEN_Pos (25)
14452#define EPWM_CTL_CPO1BKEN_Msk (0x1ul << EPWM_CTL_CPO1BKEN_Pos)
14454#define EPWM_CTL_CPO2BKEN_Pos (26)
14455#define EPWM_CTL_CPO2BKEN_Msk (0x1ul << EPWM_CTL_CPO2BKEN_Pos)
14457#define EPWM_CTL_LVDBKEN_Pos (27)
14458#define EPWM_CTL_LVDBKEN_Msk (0x1ul << EPWM_CTL_LVDBKEN_Pos)
14460#define EPWM_CTL_BRK0NFDIS_Pos (28)
14461#define EPWM_CTL_BRK0NFDIS_Msk (0x1ul << EPWM_CTL_BRK0NFDIS_Pos)
14463#define EPWM_CTL_BRK1NFDIS_Pos (29)
14464#define EPWM_CTL_BRK1NFDIS_Msk (0x1ul << EPWM_CTL_BRK1NFDIS_Pos)
14466#define EPWM_CTL_CTRLD_Pos (31)
14467#define EPWM_CTL_CTRLD_Msk (0x1ul << EPWM_CTL_CTRLD_Pos)
14469#define EPWM_STATUS_BRKIF0_Pos (0)
14470#define EPWM_STATUS_BRKIF0_Msk (0x1ul << EPWM_STATUS_BRKIF0_Pos)
14472#define EPWM_STATUS_BRKIF1_Pos (1)
14473#define EPWM_STATUS_BRKIF1_Msk (0x1ul << EPWM_STATUS_BRKIF1_Pos)
14475#define EPWM_STATUS_PIF_Pos (2)
14476#define EPWM_STATUS_PIF_Msk (0x1ul << EPWM_STATUS_PIF_Pos)
14478#define EPWM_STATUS_EIF0_Pos (4)
14479#define EPWM_STATUS_EIF0_Msk (0x1ul << EPWM_STATUS_EIF0_Pos)
14481#define EPWM_STATUS_EIF2_Pos (5)
14482#define EPWM_STATUS_EIF2_Msk (0x1ul << EPWM_STATUS_EIF2_Pos)
14484#define EPWM_STATUS_EIF4_Pos (6)
14485#define EPWM_STATUS_EIF4_Msk (0x1ul << EPWM_STATUS_EIF4_Pos)
14487#define EPWM_STATUS_BRK0LOCK_Pos (8)
14488#define EPWM_STATUS_BRK0LOCK_Msk (0x1ul << EPWM_STATUS_BRK0LOCK_Pos)
14490#define EPWM_STATUS_BRK0STS_Pos (24)
14491#define EPWM_STATUS_BRK0STS_Msk (0x1ul << EPWM_STATUS_BRK0STS_Pos)
14493#define EPWM_STATUS_BRK1STS_Pos (25)
14494#define EPWM_STATUS_BRK1STS_Msk (0x1ul << EPWM_STATUS_BRK1STS_Pos)
14496#define EPWM_PERIOD_PERIOD_Pos (0)
14497#define EPWM_PERIOD_PERIOD_Msk (0xfffful << EPWM_PERIOD_PERIOD_Pos)
14499#define EPWM_CMPDAT0_CMP_Pos (0)
14500#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos)
14502#define EPWM_CMPDAT2_CMP_Pos (0)
14503#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos)
14505#define EPWM_CMPDAT4_CMP_Pos (0)
14506#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos)
14508#define EPWM_MSKEN_MSKEN_Pos (0)
14509#define EPWM_MSKEN_MSKEN_Msk (0x3ful << EPWM_MSKEN_MSKEN_Pos)
14511#define EPWM_MSK_MSKDAT_Pos (0)
14512#define EPWM_MSK_MSKDAT_Msk (0x3ful << EPWM_MSK_MSKDAT_Pos)
14514#define EPWM_ASYMCMP0_CMP_Pos (0)
14515#define EPWM_ASYMCMP0_CMP_Msk (0xfffful << EPWM_ASYMCMP0_CMP_Pos)
14517#define EPWM_ASYMCMP2_CMP_Pos (0)
14518#define EPWM_ASYMCMP2_CMP_Msk (0xfffful << EPWM_ASYMCMP2_CMP_Pos)
14520#define EPWM_ASYMCMP4_CMP_Pos (0)
14521#define EPWM_ASYMCMP4_CMP_Msk (0xfffful << EPWM_ASYMCMP4_CMP_Pos)
14523#define EPWM_DTCTL_DTCNT_Pos (0)
14524#define EPWM_DTCTL_DTCNT_Msk (0x7fful << EPWM_DTCTL_DTCNT_Pos)
14526#define EPWM_DTCTL_DTEN0_Pos (16)
14527#define EPWM_DTCTL_DTEN0_Msk (0x1ul << EPWM_DTCTL_DTEN0_Pos)
14529#define EPWM_DTCTL_DTEN2_Pos (17)
14530#define EPWM_DTCTL_DTEN2_Msk (0x1ul << EPWM_DTCTL_DTEN2_Pos)
14532#define EPWM_DTCTL_DTEN4_Pos (18)
14533#define EPWM_DTCTL_DTEN4_Msk (0x1ul << EPWM_DTCTL_DTEN4_Pos)
14535#define EPWM_BRKOUT_BRKOUT_Pos (0)
14536#define EPWM_BRKOUT_BRKOUT_Msk (0x3ful << EPWM_BRKOUT_BRKOUT_Pos)
14538#define EPWM_NPCTL_NEGPOLAR_Pos (0)
14539#define EPWM_NPCTL_NEGPOLAR_Msk (0x3ful << EPWM_NPCTL_NEGPOLAR_Pos)
14541#define EPWM_ASYMCTL_ASYMEN_Pos (0)
14542#define EPWM_ASYMCTL_ASYMEN_Msk (0x1ul << EPWM_ASYMCTL_ASYMEN_Pos)
14544#define EPWM_ASYMCTL_ASYMMODE0_Pos (8)
14545#define EPWM_ASYMCTL_ASYMMODE0_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE0_Pos)
14547#define EPWM_ASYMCTL_ASYMMODE2_Pos (16)
14548#define EPWM_ASYMCTL_ASYMMODE2_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE2_Pos)
14550#define EPWM_ASYMCTL_ASYMMODE4_Pos (24)
14551#define EPWM_ASYMCTL_ASYMMODE4_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE4_Pos)
14553#define EPWM_PERIODCNT_PERIODCNT_Pos (0)
14554#define EPWM_PERIODCNT_PERIODCNT_Msk (0xful << EPWM_PERIODCNT_PERIODCNT_Pos)
14556#define EPWM_EINTCTL_EDGEIEN0_Pos (0)
14557#define EPWM_EINTCTL_EDGEIEN0_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN0_Pos)
14559#define EPWM_EINTCTL_EDGEIEN2_Pos (1)
14560#define EPWM_EINTCTL_EDGEIEN2_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN2_Pos)
14562#define EPWM_EINTCTL_EDGEIEN4_Pos (2)
14563#define EPWM_EINTCTL_EDGEIEN4_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN4_Pos)
14565#define EPWM_EINTCTL_EINTTYPE0_Pos (8)
14566#define EPWM_EINTCTL_EINTTYPE0_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE0_Pos)
14568#define EPWM_EINTCTL_EINTTYPE2_Pos (9)
14569#define EPWM_EINTCTL_EINTTYPE2_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE2_Pos)
14571#define EPWM_EINTCTL_EINTTYPE4_Pos (10)
14572#define EPWM_EINTCTL_EINTTYPE4_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE4_Pos)
14574#define EPWM_OUTEN0_EVENOUTEN_Pos (0)
14575#define EPWM_OUTEN0_EVENOUTEN_Msk (0x1ul << EPWM_OUTEN0_EVENOUTEN_Pos)
14577#define EPWM_OUTEN0_ODDOUTEN_Pos (1)
14578#define EPWM_OUTEN0_ODDOUTEN_Msk (0x1ul << EPWM_OUTEN0_ODDOUTEN_Pos) /* EPWM_CONST */ /* end of EPWM register group */
14582
14583
14584/*---------------------- Flash Memory Controller -------------------------*/
14590 typedef struct {
14628 __IO uint32_t ISPCTL;
14629
14641 __IO uint32_t ISPADDR;
14642
14654 __IO uint32_t ISPDAT;
14655
14666 __IO uint32_t ISPCMD;
14667
14682 __IO uint32_t ISPTRG;
14683
14695 __I uint32_t DFBA;
14696
14717 __IO uint32_t FTCTL;
14719 uint32_t RESERVE0[9];
14721
14750 __IO uint32_t ISPSTS;
14751
14799 __IO uint32_t FBWP;
14801 uint32_t RESERVE1[14];
14803
14815 __IO uint32_t MPDAT0;
14816
14827 __IO uint32_t MPDAT1;
14828
14839 __IO uint32_t MPDAT2;
14840
14851 __IO uint32_t MPDAT3;
14853 uint32_t RESERVE2[12];
14855
14889 __IO uint32_t MPSTS;
14890
14903 __IO uint32_t MPADDR;
14904
14905} FMC_T;
14906
14907
14913#define FMC_ISPCTL_ISPEN_Pos (0)
14914#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
14916#define FMC_ISPCTL_BS_Pos (1)
14917#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
14919#define FMC_ISPCTL_APUEN_Pos (3)
14920#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
14922#define FMC_ISPCTL_CFGUEN_Pos (4)
14923#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
14925#define FMC_ISPCTL_LDUEN_Pos (5)
14926#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
14928#define FMC_ISPCTL_ISPFF_Pos (6)
14929#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
14931#define FMC_ISPADDR_ISPADDR_Pos (0)
14932#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
14934#define FMC_ISPDAT_ISPDAT_Pos (0)
14935#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
14937#define FMC_ISPCMD_CMD_Pos (0)
14938#define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos)
14940#define FMC_ISPTRG_ISPGO_Pos (0)
14941#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
14943#define FMC_DFBA_DFBA_Pos (0)
14944#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
14946#define FMC_FTCTL_FOM_Pos (4)
14947#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos)
14949#define FMC_ISPSTS_ISPBUSY_Pos (0)
14950#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
14952#define FMC_ISPSTS_CBS_Pos (1)
14953#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
14955#define FMC_ISPSTS_ISPFF_Pos (6)
14956#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
14958#define FMC_ISPSTS_VECMAP_Pos (9)
14959#define FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos)
14961#define FMC_ISPSTS_CFGCRCF_Pos (26)
14962#define FMC_ISPSTS_CFGCRCF_Msk (0x1ul << FMC_ISPSTS_CFGCRCF_Pos)
14964#define FMC_FBWP_BWP_Pos (0)
14965#define FMC_FBWP_BWP_Msk (0xfffffffful << FMC_FBWP_BWP_Pos)
14967#define FMC_MPDAT0_ISPDAT0_Pos (0)
14968#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos)
14970#define FMC_MPDAT1_ISPDAT1_Pos (0)
14971#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos)
14973#define FMC_MPDAT2_ISPDAT2_Pos (0)
14974#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos)
14976#define FMC_MPDAT3_ISPDAT3_Pos (0)
14977#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos)
14979#define FMC_MPSTS_MPBUSY_Pos (0)
14980#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos)
14982#define FMC_MPSTS_ISPFF_Pos (2)
14983#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos)
14985#define FMC_MPSTS_D0_Pos (4)
14986#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos)
14988#define FMC_MPSTS_D1_Pos (5)
14989#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos)
14991#define FMC_MPSTS_D2_Pos (6)
14992#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos)
14994#define FMC_MPSTS_D3_Pos (7)
14995#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos)
14997#define FMC_MPADDR_MPADDR_Pos (0)
14998#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /* FMC_CONST */ /* end of FMC register group */
15002
15003
15004/*---------------------- General Purpose Input/Output Controller -------------------------*/
15010 typedef struct {
15011
15012
15165 __IO uint32_t MODE;
15166
15255 __IO uint32_t DINOFF;
15256
15329 __IO uint32_t DOUT;
15330
15435 __IO uint32_t DATMSK;
15436
15493 __I uint32_t PIN;
15494
15615 __IO uint32_t DBEN;
15616
15801 __IO uint32_t INTTYPE;
15802
15971 __IO uint32_t INTEN;
15972
16093 __IO uint32_t INTSRC;
16094
16135 __IO uint32_t SMTEN;
16136
16177 __IO uint32_t SLEWCTL;
16178
16179} GPIO_T;
16180
16181
16182 typedef struct {
16183
16216 __IO uint32_t DBCTL;
16217
16218} GPIO_DB_T;
16219
16225#define GPIO_MODE_MODE0_Pos (0)
16226#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos)
16228#define GPIO_MODE_MODE1_Pos (2)
16229#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos)
16231#define GPIO_MODE_MODE2_Pos (4)
16232#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos)
16234#define GPIO_MODE_MODE3_Pos (6)
16235#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos)
16237#define GPIO_MODE_MODE4_Pos (8)
16238#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos)
16240#define GPIO_MODE_MODE5_Pos (10)
16241#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos)
16243#define GPIO_MODE_MODE6_Pos (12)
16244#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos)
16246#define GPIO_MODE_MODE7_Pos (14)
16247#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos)
16249#define GPIO_MODE_MODE8_Pos (16)
16250#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos)
16252#define GPIO_MODE_MODE9_Pos (18)
16253#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos)
16255#define GPIO_MODE_MODE10_Pos (20)
16256#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos)
16258#define GPIO_MODE_MODE11_Pos (22)
16259#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos)
16261#define GPIO_MODE_MODE12_Pos (24)
16262#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos)
16264#define GPIO_MODE_MODE13_Pos (26)
16265#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos)
16267#define GPIO_MODE_MODE14_Pos (28)
16268#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos)
16270#define GPIO_MODE_MODE15_Pos (30)
16271#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos)
16273#define GPIO_DINOFF_DINOFF0_Pos (16)
16274#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos)
16276#define GPIO_DINOFF_DINOFF1_Pos (17)
16277#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos)
16279#define GPIO_DINOFF_DINOFF2_Pos (18)
16280#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos)
16282#define GPIO_DINOFF_DINOFF3_Pos (19)
16283#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos)
16285#define GPIO_DINOFF_DINOFF4_Pos (20)
16286#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos)
16288#define GPIO_DINOFF_DINOFF5_Pos (21)
16289#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos)
16291#define GPIO_DINOFF_DINOFF6_Pos (22)
16292#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos)
16294#define GPIO_DINOFF_DINOFF7_Pos (23)
16295#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos)
16297#define GPIO_DINOFF_DINOFF8_Pos (24)
16298#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos)
16300#define GPIO_DINOFF_DINOFF9_Pos (25)
16301#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos)
16303#define GPIO_DINOFF_DINOFF10_Pos (26)
16304#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos)
16306#define GPIO_DINOFF_DINOFF11_Pos (27)
16307#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos)
16309#define GPIO_DINOFF_DINOFF12_Pos (28)
16310#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos)
16312#define GPIO_DINOFF_DINOFF13_Pos (29)
16313#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos)
16315#define GPIO_DINOFF_DINOFF14_Pos (30)
16316#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos)
16318#define GPIO_DINOFF_DINOFF15_Pos (31)
16319#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos)
16321#define GPIO_DOUT_DOUT0_Pos (0)
16322#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos)
16324#define GPIO_DOUT_DOUT1_Pos (1)
16325#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos)
16327#define GPIO_DOUT_DOUT2_Pos (2)
16328#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos)
16330#define GPIO_DOUT_DOUT3_Pos (3)
16331#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos)
16333#define GPIO_DOUT_DOUT4_Pos (4)
16334#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos)
16336#define GPIO_DOUT_DOUT5_Pos (5)
16337#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos)
16339#define GPIO_DOUT_DOUT6_Pos (6)
16340#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos)
16342#define GPIO_DOUT_DOUT7_Pos (7)
16343#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos)
16345#define GPIO_DOUT_DOUT8_Pos (8)
16346#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos)
16348#define GPIO_DOUT_DOUT9_Pos (9)
16349#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos)
16351#define GPIO_DOUT_DOUT10_Pos (10)
16352#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos)
16354#define GPIO_DOUT_DOUT11_Pos (11)
16355#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos)
16357#define GPIO_DOUT_DOUT12_Pos (12)
16358#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos)
16360#define GPIO_DOUT_DOUT13_Pos (13)
16361#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos)
16363#define GPIO_DOUT_DOUT14_Pos (14)
16364#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos)
16366#define GPIO_DOUT_DOUT15_Pos (15)
16367#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos)
16369#define GPIO_DATMSK_DATMSK0_Pos (0)
16370#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos)
16372#define GPIO_DATMSK_DATMSK1_Pos (1)
16373#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos)
16375#define GPIO_DATMSK_DATMSK2_Pos (2)
16376#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos)
16378#define GPIO_DATMSK_DATMSK3_Pos (3)
16379#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos)
16381#define GPIO_DATMSK_DATMSK4_Pos (4)
16382#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos)
16384#define GPIO_DATMSK_DATMSK5_Pos (5)
16385#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos)
16387#define GPIO_DATMSK_DATMSK6_Pos (6)
16388#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos)
16390#define GPIO_DATMSK_DATMSK7_Pos (7)
16391#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos)
16393#define GPIO_DATMSK_DATMSK8_Pos (8)
16394#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos)
16396#define GPIO_DATMSK_DATMSK9_Pos (9)
16397#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos)
16399#define GPIO_DATMSK_DATMSK10_Pos (10)
16400#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos)
16402#define GPIO_DATMSK_DATMSK11_Pos (11)
16403#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos)
16405#define GPIO_DATMSK_DATMSK12_Pos (12)
16406#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos)
16408#define GPIO_DATMSK_DATMSK13_Pos (13)
16409#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos)
16411#define GPIO_DATMSK_DATMSK14_Pos (14)
16412#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos)
16414#define GPIO_DATMSK_DATMSK15_Pos (15)
16415#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos)
16417#define GPIO_PIN_PIN0_Pos (0)
16418#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos)
16420#define GPIO_PIN_PIN1_Pos (1)
16421#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos)
16423#define GPIO_PIN_PIN2_Pos (2)
16424#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos)
16426#define GPIO_PIN_PIN3_Pos (3)
16427#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos)
16429#define GPIO_PIN_PIN4_Pos (4)
16430#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos)
16432#define GPIO_PIN_PIN5_Pos (5)
16433#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos)
16435#define GPIO_PIN_PIN6_Pos (6)
16436#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos)
16438#define GPIO_PIN_PIN7_Pos (7)
16439#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos)
16441#define GPIO_PIN_PIN8_Pos (8)
16442#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos)
16444#define GPIO_PIN_PIN9_Pos (9)
16445#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos)
16447#define GPIO_PIN_PIN10_Pos (10)
16448#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos)
16450#define GPIO_PIN_PIN11_Pos (11)
16451#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos)
16453#define GPIO_PIN_PIN12_Pos (12)
16454#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos)
16456#define GPIO_PIN_PIN13_Pos (13)
16457#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos)
16459#define GPIO_PIN_PIN14_Pos (14)
16460#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos)
16462#define GPIO_PIN_PIN15_Pos (15)
16463#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos)
16465#define GPIO_DBEN_DBEN0_Pos (0)
16466#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos)
16468#define GPIO_DBEN_DBEN1_Pos (1)
16469#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos)
16471#define GPIO_DBEN_DBEN2_Pos (2)
16472#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos)
16474#define GPIO_DBEN_DBEN3_Pos (3)
16475#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos)
16477#define GPIO_DBEN_DBEN4_Pos (4)
16478#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos)
16480#define GPIO_DBEN_DBEN5_Pos (5)
16481#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos)
16483#define GPIO_DBEN_DBEN6_Pos (6)
16484#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos)
16486#define GPIO_DBEN_DBEN7_Pos (7)
16487#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos)
16489#define GPIO_DBEN_DBEN8_Pos (8)
16490#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos)
16492#define GPIO_DBEN_DBEN9_Pos (9)
16493#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos)
16495#define GPIO_DBEN_DBEN10_Pos (10)
16496#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos)
16498#define GPIO_DBEN_DBEN11_Pos (11)
16499#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos)
16501#define GPIO_DBEN_DBEN12_Pos (12)
16502#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos)
16504#define GPIO_DBEN_DBEN13_Pos (13)
16505#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos)
16507#define GPIO_DBEN_DBEN14_Pos (14)
16508#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos)
16510#define GPIO_DBEN_DBEN15_Pos (15)
16511#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos)
16513#define GPIO_INTTYPE_TYPE0_Pos (0)
16514#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos)
16516#define GPIO_INTTYPE_TYPE1_Pos (1)
16517#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos)
16519#define GPIO_INTTYPE_TYPE2_Pos (2)
16520#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos)
16522#define GPIO_INTTYPE_TYPE3_Pos (3)
16523#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos)
16525#define GPIO_INTTYPE_TYPE4_Pos (4)
16526#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos)
16528#define GPIO_INTTYPE_TYPE5_Pos (5)
16529#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos)
16531#define GPIO_INTTYPE_TYPE6_Pos (6)
16532#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos)
16534#define GPIO_INTTYPE_TYPE7_Pos (7)
16535#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos)
16537#define GPIO_INTTYPE_TYPE8_Pos (8)
16538#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos)
16540#define GPIO_INTTYPE_TYPE9_Pos (9)
16541#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos)
16543#define GPIO_INTTYPE_TYPE10_Pos (10)
16544#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos)
16546#define GPIO_INTTYPE_TYPE11_Pos (11)
16547#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos)
16549#define GPIO_INTTYPE_TYPE12_Pos (12)
16550#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos)
16552#define GPIO_INTTYPE_TYPE13_Pos (13)
16553#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos)
16555#define GPIO_INTTYPE_TYPE14_Pos (14)
16556#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos)
16558#define GPIO_INTTYPE_TYPE15_Pos (15)
16559#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos)
16561#define GPIO_INTEN_FLIEN0_Pos (0)
16562#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos)
16564#define GPIO_INTEN_FLIEN1_Pos (1)
16565#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos)
16567#define GPIO_INTEN_FLIEN2_Pos (2)
16568#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos)
16570#define GPIO_INTEN_FLIEN3_Pos (3)
16571#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos)
16573#define GPIO_INTEN_FLIEN4_Pos (4)
16574#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos)
16576#define GPIO_INTEN_FLIEN5_Pos (5)
16577#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos)
16579#define GPIO_INTEN_FLIEN6_Pos (6)
16580#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos)
16582#define GPIO_INTEN_FLIEN7_Pos (7)
16583#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos)
16585#define GPIO_INTEN_FLIEN8_Pos (8)
16586#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos)
16588#define GPIO_INTEN_FLIEN9_Pos (9)
16589#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos)
16591#define GPIO_INTEN_FLIEN10_Pos (10)
16592#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos)
16594#define GPIO_INTEN_FLIEN11_Pos (11)
16595#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos)
16597#define GPIO_INTEN_FLIEN12_Pos (12)
16598#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos)
16600#define GPIO_INTEN_FLIEN13_Pos (13)
16601#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos)
16603#define GPIO_INTEN_FLIEN14_Pos (14)
16604#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos)
16606#define GPIO_INTEN_FLIEN15_Pos (15)
16607#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos)
16609#define GPIO_INTEN_RHIEN0_Pos (16)
16610#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos)
16612#define GPIO_INTEN_RHIEN1_Pos (17)
16613#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos)
16615#define GPIO_INTEN_RHIEN2_Pos (18)
16616#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos)
16618#define GPIO_INTEN_RHIEN3_Pos (19)
16619#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos)
16621#define GPIO_INTEN_RHIEN4_Pos (20)
16622#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos)
16624#define GPIO_INTEN_RHIEN5_Pos (21)
16625#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos)
16627#define GPIO_INTEN_RHIEN6_Pos (22)
16628#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos)
16630#define GPIO_INTEN_RHIEN7_Pos (23)
16631#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos)
16633#define GPIO_INTEN_RHIEN8_Pos (24)
16634#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos)
16636#define GPIO_INTEN_RHIEN9_Pos (25)
16637#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos)
16639#define GPIO_INTEN_RHIEN10_Pos (26)
16640#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos)
16642#define GPIO_INTEN_RHIEN11_Pos (27)
16643#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos)
16645#define GPIO_INTEN_RHIEN12_Pos (28)
16646#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos)
16648#define GPIO_INTEN_RHIEN13_Pos (29)
16649#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos)
16651#define GPIO_INTEN_RHIEN14_Pos (30)
16652#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos)
16654#define GPIO_INTEN_RHIEN15_Pos (31)
16655#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos)
16657#define GPIO_INTSRC_INTSRC0_Pos (0)
16658#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos)
16660#define GPIO_INTSRC_INTSRC1_Pos (1)
16661#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos)
16663#define GPIO_INTSRC_INTSRC2_Pos (2)
16664#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos)
16666#define GPIO_INTSRC_INTSRC3_Pos (3)
16667#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos)
16669#define GPIO_INTSRC_INTSRC4_Pos (4)
16670#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos)
16672#define GPIO_INTSRC_INTSRC5_Pos (5)
16673#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos)
16675#define GPIO_INTSRC_INTSRC6_Pos (6)
16676#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos)
16678#define GPIO_INTSRC_INTSRC7_Pos (7)
16679#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos)
16681#define GPIO_INTSRC_INTSRC8_Pos (8)
16682#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos)
16684#define GPIO_INTSRC_INTSRC9_Pos (9)
16685#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos)
16687#define GPIO_INTSRC_INTSRC10_Pos (10)
16688#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos)
16690#define GPIO_INTSRC_INTSRC11_Pos (11)
16691#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos)
16693#define GPIO_INTSRC_INTSRC12_Pos (12)
16694#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos)
16696#define GPIO_INTSRC_INTSRC13_Pos (13)
16697#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos)
16699#define GPIO_INTSRC_INTSRC14_Pos (14)
16700#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos)
16702#define GPIO_INTSRC_INTSRC15_Pos (15)
16703#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos)
16705#define GPIO_SMTEN_SMTEN0_Pos (0)
16706#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos)
16708#define GPIO_SMTEN_SMTEN1_Pos (1)
16709#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos)
16711#define GPIO_SMTEN_SMTEN2_Pos (2)
16712#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos)
16714#define GPIO_SMTEN_SMTEN3_Pos (3)
16715#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos)
16717#define GPIO_SMTEN_SMTEN4_Pos (4)
16718#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos)
16720#define GPIO_SMTEN_SMTEN5_Pos (5)
16721#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos)
16723#define GPIO_SMTEN_SMTEN6_Pos (6)
16724#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos)
16726#define GPIO_SMTEN_SMTEN7_Pos (7)
16727#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos)
16729#define GPIO_SMTEN_SMTEN8_Pos (8)
16730#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos)
16732#define GPIO_SMTEN_SMTEN9_Pos (9)
16733#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos)
16735#define GPIO_SMTEN_SMTEN10_Pos (10)
16736#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos)
16738#define GPIO_SMTEN_SMTEN11_Pos (11)
16739#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos)
16741#define GPIO_SMTEN_SMTEN12_Pos (12)
16742#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos)
16744#define GPIO_SMTEN_SMTEN13_Pos (13)
16745#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos)
16747#define GPIO_SMTEN_SMTEN14_Pos (14)
16748#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos)
16750#define GPIO_SMTEN_SMTEN15_Pos (15)
16751#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos)
16753#define GPIO_SLEWCTL_HSREN0_Pos (0)
16754#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos)
16756#define GPIO_SLEWCTL_HSREN1_Pos (1)
16757#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos)
16759#define GPIO_SLEWCTL_HSREN2_Pos (2)
16760#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos)
16762#define GPIO_SLEWCTL_HSREN3_Pos (3)
16763#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos)
16765#define GPIO_SLEWCTL_HSREN4_Pos (4)
16766#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos)
16768#define GPIO_SLEWCTL_HSREN5_Pos (5)
16769#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos)
16771#define GPIO_SLEWCTL_HSREN6_Pos (6)
16772#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos)
16774#define GPIO_SLEWCTL_HSREN7_Pos (7)
16775#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos)
16777#define GPIO_SLEWCTL_HSREN8_Pos (8)
16778#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos)
16780#define GPIO_SLEWCTL_HSREN9_Pos (9)
16781#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos)
16783#define GPIO_SLEWCTL_HSREN10_Pos (10)
16784#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos)
16786#define GPIO_SLEWCTL_HSREN11_Pos (11)
16787#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos)
16789#define GPIO_SLEWCTL_HSREN12_Pos (12)
16790#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos)
16792#define GPIO_SLEWCTL_HSREN13_Pos (13)
16793#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos)
16795#define GPIO_SLEWCTL_HSREN14_Pos (14)
16796#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos)
16798#define GPIO_SLEWCTL_HSREN15_Pos (15)
16799#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos)
16801#define GPIO_DBCTL_DBCLKSEL_Pos (0)
16802#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos)
16804#define GPIO_DBCTL_DBCLKSRC_Pos (4)
16805#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos)
16807#define GPIO_DBCTL_ICLKON_Pos (5)
16808#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /* GPIO_CONST */ /* end of GPIO register group */
16812
16813
16814/*---------------------- Inter-IC Bus Controller -------------------------*/
16820 typedef struct {
16821
16822
16853 __IO uint32_t CTL;
16854
16870 __IO uint32_t ADDR0;
16871
16882 __IO uint32_t DAT;
16883
16897 __I uint32_t STATUS;
16898
16910 __IO uint32_t CLKDIV;
16911
16932 __IO uint32_t TOCTL;
16933
16949 __IO uint32_t ADDR1;
16950
16966 __IO uint32_t ADDR2;
16967
16983 __IO uint32_t ADDR3;
16984
16999 __IO uint32_t ADDRMSK0;
17000
17015 __IO uint32_t ADDRMSK1;
17016
17031 __IO uint32_t ADDRMSK2;
17032
17047 __IO uint32_t ADDRMSK3;
17049 uint32_t RESERVE0[2];
17051
17052
17064 __IO uint32_t WKCTL;
17065
17078 __IO uint32_t WKSTS;
17079
17080} I2C_T;
17081
17087#define I2C_CTL_AA_Pos (2)
17088#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos)
17090#define I2C_CTL_SI_Pos (3)
17091#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos)
17093#define I2C_CTL_STO_Pos (4)
17094#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos)
17096#define I2C_CTL_STA_Pos (5)
17097#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos)
17099#define I2C_CTL_I2CEN_Pos (6)
17100#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos)
17102#define I2C_CTL_INTEN_Pos (7)
17103#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos)
17105#define I2C_ADDR0_GC_Pos (0)
17106#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
17108#define I2C_ADDR0_ADDR_Pos (1)
17109#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos)
17111#define I2C_DAT_DAT_Pos (0)
17112#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
17114#define I2C_STATUS_STATUS_Pos (0)
17115#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
17117#define I2C_CLKDIV_DIVIDER_Pos (0)
17118#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos)
17120#define I2C_TOCTL_TOIF_Pos (0)
17121#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos)
17123#define I2C_TOCTL_TOCDIV4_Pos (1)
17124#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos)
17126#define I2C_TOCTL_TOCEN_Pos (2)
17127#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
17129#define I2C_ADDR1_GC_Pos (0)
17130#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
17132#define I2C_ADDR1_ADDR_Pos (1)
17133#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos)
17135#define I2C_ADDR2_GC_Pos (0)
17136#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos)
17138#define I2C_ADDR2_ADDR_Pos (1)
17139#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos)
17141#define I2C_ADDR3_GC_Pos (0)
17142#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos)
17144#define I2C_ADDR3_ADDR_Pos (1)
17145#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos)
17147#define I2C_ADDRMSK0_ADDRMSK_Pos (1)
17148#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)
17150#define I2C_ADDRMSK1_ADDRMSK_Pos (1)
17151#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)
17153#define I2C_ADDRMSK2_ADDRMSK_Pos (1)
17154#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos)
17156#define I2C_ADDRMSK3_ADDRMSK_Pos (1)
17157#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos)
17159#define I2C_WKCTL_WKEN_Pos (0)
17160#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos)
17162#define I2C_WKSTS_WKIF_Pos (0)
17163#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /* I2C_CONST */ /* end of I2C register group */
17167
17168
17169/*---------------------- I2S Interface Controller -------------------------*/
17175 typedef struct {
17176
17177
17280 __IO uint32_t CTL;
17281
17302 __IO uint32_t CLKDIV;
17303
17345 __IO uint32_t IEN;
17346
17443 __IO uint32_t STATUS;
17444
17457 __O uint32_t TX;
17458
17471 __I uint32_t RX;
17472
17473} I2S_T;
17474
17480#define I2S_CTL_I2SEN_Pos (0)
17481#define I2S_CTL_I2SEN_Msk (0x1ul << I2S_CTL_I2SEN_Pos)
17483#define I2S_CTL_TXEN_Pos (1)
17484#define I2S_CTL_TXEN_Msk (0x1ul << I2S_CTL_TXEN_Pos)
17486#define I2S_CTL_RXEN_Pos (2)
17487#define I2S_CTL_RXEN_Msk (0x1ul << I2S_CTL_RXEN_Pos)
17489#define I2S_CTL_MUTE_Pos (3)
17490#define I2S_CTL_MUTE_Msk (0x1ul << I2S_CTL_MUTE_Pos)
17492#define I2S_CTL_WDWIDTH_Pos (4)
17493#define I2S_CTL_WDWIDTH_Msk (0x3ul << I2S_CTL_WDWIDTH_Pos)
17495#define I2S_CTL_MONO_Pos (6)
17496#define I2S_CTL_MONO_Msk (0x1ul << I2S_CTL_MONO_Pos)
17498#define I2S_CTL_FORMAT_Pos (7)
17499#define I2S_CTL_FORMAT_Msk (0x1ul << I2S_CTL_FORMAT_Pos)
17501#define I2S_CTL_SLAVE_Pos (8)
17502#define I2S_CTL_SLAVE_Msk (0x1ul << I2S_CTL_SLAVE_Pos)
17504#define I2S_CTL_TXTH_Pos (9)
17505#define I2S_CTL_TXTH_Msk (0x7ul << I2S_CTL_TXTH_Pos)
17507#define I2S_CTL_RXTH_Pos (12)
17508#define I2S_CTL_RXTH_Msk (0x7ul << I2S_CTL_RXTH_Pos)
17510#define I2S_CTL_MCLKEN_Pos (15)
17511#define I2S_CTL_MCLKEN_Msk (0x1ul << I2S_CTL_MCLKEN_Pos)
17513#define I2S_CTL_RZCEN_Pos (16)
17514#define I2S_CTL_RZCEN_Msk (0x1ul << I2S_CTL_RZCEN_Pos)
17516#define I2S_CTL_LZCEN_Pos (17)
17517#define I2S_CTL_LZCEN_Msk (0x1ul << I2S_CTL_LZCEN_Pos)
17519#define I2S_CTL_TXCLR_Pos (18)
17520#define I2S_CTL_TXCLR_Msk (0x1ul << I2S_CTL_TXCLR_Pos)
17522#define I2S_CTL_RXCLR_Pos (19)
17523#define I2S_CTL_RXCLR_Msk (0x1ul << I2S_CTL_RXCLR_Pos)
17525#define I2S_CTL_TXPDMAEN_Pos (20)
17526#define I2S_CTL_TXPDMAEN_Msk (0x1ul << I2S_CTL_TXPDMAEN_Pos)
17528#define I2S_CTL_RXPDMAEN_Pos (21)
17529#define I2S_CTL_RXPDMAEN_Msk (0x1ul << I2S_CTL_RXPDMAEN_Pos)
17531#define I2S_CTL_RXLCH_Pos (23)
17532#define I2S_CTL_RXLCH_Msk (0x1ul << I2S_CTL_RXLCH_Pos)
17534#define I2S_CTL_PCMEN_Pos (24)
17535#define I2S_CTL_PCMEN_Msk (0x1ul << I2S_CTL_PCMEN_Pos)
17537#define I2S_CLKDIV_MCLKDIV_Pos (0)
17538#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos)
17540#define I2S_CLKDIV_BCLKDIV_Pos (8)
17541#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos)
17543#define I2S_IEN_RXUDIEN_Pos (0)
17544#define I2S_IEN_RXUDIEN_Msk (0x1ul << I2S_IEN_RXUDIEN_Pos)
17546#define I2S_IEN_RXOVIEN_Pos (1)
17547#define I2S_IEN_RXOVIEN_Msk (0x1ul << I2S_IEN_RXOVIEN_Pos)
17549#define I2S_IEN_RXTHIEN_Pos (2)
17550#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos)
17552#define I2S_IEN_TXUDIEN_Pos (8)
17553#define I2S_IEN_TXUDIEN_Msk (0x1ul << I2S_IEN_TXUDIEN_Pos)
17555#define I2S_IEN_TXOVIEN_Pos (9)
17556#define I2S_IEN_TXOVIEN_Msk (0x1ul << I2S_IEN_TXOVIEN_Pos)
17558#define I2S_IEN_TXTHIEN_Pos (10)
17559#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos)
17561#define I2S_IEN_RZCIEN_Pos (11)
17562#define I2S_IEN_RZCIEN_Msk (0x1ul << I2S_IEN_RZCIEN_Pos)
17564#define I2S_IEN_LZCIEN_Pos (12)
17565#define I2S_IEN_LZCIEN_Msk (0x1ul << I2S_IEN_LZCIEN_Pos)
17567#define I2S_STATUS_I2SIF_Pos (0)
17568#define I2S_STATUS_I2SIF_Msk (0x1ul << I2S_STATUS_I2SIF_Pos)
17570#define I2S_STATUS_RXIF_Pos (1)
17571#define I2S_STATUS_RXIF_Msk (0x1ul << I2S_STATUS_RXIF_Pos)
17573#define I2S_STATUS_TXIF_Pos (2)
17574#define I2S_STATUS_TXIF_Msk (0x1ul << I2S_STATUS_TXIF_Pos)
17576#define I2S_STATUS_RIGHT_Pos (3)
17577#define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos)
17579#define I2S_STATUS_RXUDIF_Pos (8)
17580#define I2S_STATUS_RXUDIF_Msk (0x1ul << I2S_STATUS_RXUDIF_Pos)
17582#define I2S_STATUS_RXOVIF_Pos (9)
17583#define I2S_STATUS_RXOVIF_Msk (0x1ul << I2S_STATUS_RXOVIF_Pos)
17585#define I2S_STATUS_RXTHIF_Pos (10)
17586#define I2S_STATUS_RXTHIF_Msk (0x1ul << I2S_STATUS_RXTHIF_Pos)
17588#define I2S_STATUS_RXFULL_Pos (11)
17589#define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos)
17591#define I2S_STATUS_RXEMPTY_Pos (12)
17592#define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos)
17594#define I2S_STATUS_TXUDIF_Pos (16)
17595#define I2S_STATUS_TXUDIF_Msk (0x1ul << I2S_STATUS_TXUDIF_Pos)
17597#define I2S_STATUS_TXOVIF_Pos (17)
17598#define I2S_STATUS_TXOVIF_Msk (0x1ul << I2S_STATUS_TXOVIF_Pos)
17600#define I2S_STATUS_TXTHIF_Pos (18)
17601#define I2S_STATUS_TXTHIF_Msk (0x1ul << I2S_STATUS_TXTHIF_Pos)
17603#define I2S_STATUS_TXFULL_Pos (19)
17604#define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos)
17606#define I2S_STATUS_TXEMPTY_Pos (20)
17607#define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos)
17609#define I2S_STATUS_TXBUSY_Pos (21)
17610#define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos)
17612#define I2S_STATUS_RZCIF_Pos (22)
17613#define I2S_STATUS_RZCIF_Msk (0x1ul << I2S_STATUS_RZCIF_Pos)
17615#define I2S_STATUS_LZCIF_Pos (23)
17616#define I2S_STATUS_LZCIF_Msk (0x1ul << I2S_STATUS_LZCIF_Pos)
17618#define I2S_STATUS_RXCNT_Pos (24)
17619#define I2S_STATUS_RXCNT_Msk (0xful << I2S_STATUS_RXCNT_Pos)
17621#define I2S_STATUS_TXCNT_Pos (28)
17622#define I2S_STATUS_TXCNT_Msk (0xful << I2S_STATUS_TXCNT_Pos)
17624#define I2S_TX_TX_Pos (0)
17625#define I2S_TX_TX_Msk (0xfffffffful << I2S_TX_TX_Pos)
17627#define I2S_RX_RX_Pos (0)
17628#define I2S_RX_RX_Msk (0xfffffffful << I2S_RX_RX_Pos) /* I2S_CONST */ /* end of I2S register group */
17632
17633
17634/*---------------------- OP Amplifier -------------------------*/
17640 typedef struct {
17641
17642
17675 __IO uint32_t CTL;
17676
17697 __IO uint32_t STATUS;
17698
17699} OPA_T;
17700
17706#define OPA_CTL_OPEN0_Pos (0)
17707#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos)
17709#define OPA_CTL_OPEN1_Pos (1)
17710#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos)
17712#define OPA_CTL_OPSMTEN0_Pos (4)
17713#define OPA_CTL_OPSMTEN0_Msk (0x1ul << OPA_CTL_OPSMTEN0_Pos)
17715#define OPA_CTL_OPSMTEN1_Pos (5)
17716#define OPA_CTL_OPSMTEN1_Msk (0x1ul << OPA_CTL_OPSMTEN1_Pos)
17718#define OPA_CTL_OPAIE0_Pos (8)
17719#define OPA_CTL_OPAIE0_Msk (0x1ul << OPA_CTL_OPAIE0_Pos)
17721#define OPA_CTL_OPAIE1_Pos (9)
17722#define OPA_CTL_OPAIE1_Msk (0x1ul << OPA_CTL_OPAIE1_Pos)
17724#define OPA_STATUS_OPDO0_Pos (0)
17725#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos)
17727#define OPA_STATUS_OPDO1_Pos (1)
17728#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos)
17730#define OPA_STATUS_OPDF0_Pos (4)
17731#define OPA_STATUS_OPDF0_Msk (0x1ul << OPA_STATUS_OPDF0_Pos)
17733#define OPA_STATUS_OPDF1_Pos (5)
17734#define OPA_STATUS_OPDF1_Msk (0x1ul << OPA_STATUS_OPDF1_Pos) /* OPA_CONST */ /* end of OPA register group */
17738
17739
17740/*---------------------- USB On-The-Go Controller -------------------------*/
17746 typedef struct {
17747
17748
17778 __IO uint32_t CTL;
17779
17820 __IO uint32_t PHYCTL;
17821
17871 __IO uint32_t INTEN;
17872
17935 __IO uint32_t INTSTS;
17936
17964 __I uint32_t STATUS;
17965
17966} OTG_T;
17967
17973#define OTG_CTL_VBUSDROP_Pos (0)
17974#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos)
17976#define OTG_CTL_BUSREQ_Pos (1)
17977#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos)
17979#define OTG_CTL_HNPREQEN_Pos (2)
17980#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos)
17982#define OTG_CTL_OTGEN_Pos (4)
17983#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos)
17985#define OTG_CTL_PDEVCKON_Pos (7)
17986#define OTG_CTL_PDEVCKON_Msk (0x1ul << OTG_CTL_PDEVCKON_Pos)
17988#define OTG_CTL_WKEN_Pos (8)
17989#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos)
17991#define OTG_PHYCTL_SWPDEN_Pos (0)
17992#define OTG_PHYCTL_SWPDEN_Msk (0x1ul << OTG_PHYCTL_SWPDEN_Pos)
17994#define OTG_PHYCTL_DPPDEN_Pos (1)
17995#define OTG_PHYCTL_DPPDEN_Msk (0x1ul << OTG_PHYCTL_DPPDEN_Pos)
17997#define OTG_PHYCTL_DMPDEN_Pos (2)
17998#define OTG_PHYCTL_DMPDEN_Msk (0x1ul << OTG_PHYCTL_DMPDEN_Pos)
18000#define OTG_PHYCTL_VBSTSPOL_Pos (5)
18001#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos)
18003#define OTG_PHYCTL_VBENPOL_Pos (6)
18004#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos)
18006#define OTG_PHYCTL_IDDETEN_Pos (7)
18007#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos)
18009#define OTG_PHYCTL_PHYCLK_Pos (8)
18010#define OTG_PHYCTL_PHYCLK_Msk (0x1ul << OTG_PHYCTL_PHYCLK_Pos)
18012#define OTG_PHYCTL_OTGPHYEN_Pos (9)
18013#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos)
18015#define OTG_INTEN_ROLECHGIEN_Pos (0)
18016#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos)
18018#define OTG_INTEN_VBEIEN_Pos (1)
18019#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos)
18021#define OTG_INTEN_SRPFIEN_Pos (2)
18022#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos)
18024#define OTG_INTEN_HNPFIEN_Pos (3)
18025#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos)
18027#define OTG_INTEN_GOIDLEIEN_Pos (4)
18028#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos)
18030#define OTG_INTEN_IDCHGIEN_Pos (5)
18031#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos)
18033#define OTG_INTEN_PDEVIEN_Pos (6)
18034#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos)
18036#define OTG_INTEN_HOSTIEN_Pos (7)
18037#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos)
18039#define OTG_INTEN_BVLDCHGIEN_Pos (8)
18040#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos)
18042#define OTG_INTEN_AVLDCHGIEN_Pos (9)
18043#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos)
18045#define OTG_INTEN_VBCHGIEN_Pos (10)
18046#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos)
18048#define OTG_INTEN_SECHGIEN_Pos (11)
18049#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos)
18051#define OTG_INTEN_SRPDETIEN_Pos (13)
18052#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos)
18054#define OTG_INTSTS_ROLECHGIF_Pos (0)
18055#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos)
18057#define OTG_INTSTS_VBEIF_Pos (1)
18058#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos)
18060#define OTG_INTSTS_SRPFIF_Pos (2)
18061#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos)
18063#define OTG_INTSTS_HNPFIF_Pos (3)
18064#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos)
18066#define OTG_INTSTS_GOIDLEIF_Pos (4)
18067#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos)
18069#define OTG_INTSTS_IDCHGIF_Pos (5)
18070#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos)
18072#define OTG_INTSTS_PDEVIF_Pos (6)
18073#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos)
18075#define OTG_INTSTS_HOSTIF_Pos (7)
18076#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos)
18078#define OTG_INTSTS_BVLDCHGIF_Pos (8)
18079#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos)
18081#define OTG_INTSTS_AVLDCHGIF_Pos (9)
18082#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos)
18084#define OTG_INTSTS_VBCHGIF_Pos (10)
18085#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos)
18087#define OTG_INTSTS_SECHGIF_Pos (11)
18088#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos)
18090#define OTG_INTSTS_SRPDETIF_Pos (13)
18091#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos)
18093#define OTG_STATUS_OVERCUR_Pos (0)
18094#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos)
18096#define OTG_STATUS_IDSTS_Pos (1)
18097#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos)
18099#define OTG_STATUS_SESSEND_Pos (2)
18100#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos)
18102#define OTG_STATUS_BVLD_Pos (3)
18103#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos)
18105#define OTG_STATUS_AVLD_Pos (4)
18106#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos)
18108#define OTG_STATUS_VBUSVLD_Pos (5)
18109#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /* OTG_CONST */ /* end of OTG register group */
18113
18114
18115/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
18121 typedef struct {
18122
18180 __IO uint32_t CTL;
18181
18194 __IO uint32_t ENDSA;
18195
18208 __IO uint32_t ENDDA;
18209
18223 __IO uint32_t NEXT;
18224
18225} DSCT_T;
18226
18227 typedef struct {
18228 DSCT_T DSCT[16];
18230 uint32_t RESERVE0[192];
18232
18248 __IO uint32_t CHCTL;
18249
18267 __O uint32_t STOP;
18268
18285 __O uint32_t SWREQ;
18286
18302 __I uint32_t TRGSTS;
18303
18317 __IO uint32_t PRISET;
18318
18332 __O uint32_t PRICLR;
18333
18346 __IO uint32_t INTEN;
18347
18372 __IO uint32_t INTSTS;
18373
18387 __IO uint32_t ABTSTS;
18388
18402 __IO uint32_t TDSTS;
18403
18417 __IO uint32_t SCATSTS;
18418
18431 __I uint32_t TACTSTS;
18433 uint32_t RESERVE1[3];
18435
18436
18450 __IO uint32_t SCATBA;
18451
18453 uint32_t RESERVE2[16];
18455
18456
18511 __IO uint32_t REQSEL0_3;
18512
18541 __IO uint32_t REQSEL4_7;
18542
18571 __IO uint32_t REQSEL8_11;
18572
18601 __IO uint32_t REQSEL12_15;
18602
18603} PDMA_T;
18604
18610#define PDMA_DSCT_CTL_OPMODE_Pos (0)
18611#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos)
18613#define PDMA_DSCT_CTL_TXTYPE_Pos (2)
18614#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos)
18616#define PDMA_DSCT_CTL_BURSIZE_Pos (4)
18617#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos)
18619#define PDMA_DSCT_CTL_TBINTDIS_Pos (7)
18620#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos)
18622#define PDMA_DSCT_CTL_SAINC_Pos (8)
18623#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos)
18625#define PDMA_DSCT_CTL_DAINC_Pos (10)
18626#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos)
18628#define PDMA_DSCT_CTL_TXWIDTH_Pos (12)
18629#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos)
18631#define PDMA_DSCT_CTL_TXCNT_Pos (16)
18632#define PDMA_DSCT_CTL_TXCNT_Msk (0x3ffful << PDMA_DSCT_CTL_TXCNT_Pos)
18634#define PDMA_DSCT_ENDSA_ENDSA_Pos (0)
18635#define PDMA_DSCT_ENDSA_ENDSA_Msk (0xfffffffful << PDMA_DSCT_ENDSA_ENDSA_Pos)
18637#define PDMA_DSCT_ENDDA_ENDDA_Pos (0)
18638#define PDMA_DSCT_ENDDA_ENDDA_Msk (0xfffffffful << PDMA_DSCT_ENDDA_ENDDA_Pos)
18640#define PDMA_DSCT_NEXT_NEXT_Pos (2)
18641#define PDMA_DSCT_NEXT_NEXT_Msk (0x3ffful << PDMA_DSCT_NEXT_NEXT_Pos)
18643#define PDMA_CHCTL_CHEN_Pos (0)
18644#define PDMA_CHCTL_CHEN_Msk (0xfffful << PDMA_CHCTL_CHEN_Pos)
18646#define PDMA_STOP_STOP_Pos (0)
18647#define PDMA_STOP_STOP_Msk (0xfffful << PDMA_STOP_STOP_Pos)
18649#define PDMA_SWREQ_SWREQ_Pos (0)
18650#define PDMA_SWREQ_SWREQ_Msk (0xffful << PDMA_SWREQ_SWREQ_Pos)
18652#define PDMA_TRGSTS_REQSTS_Pos (0)
18653#define PDMA_TRGSTS_REQSTS_Msk (0xfffful << PDMA_TRGSTS_REQSTS_Pos)
18655#define PDMA_PRISET_FPRISET_Pos (0)
18656#define PDMA_PRISET_FPRISET_Msk (0xfffful << PDMA_PRISET_FPRISET_Pos)
18658#define PDMA_PRICLR_FPRICLR_Pos (0)
18659#define PDMA_PRICLR_FPRICLR_Msk (0xfffful << PDMA_PRICLR_FPRICLR_Pos)
18661#define PDMA_INTEN_INTEN_Pos (0)
18662#define PDMA_INTEN_INTEN_Msk (0xfffful << PDMA_INTEN_INTEN_Pos)
18664#define PDMA_INTSTS_ABTIF_Pos (0)
18665#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos)
18667#define PDMA_INTSTS_TDIF_Pos (1)
18668#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos)
18670#define PDMA_INTSTS_TEIF_Pos (2)
18671#define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos)
18673#define PDMA_ABTSTS_ABTIF_Pos (0)
18674#define PDMA_ABTSTS_ABTIF_Msk (0xfffful << PDMA_ABTSTS_ABTIF_Pos)
18676#define PDMA_TDSTS_TDIF_Pos (0)
18677#define PDMA_TDSTS_TDIF_Msk (0xfffful << PDMA_TDSTS_TDIF_Pos)
18679#define PDMA_SCATSTS_TEMPTYF_Pos (0)
18680#define PDMA_SCATSTS_TEMPTYF_Msk (0xfffful << PDMA_SCATSTS_TEMPTYF_Pos)
18682#define PDMA_TACTSTS_TXACTF_Pos (0)
18683#define PDMA_TACTSTS_TXACTF_Msk (0xfffful << PDMA_TACTSTS_TXACTF_Pos)
18685#define PDMA_SCATBA_SCATBA_Pos (16)
18686#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos)
18688#define PDMA_REQSEL0_3_REQSRC0_Pos (0)
18689#define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos)
18691#define PDMA_REQSEL0_3_REQSRC1_Pos (8)
18692#define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos)
18694#define PDMA_REQSEL0_3_REQSRC2_Pos (16)
18695#define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos)
18697#define PDMA_REQSEL0_3_REQSRC3_Pos (24)
18698#define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos)
18700#define PDMA_REQSEL4_7_REQSRC4_Pos (0)
18701#define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos)
18703#define PDMA_REQSEL4_7_REQSRC5_Pos (8)
18704#define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos)
18706#define PDMA_REQSEL4_7_REQSRC6_Pos (16)
18707#define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos)
18709#define PDMA_REQSEL4_7_REQSRC7_Pos (24)
18710#define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos)
18712#define PDMA_REQSEL8_11_REQSRC8_Pos (0)
18713#define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos)
18715#define PDMA_REQSEL8_11_REQSRC9_Pos (8)
18716#define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos)
18718#define PDMA_REQSEL8_11_REQSRC10_Pos (16)
18719#define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos)
18721#define PDMA_REQSEL8_11_REQSRC11_Pos (24)
18722#define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos)
18724#define PDMA_REQSEL12_15_REQSRC12_Pos (0)
18725#define PDMA_REQSEL12_15_REQSRC12_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC12_Pos)
18727#define PDMA_REQSEL12_15_REQSRC13_Pos (8)
18728#define PDMA_REQSEL12_15_REQSRC13_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC13_Pos)
18730#define PDMA_REQSEL12_15_REQSRC14_Pos (16)
18731#define PDMA_REQSEL12_15_REQSRC14_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC14_Pos)
18733#define PDMA_REQSEL12_15_REQSRC15_Pos (24)
18734#define PDMA_REQSEL12_15_REQSRC15_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC15_Pos) /* PDMA_CONST */ /* end of PDMA register group */
18738
18739
18740/*---------------------- PS/2 Device Controller -------------------------*/
18746 typedef struct {
18747
18748
18795 __IO uint32_t CTL;
18796
18808 __IO uint32_t TXDAT0;
18809
18821 __IO uint32_t TXDAT1;
18822
18834 __IO uint32_t TXDAT2;
18835
18847 __IO uint32_t TXDAT3;
18848
18860 __I uint32_t RXDAT;
18861
18926 __IO uint32_t STATUS;
18927
18948 __IO uint32_t INTSTS;
18949
18950} PS2_T;
18951
18957#define PS2_CTL_PS2EN_Pos (0)
18958#define PS2_CTL_PS2EN_Msk (0x1ul << PS2_CTL_PS2EN_Pos)
18960#define PS2_CTL_TXIEN_Pos (1)
18961#define PS2_CTL_TXIEN_Msk (0x1ul << PS2_CTL_TXIEN_Pos)
18963#define PS2_CTL_RXIEN_Pos (2)
18964#define PS2_CTL_RXIEN_Msk (0x1ul << PS2_CTL_RXIEN_Pos)
18966#define PS2_CTL_TXFDEPTH_Pos (3)
18967#define PS2_CTL_TXFDEPTH_Msk (0xful << PS2_CTL_TXFDEPTH_Pos)
18969#define PS2_CTL_ACK_Pos (7)
18970#define PS2_CTL_ACK_Msk (0x1ul << PS2_CTL_ACK_Pos)
18972#define PS2_CTL_CLRFIFO_Pos (8)
18973#define PS2_CTL_CLRFIFO_Msk (0x1ul << PS2_CTL_CLRFIFO_Pos)
18975#define PS2_CTL_OVERRIDE_Pos (9)
18976#define PS2_CTL_OVERRIDE_Msk (0x1ul << PS2_CTL_OVERRIDE_Pos)
18978#define PS2_CTL_FPS2CLK_Pos (10)
18979#define PS2_CTL_FPS2CLK_Msk (0x1ul << PS2_CTL_FPS2CLK_Pos)
18981#define PS2_CTL_FPS2DAT_Pos (11)
18982#define PS2_CTL_FPS2DAT_Msk (0x1ul << PS2_CTL_FPS2DAT_Pos)
18984#define PS2_TXDAT0_DAT_Pos (0)
18985#define PS2_TXDAT0_DAT_Msk (0xfffffffful << PS2_TXDAT0_DAT_Pos)
18987#define PS2_TXDAT1_DAT_Pos (0)
18988#define PS2_TXDAT1_DAT_Msk (0xfffffffful << PS2_TXDAT1_DAT_Pos)
18990#define PS2_TXDAT2_DAT_Pos (0)
18991#define PS2_TXDAT2_DAT_Msk (0xfffffffful << PS2_TXDAT2_DAT_Pos)
18993#define PS2_TXDAT3_DAT_Pos (0)
18994#define PS2_TXDAT3_DAT_Msk (0xfffffffful << PS2_TXDAT3_DAT_Pos)
18996#define PS2_RXDAT_DAT_Pos (0)
18997#define PS2_RXDAT_DAT_Msk (0xfful << PS2_RXDAT_DAT_Pos)
18999#define PS2_STATUS_CLKSTAT_Pos (0)
19000#define PS2_STATUS_CLKSTAT_Msk (0x1ul << PS2_STATUS_CLKSTAT_Pos)
19002#define PS2_STATUS_DATSTAT_Pos (1)
19003#define PS2_STATUS_DATSTAT_Msk (0x1ul << PS2_STATUS_DATSTAT_Pos)
19005#define PS2_STATUS_FRAMEERR_Pos (2)
19006#define PS2_STATUS_FRAMEERR_Msk (0x1ul << PS2_STATUS_FRAMEERR_Pos)
19008#define PS2_STATUS_RXPARITY_Pos (3)
19009#define PS2_STATUS_RXPARITY_Msk (0x1ul << PS2_STATUS_RXPARITY_Pos)
19011#define PS2_STATUS_RXBUSY_Pos (4)
19012#define PS2_STATUS_RXBUSY_Msk (0x1ul << PS2_STATUS_RXBUSY_Pos)
19014#define PS2_STATUS_TXBUSY_Pos (5)
19015#define PS2_STATUS_TXBUSY_Msk (0x1ul << PS2_STATUS_TXBUSY_Pos)
19017#define PS2_STATUS_RXOV_Pos (6)
19018#define PS2_STATUS_RXOV_Msk (0x1ul << PS2_STATUS_RXOV_Pos)
19020#define PS2_STATUS_TXEMPTY_Pos (7)
19021#define PS2_STATUS_TXEMPTY_Msk (0x1ul << PS2_STATUS_TXEMPTY_Pos)
19023#define PS2_STATUS_BYTEIDX_Pos (8)
19024#define PS2_STATUS_BYTEIDX_Msk (0xful << PS2_STATUS_BYTEIDX_Pos)
19026#define PS2_INTSTS_RXIF_Pos (0)
19027#define PS2_INTSTS_RXIF_Msk (0x1ul << PS2_INTSTS_RXIF_Pos)
19029#define PS2_INTSTS_TXIF_Pos (1)
19030#define PS2_INTSTS_TXIF_Msk (0x1ul << PS2_INTSTS_TXIF_Pos) /* PS2_CONST */ /* end of PS2 register group */
19034
19035
19036/*---------------------- Pulse Width Modulation Controller -------------------------*/
19042 typedef struct {
19043
19044
19068 __IO uint32_t CLKPSC;
19069
19096 __IO uint32_t CLKDIV;
19097
19141 __IO uint32_t CTL;
19142
19155 __IO uint32_t CNTEN;
19156
19183 __IO uint32_t PERIOD[6];
19184
19208 __IO uint32_t CMPDAT[6];
19209
19221 __I uint32_t CNT[6];
19222
19237 __IO uint32_t MSKEN;
19238
19252 __IO uint32_t MSK;
19253
19291 __IO uint32_t DTCTL;
19292
19322 __IO uint32_t TRGADCTL;
19323
19352 __IO uint32_t TRGADCSTS;
19353
19411 __IO uint32_t BRKCTL;
19412
19431 __IO uint32_t INTCTL;
19432
19460 __IO uint32_t INTEN;
19461
19503 __IO uint32_t INTSTS;
19504
19517 __IO uint32_t POEN;
19518
19543 __IO uint32_t CAPCTL;
19544
19559 __IO uint32_t CAPINEN;
19560
19575 __I uint32_t CAPSTS;
19577 uint32_t RESERVE0[1];
19579
19580
19591 __I uint32_t RCAPDAT0;
19592
19603 __I uint32_t FCAPDAT0;
19604
19615 __I uint32_t RCAPDAT1;
19616
19627 __I uint32_t FCAPDAT1;
19628
19639 __I uint32_t RCAPDAT2;
19640
19651 __I uint32_t FCAPDAT2;
19652
19663 __I uint32_t RCAPDAT3;
19664
19675 __I uint32_t FCAPDAT3;
19676
19687 __I uint32_t RCAPDAT4;
19688
19699 __I uint32_t FCAPDAT4;
19700
19711 __I uint32_t RCAPDAT5;
19712
19723 __I uint32_t FCAPDAT5;
19725 uint32_t RESERVE1[8];
19727
19728
19741 __I uint32_t SBS[6];
19742
19743} PWM_T;
19744
19750#define PWM_CLKPSC_CLKPSC01_Pos (0)
19751#define PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos)
19753#define PWM_CLKPSC_CLKPSC23_Pos (8)
19754#define PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos)
19756#define PWM_CLKPSC_CLKPSC45_Pos (16)
19757#define PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos)
19759#define PWM_CLKDIV_CLKDIV0_Pos (0)
19760#define PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos)
19762#define PWM_CLKDIV_CLKDIV1_Pos (4)
19763#define PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos)
19765#define PWM_CLKDIV_CLKDIV2_Pos (8)
19766#define PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos)
19768#define PWM_CLKDIV_CLKDIV3_Pos (12)
19769#define PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos)
19771#define PWM_CLKDIV_CLKDIV4_Pos (16)
19772#define PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos)
19774#define PWM_CLKDIV_CLKDIV5_Pos (20)
19775#define PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos)
19777#define PWM_CTL_CMPINV_Pos (0)
19778#define PWM_CTL_CMPINV_Msk (0x3ful << PWM_CTL_CMPINV_Pos)
19780#define PWM_CTL_OUTMODE_Pos (6)
19781#define PWM_CTL_OUTMODE_Msk (0x1ul << PWM_CTL_OUTMODE_Pos)
19783#define PWM_CTL_GROUPEN_Pos (7)
19784#define PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos)
19786#define PWM_CTL_PINV_Pos (8)
19787#define PWM_CTL_PINV_Msk (0x3ful << PWM_CTL_PINV_Pos)
19789#define PWM_CTL_SYNCEN_Pos (15)
19790#define PWM_CTL_SYNCEN_Msk (0x1ul << PWM_CTL_SYNCEN_Pos)
19792#define PWM_CTL_CNTMODE_Pos (16)
19793#define PWM_CTL_CNTMODE_Msk (0x3ful << PWM_CTL_CNTMODE_Pos)
19795#define PWM_CTL_CNTTYPE_Pos (24)
19796#define PWM_CTL_CNTTYPE_Msk (0x3ful << PWM_CTL_CNTTYPE_Pos)
19798#define PWM_CTL_DBGTRIOFF_Pos (31)
19799#define PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos)
19801#define PWM_CNTEN_CNTEN_Pos (0)
19802#define PWM_CNTEN_CNTEN_Msk (0x3ful << PWM_CNTEN_CNTEN_Pos)
19804#define PWM_PERIOD0_PERIOD_Pos (0)
19805#define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos)
19807#define PWM_PERIOD1_PERIOD_Pos (0)
19808#define PWM_PERIOD1_PERIOD_Msk (0xfffful << PWM_PERIOD1_PERIOD_Pos)
19810#define PWM_PERIOD2_PERIOD_Pos (0)
19811#define PWM_PERIOD2_PERIOD_Msk (0xfffful << PWM_PERIOD2_PERIOD_Pos)
19813#define PWM_PERIOD3_PERIOD_Pos (0)
19814#define PWM_PERIOD3_PERIOD_Msk (0xfffful << PWM_PERIOD3_PERIOD_Pos)
19816#define PWM_PERIOD4_PERIOD_Pos (0)
19817#define PWM_PERIOD4_PERIOD_Msk (0xfffful << PWM_PERIOD4_PERIOD_Pos)
19819#define PWM_PERIOD5_PERIOD_Pos (0)
19820#define PWM_PERIOD5_PERIOD_Msk (0xfffful << PWM_PERIOD5_PERIOD_Pos)
19822#define PWM_CMPDAT0_CMP_Pos (0)
19823#define PWM_CMPDAT0_CMP_Msk (0xfffful << PWM_CMPDAT0_CMP_Pos)
19825#define PWM_CMPDAT1_CMP_Pos (0)
19826#define PWM_CMPDAT1_CMP_Msk (0xfffful << PWM_CMPDAT1_CMP_Pos)
19828#define PWM_CMPDAT2_CMP_Pos (0)
19829#define PWM_CMPDAT2_CMP_Msk (0xfffful << PWM_CMPDAT2_CMP_Pos)
19831#define PWM_CMPDAT3_CMP_Pos (0)
19832#define PWM_CMPDAT3_CMP_Msk (0xfffful << PWM_CMPDAT3_CMP_Pos)
19834#define PWM_CMPDAT4_CMP_Pos (0)
19835#define PWM_CMPDAT4_CMP_Msk (0xfffful << PWM_CMPDAT4_CMP_Pos)
19837#define PWM_CMPDAT5_CMP_Pos (0)
19838#define PWM_CMPDAT5_CMP_Msk (0xfffful << PWM_CMPDAT5_CMP_Pos)
19840#define PWM_CNT0_CNT_Pos (0)
19841#define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos)
19843#define PWM_CNT1_CNT_Pos (0)
19844#define PWM_CNT1_CNT_Msk (0xfffful << PWM_CNT1_CNT_Pos)
19846#define PWM_CNT2_CNT_Pos (0)
19847#define PWM_CNT2_CNT_Msk (0xfffful << PWM_CNT2_CNT_Pos)
19849#define PWM_CNT3_CNT_Pos (0)
19850#define PWM_CNT3_CNT_Msk (0xfffful << PWM_CNT3_CNT_Pos)
19852#define PWM_CNT4_CNT_Pos (0)
19853#define PWM_CNT4_CNT_Msk (0xfffful << PWM_CNT4_CNT_Pos)
19855#define PWM_CNT5_CNT_Pos (0)
19856#define PWM_CNT5_CNT_Msk (0xfffful << PWM_CNT5_CNT_Pos)
19858#define PWM_MSKEN_MSKEN_Pos (0)
19859#define PWM_MSKEN_MSKEN_Msk (0x3ful << PWM_MSKEN_MSKEN_Pos)
19861#define PWM_MSK_MSKDAT_Pos (0)
19862#define PWM_MSK_MSKDAT_Msk (0x3ful << PWM_MSK_MSKDAT_Pos)
19864#define PWM_DTCTL_DTCNT01_Pos (0)
19865#define PWM_DTCTL_DTCNT01_Msk (0xfful << PWM_DTCTL_DTCNT01_Pos)
19867#define PWM_DTCTL_DTCNT23_Pos (8)
19868#define PWM_DTCTL_DTCNT23_Msk (0xfful << PWM_DTCTL_DTCNT23_Pos)
19870#define PWM_DTCTL_DTCNT45_Pos (16)
19871#define PWM_DTCTL_DTCNT45_Msk (0xfful << PWM_DTCTL_DTCNT45_Pos)
19873#define PWM_DTCTL_DTDIV_Pos (24)
19874#define PWM_DTCTL_DTDIV_Msk (0x3ul << PWM_DTCTL_DTDIV_Pos)
19876#define PWM_DTCTL_DTEN01_Pos (28)
19877#define PWM_DTCTL_DTEN01_Msk (0x1ul << PWM_DTCTL_DTEN01_Pos)
19879#define PWM_DTCTL_DTEN23_Pos (29)
19880#define PWM_DTCTL_DTEN23_Msk (0x1ul << PWM_DTCTL_DTEN23_Pos)
19882#define PWM_DTCTL_DTEN45_Pos (30)
19883#define PWM_DTCTL_DTEN45_Msk (0x1ul << PWM_DTCTL_DTEN45_Pos)
19885#define PWM_TRGADCTL_PTRGEN_Pos (0)
19886#define PWM_TRGADCTL_PTRGEN_Msk (0x3ful << PWM_TRGADCTL_PTRGEN_Pos)
19888#define PWM_TRGADCTL_CTRGEN_Pos (8)
19889#define PWM_TRGADCTL_CTRGEN_Msk (0x3ful << PWM_TRGADCTL_CTRGEN_Pos)
19891#define PWM_TRGADCTL_FTRGEN_Pos (16)
19892#define PWM_TRGADCTL_FTRGEN_Msk (0x3ful << PWM_TRGADCTL_FTRGEN_Pos)
19894#define PWM_TRGADCTL_RTRGEN_Pos (24)
19895#define PWM_TRGADCTL_RTRGEN_Msk (0x3ful << PWM_TRGADCTL_RTRGEN_Pos)
19897#define PWM_TRGADCSTS_PTRGF_Pos (0)
19898#define PWM_TRGADCSTS_PTRGF_Msk (0x3ful << PWM_TRGADCSTS_PTRGF_Pos)
19900#define PWM_TRGADCSTS_CTRGF_Pos (8)
19901#define PWM_TRGADCSTS_CTRGF_Msk (0x3ful << PWM_TRGADCSTS_CTRGF_Pos)
19903#define PWM_TRGADCSTS_FTRGF_Pos (16)
19904#define PWM_TRGADCSTS_FTRGF_Msk (0x3ful << PWM_TRGADCSTS_FTRGF_Pos)
19906#define PWM_TRGADCSTS_RTRGF_Pos (24)
19907#define PWM_TRGADCSTS_RTRGF_Msk (0x3ful << PWM_TRGADCSTS_RTRGF_Pos)
19909#define PWM_BRKCTL_BRK0EN_Pos (0)
19910#define PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos)
19912#define PWM_BRKCTL_BRK0NFDIS_Pos (1)
19913#define PWM_BRKCTL_BRK0NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK0NFDIS_Pos)
19915#define PWM_BRKCTL_BRK0INV_Pos (2)
19916#define PWM_BRKCTL_BRK0INV_Msk (0x1ul << PWM_BRKCTL_BRK0INV_Pos)
19918#define PWM_BRKCTL_BRK0NFSEL_Pos (6)
19919#define PWM_BRKCTL_BRK0NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK0NFSEL_Pos)
19921#define PWM_BRKCTL_BRK1EN_Pos (8)
19922#define PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos)
19924#define PWM_BRKCTL_BRK1NFDIS_Pos (9)
19925#define PWM_BRKCTL_BRK1NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK1NFDIS_Pos)
19927#define PWM_BRKCTL_BRK1INV_Pos (10)
19928#define PWM_BRKCTL_BRK1INV_Msk (0x1ul << PWM_BRKCTL_BRK1INV_Pos)
19930#define PWM_BRKCTL_BK1SEL_Pos (12)
19931#define PWM_BRKCTL_BK1SEL_Msk (0x3ul << PWM_BRKCTL_BK1SEL_Pos)
19933#define PWM_BRKCTL_BRK1NFSEL_Pos (14)
19934#define PWM_BRKCTL_BRK1NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK1NFSEL_Pos)
19936#define PWM_BRKCTL_CPO0BKEN_Pos (16)
19937#define PWM_BRKCTL_CPO0BKEN_Msk (0x1ul << PWM_BRKCTL_CPO0BKEN_Pos)
19939#define PWM_BRKCTL_CPO1BKEN_Pos (17)
19940#define PWM_BRKCTL_CPO1BKEN_Msk (0x1ul << PWM_BRKCTL_CPO1BKEN_Pos)
19942#define PWM_BRKCTL_CPO2BKEN_Pos (18)
19943#define PWM_BRKCTL_CPO2BKEN_Msk (0x1ul << PWM_BRKCTL_CPO2BKEN_Pos)
19945#define PWM_BRKCTL_LVDBKEN_Pos (19)
19946#define PWM_BRKCTL_LVDBKEN_Msk (0x1ul << PWM_BRKCTL_LVDBKEN_Pos)
19948#define PWM_BRKCTL_BKOD_Pos (24)
19949#define PWM_BRKCTL_BKOD_Msk (0x3ful << PWM_BRKCTL_BKOD_Pos)
19951#define PWM_INTCTL_PINTTYPE_Pos (0)
19952#define PWM_INTCTL_PINTTYPE_Msk (0x3ful << PWM_INTCTL_PINTTYPE_Pos)
19954#define PWM_INTCTL_DINTTYPE_Pos (8)
19955#define PWM_INTCTL_DINTTYPE_Msk (0x3ful << PWM_INTCTL_DINTTYPE_Pos)
19957#define PWM_INTEN_PIEN_Pos (0)
19958#define PWM_INTEN_PIEN_Msk (0x3ful << PWM_INTEN_PIEN_Pos)
19960#define PWM_INTEN_BRKIEN_Pos (6)
19961#define PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos)
19963#define PWM_INTEN_DIEN_Pos (8)
19964#define PWM_INTEN_DIEN_Msk (0x3ful << PWM_INTEN_DIEN_Pos)
19966#define PWM_INTEN_RLIEN_Pos (16)
19967#define PWM_INTEN_RLIEN_Msk (0x3ful << PWM_INTEN_RLIEN_Pos)
19969#define PWM_INTEN_FLIEN_Pos (24)
19970#define PWM_INTEN_FLIEN_Msk (0x3ful << PWM_INTEN_FLIEN_Pos)
19972#define PWM_INTSTS_PIF_Pos (0)
19973#define PWM_INTSTS_PIF_Msk (0x3ful << PWM_INTSTS_PIF_Pos)
19975#define PWM_INTSTS_BRKIF0_Pos (6)
19976#define PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos)
19978#define PWM_INTSTS_BRKIF1_Pos (7)
19979#define PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos)
19981#define PWM_INTSTS_DIF_Pos (8)
19982#define PWM_INTSTS_DIF_Msk (0x3ful << PWM_INTSTS_DIF_Pos)
19984#define PWM_INTSTS_BRKLK0_Pos (14)
19985#define PWM_INTSTS_BRKLK0_Msk (0x1ul << PWM_INTSTS_BRKLK0_Pos)
19987#define PWM_INTSTS_CRLIF_Pos (16)
19988#define PWM_INTSTS_CRLIF_Msk (0x3ful << PWM_INTSTS_CRLIF_Pos)
19990#define PWM_INTSTS_BRKSTS0_Pos (22)
19991#define PWM_INTSTS_BRKSTS0_Msk (0x1ul << PWM_INTSTS_BRKSTS0_Pos)
19993#define PWM_INTSTS_BRKSTS1_Pos (23)
19994#define PWM_INTSTS_BRKSTS1_Msk (0x1ul << PWM_INTSTS_BRKSTS1_Pos)
19996#define PWM_INTSTS_CFLIF_Pos (24)
19997#define PWM_INTSTS_CFLIF_Msk (0x3ful << PWM_INTSTS_CFLIF_Pos)
19999#define PWM_POEN_POEN_Pos (0)
20000#define PWM_POEN_POEN_Msk (0x3ful << PWM_POEN_POEN_Pos)
20002#define PWM_CAPCTL_CAPEN_Pos (0)
20003#define PWM_CAPCTL_CAPEN_Msk (0x3ful << PWM_CAPCTL_CAPEN_Pos)
20005#define PWM_CAPCTL_CAPINV_Pos (8)
20006#define PWM_CAPCTL_CAPINV_Msk (0x3ful << PWM_CAPCTL_CAPINV_Pos)
20008#define PWM_CAPCTL_RCRLDEN_Pos (16)
20009#define PWM_CAPCTL_RCRLDEN_Msk (0x3ful << PWM_CAPCTL_RCRLDEN_Pos)
20011#define PWM_CAPCTL_FCRLDEN_Pos (24)
20012#define PWM_CAPCTL_FCRLDEN_Msk (0x3ful << PWM_CAPCTL_FCRLDEN_Pos)
20014#define PWM_CAPINEN_CAPINEN_Pos (0)
20015#define PWM_CAPINEN_CAPINEN_Msk (0x3ful << PWM_CAPINEN_CAPINEN_Pos)
20017#define PWM_CAPSTS_CRIFOV_Pos (0)
20018#define PWM_CAPSTS_CRIFOV_Msk (0x3ful << PWM_CAPSTS_CRIFOV_Pos)
20020#define PWM_CAPSTS_FLIFOV_Pos (8)
20021#define PWM_CAPSTS_FLIFOV_Msk (0x3ful << PWM_CAPSTS_FLIFOV_Pos)
20023#define PWM_RCAPDAT0_RCAPDAT_Pos (0)
20024#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos)
20026#define PWM_FCAPDAT0_FCAPDAT_Pos (0)
20027#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos)
20029#define PWM_RCAPDAT1_RCAPDAT_Pos (0)
20030#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos)
20032#define PWM_FCAPDAT1_FCAPDAT_Pos (0)
20033#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos)
20035#define PWM_RCAPDAT2_RCAPDAT_Pos (0)
20036#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos)
20038#define PWM_FCAPDAT2_FCAPDAT_Pos (0)
20039#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos)
20041#define PWM_RCAPDAT3_RCAPDAT_Pos (0)
20042#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos)
20044#define PWM_FCAPDAT3_FCAPDAT_Pos (0)
20045#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos)
20047#define PWM_RCAPDAT4_RCAPDAT_Pos (0)
20048#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos)
20050#define PWM_FCAPDAT4_FCAPDAT_Pos (0)
20051#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos)
20053#define PWM_RCAPDAT5_RCAPDAT_Pos (0)
20054#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos)
20056#define PWM_FCAPDAT5_FCAPDAT_Pos (0)
20057#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos)
20059#define PWM_SBS0_SYNCBUSY_Pos (0)
20060#define PWM_SBS0_SYNCBUSY_Msk (0x1ul << PWM_SBS0_SYNCBUSY_Pos)
20062#define PWM_SBS1_SYNCBUSY_Pos (0)
20063#define PWM_SBS1_SYNCBUSY_Msk (0x1ul << PWM_SBS1_SYNCBUSY_Pos)
20065#define PWM_SBS2_SYNCBUSY_Pos (0)
20066#define PWM_SBS2_SYNCBUSY_Msk (0x1ul << PWM_SBS2_SYNCBUSY_Pos)
20068#define PWM_SBS3_SYNCBUSY_Pos (0)
20069#define PWM_SBS3_SYNCBUSY_Msk (0x1ul << PWM_SBS3_SYNCBUSY_Pos)
20071#define PWM_SBS4_SYNCBUSY_Pos (0)
20072#define PWM_SBS4_SYNCBUSY_Msk (0x1ul << PWM_SBS4_SYNCBUSY_Pos)
20074#define PWM_SBS5_SYNCBUSY_Pos (0)
20075#define PWM_SBS5_SYNCBUSY_Msk (0x1ul << PWM_SBS5_SYNCBUSY_Pos) /* PWM_CONST */ /* end of PWM register group */
20079
20080
20081/*---------------------- Quadrature Encoder Interface -------------------------*/
20087 typedef struct {
20088
20089
20106 __IO uint32_t CNT;
20107
20118 __IO uint32_t CNTHOLD;
20119
20130 __IO uint32_t CNTLATCH;
20131
20143 __IO uint32_t CNTCMP;
20145 uint32_t RESERVE0[1];
20147
20148
20159 __IO uint32_t CNTMAX;
20160
20247 __IO uint32_t CTR;
20249 uint32_t RESERVE1[4];
20251
20252
20287 __IO uint32_t STATUS;
20288
20289} QEI_T;
20290
20296#define QEI_CNT_VAL_Pos (0)
20297#define QEI_CNT_VAL_Msk (0xfffffffful << QEI_CNT_VAL_Pos)
20299#define QEI_CNTHOLD_VAL_Pos (0)
20300#define QEI_CNTHOLD_VAL_Msk (0xfffffffful << QEI_CNTHOLD_VAL_Pos)
20302#define QEI_CNTLATCH_VAL_Pos (0)
20303#define QEI_CNTLATCH_VAL_Msk (0xfffffffful << QEI_CNTLATCH_VAL_Pos)
20305#define QEI_CNTCMP_VAL_Pos (0)
20306#define QEI_CNTCMP_VAL_Msk (0xfffffffful << QEI_CNTCMP_VAL_Pos)
20308#define QEI_CNTMAX_VAL_Pos (0)
20309#define QEI_CNTMAX_VAL_Msk (0xfffffffful << QEI_CNTMAX_VAL_Pos)
20311#define QEI_CTR_NFCLKSEL_Pos (0)
20312#define QEI_CTR_NFCLKSEL_Msk (0x3ul << QEI_CTR_NFCLKSEL_Pos)
20314#define QEI_CTR_NFDIS_Pos (3)
20315#define QEI_CTR_NFDIS_Msk (0x1ul << QEI_CTR_NFDIS_Pos)
20317#define QEI_CTR_CHAEN_Pos (4)
20318#define QEI_CTR_CHAEN_Msk (0x1ul << QEI_CTR_CHAEN_Pos)
20320#define QEI_CTR_CHBEN_Pos (5)
20321#define QEI_CTR_CHBEN_Msk (0x1ul << QEI_CTR_CHBEN_Pos)
20323#define QEI_CTR_IDXEN_Pos (6)
20324#define QEI_CTR_IDXEN_Msk (0x1ul << QEI_CTR_IDXEN_Pos)
20326#define QEI_CTR_MODE_Pos (8)
20327#define QEI_CTR_MODE_Msk (0x3ul << QEI_CTR_MODE_Pos)
20329#define QEI_CTR_CHAINV_Pos (12)
20330#define QEI_CTR_CHAINV_Msk (0x1ul << QEI_CTR_CHAINV_Pos)
20332#define QEI_CTR_CHBINV_Pos (13)
20333#define QEI_CTR_CHBINV_Msk (0x1ul << QEI_CTR_CHBINV_Pos)
20335#define QEI_CTR_IDXINV_Pos (14)
20336#define QEI_CTR_IDXINV_Msk (0x1ul << QEI_CTR_IDXINV_Pos)
20338#define QEI_CTR_OVUNIEN_Pos (16)
20339#define QEI_CTR_OVUNIEN_Msk (0x1ul << QEI_CTR_OVUNIEN_Pos)
20341#define QEI_CTR_DIRIEN_Pos (17)
20342#define QEI_CTR_DIRIEN_Msk (0x1ul << QEI_CTR_DIRIEN_Pos)
20344#define QEI_CTR_CMPIEN_Pos (18)
20345#define QEI_CTR_CMPIEN_Msk (0x1ul << QEI_CTR_CMPIEN_Pos)
20347#define QEI_CTR_IDXIEN_Pos (19)
20348#define QEI_CTR_IDXIEN_Msk (0x1ul << QEI_CTR_IDXIEN_Pos)
20350#define QEI_CTR_HOLDTMR0_Pos (20)
20351#define QEI_CTR_HOLDTMR0_Msk (0x1ul << QEI_CTR_HOLDTMR0_Pos)
20353#define QEI_CTR_HOLDTMR1_Pos (21)
20354#define QEI_CTR_HOLDTMR1_Msk (0x1ul << QEI_CTR_HOLDTMR1_Pos)
20356#define QEI_CTR_HOLDTMR2_Pos (22)
20357#define QEI_CTR_HOLDTMR2_Msk (0x1ul << QEI_CTR_HOLDTMR2_Pos)
20359#define QEI_CTR_HOLDTMR3_Pos (23)
20360#define QEI_CTR_HOLDTMR3_Msk (0x1ul << QEI_CTR_HOLDTMR3_Pos)
20362#define QEI_CTR_HOLDCNT_Pos (24)
20363#define QEI_CTR_HOLDCNT_Msk (0x1ul << QEI_CTR_HOLDCNT_Pos)
20365#define QEI_CTR_IDXLATEN_Pos (25)
20366#define QEI_CTR_IDXLATEN_Msk (0x1ul << QEI_CTR_IDXLATEN_Pos)
20368#define QEI_CTR_IDXRLDEN_Pos (27)
20369#define QEI_CTR_IDXRLDEN_Msk (0x1ul << QEI_CTR_IDXRLDEN_Pos)
20371#define QEI_CTR_CMPENN_Pos (28)
20372#define QEI_CTR_CMPENN_Msk (0x1ul << QEI_CTR_CMPENN_Pos)
20374#define QEI_CTR_QEIEN_Pos (29)
20375#define QEI_CTR_QEIEN_Msk (0x1ul << QEI_CTR_QEIEN_Pos)
20377#define QEI_STATUS_IDXF_Pos (0)
20378#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos)
20380#define QEI_STATUS_CMPF_Pos (1)
20381#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos)
20383#define QEI_STATUS_OVUNF_Pos (2)
20384#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos)
20386#define QEI_STATUS_DIRCHGF_Pos (3)
20387#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos)
20389#define QEI_STATUS_DIRF_Pos (8)
20390#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /* QEI_CONST */ /* end of QEI register group */
20394
20395
20396/*---------------------- Real Time Clock Controller -------------------------*/
20402 typedef struct {
20403
20420 __IO uint32_t INIT;
20421
20436 __O uint32_t RWEN;
20437
20450 __IO uint32_t FREQADJ;
20451
20466 __IO uint32_t TIME;
20467
20482 __IO uint32_t CAL;
20483
20496 __IO uint32_t CLKFMT;
20497
20515 __IO uint32_t WEEKDAY;
20516
20531 __IO uint32_t TALM;
20532
20547 __IO uint32_t CALM;
20548
20560 __I uint32_t LEAPYEAR;
20561
20576 __IO uint32_t INTEN;
20577
20594 __IO uint32_t INTSTS;
20595
20615 __IO uint32_t TICK;
20617 uint32_t RESERVE0[2];
20619
20620
20639 __IO uint32_t SPRCTL;
20640
20653 __IO uint32_t SPR[24];
20655 uint32_t RESERVE1[28];
20657
20658
20691 __IO uint32_t TAMPCTL;
20692
20709 __IO uint32_t TAMPSTS;
20711 uint32_t RESERVE2[3];
20713
20714
20738 __IO uint32_t TAMP0PCTL;
20739
20763 __IO uint32_t TAMP1PCTL;
20764
20788 __IO uint32_t LXTIPCTL;
20789
20813 __IO uint32_t LXTOPCTL;
20815 uint32_t RESERVE3[3];
20817
20818
20833 __IO uint32_t TAMSK;
20834
20849 __IO uint32_t CAMSK;
20850
20851} RTC_T;
20852
20858#define RTC_INIT_INIT_Active_Pos (0)
20859#define RTC_INIT_INIT_Active_Msk (0x1ul << RTC_INIT_INIT_Active_Pos)
20861#define RTC_INIT_INIT_Pos (1)
20862#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos)
20864#define RTC_RWEN_RWEN_Pos (0)
20865#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos)
20867#define RTC_RWEN_RWENF_Pos (16)
20868#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos)
20870#define RTC_FREQADJ_FRACTION_Pos (0)
20871#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos)
20873#define RTC_FREQADJ_INTEGER_Pos (8)
20874#define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos)
20876#define RTC_TIME_SEC_Pos (0)
20877#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos)
20879#define RTC_TIME_TENSEC_Pos (4)
20880#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos)
20882#define RTC_TIME_MIN_Pos (8)
20883#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos)
20885#define RTC_TIME_TENMIN_Pos (12)
20886#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos)
20888#define RTC_TIME_HR_Pos (16)
20889#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos)
20891#define RTC_TIME_TENHR_Pos (20)
20892#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos)
20894#define RTC_CAL_DAY_Pos (0)
20895#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos)
20897#define RTC_CAL_TENDAY_Pos (4)
20898#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos)
20900#define RTC_CAL_MON_Pos (8)
20901#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos)
20903#define RTC_CAL_TENMON_Pos (12)
20904#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos)
20906#define RTC_CAL_YEAR_Pos (16)
20907#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos)
20909#define RTC_CAL_TENYEAR_Pos (20)
20910#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos)
20912#define RTC_CLKFMT_24HEN_Pos (0)
20913#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos)
20915#define RTC_WEEKDAY_WEEKDAY_Pos (0)
20916#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)
20918#define RTC_TALM_SEC_Pos (0)
20919#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos)
20921#define RTC_TALM_TENSEC_Pos (4)
20922#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos)
20924#define RTC_TALM_MIN_Pos (8)
20925#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos)
20927#define RTC_TALM_TENMIN_Pos (12)
20928#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos)
20930#define RTC_TALM_HR_Pos (16)
20931#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos)
20933#define RTC_TALM_TENHR_Pos (20)
20934#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos)
20936#define RTC_CALM_DAY_Pos (0)
20937#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos)
20939#define RTC_CALM_TENDAY_Pos (4)
20940#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos)
20942#define RTC_CALM_MON_Pos (8)
20943#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos)
20945#define RTC_CALM_TENMON_Pos (12)
20946#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos)
20948#define RTC_CALM_YEAR_Pos (16)
20949#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos)
20951#define RTC_CALM_TENYEAR_Pos (20)
20952#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos)
20954#define RTC_LEAPYEAR_LEAPYEAR_Pos (0)
20955#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)
20957#define RTC_INTEN_ALMIEN_Pos (0)
20958#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos)
20960#define RTC_INTEN_TICKIEN_Pos (1)
20961#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos)
20963#define RTC_INTSTS_ALMIF_Pos (0)
20964#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos)
20966#define RTC_INTSTS_TICKIF_Pos (1)
20967#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos)
20969#define RTC_TICK_TICKSEL_Pos (0)
20970#define RTC_TICK_TICKSEL_Msk (0x7ul << RTC_TICK_TICKSEL_Pos)
20972#define RTC_SPRCTL_SPRRWEN_Pos (2)
20973#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)
20975#define RTC_SPRCTL_SPRRWRDY_Pos (7)
20976#define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos)
20978#define RTC_TAMPCTL_TIEN_Pos (0)
20979#define RTC_TAMPCTL_TIEN_Msk (0x1ul << RTC_TAMPCTL_TIEN_Pos)
20981#define RTC_TAMPCTL_DESTROYEN_Pos (1)
20982#define RTC_TAMPCTL_DESTROYEN_Msk (0x1ul << RTC_TAMPCTL_DESTROYEN_Pos)
20984#define RTC_TAMPCTL_TAMPEN0_Pos (2)
20985#define RTC_TAMPCTL_TAMPEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPEN0_Pos)
20987#define RTC_TAMPCTL_TAMPEN1_Pos (3)
20988#define RTC_TAMPCTL_TAMPEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPEN1_Pos)
20990#define RTC_TAMPCTL_TAMPDBEN0_Pos (4)
20991#define RTC_TAMPCTL_TAMPDBEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN0_Pos)
20993#define RTC_TAMPCTL_TAMPDBEN1_Pos (5)
20994#define RTC_TAMPCTL_TAMPDBEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN1_Pos)
20996#define RTC_TAMPCTL_TAMPLV0_Pos (6)
20997#define RTC_TAMPCTL_TAMPLV0_Msk (0x1ul << RTC_TAMPCTL_TAMPLV0_Pos)
20999#define RTC_TAMPCTL_TAMPLV1_Pos (7)
21000#define RTC_TAMPCTL_TAMPLV1_Msk (0x1ul << RTC_TAMPCTL_TAMPLV1_Pos)
21002#define RTC_TAMPSTS_TAMPSTS0_Pos (0)
21003#define RTC_TAMPSTS_TAMPSTS0_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS0_Pos)
21005#define RTC_TAMPSTS_TAMPSTS1_Pos (1)
21006#define RTC_TAMPSTS_TAMPSTS1_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS1_Pos)
21008#define RTC_TAMP0PCTL_OUTLV_Pos (0)
21009#define RTC_TAMP0PCTL_OUTLV_Msk (0x1ul << RTC_TAMP0PCTL_OUTLV_Pos)
21011#define RTC_TAMP0PCTL_OUTEN_Pos (1)
21012#define RTC_TAMP0PCTL_OUTEN_Msk (0x1ul << RTC_TAMP0PCTL_OUTEN_Pos)
21014#define RTC_TAMP0PCTL_TRIEN_Pos (2)
21015#define RTC_TAMP0PCTL_TRIEN_Msk (0x1ul << RTC_TAMP0PCTL_TRIEN_Pos)
21017#define RTC_TAMP0PCTL_TYPE_Pos (3)
21018#define RTC_TAMP0PCTL_TYPE_Msk (0x1ul << RTC_TAMP0PCTL_TYPE_Pos)
21020#define RTC_TAMP0PCTL_DINOFF_Pos (4)
21021#define RTC_TAMP0PCTL_DINOFF_Msk (0x1ul << RTC_TAMP0PCTL_DINOFF_Pos)
21023#define RTC_TAMP1PCTL_OUTLV_Pos (0)
21024#define RTC_TAMP1PCTL_OUTLV_Msk (0x1ul << RTC_TAMP1PCTL_OUTLV_Pos)
21026#define RTC_TAMP1PCTL_OUTEN_Pos (1)
21027#define RTC_TAMP1PCTL_OUTEN_Msk (0x1ul << RTC_TAMP1PCTL_OUTEN_Pos)
21029#define RTC_TAMP1PCTL_TRIEN_Pos (2)
21030#define RTC_TAMP1PCTL_TRIEN_Msk (0x1ul << RTC_TAMP1PCTL_TRIEN_Pos)
21032#define RTC_TAMP1PCTL_TYPE_Pos (3)
21033#define RTC_TAMP1PCTL_TYPE_Msk (0x1ul << RTC_TAMP1PCTL_TYPE_Pos)
21035#define RTC_TAMP1PCTL_DINOFF_Pos (4)
21036#define RTC_TAMP1PCTL_DINOFF_Msk (0x1ul << RTC_TAMP1PCTL_DINOFF_Pos)
21038#define RTC_LXTIPCTL_OUTLV_Pos (0)
21039#define RTC_LXTIPCTL_OUTLV_Msk (0x1ul << RTC_LXTIPCTL_OUTLV_Pos)
21041#define RTC_LXTIPCTL_OUTEN_Pos (1)
21042#define RTC_LXTIPCTL_OUTEN_Msk (0x1ul << RTC_LXTIPCTL_OUTEN_Pos)
21044#define RTC_LXTIPCTL_TRIEN_Pos (2)
21045#define RTC_LXTIPCTL_TRIEN_Msk (0x1ul << RTC_LXTIPCTL_TRIEN_Pos)
21047#define RTC_LXTIPCTL_TYPE_Pos (3)
21048#define RTC_LXTIPCTL_TYPE_Msk (0x1ul << RTC_LXTIPCTL_TYPE_Pos)
21050#define RTC_LXTIPCTL_DINOFF_Pos (4)
21051#define RTC_LXTIPCTL_DINOFF_Msk (0x1ul << RTC_LXTIPCTL_DINOFF_Pos)
21053#define RTC_LXTOPCTL_OUTLV_Pos (0)
21054#define RTC_LXTOPCTL_OUTLV_Msk (0x1ul << RTC_LXTOPCTL_OUTLV_Pos)
21056#define RTC_LXTOPCTL_OUTEN_Pos (1)
21057#define RTC_LXTOPCTL_OUTEN_Msk (0x1ul << RTC_LXTOPCTL_OUTEN_Pos)
21059#define RTC_LXTOPCTL_TRIEN_Pos (2)
21060#define RTC_LXTOPCTL_TRIEN_Msk (0x1ul << RTC_LXTOPCTL_TRIEN_Pos)
21062#define RTC_LXTOPCTL_TYPE_Pos (3)
21063#define RTC_LXTOPCTL_TYPE_Msk (0x1ul << RTC_LXTOPCTL_TYPE_Pos)
21065#define RTC_LXTOPCTL_DINOFF_Pos (4)
21066#define RTC_LXTOPCTL_DINOFF_Msk (0x1ul << RTC_LXTOPCTL_DINOFF_Pos)
21068#define RTC_TAMSK_MSEC_Pos (0)
21069#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos)
21071#define RTC_TAMSK_MTENSEC_Pos (1)
21072#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos)
21074#define RTC_TAMSK_MMIN_Pos (2)
21075#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos)
21077#define RTC_TAMSK_MTENMIN_Pos (3)
21078#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos)
21080#define RTC_TAMSK_MHR_Pos (4)
21081#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos)
21083#define RTC_TAMSK_MTENHR_Pos (5)
21084#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos)
21086#define RTC_CAMSK_MDAY_Pos (0)
21087#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos)
21089#define RTC_CAMSK_MTENDAY_Pos (1)
21090#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos)
21092#define RTC_CAMSK_MMON_Pos (2)
21093#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos)
21095#define RTC_CAMSK_MTENMON_Pos (3)
21096#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos)
21098#define RTC_CAMSK_MYEAR_Pos (4)
21099#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos)
21101#define RTC_CAMSK_MTENYEAR_Pos (5)
21102#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /* RTC_CONST */ /* end of RTC register group */
21106
21107
21108/*---------------------- Smart Card Host Interface Controller -------------------------*/
21114 typedef struct {
21115
21116
21131 __IO uint32_t DAT;
21132
21226 __IO uint32_t CTL;
21227
21325 __IO uint32_t ALTCTL;
21326
21338 __IO uint32_t EGT;
21339
21353 __IO uint32_t RXTOUT;
21354
21372 __IO uint32_t ETUCTL;
21373
21427 __IO uint32_t INTEN;
21428
21479 __IO uint32_t INTSTS;
21480
21569 __IO uint32_t STATUS;
21570
21639 __IO uint32_t PINCTL;
21640
21654 __IO uint32_t TMRCTL0;
21655
21669 __IO uint32_t TMRCTL1;
21670
21684 __IO uint32_t TMRCTL2;
21685
21714 __IO uint32_t UARTCTL;
21715
21726 __I uint32_t TMRDAT0;
21727
21740 __I uint32_t TMRDAT1_2;
21741
21742} SC_T;
21743
21749#define SC_DAT_DAT_Pos (0)
21750#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
21752#define SC_CTL_SCEN_Pos (0)
21753#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos)
21755#define SC_CTL_RXOFF_Pos (1)
21756#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos)
21758#define SC_CTL_TXOFF_Pos (2)
21759#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos)
21761#define SC_CTL_AUTOCEN_Pos (3)
21762#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos)
21764#define SC_CTL_CONSEL_Pos (4)
21765#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos)
21767#define SC_CTL_RXTRGLV_Pos (6)
21768#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos)
21770#define SC_CTL_BGT_Pos (8)
21771#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
21773#define SC_CTL_TMRSEL_Pos (13)
21774#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos)
21776#define SC_CTL_NSB_Pos (15)
21777#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos)
21779#define SC_CTL_RXRTY_Pos (16)
21780#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos)
21782#define SC_CTL_RXRTYEN_Pos (19)
21783#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos)
21785#define SC_CTL_TXRTY_Pos (20)
21786#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos)
21788#define SC_CTL_TXRTYEN_Pos (23)
21789#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos)
21791#define SC_CTL_CDDBSEL_Pos (24)
21792#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos)
21794#define SC_CTL_CDLV_Pos (26)
21795#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos)
21797#define SC_CTL_SYNC_Pos (30)
21798#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos)
21800#define SC_ALTCTL_TXRST_Pos (0)
21801#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos)
21803#define SC_ALTCTL_RXRST_Pos (1)
21804#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos)
21806#define SC_ALTCTL_DACTEN_Pos (2)
21807#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos)
21809#define SC_ALTCTL_ACTEN_Pos (3)
21810#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos)
21812#define SC_ALTCTL_WARSTEN_Pos (4)
21813#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos)
21815#define SC_ALTCTL_CNTEN0_Pos (5)
21816#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos)
21818#define SC_ALTCTL_CNTEN1_Pos (6)
21819#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos)
21821#define SC_ALTCTL_CNTEN2_Pos (7)
21822#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos)
21824#define SC_ALTCTL_INITSEL_Pos (8)
21825#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos)
21827#define SC_ALTCTL_ADACEN_Pos (11)
21828#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos)
21830#define SC_ALTCTL_RXBGTEN_Pos (12)
21831#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos)
21833#define SC_ALTCTL_ACTSTS0_Pos (13)
21834#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos)
21836#define SC_ALTCTL_ACTSTS1_Pos (14)
21837#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos)
21839#define SC_ALTCTL_ACTSTS2_Pos (15)
21840#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos)
21842#define SC_EGT_EGT_Pos (0)
21843#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos)
21845#define SC_RXTOUT_RFTM_Pos (0)
21846#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos)
21848#define SC_ETUCTL_ETURDIV_Pos (0)
21849#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos)
21851#define SC_ETUCTL_CMPEN_Pos (15)
21852#define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos)
21854#define SC_INTEN_RDAIEN_Pos (0)
21855#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos)
21857#define SC_INTEN_TBEIEN_Pos (1)
21858#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos)
21860#define SC_INTEN_TERRIEN_Pos (2)
21861#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos)
21863#define SC_INTEN_TMR0IEN_Pos (3)
21864#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos)
21866#define SC_INTEN_TMR1IEN_Pos (4)
21867#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos)
21869#define SC_INTEN_TMR2IEN_Pos (5)
21870#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos)
21872#define SC_INTEN_BGTIEN_Pos (6)
21873#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos)
21875#define SC_INTEN_CDIEN_Pos (7)
21876#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos)
21878#define SC_INTEN_INITIEN_Pos (8)
21879#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos)
21881#define SC_INTEN_RXTOIF_Pos (9)
21882#define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos)
21884#define SC_INTEN_ACERRIEN_Pos (10)
21885#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos)
21887#define SC_INTSTS_RDAIF_Pos (0)
21888#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos)
21890#define SC_INTSTS_TBEIF_Pos (1)
21891#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos)
21893#define SC_INTSTS_TERRIF_Pos (2)
21894#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos)
21896#define SC_INTSTS_TMR0IF_Pos (3)
21897#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos)
21899#define SC_INTSTS_TMR1IF_Pos (4)
21900#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos)
21902#define SC_INTSTS_TMR2IF_Pos (5)
21903#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos)
21905#define SC_INTSTS_BGTIF_Pos (6)
21906#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos)
21908#define SC_INTSTS_CDIF_Pos (7)
21909#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos)
21911#define SC_INTSTS_INITIF_Pos (8)
21912#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos)
21914#define SC_INTSTS_RBTOIF_Pos (9)
21915#define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos)
21917#define SC_INTSTS_ACERRIF_Pos (10)
21918#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos)
21920#define SC_STATUS_RXOV_Pos (0)
21921#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos)
21923#define SC_STATUS_RXEMPTY_Pos (1)
21924#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos)
21926#define SC_STATUS_RXFULL_Pos (2)
21927#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos)
21929#define SC_STATUS_PEF_Pos (4)
21930#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos)
21932#define SC_STATUS_FEF_Pos (5)
21933#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos)
21935#define SC_STATUS_BEF_Pos (6)
21936#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos)
21938#define SC_STATUS_TXOV_Pos (8)
21939#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos)
21941#define SC_STATUS_TXEMPTY_Pos (9)
21942#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos)
21944#define SC_STATUS_TXFULL_Pos (10)
21945#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos)
21947#define SC_STATUS_CREMOVE_Pos (11)
21948#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos)
21950#define SC_STATUS_CINSERT_Pos (12)
21951#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos)
21953#define SC_STATUS_CDPINSTS_Pos (13)
21954#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos)
21956#define SC_STATUS_RXPOINT_Pos (16)
21957#define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos)
21959#define SC_STATUS_RXRERR_Pos (21)
21960#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos)
21962#define SC_STATUS_RXOVERR_Pos (22)
21963#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos)
21965#define SC_STATUS_RXACT_Pos (23)
21966#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos)
21968#define SC_STATUS_TXPOINT_Pos (24)
21969#define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos)
21971#define SC_STATUS_TXRERR_Pos (29)
21972#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos)
21974#define SC_STATUS_TXOVERR_Pos (30)
21975#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos)
21977#define SC_STATUS_TXACT_Pos (31)
21978#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos)
21980#define SC_PINCTL_PWREN_Pos (0)
21981#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos)
21983#define SC_PINCTL_SCRST_Pos (1)
21984#define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos)
21986#define SC_PINCTL_CLKKEEP_Pos (6)
21987#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos)
21989#define SC_PINCTL_SCDOUT_Pos (9)
21990#define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos)
21992#define SC_PINCTL_PWRINV_Pos (11)
21993#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos)
21995#define SC_PINCTL_DATSTS_Pos (16)
21996#define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos)
21998#define SC_PINCTL_PWRSTS_Pos (17)
21999#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos)
22001#define SC_PINCTL_RSTSTS_Pos (18)
22002#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos)
22004#define SC_PINCTL_SYNC_Pos (30)
22005#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos)
22007#define SC_TMRCTL0_CNT_Pos (0)
22008#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos)
22010#define SC_TMRCTL0_OPMODE_Pos (24)
22011#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos)
22013#define SC_TMRCTL1_CNT_Pos (0)
22014#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos)
22016#define SC_TMRCTL1_OPMODE_Pos (24)
22017#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos)
22019#define SC_TMRCTL2_CNT_Pos (0)
22020#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos)
22022#define SC_TMRCTL2_OPMODE_Pos (24)
22023#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos)
22025#define SC_UARTCTL_UARTEN_Pos (0)
22026#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos)
22028#define SC_UARTCTL_WLS_Pos (4)
22029#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos)
22031#define SC_UARTCTL_PBOFF_Pos (6)
22032#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos)
22034#define SC_UARTCTL_OPE_Pos (7)
22035#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos)
22037#define SC_TMRDAT0_TDR0_Pos (0)
22038#define SC_TMRDAT0_TDR0_Msk (0xfffffful << SC_TMRDAT0_TDR0_Pos)
22040#define SC_TMRDAT1_2_TDR1_Pos (0)
22041#define SC_TMRDAT1_2_TDR1_Msk (0xfful << SC_TMRDAT1_2_TDR1_Pos)
22043#define SC_TMRDAT1_2_TDR2_Pos (8)
22044#define SC_TMRDAT1_2_TDR2_Msk (0xfful << SC_TMRDAT1_2_TDR2_Pos) /* SC_CONST */ /* end of SC register group */
22048
22049
22050/*---------------------- SD Card Host Interface -------------------------*/
22056 typedef struct {
22057
22068 uint32_t FB[32];
22070 uint32_t RESERVE0[224];
22072
22073
22101 __IO uint32_t DMACTL;
22103 uint32_t RESERVE1[1];
22105
22106
22122 __IO uint32_t DMASA;
22123
22135 __I uint32_t DMABCNT;
22136
22151 __IO uint32_t DMAINTEN;
22152
22170 __IO uint32_t DMAINTSTS;
22172 uint32_t RESERVE2[250];
22174
22175
22192 __IO uint32_t GCTL;
22193
22205 __IO uint32_t GINTEN;
22206
22221 __I uint32_t GINTSTS;
22223 uint32_t RESERVE3[5];
22225
22226
22291 __IO uint32_t CTL;
22292
22304 __IO uint32_t CMDARG;
22305
22352 __IO uint32_t INTEN;
22353
22437 __IO uint32_t INTSTS;
22438
22450 __I uint32_t RESP0;
22451
22463 __I uint32_t RESP1;
22464
22477 __IO uint32_t BLEN;
22478
22493 __IO uint32_t TOUT;
22494
22495} SDH_T;
22496
22502#define SDH_DMACTL_DMAEN_Pos (0)
22503#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos)
22505#define SDH_DMACTL_DMARST_Pos (1)
22506#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos)
22508#define SDH_DMACTL_SGEN_Pos (3)
22509#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos)
22511#define SDH_DMACTL_DMABUSY_Pos (9)
22512#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos)
22514#define SDH_DMASA_ORDER_Pos (0)
22515#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos)
22517#define SDH_DMASA_DMASA_Pos (1)
22518#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos)
22520#define SDH_DMABCNT_BCNT_Pos (0)
22521#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos)
22523#define SDH_DMAINTEN_ABORTIEN_Pos (0)
22524#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos)
22526#define SDH_DMAINTEN_WEOTIEN_Pos (1)
22527#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos)
22529#define SDH_DMAINTSTS_ABORTIF_Pos (0)
22530#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos)
22532#define SDH_DMAINTSTS_WEOTIF_Pos (1)
22533#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos)
22535#define SDH_GCTL_GCTLRST_Pos (0)
22536#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos)
22538#define SDH_GCTL_SDEN_Pos (1)
22539#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos)
22541#define SDH_GINTEN_DTAIEN_Pos (0)
22542#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos)
22544#define SDH_GINTSTS_DTAIF_Pos (0)
22545#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos)
22547#define SDH_CTL_COEN_Pos (0)
22548#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos)
22550#define SDH_CTL_RIEN_Pos (1)
22551#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos)
22553#define SDH_CTL_DIEN_Pos (2)
22554#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos)
22556#define SDH_CTL_DOEN_Pos (3)
22557#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos)
22559#define SDH_CTL_R2EN_Pos (4)
22560#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos)
22562#define SDH_CTL_CLK74OEN_Pos (5)
22563#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos)
22565#define SDH_CTL_CLK8OEN_Pos (6)
22566#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos)
22568#define SDH_CTL_CLKKEEP0_Pos (7)
22569#define SDH_CTL_CLKKEEP0_Msk (0x1ul << SDH_CTL_CLKKEEP0_Pos)
22571#define SDH_CTL_CMDCODE_Pos (8)
22572#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos)
22574#define SDH_CTL_CTLRST_Pos (14)
22575#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos)
22577#define SDH_CTL_DBW_Pos (15)
22578#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos)
22580#define SDH_CTL_BLKCNT_Pos (16)
22581#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos)
22583#define SDH_CTL_SDNWR_Pos (24)
22584#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos)
22586#define SDH_CTL_SDPORT_Pos (29)
22587#define SDH_CTL_SDPORT_Msk (0x3ul << SDH_CTL_SDPORT_Pos)
22589#define SDH_CTL_CLKKEEP1_Pos (31)
22590#define SDH_CTL_CLKKEEP1_Msk (0x1ul << SDH_CTL_CLKKEEP1_Pos)
22592#define SDH_CMDARG_ARGUMENT_Pos (0)
22593#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos)
22595#define SDH_INTEN_BLKDIEN_Pos (0)
22596#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos)
22598#define SDH_INTEN_CRCIEN_Pos (1)
22599#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos)
22601#define SDH_INTEN_CDIEN0_Pos (8)
22602#define SDH_INTEN_CDIEN0_Msk (0x1ul << SDH_INTEN_CDIEN0_Pos)
22604#define SDH_INTEN_CDIEN1_Pos (9)
22605#define SDH_INTEN_CDIEN1_Msk (0x1ul << SDH_INTEN_CDIEN1_Pos)
22607#define SDH_INTEN_SDHOST0IEN_Pos (10)
22608#define SDH_INTEN_SDHOST0IEN_Msk (0x1ul << SDH_INTEN_SDHOST0IEN_Pos)
22610#define SDH_INTEN_SDHOST1IEN_Pos (11)
22611#define SDH_INTEN_SDHOST1IEN_Msk (0x1ul << SDH_INTEN_SDHOST1IEN_Pos)
22613#define SDH_INTEN_RTOIEN_Pos (12)
22614#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos)
22616#define SDH_INTEN_DITOIEN_Pos (13)
22617#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos)
22619#define SDH_INTEN_WKIEN_Pos (14)
22620#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos)
22622#define SDH_INTEN_CDSRC0_Pos (30)
22623#define SDH_INTEN_CDSRC0_Msk (0x1ul << SDH_INTEN_CDSRC0_Pos)
22625#define SDH_INTEN_CDSRC1_Pos (31)
22626#define SDH_INTEN_CDSRC1_Msk (0x1ul << SDH_INTEN_CDSRC1_Pos)
22628#define SDH_INTSTS_BLKDIF_Pos (0)
22629#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos)
22631#define SDH_INTSTS_CRCIF_Pos (1)
22632#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos)
22634#define SDH_INTSTS_CRC7_Pos (2)
22635#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos)
22637#define SDH_INTSTS_CRC16_Pos (3)
22638#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos)
22640#define SDH_INTSTS_CRCSTS_Pos (4)
22641#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos)
22643#define SDH_INTSTS_DAT0STS_Pos (7)
22644#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos)
22646#define SDH_INTSTS_CDIF0_Pos (8)
22647#define SDH_INTSTS_CDIF0_Msk (0x1ul << SDH_INTSTS_CDIF0_Pos)
22649#define SDH_INTSTS_CDIF1_Pos (9)
22650#define SDH_INTSTS_CDIF1_Msk (0x1ul << SDH_INTSTS_CDIF1_Pos)
22652#define SDH_INTSTS_SDHOST0IF_Pos (10)
22653#define SDH_INTSTS_SDHOST0IF_Msk (0x1ul << SDH_INTSTS_SDHOST0IF_Pos)
22655#define SDH_INTSTS_SDHOST1IF_Pos (11)
22656#define SDH_INTSTS_SDHOST1IF_Msk (0x1ul << SDH_INTSTS_SDHOST1IF_Pos)
22658#define SDH_INTSTS_RTOIF_Pos (12)
22659#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos)
22661#define SDH_INTSTS_DINTOIF_Pos (13)
22662#define SDH_INTSTS_DINTOIF_Msk (0x1ul << SDH_INTSTS_DINTOIF_Pos)
22664#define SDH_INTSTS_CDSTS0_Pos (16)
22665#define SDH_INTSTS_CDSTS0_Msk (0x1ul << SDH_INTSTS_CDSTS0_Pos)
22667#define SDH_INTSTS_CDSTS1_Pos (17)
22668#define SDH_INTSTS_CDSTS1_Msk (0x1ul << SDH_INTSTS_CDSTS1_Pos)
22670#define SDH_INTSTS_DAT1STS_Pos (18)
22671#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos)
22673#define SDH_RESP0_RESPTK0_Pos (0)
22674#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos)
22676#define SDH_RESP1_RESPTK1_Pos (0)
22677#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos)
22679#define SDH_BLEN_BLKLEN_Pos (0)
22680#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos)
22682#define SDH_TOUT_TOUT_Pos (0)
22683#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /* SDH_CONST */ /* end of SDH register group */
22687
22688
22689/*---------------------- Serial Peripheral Interface Controller -------------------------*/
22695 typedef struct {
22696
22697
22774 __IO uint32_t CTL;
22775
22789 __IO uint32_t CLKDIV;
22790
22848 __IO uint32_t SSCTL;
22849
22873 __IO uint32_t PDMACTL;
22874
22919 __IO uint32_t FIFOCTL;
22920
23019 __IO uint32_t STATUS;
23021 uint32_t RESERVE0[2];
23023
23024
23039 __O uint32_t TX;
23041 uint32_t RESERVE1[3];
23043
23044
23058 __I uint32_t RX;
23059
23060} SPI_T;
23061
23067#define SPI_CTL_SPIEN_Pos (0)
23068#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos)
23070#define SPI_CTL_RXNEG_Pos (1)
23071#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos)
23073#define SPI_CTL_TXNEG_Pos (2)
23074#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos)
23076#define SPI_CTL_CLKPOL_Pos (3)
23077#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos)
23079#define SPI_CTL_SUSPITV_Pos (4)
23080#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos)
23082#define SPI_CTL_DWIDTH_Pos (8)
23083#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos)
23085#define SPI_CTL_LSB_Pos (13)
23086#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
23088#define SPI_CTL_TWOBIT_Pos (16)
23089#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos)
23091#define SPI_CTL_UNITIEN_Pos (17)
23092#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos)
23094#define SPI_CTL_SLAVE_Pos (18)
23095#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
23097#define SPI_CTL_REORDER_Pos (19)
23098#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
23100#define SPI_CTL_QDIODIR_Pos (20)
23101#define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos)
23103#define SPI_CTL_DUALIOEN_Pos (21)
23104#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos)
23106#define SPI_CTL_QUADIOEN_Pos (22)
23107#define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos)
23109#define SPI_CLKDIV_DIVIDER_Pos (0)
23110#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos)
23112#define SPI_SSCTL_SS_Pos (0)
23113#define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos)
23115#define SPI_SSCTL_SSACTPOL_Pos (2)
23116#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos)
23118#define SPI_SSCTL_AUTOSS_Pos (3)
23119#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos)
23121#define SPI_SSCTL_SLV3WIRE_Pos (4)
23122#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)
23124#define SPI_SSCTL_SLVTOIEN_Pos (5)
23125#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos)
23127#define SPI_SSCTL_SLVTORST_Pos (6)
23128#define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos)
23130#define SPI_SSCTL_SLVBEIEN_Pos (8)
23131#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos)
23133#define SPI_SSCTL_SLVURIEN_Pos (9)
23134#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos)
23136#define SPI_SSCTL_SSACTIEN_Pos (12)
23137#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos)
23139#define SPI_SSCTL_SSINAIEN_Pos (13)
23140#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos)
23142#define SPI_SSCTL_SLVTOCNT_Pos (16)
23143#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos)
23145#define SPI_PDMACTL_TXPDMAEN_Pos (0)
23146#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)
23148#define SPI_PDMACTL_RXPDMAEN_Pos (1)
23149#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)
23151#define SPI_PDMACTL_PDMARST_Pos (2)
23152#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos)
23154#define SPI_FIFOCTL_RXRST_Pos (0)
23155#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos)
23157#define SPI_FIFOCTL_TXRST_Pos (1)
23158#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos)
23160#define SPI_FIFOCTL_RXTHIEN_Pos (2)
23161#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)
23163#define SPI_FIFOCTL_TXTHIEN_Pos (3)
23164#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)
23166#define SPI_FIFOCTL_RXTOIEN_Pos (4)
23167#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)
23169#define SPI_FIFOCTL_RXOVIEN_Pos (5)
23170#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)
23172#define SPI_FIFOCTL_TXUFPOL_Pos (6)
23173#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos)
23175#define SPI_FIFOCTL_TXUFIEN_Pos (7)
23176#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos)
23178#define SPI_FIFOCTL_RXTH_Pos (24)
23179#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos)
23181#define SPI_FIFOCTL_TXTH_Pos (28)
23182#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos)
23184#define SPI_STATUS_BUSY_Pos (0)
23185#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos)
23187#define SPI_STATUS_UNITIF_Pos (1)
23188#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos)
23190#define SPI_STATUS_SSACTIF_Pos (2)
23191#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos)
23193#define SPI_STATUS_SSINAIF_Pos (3)
23194#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos)
23196#define SPI_STATUS_SSLINE_Pos (4)
23197#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos)
23199#define SPI_STATUS_SLVTOIF_Pos (5)
23200#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos)
23202#define SPI_STATUS_SLVBEIF_Pos (6)
23203#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos)
23205#define SPI_STATUS_SLVUDRIF_Pos (7)
23206#define SPI_STATUS_SLVUDRIF_Msk (0x1ul << SPI_STATUS_SLVUDRIF_Pos)
23208#define SPI_STATUS_RXEMPTY_Pos (8)
23209#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos)
23211#define SPI_STATUS_RXFULL_Pos (9)
23212#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos)
23214#define SPI_STATUS_RXTHIF_Pos (10)
23215#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos)
23217#define SPI_STATUS_RXOVIF_Pos (11)
23218#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos)
23220#define SPI_STATUS_RXTOIF_Pos (12)
23221#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos)
23223#define SPI_STATUS_SPIENSTS_Pos (15)
23224#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos)
23226#define SPI_STATUS_TXEMPTY_Pos (16)
23227#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos)
23229#define SPI_STATUS_TXFULL_Pos (17)
23230#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos)
23232#define SPI_STATUS_TXTHIF_Pos (18)
23233#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos)
23235#define SPI_STATUS_TXUFIF_Pos (19)
23236#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos)
23238#define SPI_STATUS_TXRXRST_Pos (23)
23239#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos)
23241#define SPI_STATUS_RXCNT_Pos (24)
23242#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos)
23244#define SPI_STATUS_TXCNT_Pos (28)
23245#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos)
23247#define SPI_TX_TX_Pos (0)
23248#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos)
23250#define SPI_RX_RX_Pos (0)
23251#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /* SPI_CONST */ /* end of SPI register group */
23255
23256
23257/*---------------------- System Manger Controller -------------------------*/
23263 typedef struct {
23264
23265
23277 __I uint32_t PDID;
23278
23315 __IO uint32_t RSTSTS;
23316
23394 __IO uint32_t IPRST0;
23395
23479 __IO uint32_t IPRST1;
23480
23522 __IO uint32_t IPRST2;
23524 uint32_t RESERVE0[1];
23526
23527
23584 __IO uint32_t BODCTL;
23585
23600 __IO uint32_t TEMPCTL;
23601
23615 __I uint32_t VCID;
23616
23632 __IO uint32_t PORCTL;
23633
23655 __IO uint32_t VREFCTL;
23656
23674 __IO uint32_t USBPHY;
23675
23692 __IO uint32_t GPA_MFPL;
23693
23710 __IO uint32_t GPA_MFPH;
23711
23728 __IO uint32_t GPB_MFPL;
23729
23746 __IO uint32_t GPB_MFPH;
23747
23764 __IO uint32_t GPC_MFPL;
23765
23782 __IO uint32_t GPC_MFPH;
23783
23800 __IO uint32_t GPD_MFPL;
23801
23818 __IO uint32_t GPD_MFPH;
23819
23836 __IO uint32_t GPE_MFPL;
23837
23854 __IO uint32_t GPE_MFPH;
23855
23872 __IO uint32_t GPF_MFPL;
23873
23890 __IO uint32_t GPF_MFPH;
23891
23908 __IO uint32_t GPG_MFPL;
23909
23926 __IO uint32_t GPG_MFPH;
23927
23944 __IO uint32_t GPH_MFPL;
23945
23962 __IO uint32_t GPH_MFPH;
23963
23980 __IO uint32_t GPI_MFPL;
23981
23998 __IO uint32_t GPI_MFPH;
24000 uint32_t RESERVE1[18];
24002
24003
24015 __IO uint32_t SRAM_INTCTL;
24016
24031 __IO uint32_t SRAM_STATUS;
24032
24042 __I uint32_t SRAM0_ERRADDR;
24043
24054 __I uint32_t SRAM1_ERRADDR;
24056 uint32_t RESERVE2[8];
24058
24059
24094 __IO uint32_t IRCTCTL;
24095
24114 __IO uint32_t IRCTIEN;
24115
24141 __IO uint32_t IRCTISTS;
24143 uint32_t RESERVE3[1];
24145
24146
24177 __IO uint32_t REGLCTL;
24178
24179} SYS_T;
24180
24186#define SYS_PDID_SYS_PDID_Pos (0)
24187#define SYS_PDID_SYS_PDID_Msk (0xfffffffful << SYS_PDID_SYS_PDID_Pos)
24189#define SYS_RSTSTS_PORF_Pos (0)
24190#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos)
24192#define SYS_RSTSTS_PINRF_Pos (1)
24193#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos)
24195#define SYS_RSTSTS_WDTRF_Pos (2)
24196#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos)
24198#define SYS_RSTSTS_LVRF_Pos (3)
24199#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos)
24201#define SYS_RSTSTS_BODRF_Pos (4)
24202#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos)
24204#define SYS_RSTSTS_SYSRF_Pos (5)
24205#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos)
24207#define SYS_RSTSTS_CPURF_Pos (7)
24208#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos)
24210#define SYS_IPRST0_CHIPRST_Pos (0)
24211#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos)
24213#define SYS_IPRST0_CPURST_Pos (1)
24214#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos)
24216#define SYS_IPRST0_PDMARST_Pos (2)
24217#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos)
24219#define SYS_IPRST0_EBIRST_Pos (3)
24220#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos)
24222#define SYS_IPRST0_USBHRST_Pos (4)
24223#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos)
24225#define SYS_IPRST0_EMACRST_Pos (5)
24226#define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos)
24228#define SYS_IPRST0_SDHRST_Pos (6)
24229#define SYS_IPRST0_SDHRST_Msk (0x1ul << SYS_IPRST0_SDHRST_Pos)
24231#define SYS_IPRST0_CRCRST_Pos (7)
24232#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos)
24234#define SYS_IPRST0_CAPRST_Pos (8)
24235#define SYS_IPRST0_CAPRST_Msk (0x1ul << SYS_IPRST0_CAPRST_Pos)
24237#define SYS_IPRST0_CRPTRST_Pos (12)
24238#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos)
24240#define SYS_IPRST1_GPIORST_Pos (1)
24241#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos)
24243#define SYS_IPRST1_TMR0RST_Pos (2)
24244#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos)
24246#define SYS_IPRST1_TMR1RST_Pos (3)
24247#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos)
24249#define SYS_IPRST1_TMR2RST_Pos (4)
24250#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos)
24252#define SYS_IPRST1_TMR3RST_Pos (5)
24253#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos)
24255#define SYS_IPRST1_ACMPRST_Pos (7)
24256#define SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos)
24258#define SYS_IPRST1_I2C0RST_Pos (8)
24259#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos)
24261#define SYS_IPRST1_I2C1RST_Pos (9)
24262#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos)
24264#define SYS_IPRST1_I2C2RST_Pos (10)
24265#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos)
24267#define SYS_IPRST1_I2C3RST_Pos (11)
24268#define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos)
24270#define SYS_IPRST1_SPI0RST_Pos (12)
24271#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos)
24273#define SYS_IPRST1_SPI1RST_Pos (13)
24274#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos)
24276#define SYS_IPRST1_SPI2RST_Pos (14)
24277#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos)
24279#define SYS_IPRST1_SPI3RST_Pos (15)
24280#define SYS_IPRST1_SPI3RST_Msk (0x1ul << SYS_IPRST1_SPI3RST_Pos)
24282#define SYS_IPRST1_UART0RST_Pos (16)
24283#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos)
24285#define SYS_IPRST1_UART1RST_Pos (17)
24286#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos)
24288#define SYS_IPRST1_UART2RST_Pos (18)
24289#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos)
24291#define SYS_IPRST1_UART3RST_Pos (19)
24292#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos)
24294#define SYS_IPRST1_UART4RST_Pos (20)
24295#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos)
24297#define SYS_IPRST1_UART5RST_Pos (21)
24298#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos)
24300#define SYS_IPRST1_CAN0RST_Pos (24)
24301#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos)
24303#define SYS_IPRST1_CAN1RST_Pos (25)
24304#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos)
24306#define SYS_IPRST1_USBDRST_Pos (27)
24307#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos)
24309#define SYS_IPRST1_ADCRST_Pos (28)
24310#define SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos)
24312#define SYS_IPRST1_I2S0RST_Pos (29)
24313#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos)
24315#define SYS_IPRST1_I2S1RST_Pos (30)
24316#define SYS_IPRST1_I2S1RST_Msk (0x1ul << SYS_IPRST1_I2S1RST_Pos)
24318#define SYS_IPRST1_PS2RST_Pos (31)
24319#define SYS_IPRST1_PS2RST_Msk (0x1ul << SYS_IPRST1_PS2RST_Pos)
24321#define SYS_IPRST2_SC0RST_Pos (0)
24322#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos)
24324#define SYS_IPRST2_SC1RST_Pos (1)
24325#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos)
24327#define SYS_IPRST2_SC2RST_Pos (2)
24328#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos)
24330#define SYS_IPRST2_SC3RST_Pos (3)
24331#define SYS_IPRST2_SC3RST_Msk (0x1ul << SYS_IPRST2_SC3RST_Pos)
24333#define SYS_IPRST2_SC4RST_Pos (4)
24334#define SYS_IPRST2_SC4RST_Msk (0x1ul << SYS_IPRST2_SC4RST_Pos)
24336#define SYS_IPRST2_SC5RST_Pos (5)
24337#define SYS_IPRST2_SC5RST_Msk (0x1ul << SYS_IPRST2_SC5RST_Pos)
24339#define SYS_IPRST2_I2C4RST_Pos (8)
24340#define SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos)
24342#define SYS_IPRST2_PWM0RST_Pos (16)
24343#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos)
24345#define SYS_IPRST2_PWM1RST_Pos (17)
24346#define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos)
24348#define SYS_IPRST2_QEI0RST_Pos (22)
24349#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos)
24351#define SYS_IPRST2_QEI1RST_Pos (23)
24352#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos)
24354#define SYS_BODCTL_BODEN_Pos (0)
24355#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos)
24357#define SYS_BODCTL_BODVL_Pos (1)
24358#define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos)
24360#define SYS_BODCTL_BODRSTEN_Pos (3)
24361#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos)
24363#define SYS_BODCTL_BODINTF_Pos (4)
24364#define SYS_BODCTL_BODINTF_Msk (0x1ul << SYS_BODCTL_BODINTF_Pos)
24366#define SYS_BODCTL_BODLPM_Pos (5)
24367#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos)
24369#define SYS_BODCTL_BODOUT_Pos (6)
24370#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos)
24372#define SYS_BODCTL_LVREN_Pos (7)
24373#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos)
24375#define SYS_TEMPCTL_VTEMPEN_Pos (0)
24376#define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos)
24378#define SYS_VCID_VCID_Pos (0)
24379#define SYS_VCID_VCID_Msk (0xfffful << SYS_VCID_VCID_Pos)
24381#define SYS_PORCTL_POROFF_Pos (0)
24382#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos)
24384#define SYS_VREFCTL_VREFCTL_Pos (0)
24385#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos)
24387#define SYS_VREFCTL_ADCMODESEL_Pos (8)
24388#define SYS_VREFCTL_ADCMODESEL_Msk (0x1ul << SYS_VREFCTL_ADCMODESEL_Pos)
24390#define SYS_VREFCTL_PWMSYNCMODE_Pos (9)
24391#define SYS_VREFCTL_PWMSYNCMODE_Msk (0x1ul << SYS_VREFCTL_PWMSYNCMODE_Pos)
24393#define SYS_USBPHY_USBROLE_Pos (0)
24394#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos)
24396#define SYS_USBPHY_LDO33EN_Pos (8)
24397#define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos)
24399#define SYS_GPA_MFPL_PA0MFP_Pos (0)
24400#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos)
24402#define SYS_GPA_MFPL_PA1MFP_Pos (4)
24403#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos)
24405#define SYS_GPA_MFPL_PA2MFP_Pos (8)
24406#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos)
24408#define SYS_GPA_MFPL_PA3MFP_Pos (12)
24409#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos)
24411#define SYS_GPA_MFPL_PA4MFP_Pos (16)
24412#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos)
24414#define SYS_GPA_MFPL_PA5MFP_Pos (20)
24415#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos)
24417#define SYS_GPA_MFPL_PA6MFP_Pos (24)
24418#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos)
24420#define SYS_GPA_MFPL_PA7MFP_Pos (28)
24421#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos)
24423#define SYS_GPA_MFPH_PA8MFP_Pos (0)
24424#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos)
24426#define SYS_GPA_MFPH_PA9MFP_Pos (4)
24427#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos)
24429#define SYS_GPA_MFPH_PA10MFP_Pos (8)
24430#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos)
24432#define SYS_GPA_MFPH_PA11MFP_Pos (12)
24433#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos)
24435#define SYS_GPA_MFPH_PA12MFP_Pos (16)
24436#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos)
24438#define SYS_GPA_MFPH_PA13MFP_Pos (20)
24439#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos)
24441#define SYS_GPA_MFPH_PA14MFP_Pos (24)
24442#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos)
24444#define SYS_GPA_MFPH_PA15MFP_Pos (28)
24445#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos)
24447#define SYS_GPB_MFPL_PB0MFP_Pos (0)
24448#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos)
24450#define SYS_GPB_MFPL_PB1MFP_Pos (4)
24451#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos)
24453#define SYS_GPB_MFPL_PB2MFP_Pos (8)
24454#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos)
24456#define SYS_GPB_MFPL_PB3MFP_Pos (12)
24457#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos)
24459#define SYS_GPB_MFPL_PB4MFP_Pos (16)
24460#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos)
24462#define SYS_GPB_MFPL_PB5MFP_Pos (20)
24463#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos)
24465#define SYS_GPB_MFPL_PB6MFP_Pos (24)
24466#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos)
24468#define SYS_GPB_MFPL_PB7MFP_Pos (28)
24469#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos)
24471#define SYS_GPB_MFPH_PB8MFP_Pos (0)
24472#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos)
24474#define SYS_GPB_MFPH_PB9MFP_Pos (4)
24475#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos)
24477#define SYS_GPB_MFPH_PB10MFP_Pos (8)
24478#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos)
24480#define SYS_GPB_MFPH_PB11MFP_Pos (12)
24481#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos)
24483#define SYS_GPB_MFPH_PB12MFP_Pos (16)
24484#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos)
24486#define SYS_GPB_MFPH_PB13MFP_Pos (20)
24487#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos)
24489#define SYS_GPB_MFPH_PB14MFP_Pos (24)
24490#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos)
24492#define SYS_GPB_MFPH_PB15MFP_Pos (28)
24493#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos)
24495#define SYS_GPC_MFPL_PC0MFP_Pos (0)
24496#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos)
24498#define SYS_GPC_MFPL_PC1MFP_Pos (4)
24499#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos)
24501#define SYS_GPC_MFPL_PC2MFP_Pos (8)
24502#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos)
24504#define SYS_GPC_MFPL_PC3MFP_Pos (12)
24505#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos)
24507#define SYS_GPC_MFPL_PC4MFP_Pos (16)
24508#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos)
24510#define SYS_GPC_MFPL_PC5MFP_Pos (20)
24511#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos)
24513#define SYS_GPC_MFPL_PC6MFP_Pos (24)
24514#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos)
24516#define SYS_GPC_MFPL_PC7MFP_Pos (28)
24517#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos)
24519#define SYS_GPC_MFPH_PC8MFP_Pos (0)
24520#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos)
24522#define SYS_GPC_MFPH_PC9MFP_Pos (4)
24523#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos)
24525#define SYS_GPC_MFPH_PC10MFP_Pos (8)
24526#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos)
24528#define SYS_GPC_MFPH_PC11MFP_Pos (12)
24529#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos)
24531#define SYS_GPC_MFPH_PC12MFP_Pos (16)
24532#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos)
24534#define SYS_GPC_MFPH_PC13MFP_Pos (20)
24535#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos)
24537#define SYS_GPC_MFPH_PC14MFP_Pos (24)
24538#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos)
24540#define SYS_GPC_MFPH_PC15MFP_Pos (28)
24541#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos)
24543#define SYS_GPD_MFPL_PD0MFP_Pos (0)
24544#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos)
24546#define SYS_GPD_MFPL_PD1MFP_Pos (4)
24547#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos)
24549#define SYS_GPD_MFPL_PD2MFP_Pos (8)
24550#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos)
24552#define SYS_GPD_MFPL_PD3MFP_Pos (12)
24553#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos)
24555#define SYS_GPD_MFPL_PD4MFP_Pos (16)
24556#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos)
24558#define SYS_GPD_MFPL_PD5MFP_Pos (20)
24559#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos)
24561#define SYS_GPD_MFPL_PD6MFP_Pos (24)
24562#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos)
24564#define SYS_GPD_MFPL_PD7MFP_Pos (28)
24565#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos)
24567#define SYS_GPD_MFPH_PD8MFP_Pos (0)
24568#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos)
24570#define SYS_GPD_MFPH_PD9MFP_Pos (4)
24571#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos)
24573#define SYS_GPD_MFPH_PD10MFP_Pos (8)
24574#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos)
24576#define SYS_GPD_MFPH_PD11MFP_Pos (12)
24577#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos)
24579#define SYS_GPD_MFPH_PD12MFP_Pos (16)
24580#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos)
24582#define SYS_GPD_MFPH_PD13MFP_Pos (20)
24583#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos)
24585#define SYS_GPD_MFPH_PD14MFP_Pos (24)
24586#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos)
24588#define SYS_GPD_MFPH_PD15MFP_Pos (28)
24589#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos)
24591#define SYS_GPE_MFPL_PE0MFP_Pos (0)
24592#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos)
24594#define SYS_GPE_MFPL_PE1MFP_Pos (4)
24595#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos)
24597#define SYS_GPE_MFPL_PE2MFP_Pos (8)
24598#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos)
24600#define SYS_GPE_MFPL_PE3MFP_Pos (12)
24601#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos)
24603#define SYS_GPE_MFPL_PE4MFP_Pos (16)
24604#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos)
24606#define SYS_GPE_MFPL_PE5MFP_Pos (20)
24607#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos)
24609#define SYS_GPE_MFPL_PE6MFP_Pos (24)
24610#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos)
24612#define SYS_GPE_MFPL_PE7MFP_Pos (28)
24613#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos)
24615#define SYS_GPE_MFPH_PE8MFP_Pos (0)
24616#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos)
24618#define SYS_GPE_MFPH_PE9MFP_Pos (4)
24619#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos)
24621#define SYS_GPE_MFPH_PE10MFP_Pos (8)
24622#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos)
24624#define SYS_GPE_MFPH_PE11MFP_Pos (12)
24625#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos)
24627#define SYS_GPE_MFPH_PE12MFP_Pos (16)
24628#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos)
24630#define SYS_GPE_MFPH_PE13MFP_Pos (20)
24631#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos)
24633#define SYS_GPE_MFPH_PE14MFP_Pos (24)
24634#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos)
24636#define SYS_GPE_MFPH_PE15MFP_Pos (28)
24637#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos)
24639#define SYS_GPF_MFPL_PF0MFP_Pos (0)
24640#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos)
24642#define SYS_GPF_MFPL_PF1MFP_Pos (4)
24643#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos)
24645#define SYS_GPF_MFPL_PF2MFP_Pos (8)
24646#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos)
24648#define SYS_GPF_MFPL_PF3MFP_Pos (12)
24649#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos)
24651#define SYS_GPF_MFPL_PF4MFP_Pos (16)
24652#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos)
24654#define SYS_GPF_MFPL_PF5MFP_Pos (20)
24655#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos)
24657#define SYS_GPF_MFPL_PF6MFP_Pos (24)
24658#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos)
24660#define SYS_GPF_MFPL_PF7MFP_Pos (28)
24661#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos)
24663#define SYS_GPF_MFPH_PF8MFP_Pos (0)
24664#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos)
24666#define SYS_GPF_MFPH_PF9MFP_Pos (4)
24667#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos)
24669#define SYS_GPF_MFPH_PF10MFP_Pos (8)
24670#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos)
24672#define SYS_GPF_MFPH_PF11MFP_Pos (12)
24673#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos)
24675#define SYS_GPF_MFPH_PF12MFP_Pos (16)
24676#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos)
24678#define SYS_GPF_MFPH_PF13MFP_Pos (20)
24679#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos)
24681#define SYS_GPF_MFPH_PF14MFP_Pos (24)
24682#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos)
24684#define SYS_GPF_MFPH_PF15MFP_Pos (28)
24685#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos)
24687#define SYS_GPG_MFPL_PG0MFP_Pos (0)
24688#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos)
24690#define SYS_GPG_MFPL_PG1MFP_Pos (4)
24691#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos)
24693#define SYS_GPG_MFPL_PG2MFP_Pos (8)
24694#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos)
24696#define SYS_GPG_MFPL_PG3MFP_Pos (12)
24697#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos)
24699#define SYS_GPG_MFPL_PG4MFP_Pos (16)
24700#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos)
24702#define SYS_GPG_MFPL_PG5MFP_Pos (20)
24703#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos)
24705#define SYS_GPG_MFPL_PG6MFP_Pos (24)
24706#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos)
24708#define SYS_GPG_MFPL_PG7MFP_Pos (28)
24709#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos)
24711#define SYS_GPG_MFPH_PG8MFP_Pos (0)
24712#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos)
24714#define SYS_GPG_MFPH_PG9MFP_Pos (4)
24715#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos)
24717#define SYS_GPG_MFPH_PG10MFP_Pos (8)
24718#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos)
24720#define SYS_GPG_MFPH_PG11MFP_Pos (12)
24721#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos)
24723#define SYS_GPG_MFPH_PG12MFP_Pos (16)
24724#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos)
24726#define SYS_GPG_MFPH_PG13MFP_Pos (20)
24727#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos)
24729#define SYS_GPG_MFPH_PG14MFP_Pos (24)
24730#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos)
24732#define SYS_GPG_MFPH_PG15MFP_Pos (28)
24733#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos)
24735#define SYS_GPH_MFPL_PH0MFP_Pos (0)
24736#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos)
24738#define SYS_GPH_MFPL_PH1MFP_Pos (4)
24739#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos)
24741#define SYS_GPH_MFPL_PH2MFP_Pos (8)
24742#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos)
24744#define SYS_GPH_MFPL_PH3MFP_Pos (12)
24745#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos)
24747#define SYS_GPH_MFPL_PH4MFP_Pos (16)
24748#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos)
24750#define SYS_GPH_MFPL_PH5MFP_Pos (20)
24751#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos)
24753#define SYS_GPH_MFPL_PH6MFP_Pos (24)
24754#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos)
24756#define SYS_GPH_MFPL_PH7MFP_Pos (28)
24757#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos)
24759#define SYS_GPH_MFPH_PH8MFP_Pos (0)
24760#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos)
24762#define SYS_GPH_MFPH_PH9MFP_Pos (4)
24763#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos)
24765#define SYS_GPH_MFPH_PH10MFP_Pos (8)
24766#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos)
24768#define SYS_GPH_MFPH_PH11MFP_Pos (12)
24769#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos)
24771#define SYS_GPH_MFPH_PH12MFP_Pos (16)
24772#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos)
24774#define SYS_GPH_MFPH_PH13MFP_Pos (20)
24775#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos)
24777#define SYS_GPH_MFPH_PH14MFP_Pos (24)
24778#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos)
24780#define SYS_GPH_MFPH_PH15MFP_Pos (28)
24781#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos)
24783#define SYS_GPI_MFPL_PI0MFP_Pos (0)
24784#define SYS_GPI_MFPL_PI0MFP_Msk (0xful << SYS_GPI_MFPL_PI0MFP_Pos)
24786#define SYS_GPI_MFPL_PI1MFP_Pos (4)
24787#define SYS_GPI_MFPL_PI1MFP_Msk (0xful << SYS_GPI_MFPL_PI1MFP_Pos)
24789#define SYS_GPI_MFPL_PI2MFP_Pos (8)
24790#define SYS_GPI_MFPL_PI2MFP_Msk (0xful << SYS_GPI_MFPL_PI2MFP_Pos)
24792#define SYS_GPI_MFPL_PI3MFP_Pos (12)
24793#define SYS_GPI_MFPL_PI3MFP_Msk (0xful << SYS_GPI_MFPL_PI3MFP_Pos)
24795#define SYS_GPI_MFPL_PI4MFP_Pos (16)
24796#define SYS_GPI_MFPL_PI4MFP_Msk (0xful << SYS_GPI_MFPL_PI4MFP_Pos)
24798#define SYS_GPI_MFPL_PI5MFP_Pos (20)
24799#define SYS_GPI_MFPL_PI5MFP_Msk (0xful << SYS_GPI_MFPL_PI5MFP_Pos)
24801#define SYS_GPI_MFPL_PI6MFP_Pos (24)
24802#define SYS_GPI_MFPL_PI6MFP_Msk (0xful << SYS_GPI_MFPL_PI6MFP_Pos)
24804#define SYS_GPI_MFPL_PI7MFP_Pos (28)
24805#define SYS_GPI_MFPL_PI7MFP_Msk (0xful << SYS_GPI_MFPL_PI7MFP_Pos)
24807#define SYS_GPI_MFPH_PI8MFP_Pos (0)
24808#define SYS_GPI_MFPH_PI8MFP_Msk (0xful << SYS_GPI_MFPH_PI8MFP_Pos)
24810#define SYS_GPI_MFPH_PI9MFP_Pos (4)
24811#define SYS_GPI_MFPH_PI9MFP_Msk (0xful << SYS_GPI_MFPH_PI9MFP_Pos)
24813#define SYS_GPI_MFPH_PI10MFP_Pos (8)
24814#define SYS_GPI_MFPH_PI10MFP_Msk (0xful << SYS_GPI_MFPH_PI10MFP_Pos)
24816#define SYS_GPI_MFPH_PI11MFP_Pos (12)
24817#define SYS_GPI_MFPH_PI11MFP_Msk (0xful << SYS_GPI_MFPH_PI11MFP_Pos)
24819#define SYS_GPI_MFPH_PI12MFP_Pos (16)
24820#define SYS_GPI_MFPH_PI12MFP_Msk (0xful << SYS_GPI_MFPH_PI12MFP_Pos)
24822#define SYS_GPI_MFPH_PI13MFP_Pos (20)
24823#define SYS_GPI_MFPH_PI13MFP_Msk (0xful << SYS_GPI_MFPH_PI13MFP_Pos)
24825#define SYS_GPI_MFPH_PI14MFP_Pos (24)
24826#define SYS_GPI_MFPH_PI14MFP_Msk (0xful << SYS_GPI_MFPH_PI14MFP_Pos)
24828#define SYS_GPI_MFPH_PI15MFP_Pos (28)
24829#define SYS_GPI_MFPH_PI15MFP_Msk (0xful << SYS_GPI_MFPH_PI15MFP_Pos)
24831#define SYS_SRAM_INTCTL_PERRIEN_Pos (0)
24832#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos)
24834#define SYS_SRAM_STATUS_PERRIF0_Pos (0)
24835#define SYS_SRAM_STATUS_PERRIF0_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF0_Pos)
24837#define SYS_SRAM_STATUS_PERRIF1_Pos (1)
24838#define SYS_SRAM_STATUS_PERRIF1_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF1_Pos)
24840#define SYS_SRAM0_ERRADDR_PERRADDR_Pos (0)
24841#define SYS_SRAM0_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM0_ERRADDR_PERRADDR_Pos)
24843#define SYS_SRAM1_ERRADDR_PERRADDR_Pos (0)
24844#define SYS_SRAM1_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM1_ERRADDR_PERRADDR_Pos)
24846#define SYS_IRCTCTL_FREQSEL_Pos (0)
24847#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos)
24849#define SYS_IRCTCTL_CALCLOOP_Pos (4)
24850#define SYS_IRCTCTL_CALCLOOP_Msk (0x3ul << SYS_IRCTCTL_CALCLOOP_Pos)
24852#define SYS_IRCTCTL_RETRYCNT_Pos (6)
24853#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos)
24855#define SYS_IRCTCTL_CESTOPEN_Pos (8)
24856#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos)
24858#define SYS_IRCTIEN_TFAILIEN_Pos (1)
24859#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos)
24861#define SYS_IRCTIEN_CLKEIEN_Pos (2)
24862#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos)
24864#define SYS_IRCTISTS_FREQLOCK_Pos (0)
24865#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos)
24867#define SYS_IRCTISTS_TFAILIF_Pos (1)
24868#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos)
24870#define SYS_IRCTISTS_CLKERRIF_Pos (2)
24871#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos)
24873#define SYS_REGLCTL_REGLCTL_Pos (0)
24874#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos)
24876#define SYS_REGLCTL_SYS_REGLCTL_Pos (0)
24877#define SYS_REGLCTL_SYS_REGLCTL_Msk (0xfful << SYS_REGLCTL_SYS_REGLCTL_Pos) /* SYS_CONST */ /* end of SYS register group */
24881
24882
24883/*---------------------- Timer Controller -------------------------*/
24889 typedef struct {
24890
24891
24954 __IO uint32_t CTL;
24955
24971 __IO uint32_t CMP;
24972
24991 __IO uint32_t INTSTS;
24992
25006 __I uint32_t CNT;
25007
25018 __I uint32_t CAP;
25019
25059 __IO uint32_t EXTCTL;
25060
25075 __IO uint32_t EINTSTS;
25076
25077} TIMER_T;
25078
25084#define TIMER_CTL_PSC_Pos (0)
25085#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos)
25087#define TIMER_CTL_CNTDATEN_Pos (16)
25088#define TIMER_CTL_CNTDATEN_Msk (0x1ul << TIMER_CTL_CNTDATEN_Pos)
25090#define TIMER_CTL_TOGDIS1_Pos (21)
25091#define TIMER_CTL_TOGDIS1_Msk (0x1ul << TIMER_CTL_TOGDIS1_Pos)
25093#define TIMER_CTL_TOGDIS2_Pos (22)
25094#define TIMER_CTL_TOGDIS2_Msk (0x1ul << TIMER_CTL_TOGDIS2_Pos)
25096#define TIMER_CTL_WKEN_Pos (23)
25097#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
25099#define TIMER_CTL_EXTCNTEN_Pos (24)
25100#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
25102#define TIMER_CTL_ACTSTS_Pos (25)
25103#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
25105#define TIMER_CTL_RSTCNT_Pos (26)
25106#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
25108#define TIMER_CTL_OPMODE_Pos (27)
25109#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
25111#define TIMER_CTL_INTEN_Pos (29)
25112#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos)
25114#define TIMER_CTL_CNTEN_Pos (30)
25115#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
25117#define TIMER_CTL_ICEDEBUG_Pos (31)
25118#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
25120#define TIMER_CMP_CMPDAT_Pos (0)
25121#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos)
25123#define TIMER_INTSTS_TIF_Pos (0)
25124#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos)
25126#define TIMER_INTSTS_TWKF_Pos (1)
25127#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos)
25129#define TIMER_CNT_TIMER_CNT_Pos (0)
25130#define TIMER_CNT_TIMER_CNT_Msk (0xfffffful << TIMER_CNT_TIMER_CNT_Pos)
25132#define TIMER_CAP_CAPDAT_Pos (0)
25133#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos)
25135#define TIMER_EXTCTL_CNTPHASE_Pos (0)
25136#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)
25138#define TIMER_EXTCTL_CAPEDGE_Pos (1)
25139#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)
25141#define TIMER_EXTCTL_CAPEN_Pos (3)
25142#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos)
25144#define TIMER_EXTCTL_CAPFUNCS_Pos (4)
25145#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)
25147#define TIMER_EXTCTL_CAPIEN_Pos (5)
25148#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)
25150#define TIMER_EXTCTL_CAPDBEN_Pos (6)
25151#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)
25153#define TIMER_EXTCTL_ECNTDBEN_Pos (7)
25154#define TIMER_EXTCTL_ECNTDBEN_Msk (0x1ul << TIMER_EXTCTL_ECNTDBEN_Pos)
25156#define TIMER_EINTSTS_CAPIF_Pos (0)
25157#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /* TIMER_CONST */ /* end of TMR register group */
25162
25163
25164/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
25170 typedef struct {
25171
25172
25188 __IO uint32_t DAT;
25189
25242 __IO uint32_t INTEN;
25243
25288 __IO uint32_t FIFO;
25289
25321 __IO uint32_t LINE;
25322
25344 __IO uint32_t MODEM;
25345
25363 __IO uint32_t MODEMSTS;
25364
25425 __IO uint32_t FIFOSTS;
25426
25529 __IO uint32_t INTSTS;
25530
25548 __IO uint32_t TOUT;
25549
25573 __IO uint32_t BAUD;
25574
25593 __IO uint32_t IRDA;
25594
25635 __IO uint32_t ALTCTL;
25636
25651 __IO uint32_t FUNCSEL;
25652
25731 __IO uint32_t LINCTL;
25732
25780 __IO uint32_t LINSTS;
25781
25798 __IO uint32_t LINDEBUG;
25799
25800
25801} UART_T;
25802
25808#define UART_DAT_DAT_Pos (0)
25809#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos)
25811#define UART_INTEN_RDAIEN_Pos (0)
25812#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos)
25814#define UART_INTEN_THREIEN_Pos (1)
25815#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos)
25817#define UART_INTEN_RLSIEN_Pos (2)
25818#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos)
25820#define UART_INTEN_MODEMIEN_Pos (3)
25821#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos)
25823#define UART_INTEN_RXTOIEN_Pos (4)
25824#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos)
25826#define UART_INTEN_BUFERRIEN_Pos (5)
25827#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos)
25829#define UART_INTEN_WKCTSIEN_Pos (6)
25830#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos)
25832#define UART_INTEN_LINIEN_Pos (8)
25833#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos)
25835#define UART_INTEN_TOCNTEN_Pos (11)
25836#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos)
25838#define UART_INTEN_ATORTSEN_Pos (12)
25839#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos)
25841#define UART_INTEN_ATOCTSEN_Pos (13)
25842#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos)
25844#define UART_INTEN_TXPDMAEN_Pos (14)
25845#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos)
25847#define UART_INTEN_RXPDMAEN_Pos (15)
25848#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos)
25850#define UART_FIFO_RXRST_Pos (1)
25851#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos)
25853#define UART_FIFO_TXRST_Pos (2)
25854#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos)
25856#define UART_FIFO_RFITL_Pos (4)
25857#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos)
25859#define UART_FIFO_RXOFF_Pos (8)
25860#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos)
25862#define UART_FIFO_RTSTRGLV_Pos (16)
25863#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos)
25865#define UART_LINE_WLS_Pos (0)
25866#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos)
25868#define UART_LINE_NSB_Pos (2)
25869#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos)
25871#define UART_LINE_PBE_Pos (3)
25872#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos)
25874#define UART_LINE_EPE_Pos (4)
25875#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos)
25877#define UART_LINE_SPE_Pos (5)
25878#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos)
25880#define UART_LINE_BCB_Pos (6)
25881#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos)
25883#define UART_MODEM_RTS_Pos (1)
25884#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos)
25886#define UART_MODEM_RTSACTLV_Pos (9)
25887#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos)
25889#define UART_MODEM_RTSSTS_Pos (13)
25890#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos)
25892#define UART_MODEMSTS_CTSDETF_Pos (0)
25893#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos)
25895#define UART_MODEMSTS_CTSSTS_Pos (4)
25896#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos)
25898#define UART_MODEMSTS_CTSACTLV_Pos (8)
25899#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)
25901#define UART_FIFOSTS_RXOVIF_Pos (0)
25902#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos)
25904#define UART_FIFOSTS_SCERR_Pos (2)
25905#define UART_FIFOSTS_SCERR_Msk (0x1ul << UART_FIFOSTS_SCERR_Pos)
25907#define UART_FIFOSTS_ADDRDETF_Pos (3)
25908#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)
25910#define UART_FIFOSTS_PEF_Pos (4)
25911#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos)
25913#define UART_FIFOSTS_FEF_Pos (5)
25914#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos)
25916#define UART_FIFOSTS_BIF_Pos (6)
25917#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos)
25919#define UART_FIFOSTS_RXPTR_Pos (8)
25920#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos)
25922#define UART_FIFOSTS_RXEMPTY_Pos (14)
25923#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)
25925#define UART_FIFOSTS_RXFULL_Pos (15)
25926#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos)
25928#define UART_FIFOSTS_TXPTR_Pos (16)
25929#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos)
25931#define UART_FIFOSTS_TXEMPTY_Pos (22)
25932#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)
25934#define UART_FIFOSTS_TXFULL_Pos (23)
25935#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos)
25937#define UART_FIFOSTS_TXOVIF_Pos (24)
25938#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos)
25940#define UART_FIFOSTS_TXEMPTYF_Pos (28)
25941#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)
25943#define UART_INTSTS_RDAIF_Pos (0)
25944#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos)
25946#define UART_INTSTS_THREIF_Pos (1)
25947#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos)
25949#define UART_INTSTS_RLSIF_Pos (2)
25950#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos)
25952#define UART_INTSTS_MODEMIF_Pos (3)
25953#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos)
25955#define UART_INTSTS_RXTOIF_Pos (4)
25956#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos)
25958#define UART_INTSTS_BUFERRIF_Pos (5)
25959#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos)
25961#define UART_INTSTS_LINIF_Pos (7)
25962#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos)
25964#define UART_INTSTS_RDAINT_Pos (8)
25965#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos)
25967#define UART_INTSTS_THREINT_Pos (9)
25968#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos)
25970#define UART_INTSTS_RLSINT_Pos (10)
25971#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos)
25973#define UART_INTSTS_MODEMINT_Pos (11)
25974#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos)
25976#define UART_INTSTS_RXTOINT_Pos (12)
25977#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos)
25979#define UART_INTSTS_BUFERRINT_Pos (13)
25980#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos)
25982#define UART_INTSTS_LININT_Pos (15)
25983#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos)
25985#define UART_INTSTS_HWRLSIF_Pos (18)
25986#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos)
25988#define UART_INTSTS_HWMODIF_Pos (19)
25989#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos)
25991#define UART_INTSTS_HWTOIF_Pos (20)
25992#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos)
25994#define UART_INTSTS_HWBUFEIF_Pos (21)
25995#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos)
25997#define UART_INTSTS_HWRLSINT_Pos (26)
25998#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos)
26000#define UART_INTSTS_HWMODINT_Pos (27)
26001#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos)
26003#define UART_INTSTS_HWTOINT_Pos (28)
26004#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos)
26006#define UART_INTSTS_HWBUFEINT_Pos (29)
26007#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos)
26009#define UART_TOUT_TOIC_Pos (0)
26010#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos)
26012#define UART_TOUT_DLY_Pos (8)
26013#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos)
26015#define UART_BAUD_BRD_Pos (0)
26016#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
26018#define UART_BAUD_EDIVM1_Pos (24)
26019#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos)
26021#define UART_BAUD_BAUDM0_Pos (28)
26022#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos)
26024#define UART_BAUD_BAUDM1_Pos (29)
26025#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos)
26027#define UART_IRDA_TXEN_Pos (1)
26028#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos)
26030#define UART_IRDA_TXINV_Pos (5)
26031#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos)
26033#define UART_IRDA_RXINV_Pos (6)
26034#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos)
26036#define UART_IRDA_FIXPULSE_Pos (7)
26037#define UART_IRDA_FIXPULSE_Msk (0x1ul << UART_IRDA_FIXPULSE_Pos)
26039#define UART_ALTCTL_BKFL_Pos (0)
26040#define UART_ALTCTL_BKFL_Msk (0xful << UART_ALTCTL_BKFL_Pos)
26042#define UART_ALTCTL_LINRXEN_Pos (6)
26043#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos)
26045#define UART_ALTCTL_LINTXEN_Pos (7)
26046#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos)
26048#define UART_ALTCTL_RS485NMM_Pos (8)
26049#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos)
26051#define UART_ALTCTL_RS485AAD_Pos (9)
26052#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos)
26054#define UART_ALTCTL_RS485AUD_Pos (10)
26055#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos)
26057#define UART_ALTCTL_ADDRDEN_Pos (15)
26058#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos)
26060#define UART_ALTCTL_ADDRMV_Pos (24)
26061#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos)
26063#define UART_FUNCSEL_FUNCSEL_Pos (0)
26064#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos)
26066#define UART_LINCTL_SLVEN_Pos (0)
26067#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos)
26069#define UART_LINCTL_SLVHDEN_Pos (1)
26070#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos)
26072#define UART_LINCTL_SLVAREN_Pos (2)
26073#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos)
26075#define UART_LINCTL_SLVDUEN_Pos (3)
26076#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos)
26078#define UART_LINCTL_MUTE_Pos (4)
26079#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos)
26081#define UART_LINCTL_SENDH_Pos (8)
26082#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos)
26084#define UART_LINCTL_IDPEN_Pos (9)
26085#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos)
26087#define UART_LINCTL_BRKDETEN_Pos (10)
26088#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos)
26090#define UART_LINCTL_RXOFF_Pos (11)
26091#define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos)
26093#define UART_LINCTL_BITERREN_Pos (12)
26094#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos)
26096#define UART_LINCTL_BRKFL_Pos (16)
26097#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos)
26099#define UART_LINCTL_BSL_Pos (20)
26100#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos)
26102#define UART_LINCTL_HSEL_Pos (22)
26103#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos)
26105#define UART_LINCTL_PID_Pos (24)
26106#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos)
26108#define UART_LINSTS_SLVHDETF_Pos (0)
26109#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos)
26111#define UART_LINSTS_SLVHEF_Pos (1)
26112#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos)
26114#define UART_LINSTS_SLVIDPEF_Pos (2)
26115#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos)
26117#define UART_LINSTS_SLVSYNCF_Pos (3)
26118#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos)
26120#define UART_LINSTS_BRKDETF_Pos (8)
26121#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos)
26123#define UART_LINSTS_BITEF_Pos (9)
26124#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos)
26126#define UART_LINDEBUG_DEVERRF_Pos (0)
26127#define UART_LINDEBUG_DEVERRF_Msk (0x1ul << UART_LINDEBUG_DEVERRF_Pos)
26129#define UART_LINDEBUG_TOF_Pos (1)
26130#define UART_LINDEBUG_TOF_Msk (0x1ul << UART_LINDEBUG_TOF_Pos)
26132#define UART_LINDEBUG_FRAMEERRF_Pos (2)
26133#define UART_LINDEBUG_FRAMEERRF_Msk (0x1ul << UART_LINDEBUG_FRAMEERRF_Pos)
26135#define UART_LINDEBUG_SYNCERRF_Pos (3)
26136#define UART_LINDEBUG_SYNCERRF_Msk (0x1ul << UART_LINDEBUG_SYNCERRF_Pos) /* UART_CONST */ /* end of UART register group */
26140
26141
26142/*---------------------- USB Host Controller -------------------------*/
26148 typedef struct {
26161 __I uint32_t HcRevision;
26162
26200 __IO uint32_t HcControl;
26201
26222 __IO uint32_t HcCommandStatus;
26223
26246 __IO uint32_t HcInterruptStatus;
26247
26279 __IO uint32_t HcInterruptEnable;
26280
26311 __IO uint32_t HcInterruptDisable;
26312
26323 __IO uint32_t HcHCCA;
26324
26335 __IO uint32_t HcPeriodCurrentED;
26336
26347 __IO uint32_t HcControlHeadED;
26348
26359 __IO uint32_t HcControlCurrentED;
26360
26371 __IO uint32_t HcBulkHeadED;
26372
26383 __IO uint32_t HcBulkCurrentED;
26384
26395 __IO uint32_t HcDoneHead;
26396
26412 __IO uint32_t HcFmInterval;
26413
26428 __I uint32_t HcFmRemaining;
26429
26441 __I uint32_t HcFmNumber;
26442
26453 __IO uint32_t HcPeriodicStart;
26454
26467 __IO uint32_t HcLSThreshold;
26468
26509 __IO uint32_t HcRhDescriptorA;
26510
26527 __IO uint32_t HcRhDescriptorB;
26528
26561 __IO uint32_t HcRhStatus;
26562
26634 __IO uint32_t HcRhPortStatus[2];
26636 uint32_t RESERVE0[105];
26638
26639
26652 __IO uint32_t HcPhyControl;
26653
26691 __IO uint32_t HcMiscControl;
26692
26693} USBH_T;
26694
26700#define USBH_HcRevision_REV_Pos (0)
26701#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos)
26703#define USBH_HcControl_CBSR_Pos (0)
26704#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos)
26706#define USBH_HcControl_PLE_Pos (2)
26707#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos)
26709#define USBH_HcControl_IE_Pos (3)
26710#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos)
26712#define USBH_HcControl_CLE_Pos (4)
26713#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos)
26715#define USBH_HcControl_BLE_Pos (5)
26716#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos)
26718#define USBH_HcControl_HCFS_Pos (6)
26719#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos)
26721#define USBH_HcCommandStatus_HCR_Pos (0)
26722#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos)
26724#define USBH_HcCommandStatus_CLF_Pos (1)
26725#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos)
26727#define USBH_HcCommandStatus_BLF_Pos (2)
26728#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos)
26730#define USBH_HcCommandStatus_SOC_Pos (16)
26731#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos)
26733#define USBH_HcInterruptStatus_SO_Pos (0)
26734#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos)
26736#define USBH_HcInterruptStatus_WDH_Pos (1)
26737#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos)
26739#define USBH_HcInterruptStatus_SF_Pos (2)
26740#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos)
26742#define USBH_HcInterruptStatus_RD_Pos (3)
26743#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos)
26745#define USBH_HcInterruptStatus_FNO_Pos (5)
26746#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos)
26748#define USBH_HcInterruptStatus_RHSC_Pos (6)
26749#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)
26751#define USBH_HcInterruptEnable_SO_Pos (0)
26752#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos)
26754#define USBH_HcInterruptEnable_WDH_Pos (1)
26755#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos)
26757#define USBH_HcInterruptEnable_SF_Pos (2)
26758#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos)
26760#define USBH_HcInterruptEnable_RD_Pos (3)
26761#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos)
26763#define USBH_HcInterruptEnable_FNO_Pos (5)
26764#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos)
26766#define USBH_HcInterruptEnable_RHSC_Pos (6)
26767#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)
26769#define USBH_HcInterruptEnable_MIE_Pos (31)
26770#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos)
26772#define USBH_HcInterruptDisable_SO_Pos (0)
26773#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos)
26775#define USBH_HcInterruptDisable_WDH_Pos (1)
26776#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos)
26778#define USBH_HcInterruptDisable_SF_Pos (2)
26779#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos)
26781#define USBH_HcInterruptDisable_RD_Pos (3)
26782#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos)
26784#define USBH_HcInterruptDisable_FNO_Pos (5)
26785#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos)
26787#define USBH_HcInterruptDisable_RHSC_Pos (6)
26788#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)
26790#define USBH_HcInterruptDisable_MIE_Pos (31)
26791#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos)
26793#define USBH_HcHCCA_HCCA_Pos (8)
26794#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos)
26796#define USBH_HcPeriodCurrentED_PCED_Pos (4)
26797#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)
26799#define USBH_HcControlHeadED_CHED_Pos (4)
26800#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos)
26802#define USBH_HcControlCurrentED_CCED_Pos (4)
26803#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos)
26805#define USBH_HcBulkHeadED_BHED_Pos (4)
26806#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)
26808#define USBH_HcBulkCurrentED_BCED_Pos (4)
26809#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)
26811#define USBH_HcDoneHead_DH_Pos (4)
26812#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos)
26814#define USBH_HcFmInterval_FI_Pos (0)
26815#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos)
26817#define USBH_HcFmInterval_FSMPS_Pos (16)
26818#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos)
26820#define USBH_HcFmInterval_FIT_Pos (31)
26821#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos)
26823#define USBH_HcFmRemaining_FR_Pos (0)
26824#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos)
26826#define USBH_HcFmRemaining_FRT_Pos (31)
26827#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos)
26829#define USBH_HcFmNumber_FN_Pos (0)
26830#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos)
26832#define USBH_HcPeriodicStart_PS_Pos (0)
26833#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos)
26835#define USBH_HcLSThreshold_LST_Pos (0)
26836#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos)
26838#define USBH_HcRhDescriptorA_NDP_Pos (0)
26839#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos)
26841#define USBH_HcRhDescriptorA_PSM_Pos (8)
26842#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)
26844#define USBH_HcRhDescriptorA_NPS_Pos (9)
26845#define USBH_HcRhDescriptorA_NPS_Msk (0x1ul << USBH_HcRhDescriptorA_NPS_Pos)
26847#define USBH_HcRhDescriptorA_DT_Pos (10)
26848#define USBH_HcRhDescriptorA_DT_Msk (0x1ul << USBH_HcRhDescriptorA_DT_Pos)
26850#define USBH_HcRhDescriptorA_OCPM_Pos (11)
26851#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)
26853#define USBH_HcRhDescriptorA_NOCP_Pos (12)
26854#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)
26856#define USBH_HcRhDescriptorA_POTPGT_Pos (24)
26857#define USBH_HcRhDescriptorA_POTPGT_Msk (0xfful << USBH_HcRhDescriptorA_POTPGT_Pos)
26859#define USBH_HcRhDescriptorB_PPCM_Pos (16)
26860#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)
26862#define USBH_HcRhStatus_LPS_Pos (0)
26863#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos)
26865#define USBH_HcRhStatus_OCI_Pos (1)
26866#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos)
26868#define USBH_HcRhStatus_DRWE_Pos (15)
26869#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos)
26871#define USBH_HcRhStatus_LPSC_Pos (16)
26872#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos)
26874#define USBH_HcRhStatus_OCIC_Pos (17)
26875#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos)
26877#define USBH_HcRhStatus_CRWE_Pos (31)
26878#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos)
26880#define USBH_HcRhPortStatus_CCS_Pos (0)
26881#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos)
26883#define USBH_HcRhPortStatus_PES_Pos (1)
26884#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos)
26886#define USBH_HcRhPortStatus_PSS_Pos (2)
26887#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos)
26889#define USBH_HcRhPortStatus_POCI_Pos (3)
26890#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos)
26892#define USBH_HcRhPortStatus_PRS_Pos (4)
26893#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos)
26895#define USBH_HcRhPortStatus_PPS_Pos (8)
26896#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos)
26898#define USBH_HcRhPortStatus_LSDA_Pos (9)
26899#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)
26901#define USBH_HcRhPortStatus_CSC_Pos (16)
26902#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos)
26904#define USBH_HcRhPortStatus_PESC_Pos (17)
26905#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos)
26907#define USBH_HcRhPortStatus_PSSC_Pos (18)
26908#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)
26910#define USBH_HcRhPortStatus_OCIC_Pos (19)
26911#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)
26913#define USBH_HcRhPortStatus_PRSC_Pos (20)
26914#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)
26916#define USBH_HcPhyControl_STBYEN_Pos (27)
26917#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos)
26919#define USBH_HcMiscControl_DBR16_Pos (0)
26920#define USBH_HcMiscControl_DBR16_Msk (0x1ul << USBH_HcMiscControl_DBR16_Pos)
26922#define USBH_HcMiscControl_ABORT_Pos (1)
26923#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos)
26925#define USBH_HcMiscControl_OCAL_Pos (3)
26926#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos)
26928#define USBH_HcMiscControl_PCAL_Pos (4)
26929#define USBH_HcMiscControl_PCAL_Msk (0x1ul << USBH_HcMiscControl_PCAL_Pos)
26931#define USBH_HcMiscControl_SIEPD_Pos (8)
26932#define USBH_HcMiscControl_SIEPD_Msk (0x1ul << USBH_HcMiscControl_SIEPD_Pos)
26934#define USBH_HcMiscControl_DPRT1_Pos (16)
26935#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos)
26937#define USBH_HcMiscControl_DPRT2_Pos (17)
26938#define USBH_HcMiscControl_DPRT2_Msk (0x1ul << USBH_HcMiscControl_DPRT2_Pos) /* USBH_CONST */ /* end of USBH register group */
26942
26943
26944/*---------------------- USB Device Controller -------------------------*/
26952 typedef struct {
26953
26954 union {
26955
26967 __IO uint32_t EPDAT;
26979 __IO uint8_t EPDAT_BYTE;
26980
26981 };
26982
27050 __IO uint32_t EPINTSTS;
27051
27112 __IO uint32_t EPINTEN;
27113
27126 __I uint32_t EPDATCNT;
27127
27176 __IO uint32_t EPRSPCTL;
27177
27188 __IO uint32_t EPMPS;
27189
27201 __IO uint32_t EPTXCNT;
27202
27228 __IO uint32_t EPCFG;
27229
27240 __IO uint32_t EPBUFSTART;
27241
27252 __IO uint32_t EPBUFEND;
27253
27254
27255} USBD_EP_T;
27256
27257
27258 typedef struct {
27259
27260
27327 __I uint32_t GINTSTS;
27329 uint32_t RESERVE0[1];
27331
27332
27397 __IO uint32_t GINTEN;
27399 uint32_t RESERVE1[1];
27401
27402
27448 __IO uint32_t BUSINTSTS;
27449
27490 __IO uint32_t BUSINTEN;
27491
27510 __IO uint32_t OPER;
27511
27524 __I uint32_t FRAMECNT;
27525
27537 __IO uint32_t FADDR;
27538
27557 __IO uint32_t TEST;
27558
27559 union {
27560
27572 __IO uint32_t CEPDAT;
27584 __IO uint8_t CEPDAT_BYTE;
27585
27586 };
27587
27622 __IO uint32_t CEPCTL;
27623
27671 __IO uint32_t CEPINTEN;
27672
27735 __IO uint32_t CEPINTSTS;
27736
27749 __IO uint32_t CEPTXCNT;
27750
27761 __I uint32_t CEPRXCNT;
27762
27773 __I uint32_t CEPDATCNT;
27774
27816 __I uint32_t SETUP1_0;
27817
27832 __I uint32_t SETUP3_2;
27833
27848 __I uint32_t SETUP5_4;
27849
27864 __I uint32_t SETUP7_6;
27865
27876 __IO uint32_t CEPBUFSTART;
27877
27888 __IO uint32_t CEPBUFEND;
27889
27912 __IO uint32_t DMACTL;
27913
27924 __IO uint32_t DMACNT;
27925
27926 USBD_EP_T EP[12];
27928 uint32_t RESERVE2[303];
27930
27931
27943 __IO uint32_t DMAADDR;
27944
27965 __IO uint32_t PHYCTL;
27966
27967} USBD_T;
27968
27974#define USBD_GINTSTS_USBIF_Pos (0)
27975#define USBD_GINTSTS_USBIF_Msk (0x1ul << USBD_GINTSTS_USBIF_Pos)
27977#define USBD_GINTSTS_CEPIF_Pos (1)
27978#define USBD_GINTSTS_CEPIF_Msk (0x1ul << USBD_GINTSTS_CEPIF_Pos)
27980#define USBD_GINTSTS_EPAIF_Pos (2)
27981#define USBD_GINTSTS_EPAIF_Msk (0x1ul << USBD_GINTSTS_EPAIF_Pos)
27983#define USBD_GINTSTS_EPBIF_Pos (3)
27984#define USBD_GINTSTS_EPBIF_Msk (0x1ul << USBD_GINTSTS_EPBIF_Pos)
27986#define USBD_GINTSTS_EPCIF_Pos (4)
27987#define USBD_GINTSTS_EPCIF_Msk (0x1ul << USBD_GINTSTS_EPCIF_Pos)
27989#define USBD_GINTSTS_EPDIF_Pos (5)
27990#define USBD_GINTSTS_EPDIF_Msk (0x1ul << USBD_GINTSTS_EPDIF_Pos)
27992#define USBD_GINTSTS_EPEIF_Pos (6)
27993#define USBD_GINTSTS_EPEIF_Msk (0x1ul << USBD_GINTSTS_EPEIF_Pos)
27995#define USBD_GINTSTS_EPFIF_Pos (7)
27996#define USBD_GINTSTS_EPFIF_Msk (0x1ul << USBD_GINTSTS_EPFIF_Pos)
27998#define USBD_GINTSTS_EPGIF_Pos (8)
27999#define USBD_GINTSTS_EPGIF_Msk (0x1ul << USBD_GINTSTS_EPGIF_Pos)
28001#define USBD_GINTSTS_EPHIF_Pos (9)
28002#define USBD_GINTSTS_EPHIF_Msk (0x1ul << USBD_GINTSTS_EPHIF_Pos)
28004#define USBD_GINTSTS_EPIIF_Pos (10)
28005#define USBD_GINTSTS_EPIIF_Msk (0x1ul << USBD_GINTSTS_EPIIF_Pos)
28007#define USBD_GINTSTS_EPJIF_Pos (11)
28008#define USBD_GINTSTS_EPJIF_Msk (0x1ul << USBD_GINTSTS_EPJIF_Pos)
28010#define USBD_GINTSTS_EPKIF_Pos (12)
28011#define USBD_GINTSTS_EPKIF_Msk (0x1ul << USBD_GINTSTS_EPKIF_Pos)
28013#define USBD_GINTSTS_EPLIF_Pos (13)
28014#define USBD_GINTSTS_EPLIF_Msk (0x1ul << USBD_GINTSTS_EPLIF_Pos)
28016#define USBD_GINTEN_USBIE_Pos (0)
28017#define USBD_GINTEN_USBIE_Msk (0x1ul << USBD_GINTEN_USBIE_Pos)
28019#define USBD_GINTEN_CEPIE_Pos (1)
28020#define USBD_GINTEN_CEPIE_Msk (0x1ul << USBD_GINTEN_CEPIE_Pos)
28022#define USBD_GINTEN_EPAIE_Pos (2)
28023#define USBD_GINTEN_EPAIE_Msk (0x1ul << USBD_GINTEN_EPAIE_Pos)
28025#define USBD_GINTEN_EPBIE_Pos (3)
28026#define USBD_GINTEN_EPBIE_Msk (0x1ul << USBD_GINTEN_EPBIE_Pos)
28028#define USBD_GINTEN_EPCIE_Pos (4)
28029#define USBD_GINTEN_EPCIE_Msk (0x1ul << USBD_GINTEN_EPCIE_Pos)
28031#define USBD_GINTEN_EPDIE_Pos (5)
28032#define USBD_GINTEN_EPDIE_Msk (0x1ul << USBD_GINTEN_EPDIE_Pos)
28034#define USBD_GINTEN_EPEIE_Pos (6)
28035#define USBD_GINTEN_EPEIE_Msk (0x1ul << USBD_GINTEN_EPEIE_Pos)
28037#define USBD_GINTEN_EPFIE_Pos (7)
28038#define USBD_GINTEN_EPFIE_Msk (0x1ul << USBD_GINTEN_EPFIE_Pos)
28040#define USBD_GINTEN_EPGIE_Pos (8)
28041#define USBD_GINTEN_EPGIE_Msk (0x1ul << USBD_GINTEN_EPGIE_Pos)
28043#define USBD_GINTEN_EPHIE_Pos (9)
28044#define USBD_GINTEN_EPHIE_Msk (0x1ul << USBD_GINTEN_EPHIE_Pos)
28046#define USBD_GINTEN_EPIIE_Pos (10)
28047#define USBD_GINTEN_EPIIE_Msk (0x1ul << USBD_GINTEN_EPIIE_Pos)
28049#define USBD_GINTEN_EPJIE_Pos (11)
28050#define USBD_GINTEN_EPJIE_Msk (0x1ul << USBD_GINTEN_EPJIE_Pos)
28052#define USBD_GINTEN_EPKIE_Pos (12)
28053#define USBD_GINTEN_EPKIE_Msk (0x1ul << USBD_GINTEN_EPKIE_Pos)
28055#define USBD_GINTEN_EPLIE_Pos (13)
28056#define USBD_GINTEN_EPLIE_Msk (0x1ul << USBD_GINTEN_EPLIE_Pos)
28058#define USBD_BUSINTSTS_SOFIF_Pos (0)
28059#define USBD_BUSINTSTS_SOFIF_Msk (0x1ul << USBD_BUSINTSTS_SOFIF_Pos)
28061#define USBD_BUSINTSTS_RSTIF_Pos (1)
28062#define USBD_BUSINTSTS_RSTIF_Msk (0x1ul << USBD_BUSINTSTS_RSTIF_Pos)
28064#define USBD_BUSINTSTS_RESUMEIF_Pos (2)
28065#define USBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos)
28067#define USBD_BUSINTSTS_SUSPENDIF_Pos (3)
28068#define USBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos)
28070#define USBD_BUSINTSTS_HISPDIF_Pos (4)
28071#define USBD_BUSINTSTS_HISPDIF_Msk (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos)
28073#define USBD_BUSINTSTS_DMADONEIF_Pos (5)
28074#define USBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos)
28076#define USBD_BUSINTSTS_PHYCLKVLDIF_Pos (6)
28077#define USBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos)
28079#define USBD_BUSINTSTS_VBUSDETIF_Pos (8)
28080#define USBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos)
28082#define USBD_BUSINTEN_SOFIEN_Pos (0)
28083#define USBD_BUSINTEN_SOFIEN_Msk (0x1ul << USBD_BUSINTEN_SOFIEN_Pos)
28085#define USBD_BUSINTEN_RSTIEN_Pos (1)
28086#define USBD_BUSINTEN_RSTIEN_Msk (0x1ul << USBD_BUSINTEN_RSTIEN_Pos)
28088#define USBD_BUSINTEN_RESUMEIEN_Pos (2)
28089#define USBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos)
28091#define USBD_BUSINTEN_SUSPENDIEN_Pos (3)
28092#define USBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos)
28094#define USBD_BUSINTEN_HISPDIEN_Pos (4)
28095#define USBD_BUSINTEN_HISPDIEN_Msk (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos)
28097#define USBD_BUSINTEN_DMADONEIEN_Pos (5)
28098#define USBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos)
28100#define USBD_BUSINTEN_PHYCLKVLDIEN_Pos (6)
28101#define USBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos)
28103#define USBD_BUSINTEN_VBUSDETIEN_Pos (8)
28104#define USBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos)
28106#define USBD_OPER_RESUMEEN_Pos (0)
28107#define USBD_OPER_RESUMEEN_Msk (0x1ul << USBD_OPER_RESUMEEN_Pos)
28109#define USBD_OPER_HISPDEN_Pos (1)
28110#define USBD_OPER_HISPDEN_Msk (0x1ul << USBD_OPER_HISPDEN_Pos)
28112#define USBD_OPER_CURSPD_Pos (2)
28113#define USBD_OPER_CURSPD_Msk (0x1ul << USBD_OPER_CURSPD_Pos)
28115#define USBD_FRAMECNT_MFRAMECNT_Pos (0)
28116#define USBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos)
28118#define USBD_FRAMECNT_FRAMECNT_Pos (3)
28119#define USBD_FRAMECNT_FRAMECNT_Msk (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos)
28121#define USBD_FADDR_FADDR_Pos (0)
28122#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos)
28124#define USBD_TEST_TESTMODE_Pos (0)
28125#define USBD_TEST_TESTMODE_Msk (0x7ul << USBD_TEST_TESTMODE_Pos)
28127#define USBD_CEPDAT_DAT_Pos (0)
28128#define USBD_CEPDAT_DAT_Msk (0xfffffffful << USBD_CEPDAT_DAT_Pos)
28130#define USBD_CEPCTL_NAKCLR_Pos (0)
28131#define USBD_CEPCTL_NAKCLR_Msk (0x1ul << USBD_CEPCTL_NAKCLR_Pos)
28133#define USBD_CEPCTL_STALLEN_Pos (1)
28134#define USBD_CEPCTL_STALLEN_Msk (0x1ul << USBD_CEPCTL_STALLEN_Pos)
28136#define USBD_CEPCTL_ZEROLEN_Pos (2)
28137#define USBD_CEPCTL_ZEROLEN_Msk (0x1ul << USBD_CEPCTL_ZEROLEN_Pos)
28139#define USBD_CEPCTL_FLUSH_Pos (3)
28140#define USBD_CEPCTL_FLUSH_Msk (0x1ul << USBD_CEPCTL_FLUSH_Pos)
28142#define USBD_CEPINTEN_SETUPTKIEN_Pos (0)
28143#define USBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos)
28145#define USBD_CEPINTEN_SETUPPKIEN_Pos (1)
28146#define USBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos)
28148#define USBD_CEPINTEN_OUTTKIEN_Pos (2)
28149#define USBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos)
28151#define USBD_CEPINTEN_INTKIEN_Pos (3)
28152#define USBD_CEPINTEN_INTKIEN_Msk (0x1ul << USBD_CEPINTEN_INTKIEN_Pos)
28154#define USBD_CEPINTEN_PINGIEN_Pos (4)
28155#define USBD_CEPINTEN_PINGIEN_Msk (0x1ul << USBD_CEPINTEN_PINGIEN_Pos)
28157#define USBD_CEPINTEN_TXPKIEN_Pos (5)
28158#define USBD_CEPINTEN_TXPKIEN_Msk (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos)
28160#define USBD_CEPINTEN_RXPKIEN_Pos (6)
28161#define USBD_CEPINTEN_RXPKIEN_Msk (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos)
28163#define USBD_CEPINTEN_NAKIEN_Pos (7)
28164#define USBD_CEPINTEN_NAKIEN_Msk (0x1ul << USBD_CEPINTEN_NAKIEN_Pos)
28166#define USBD_CEPINTEN_STALLIEN_Pos (8)
28167#define USBD_CEPINTEN_STALLIEN_Msk (0x1ul << USBD_CEPINTEN_STALLIEN_Pos)
28169#define USBD_CEPINTEN_ERRIEN_Pos (9)
28170#define USBD_CEPINTEN_ERRIEN_Msk (0x1ul << USBD_CEPINTEN_ERRIEN_Pos)
28172#define USBD_CEPINTEN_STSDONEIEN_Pos (10)
28173#define USBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos)
28175#define USBD_CEPINTEN_BUFFULLIEN_Pos (11)
28176#define USBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos)
28178#define USBD_CEPINTEN_BUFEMPTYIEN_Pos (12)
28179#define USBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos)
28181#define USBD_CEPINTSTS_SETUPTKIF_Pos (0)
28182#define USBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos)
28184#define USBD_CEPINTSTS_SETUPPKIF_Pos (1)
28185#define USBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos)
28187#define USBD_CEPINTSTS_OUTTKIF_Pos (2)
28188#define USBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos)
28190#define USBD_CEPINTSTS_INTKIF_Pos (3)
28191#define USBD_CEPINTSTS_INTKIF_Msk (0x1ul << USBD_CEPINTSTS_INTKIF_Pos)
28193#define USBD_CEPINTSTS_PINGIF_Pos (4)
28194#define USBD_CEPINTSTS_PINGIF_Msk (0x1ul << USBD_CEPINTSTS_PINGIF_Pos)
28196#define USBD_CEPINTSTS_TXPKIF_Pos (5)
28197#define USBD_CEPINTSTS_TXPKIF_Msk (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos)
28199#define USBD_CEPINTSTS_RXPKIF_Pos (6)
28200#define USBD_CEPINTSTS_RXPKIF_Msk (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos)
28202#define USBD_CEPINTSTS_NAKIF_Pos (7)
28203#define USBD_CEPINTSTS_NAKIF_Msk (0x1ul << USBD_CEPINTSTS_NAKIF_Pos)
28205#define USBD_CEPINTSTS_STALLIF_Pos (8)
28206#define USBD_CEPINTSTS_STALLIF_Msk (0x1ul << USBD_CEPINTSTS_STALLIF_Pos)
28208#define USBD_CEPINTSTS_ERRIF_Pos (9)
28209#define USBD_CEPINTSTS_ERRIF_Msk (0x1ul << USBD_CEPINTSTS_ERRIF_Pos)
28211#define USBD_CEPINTSTS_STSDONEIF_Pos (10)
28212#define USBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos)
28214#define USBD_CEPINTSTS_BUFFULLIF_Pos (11)
28215#define USBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos)
28217#define USBD_CEPINTSTS_BUFEMPTYIF_Pos (12)
28218#define USBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos)
28220#define USBD_CEPTXCNT_TXCNT_Pos (0)
28221#define USBD_CEPTXCNT_TXCNT_Msk (0xfful << USBD_CEPTXCNT_TXCNT_Pos)
28223#define USBD_CEPRXCNT_RXCNT_Pos (0)
28224#define USBD_CEPRXCNT_RXCNT_Msk (0xfful << USBD_CEPRXCNT_RXCNT_Pos)
28226#define USBD_CEPDATCNT_DATCNT_Pos (0)
28227#define USBD_CEPDATCNT_DATCNT_Msk (0xfffful << USBD_CEPDATCNT_DATCNT_Pos)
28229#define USBD_SETUP1_0_SETUP0_Pos (0)
28230#define USBD_SETUP1_0_SETUP0_Msk (0xfful << USBD_SETUP1_0_SETUP0_Pos)
28232#define USBD_SETUP1_0_SETUP1_Pos (8)
28233#define USBD_SETUP1_0_SETUP1_Msk (0xfful << USBD_SETUP1_0_SETUP1_Pos)
28235#define USBD_SETUP3_2_SETUP2_Pos (0)
28236#define USBD_SETUP3_2_SETUP2_Msk (0xfful << USBD_SETUP3_2_SETUP2_Pos)
28238#define USBD_SETUP3_2_SETUP3_Pos (8)
28239#define USBD_SETUP3_2_SETUP3_Msk (0xfful << USBD_SETUP3_2_SETUP3_Pos)
28241#define USBD_SETUP5_4_SETUP4_Pos (0)
28242#define USBD_SETUP5_4_SETUP4_Msk (0xfful << USBD_SETUP5_4_SETUP4_Pos)
28244#define USBD_SETUP5_4_SETUP5_Pos (8)
28245#define USBD_SETUP5_4_SETUP5_Msk (0xfful << USBD_SETUP5_4_SETUP5_Pos)
28247#define USBD_SETUP7_6_SETUP6_Pos (0)
28248#define USBD_SETUP7_6_SETUP6_Msk (0xfful << USBD_SETUP7_6_SETUP6_Pos)
28250#define USBD_SETUP7_6_SETUP7_Pos (8)
28251#define USBD_SETUP7_6_SETUP7_Msk (0xfful << USBD_SETUP7_6_SETUP7_Pos)
28253#define USBD_CEPBUFSTART_SADDR_Pos (0)
28254#define USBD_CEPBUFSTART_SADDR_Msk (0xffful << USBD_CEPBUFSTART_SADDR_Pos)
28256#define USBD_CEPBUFEND_EADDR_Pos (0)
28257#define USBD_CEPBUFEND_EADDR_Msk (0xffful << USBD_CEPBUFEND_EADDR_Pos)
28259#define USBD_DMACTL_EPNUM_Pos (0)
28260#define USBD_DMACTL_EPNUM_Msk (0xful << USBD_DMACTL_EPNUM_Pos)
28262#define USBD_DMACTL_DMARD_Pos (4)
28263#define USBD_DMACTL_DMARD_Msk (0x1ul << USBD_DMACTL_DMARD_Pos)
28265#define USBD_DMACTL_DMAEN_Pos (5)
28266#define USBD_DMACTL_DMAEN_Msk (0x1ul << USBD_DMACTL_DMAEN_Pos)
28268#define USBD_DMACTL_SGEN_Pos (6)
28269#define USBD_DMACTL_SGEN_Msk (0x1ul << USBD_DMACTL_SGEN_Pos)
28271#define USBD_DMACTL_DMARST_Pos (7)
28272#define USBD_DMACTL_DMARST_Msk (0x1ul << USBD_DMACTL_DMARST_Pos)
28274#define USBD_DMACNT_DMACNT_Pos (0)
28275#define USBD_DMACNT_DMACNT_Msk (0xffffful << USBD_DMACNT_DMACNT_Pos)
28277#define USBD_EPDAT_EPDAT_Pos (0)
28278#define USBD_EPDAT_EPDAT_Msk (0xfffffffful << USBD_EPDAT_EPDAT_Pos)
28280#define USBD_EPINTSTS_BUFFULLIF_Pos (0)
28281#define USBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos)
28283#define USBD_EPINTSTS_BUFEMPTYIF_Pos (1)
28284#define USBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos)
28286#define USBD_EPINTSTS_SHORTTXIF_Pos (2)
28287#define USBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos)
28289#define USBD_EPINTSTS_TXPKIF_Pos (3)
28290#define USBD_EPINTSTS_TXPKIF_Msk (0x1ul << USBD_EPINTSTS_TXPKIF_Pos)
28292#define USBD_EPINTSTS_RXPKIF_Pos (4)
28293#define USBD_EPINTSTS_RXPKIF_Msk (0x1ul << USBD_EPINTSTS_RXPKIF_Pos)
28295#define USBD_EPINTSTS_OUTTKIF_Pos (5)
28296#define USBD_EPINTSTS_OUTTKIF_Msk (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos)
28298#define USBD_EPINTSTS_INTKIF_Pos (6)
28299#define USBD_EPINTSTS_INTKIF_Msk (0x1ul << USBD_EPINTSTS_INTKIF_Pos)
28301#define USBD_EPINTSTS_PINGIF_Pos (7)
28302#define USBD_EPINTSTS_PINGIF_Msk (0x1ul << USBD_EPINTSTS_PINGIF_Pos)
28304#define USBD_EPINTSTS_NAKIF_Pos (8)
28305#define USBD_EPINTSTS_NAKIF_Msk (0x1ul << USBD_EPINTSTS_NAKIF_Pos)
28307#define USBD_EPINTSTS_STALLIF_Pos (9)
28308#define USBD_EPINTSTS_STALLIF_Msk (0x1ul << USBD_EPINTSTS_STALLIF_Pos)
28310#define USBD_EPINTSTS_NYETIF_Pos (10)
28311#define USBD_EPINTSTS_NYETIF_Msk (0x1ul << USBD_EPINTSTS_NYETIF_Pos)
28313#define USBD_EPINTSTS_ERRIF_Pos (11)
28314#define USBD_EPINTSTS_ERRIF_Msk (0x1ul << USBD_EPINTSTS_ERRIF_Pos)
28316#define USBD_EPINTSTS_SHORTRXIF_Pos (12)
28317#define USBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos)
28319#define USBD_EPINTEN_BUFFULLIEN_Pos (0)
28320#define USBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos)
28322#define USBD_EPINTEN_BUFEMPTYIEN_Pos (1)
28323#define USBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos)
28325#define USBD_EPINTEN_SHORTTXIEN_Pos (2)
28326#define USBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos)
28328#define USBD_EPINTEN_TXPKIEN_Pos (3)
28329#define USBD_EPINTEN_TXPKIEN_Msk (0x1ul << USBD_EPINTEN_TXPKIEN_Pos)
28331#define USBD_EPINTEN_RXPKIEN_Pos (4)
28332#define USBD_EPINTEN_RXPKIEN_Msk (0x1ul << USBD_EPINTEN_RXPKIEN_Pos)
28334#define USBD_EPINTEN_OUTTKIEN_Pos (5)
28335#define USBD_EPINTEN_OUTTKIEN_Msk (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos)
28337#define USBD_EPINTEN_INTKIEN_Pos (6)
28338#define USBD_EPINTEN_INTKIEN_Msk (0x1ul << USBD_EPINTEN_INTKIEN_Pos)
28340#define USBD_EPINTEN_PINGIEN_Pos (7)
28341#define USBD_EPINTEN_PINGIEN_Msk (0x1ul << USBD_EPINTEN_PINGIEN_Pos)
28343#define USBD_EPINTEN_NAKIEN_Pos (8)
28344#define USBD_EPINTEN_NAKIEN_Msk (0x1ul << USBD_EPINTEN_NAKIEN_Pos)
28346#define USBD_EPINTEN_STALLIEN_Pos (9)
28347#define USBD_EPINTEN_STALLIEN_Msk (0x1ul << USBD_EPINTEN_STALLIEN_Pos)
28349#define USBD_EPINTEN_NYETIEN_Pos (10)
28350#define USBD_EPINTEN_NYETIEN_Msk (0x1ul << USBD_EPINTEN_NYETIEN_Pos)
28352#define USBD_EPINTEN_ERRIEN_Pos (11)
28353#define USBD_EPINTEN_ERRIEN_Msk (0x1ul << USBD_EPINTEN_ERRIEN_Pos)
28355#define USBD_EPINTEN_SHORTRXIEN_Pos (12)
28356#define USBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos)
28358#define USBD_EPDATCNT_DATCNT_Pos (0)
28359#define USBD_EPDATCNT_DATCNT_Msk (0xfffful << USBD_EPDATCNT_DATCNT_Pos)
28361#define USBD_EPDATCNT_DMALOOP_Pos (16)
28362#define USBD_EPDATCNT_DMALOOP_Msk (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos)
28364#define USBD_EPRSPCTL_FLUSH_Pos (0)
28365#define USBD_EPRSPCTL_FLUSH_Msk (0x1ul << USBD_EPRSPCTL_FLUSH_Pos)
28367#define USBD_EPRSPCTL_MODE_Pos (1)
28368#define USBD_EPRSPCTL_MODE_Msk (0x3ul << USBD_EPRSPCTL_MODE_Pos)
28370#define USBD_EPRSPCTL_TOGGLE_Pos (3)
28371#define USBD_EPRSPCTL_TOGGLE_Msk (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos)
28373#define USBD_EPRSPCTL_HALT_Pos (4)
28374#define USBD_EPRSPCTL_HALT_Msk (0x1ul << USBD_EPRSPCTL_HALT_Pos)
28376#define USBD_EPRSPCTL_ZEROLEN_Pos (5)
28377#define USBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos)
28379#define USBD_EPRSPCTL_SHORTTXEN_Pos (6)
28380#define USBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos)
28382#define USBD_EPRSPCTL_DISBUF_Pos (7)
28383#define USBD_EPRSPCTL_DISBUF_Msk (0x1ul << USBD_EPRSPCTL_DISBUF_Pos)
28385#define USBD_EPMPS_EPMPS_Pos (0)
28386#define USBD_EPMPS_EPMPS_Msk (0x7fful << USBD_EPMPS_EPMPS_Pos)
28388#define USBD_EPTXCNT_TXCNT_Pos (0)
28389#define USBD_EPTXCNT_TXCNT_Msk (0x7fful << USBD_EPTXCNT_TXCNT_Pos)
28391#define USBD_EPCFG_EPEN_Pos (0)
28392#define USBD_EPCFG_EPEN_Msk (0x1ul << USBD_EPCFG_EPEN_Pos)
28394#define USBD_EPCFG_EPTYPE_Pos (1)
28395#define USBD_EPCFG_EPTYPE_Msk (0x3ul << USBD_EPCFG_EPTYPE_Pos)
28397#define USBD_EPCFG_EPDIR_Pos (3)
28398#define USBD_EPCFG_EPDIR_Msk (0x1ul << USBD_EPCFG_EPDIR_Pos)
28400#define USBD_EPCFG_EPNUM_Pos (4)
28401#define USBD_EPCFG_EPNUM_Msk (0xful << USBD_EPCFG_EPNUM_Pos)
28403#define USBD_EPBUFSTART_SADDR_Pos (0)
28404#define USBD_EPBUFSTART_SADDR_Msk (0xffful << USBD_EPBUFSTART_SADDR_Pos)
28406#define USBD_EPBUFEND_EADDR_Pos (0)
28407#define USBD_EPBUFEND_EADDR_Msk (0xffful << USBD_EPBUFEND_EADDR_Pos)
28409#define USBD_DMAADDR_DMAADDR_Pos (0)
28410#define USBD_DMAADDR_DMAADDR_Msk (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos)
28412#define USBD_PHYCTL_DPPUEN_Pos (8)
28413#define USBD_PHYCTL_DPPUEN_Msk (0x1ul << USBD_PHYCTL_DPPUEN_Pos)
28415#define USBD_PHYCTL_PHYEN_Pos (9)
28416#define USBD_PHYCTL_PHYEN_Msk (0x1ul << USBD_PHYCTL_PHYEN_Pos)
28418#define USBD_PHYCTL_WKEN_Pos (24)
28419#define USBD_PHYCTL_WKEN_Msk (0x1ul << USBD_PHYCTL_WKEN_Pos)
28421#define USBD_PHYCTL_VBUSDET_Pos (31)
28422#define USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) /* USBD_CONST */ /* end of USBD register group */
28426
28427
28428/*---------------------- Watch Dog Timer Controller -------------------------*/
28434 typedef struct {
28435
28436
28496 __IO uint32_t CTL;
28497
28514 __IO uint32_t ALTCTL;
28515
28516} WDT_T;
28517
28523#define WDT_CTL_RSTCNT_Pos (0)
28524#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)
28526#define WDT_CTL_RSTEN_Pos (1)
28527#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)
28529#define WDT_CTL_RSTF_Pos (2)
28530#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos)
28532#define WDT_CTL_IF_Pos (3)
28533#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos)
28535#define WDT_CTL_WKEN_Pos (4)
28536#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)
28538#define WDT_CTL_WKF_Pos (5)
28539#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos)
28541#define WDT_CTL_INTEN_Pos (6)
28542#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos)
28544#define WDT_CTL_WDTEN_Pos (7)
28545#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)
28547#define WDT_CTL_TOUTSEL_Pos (8)
28548#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos)
28550#define WDT_CTL_ICEDEBUG_Pos (31)
28551#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos)
28553#define WDT_ALTCTL_RSTDSEL_Pos (0)
28554#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /* WDT_CONST */ /* end of WDT register group */
28558
28559
28560/*---------------------- Window Watchdog Timer -------------------------*/
28566 typedef struct {
28567
28568
28581 __O uint32_t RLDCNT;
28582
28625 __IO uint32_t CTL;
28626
28645 __IO uint32_t STATUS;
28646
28657 __I uint32_t CNT;
28658
28659} WWDT_T;
28660
28666#define WWDT_RLDCNT_RLDCNT_Pos (0)
28667#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)
28669#define WWDT_CTL_WWDTEN_Pos (0)
28670#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos)
28672#define WWDT_CTL_INTEN_Pos (1)
28673#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos)
28675#define WWDT_CTL_PSCSEL_Pos (8)
28676#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos)
28678#define WWDT_CTL_CMPDAT_Pos (16)
28679#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos)
28681#define WWDT_CTL_ICEDEBUG_Pos (31)
28682#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos)
28684#define WWDT_STATUS_WWDTIF_Pos (0)
28685#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos)
28687#define WWDT_STATUS_WWDTRF_Pos (1)
28688#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos)
28690#define WWDT_CNT_CNTDAT_Pos (0)
28691#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /* WWDT_CONST */ /* end of WWDT register group */
28695
28696#if defined ( __CC_ARM )
28697#pragma no_anon_unions
28698#endif
28699
28700 /* end of group NUC472_442_Peripherals */
28702
28707/* Peripheral and SRAM base address */
28708#define FLASH_BASE ((uint32_t)0x00000000)
28709#define SRAM_BASE ((uint32_t)0x20000000)
28710#define PERIPH_BASE ((uint32_t)0x40000000)
28711#define AHBPERIPH_BASE PERIPH_BASE
28712#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
28715#define SYS_BASE (AHBPERIPH_BASE + 0x00000)
28716#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
28717#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
28718#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
28719#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
28720#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
28721#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
28722#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
28723#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180)
28724#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0)
28725#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200)
28726#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
28727#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
28728#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
28729#define USBH_BASE (AHBPERIPH_BASE + 0x09000)
28730#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000)
28731#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
28732#define SD_BASE (AHBPERIPH_BASE + 0x0D000)
28733#define EBI_BASE (AHBPERIPH_BASE + 0x10000)
28734#define UDC20_BASE (AHBPERIPH_BASE + 0x19000)
28735#define CAP_BASE (AHBPERIPH_BASE + 0x30000)
28736#define CRC_BASE (AHBPERIPH_BASE + 0x31000)
28737
28739#define WDT_BASE (APBPERIPH_BASE + 0x00000)
28740#define WWDT_BASE (APBPERIPH_BASE + 0x00100)
28741#define OPA_BASE (APBPERIPH_BASE + 0x06000)
28742#define I2S0_BASE (APBPERIPH_BASE + 0x08000)
28743#define TIMER0_BASE (APBPERIPH_BASE + 0x10000)
28744#define TIMER1_BASE (APBPERIPH_BASE + 0x10020)
28745#define PWM0_BASE (APBPERIPH_BASE + 0x18000)
28746#define EPWM0_BASE (APBPERIPH_BASE + 0x1C000)
28747#define SPI0_BASE (APBPERIPH_BASE + 0x20000)
28748#define SPI2_BASE (APBPERIPH_BASE + 0x22000)
28749#define UART0_BASE (APBPERIPH_BASE + 0x30000)
28750#define UART2_BASE (APBPERIPH_BASE + 0x32000)
28751#define UART4_BASE (APBPERIPH_BASE + 0x34000)
28752#define I2C0_BASE (APBPERIPH_BASE + 0x40000)
28753#define I2C2_BASE (APBPERIPH_BASE + 0x42000)
28754#define I2C4_BASE (APBPERIPH_BASE + 0x44000)
28755#define SC0_BASE (APBPERIPH_BASE + 0x50000)
28756#define SC2_BASE (APBPERIPH_BASE + 0x52000)
28757#define SC4_BASE (APBPERIPH_BASE + 0x54000)
28758#define CAN0_BASE (APBPERIPH_BASE + 0x60000)
28759#define QEI0_BASE (APBPERIPH_BASE + 0x70000)
28760#define ECAP0_BASE (APBPERIPH_BASE + 0x74000)
28761#define PS2D_BASE (APBPERIPH_BASE + 0xA0000)
28762
28764#define RTC_BASE (APBPERIPH_BASE + 0x01000)
28765#define ADC_BASE (APBPERIPH_BASE + 0x03000)
28766#define EADC_BASE (APBPERIPH_BASE + 0x04000)
28767#define ACMP_BASE (APBPERIPH_BASE + 0x05000)
28768#define I2S1_BASE (APBPERIPH_BASE + 0x09000)
28769#define OTG_BASE (APBPERIPH_BASE + 0x0D000)
28770#define TIMER2_BASE (APBPERIPH_BASE + 0x11000)
28771#define TIMER3_BASE (APBPERIPH_BASE + 0x11020)
28772#define PWM1_BASE (APBPERIPH_BASE + 0x19000)
28773#define EPWM1_BASE (APBPERIPH_BASE + 0x1D000)
28774#define SPI1_BASE (APBPERIPH_BASE + 0x21000)
28775#define SPI3_BASE (APBPERIPH_BASE + 0x23000)
28776#define UART1_BASE (APBPERIPH_BASE + 0x31000)
28777#define UART3_BASE (APBPERIPH_BASE + 0x33000)
28778#define UART5_BASE (APBPERIPH_BASE + 0x35000)
28779#define I2C1_BASE (APBPERIPH_BASE + 0x41000)
28780#define I2C3_BASE (APBPERIPH_BASE + 0x43000)
28781#define SC1_BASE (APBPERIPH_BASE + 0x51000)
28782#define SC3_BASE (APBPERIPH_BASE + 0x53000)
28783#define SC5_BASE (APBPERIPH_BASE + 0x55000)
28784#define CAN1_BASE (APBPERIPH_BASE + 0x61000)
28785#define QEI1_BASE (APBPERIPH_BASE + 0x71000)
28786#define ECAP1_BASE (APBPERIPH_BASE + 0x75000)
28787#define CRPT_BASE (0x50080000UL)
28788 /* end of group NUC472_442_PERIPHERAL_MEM_MAP */
28790
28791
28797#define SYS ((SYS_T *) SYS_BASE)
28798#define CLK ((CLK_T *) CLK_BASE)
28799#define PA ((GPIO_T *) GPIOA_BASE)
28800#define PB ((GPIO_T *) GPIOB_BASE)
28801#define PC ((GPIO_T *) GPIOC_BASE)
28802#define PD ((GPIO_T *) GPIOD_BASE)
28803#define PE ((GPIO_T *) GPIOE_BASE)
28804#define PF ((GPIO_T *) GPIOF_BASE)
28805#define PG ((GPIO_T *) GPIOG_BASE)
28806#define PH ((GPIO_T *) GPIOH_BASE)
28807#define GPA ((GPIO_T *) GPIOA_BASE)
28808#define GPB ((GPIO_T *) GPIOB_BASE)
28809#define GPC ((GPIO_T *) GPIOC_BASE)
28810#define GPD ((GPIO_T *) GPIOD_BASE)
28811#define GPE ((GPIO_T *) GPIOE_BASE)
28812#define GPF ((GPIO_T *) GPIOF_BASE)
28813#define GPG ((GPIO_T *) GPIOG_BASE)
28814#define GPH ((GPIO_T *) GPIOH_BASE)
28815#define GPI ((GPIO_T *) GPIOI_BASE)
28816#define GPIO ((GPIO_DB_T *) GPIO_DBCTL_BASE)
28817#define PDMA ((PDMA_T *) PDMA_BASE)
28818#define USBH ((USBH_T *) USBH_BASE)
28819#define EMAC ((EMAC_T *) EMAC_BASE)
28820#define FMC ((FMC_T *) FMC_BASE)
28821#define SD ((SDH_T *) SD_BASE)
28822#define EBI ((EBI_T *) EBI_BASE)
28823#define ICAP ((CAP_T *) CAP_BASE)
28824#define CRC ((CRC_T *) CRC_BASE)
28825
28826#define WDT ((WDT_T *) WDT_BASE)
28827#define WWDT ((WWDT_T *) WWDT_BASE)
28828#define RTC ((RTC_T *) RTC_BASE)
28829#define ADC ((ADC_T *) ADC_BASE)
28830#define EADC ((EADC_T *) EADC_BASE)
28831#define ACMP ((ACMP_T *) ACMP_BASE)
28832
28833#define I2S0 ((I2S_T *) I2S0_BASE)
28834#define I2S1 ((I2S_T *) I2S1_BASE)
28835#define USBD ((USBD_T *) UDC20_BASE)
28836#define OTG ((OTG_T *) OTG_BASE)
28837#define TIMER0 ((TIMER_T *) TIMER0_BASE)
28838#define TIMER1 ((TIMER_T *) TIMER1_BASE)
28839#define TIMER2 ((TIMER_T *) TIMER2_BASE)
28840#define TIMER3 ((TIMER_T *) TIMER3_BASE)
28841#define PWM0 ((PWM_T *) PWM0_BASE)
28842#define PWM1 ((PWM_T *) PWM1_BASE)
28843#define EPWM0 ((EPWM_T *) EPWM0_BASE)
28844#define EPWM1 ((EPWM_T *) EPWM1_BASE)
28845#define ECAP0 ((ECAP_T *) ECAP0_BASE)
28846#define ECAP1 ((ECAP_T *) ECAP1_BASE)
28847#define QEI0 ((QEI_T *) QEI0_BASE)
28848#define QEI1 ((QEI_T *) QEI1_BASE)
28849#define SPI0 ((SPI_T *) SPI0_BASE)
28850#define SPI1 ((SPI_T *) SPI1_BASE)
28851#define SPI2 ((SPI_T *) SPI2_BASE)
28852#define SPI3 ((SPI_T *) SPI3_BASE)
28853#define UART0 ((UART_T *) UART0_BASE)
28854#define UART1 ((UART_T *) UART1_BASE)
28855#define UART2 ((UART_T *) UART2_BASE)
28856#define UART3 ((UART_T *) UART3_BASE)
28857#define UART4 ((UART_T *) UART4_BASE)
28858#define UART5 ((UART_T *) UART5_BASE)
28859#define I2C0 ((I2C_T *) I2C0_BASE)
28860#define I2C1 ((I2C_T *) I2C1_BASE)
28861#define I2C2 ((I2C_T *) I2C2_BASE)
28862#define I2C3 ((I2C_T *) I2C3_BASE)
28863#define I2C4 ((I2C_T *) I2C4_BASE)
28864#define SC0 ((SC_T *) SC0_BASE)
28865#define SC1 ((SC_T *) SC1_BASE)
28866#define SC2 ((SC_T *) SC2_BASE)
28867#define SC3 ((SC_T *) SC3_BASE)
28868#define SC4 ((SC_T *) SC4_BASE)
28869#define SC5 ((SC_T *) SC5_BASE)
28870#define CAN0 ((CAN_T *) CAN0_BASE)
28871#define CAN1 ((CAN_T *) CAN1_BASE)
28872#define PS2 ((PS2_T *) PS2D_BASE)
28873#define CRPT ((CRPT_T *) CRPT_BASE) /* end of group NUC472_442_PERIPHERAL_DECLARATION */
28875
28881 typedef volatile unsigned char vu8;
28882 typedef volatile unsigned short vu16;
28883 typedef volatile unsigned long vu32;
28884
28890#define M8(addr) (*((vu8 *) (addr)))
28891
28898#define M16(addr) (*((vu16 *) (addr)))
28899
28906#define M32(addr) (*((vu32 *) (addr)))
28907
28915#define outpw(port,value) *((volatile unsigned int *)(port)) = value
28916
28923#define inpw(port) (*((volatile unsigned int *)(port)))
28924
28932#define outps(port,value) *((volatile unsigned short *)(port)) = value
28933
28940#define inps(port) (*((volatile unsigned short *)(port)))
28941
28948#define outpb(port,value) *((volatile unsigned char *)(port)) = value
28949
28955#define inpb(port) (*((volatile unsigned char *)(port)))
28956
28964#define outp32(port,value) *((volatile unsigned int *)(port)) = value
28965
28972#define inp32(port) (*((volatile unsigned int *)(port)))
28973
28981#define outp16(port,value) *((volatile unsigned short *)(port)) = value
28982
28989#define inp16(port) (*((volatile unsigned short *)(port)))
28990
28997#define outp8(port,value) *((volatile unsigned char *)(port)) = value
28998
29004#define inp8(port) (*((volatile unsigned char *)(port)))
29005
29006 /* end of group NUC472_442_IO_ROUTINE */
29008
29009/******************************************************************************/
29010/* Legacy Constants */
29011/******************************************************************************/
29017#ifndef NULL
29018#define NULL (0)
29019#endif
29020
29021#define TRUE (1)
29022#define FALSE (0)
29023
29024#define ENABLE (1)
29025#define DISABLE (0)
29026
29027/* Define one bit mask */
29028#define BIT0 (0x00000001)
29029#define BIT1 (0x00000002)
29030#define BIT2 (0x00000004)
29031#define BIT3 (0x00000008)
29032#define BIT4 (0x00000010)
29033#define BIT5 (0x00000020)
29034#define BIT6 (0x00000040)
29035#define BIT7 (0x00000080)
29036#define BIT8 (0x00000100)
29037#define BIT9 (0x00000200)
29038#define BIT10 (0x00000400)
29039#define BIT11 (0x00000800)
29040#define BIT12 (0x00001000)
29041#define BIT13 (0x00002000)
29042#define BIT14 (0x00004000)
29043#define BIT15 (0x00008000)
29044#define BIT16 (0x00010000)
29045#define BIT17 (0x00020000)
29046#define BIT18 (0x00040000)
29047#define BIT19 (0x00080000)
29048#define BIT20 (0x00100000)
29049#define BIT21 (0x00200000)
29050#define BIT22 (0x00400000)
29051#define BIT23 (0x00800000)
29052#define BIT24 (0x01000000)
29053#define BIT25 (0x02000000)
29054#define BIT26 (0x04000000)
29055#define BIT27 (0x08000000)
29056#define BIT28 (0x10000000)
29057#define BIT29 (0x20000000)
29058#define BIT30 (0x40000000)
29059#define BIT31 (0x80000000)
29060
29061/* Byte Mask Definitions */
29062#define BYTE0_Msk (0x000000FF)
29063#define BYTE1_Msk (0x0000FF00)
29064#define BYTE2_Msk (0x00FF0000)
29065#define BYTE3_Msk (0xFF000000)
29066
29067#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
29068#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
29069#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
29070#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /* end of group NUC472_442_legacy_Constants */
29073
29074
29075/******************************************************************************/
29076/* Peripheral header files */
29077/******************************************************************************/
29078#include "sys.h"
29079#include "clk.h"
29080
29081#include "acmp.h"
29082#include "adc.h"
29083#include "eadc.h"
29084#include "cap.h"
29085#include "crypto.h"
29086#include "pdma.h"
29087#include "ebi.h"
29088#include "emac.h"
29089#include "fmc.h"
29090#include "gpio.h"
29091#include "i2c.h"
29092#include "pwm.h"
29093#include "epwm.h"
29094#include "rtc.h"
29095#include "sc.h"
29096#include "scuart.h"
29097#include "spi.h"
29098#include "timer.h"
29099#include "uart.h"
29100#include "usbd.h"
29101#include "wdt.h"
29102#include "wwdt.h"
29103#include "i2s.h"
29104#include "can.h"
29105#include "sd.h"
29106#include "ps2.h"
29107#include "crc.h"
29108
29109#ifdef __cplusplus
29110}
29111#endif
29112
29113#endif /* __NUC472_442_H__ */
29114
29115/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
29116
acmp.h
NUC472/NUC442 Analog Comparator(ACMP) driver header file.
adc.h
NUC472/NUC442 ADC driver header file.
can.h
NUC472/NUC442 CAN driver header file.
cap.h
NUC470 series Image Capture Driver Header File.
clk.h
NUC472/NUC442 CLK Header File.
crc.h
NUC472/NUC442 series CRC driver header file.
crypto.h
Cryptographic Accelerator driver header file.
eadc.h
NUC472/NUC442 EADC driver header file.
ebi.h
NUC472/NUC442 EBI driver header file.
emac.h
NUC472/NUC442 EMAC driver header file.
epwm.h
NUC472/NUC442 EPWM driver header file.
fmc.h
NUC472/NUC442 Flash Memory Controller Driver Header File.
gpio.h
NUC472/NUC442 GPIO driver header file.
IRQn_Type
enum IRQn IRQn_Type
IRQn
IRQn
Definition: NUC472_442.h:71
PWM0CH3_IRQn
@ PWM0CH3_IRQn
Definition: NUC472_442.h:128
PendSV_IRQn
@ PendSV_IRQn
Definition: NUC472_442.h:79
EINT0_IRQn
@ EINT0_IRQn
Definition: NUC472_442.h:91
GPF_IRQn
@ GPF_IRQn
Definition: NUC472_442.h:104
USBH_IRQn
@ USBH_IRQn
Definition: NUC472_442.h:146
EINT6_IRQn
@ EINT6_IRQn
Definition: NUC472_442.h:97
PWM1CH2_IRQn
@ PWM1CH2_IRQn
Definition: NUC472_442.h:135
I2C2_IRQn
@ I2C2_IRQn
Definition: NUC472_442.h:162
I2C0_IRQn
@ I2C0_IRQn
Definition: NUC472_442.h:160
UART3_IRQn
@ UART3_IRQn
Definition: NUC472_442.h:157
GPI_IRQn
@ GPI_IRQn
Definition: NUC472_442.h:107
EINT3_IRQn
@ EINT3_IRQn
Definition: NUC472_442.h:94
EINT4_IRQn
@ EINT4_IRQn
Definition: NUC472_442.h:95
PS2D_IRQn
@ PS2D_IRQn
Definition: NUC472_442.h:176
GPA_IRQn
@ GPA_IRQn
Definition: NUC472_442.h:99
CLKF_IRQn
@ CLKF_IRQn
Definition: NUC472_442.h:88
I2C4_IRQn
@ I2C4_IRQn
Definition: NUC472_442.h:164
CAN0_IRQn
@ CAN0_IRQn
Definition: NUC472_442.h:171
EADC2_IRQn
@ EADC2_IRQn
Definition: NUC472_442.h:118
TAMPER_IRQn
@ TAMPER_IRQn
Definition: NUC472_442.h:90
GPG_IRQn
@ GPG_IRQn
Definition: NUC472_442.h:105
OPA1_IRQn
@ OPA1_IRQn
Definition: NUC472_442.h:122
SC0_IRQn
@ SC0_IRQn
Definition: NUC472_442.h:165
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: NUC472_442.h:74
EADC0_IRQn
@ EADC0_IRQn
Definition: NUC472_442.h:116
USBD_IRQn
@ USBD_IRQn
Definition: NUC472_442.h:145
SD_IRQn
@ SD_IRQn
Definition: NUC472_442.h:175
EINT2_IRQn
@ EINT2_IRQn
Definition: NUC472_442.h:93
PWRWU_IRQn
@ PWRWU_IRQn
Definition: NUC472_442.h:86
PWM0CH1_IRQn
@ PWM0CH1_IRQn
Definition: NUC472_442.h:126
SVCall_IRQn
@ SVCall_IRQn
Definition: NUC472_442.h:77
PWM0CH2_IRQn
@ PWM0CH2_IRQn
Definition: NUC472_442.h:127
ADC_IRQn
@ ADC_IRQn
Definition: NUC472_442.h:113
SPI3_IRQn
@ SPI3_IRQn
Definition: NUC472_442.h:153
SPI2_IRQn
@ SPI2_IRQn
Definition: NUC472_442.h:152
EINT5_IRQn
@ EINT5_IRQn
Definition: NUC472_442.h:96
PWM0CH0_IRQn
@ PWM0CH0_IRQn
Definition: NUC472_442.h:125
EINT7_IRQn
@ EINT7_IRQn
Definition: NUC472_442.h:98
ICAP0_IRQn
@ ICAP0_IRQn
Definition: NUC472_442.h:123
OPA0_IRQn
@ OPA0_IRQn
Definition: NUC472_442.h:121
EADC1_IRQn
@ EADC1_IRQn
Definition: NUC472_442.h:117
UsageFault_IRQn
@ UsageFault_IRQn
Definition: NUC472_442.h:76
GPC_IRQn
@ GPC_IRQn
Definition: NUC472_442.h:101
CAP_IRQn
@ CAP_IRQn
Definition: NUC472_442.h:177
SysTick_IRQn
@ SysTick_IRQn
Definition: NUC472_442.h:80
GPH_IRQn
@ GPH_IRQn
Definition: NUC472_442.h:106
EPWM0BRK_IRQn
@ EPWM0BRK_IRQn
Definition: NUC472_442.h:142
ACMP_IRQn
@ ACMP_IRQn
Definition: NUC472_442.h:120
PWM1CH3_IRQn
@ PWM1CH3_IRQn
Definition: NUC472_442.h:136
GPD_IRQn
@ GPD_IRQn
Definition: NUC472_442.h:102
EMAC_TX_IRQn
@ EMAC_TX_IRQn
Definition: NUC472_442.h:148
PWM1CH5_IRQn
@ PWM1CH5_IRQn
Definition: NUC472_442.h:138
WDT_IRQn
@ WDT_IRQn
Definition: NUC472_442.h:114
EPWM0_IRQn
@ EPWM0_IRQn
Definition: NUC472_442.h:141
PDMA_IRQn
@ PDMA_IRQn
Definition: NUC472_442.h:112
CAN1_IRQn
@ CAN1_IRQn
Definition: NUC472_442.h:172
TMR1_IRQn
@ TMR1_IRQn
Definition: NUC472_442.h:109
BusFault_IRQn
@ BusFault_IRQn
Definition: NUC472_442.h:75
WWDT_IRQn
@ WWDT_IRQn
Definition: NUC472_442.h:115
EMAC_RX_IRQn
@ EMAC_RX_IRQn
Definition: NUC472_442.h:149
CRC_IRQn
@ CRC_IRQn
Definition: NUC472_442.h:179
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: NUC472_442.h:78
TMR2_IRQn
@ TMR2_IRQn
Definition: NUC472_442.h:110
SC3_IRQn
@ SC3_IRQn
Definition: NUC472_442.h:168
UART1_IRQn
@ UART1_IRQn
Definition: NUC472_442.h:155
SC5_IRQn
@ SC5_IRQn
Definition: NUC472_442.h:170
QEI1_IRQn
@ QEI1_IRQn
Definition: NUC472_442.h:140
IRC_IRQn
@ IRC_IRQn
Definition: NUC472_442.h:85
I2S0_IRQn
@ I2S0_IRQn
Definition: NUC472_442.h:173
PWM1BRK_IRQn
@ PWM1BRK_IRQn
Definition: NUC472_442.h:139
CRPT_IRQn
@ CRPT_IRQn
Definition: NUC472_442.h:178
EPWM1BRK_IRQn
@ EPWM1BRK_IRQn
Definition: NUC472_442.h:144
EADC3_IRQn
@ EADC3_IRQn
Definition: NUC472_442.h:119
SPI1_IRQn
@ SPI1_IRQn
Definition: NUC472_442.h:151
USB_OTG_IRQn
@ USB_OTG_IRQn
Definition: NUC472_442.h:147
UART2_IRQn
@ UART2_IRQn
Definition: NUC472_442.h:156
EPWM1_IRQn
@ EPWM1_IRQn
Definition: NUC472_442.h:143
I2C3_IRQn
@ I2C3_IRQn
Definition: NUC472_442.h:163
TMR0_IRQn
@ TMR0_IRQn
Definition: NUC472_442.h:108
PWM0CH4_IRQn
@ PWM0CH4_IRQn
Definition: NUC472_442.h:129
BOD_IRQn
@ BOD_IRQn
Definition: NUC472_442.h:84
UART5_IRQn
@ UART5_IRQn
Definition: NUC472_442.h:159
PWM1CH0_IRQn
@ PWM1CH0_IRQn
Definition: NUC472_442.h:133
PWM1CH1_IRQn
@ PWM1CH1_IRQn
Definition: NUC472_442.h:134
EINT1_IRQn
@ EINT1_IRQn
Definition: NUC472_442.h:92
SC4_IRQn
@ SC4_IRQn
Definition: NUC472_442.h:169
PWM0_BRK_IRQn
@ PWM0_BRK_IRQn
Definition: NUC472_442.h:131
RTC_IRQn
@ RTC_IRQn
Definition: NUC472_442.h:89
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: NUC472_442.h:73
UART4_IRQn
@ UART4_IRQn
Definition: NUC472_442.h:158
TMR3_IRQn
@ TMR3_IRQn
Definition: NUC472_442.h:111
SC1_IRQn
@ SC1_IRQn
Definition: NUC472_442.h:166
I2S1_IRQn
@ I2S1_IRQn
Definition: NUC472_442.h:174
QEI0_IRQn
@ QEI0_IRQn
Definition: NUC472_442.h:132
UART0_IRQn
@ UART0_IRQn
Definition: NUC472_442.h:154
ICAP1_IRQn
@ ICAP1_IRQn
Definition: NUC472_442.h:124
SRAMF_IRQn
@ SRAMF_IRQn
Definition: NUC472_442.h:87
GPE_IRQn
@ GPE_IRQn
Definition: NUC472_442.h:103
SC2_IRQn
@ SC2_IRQn
Definition: NUC472_442.h:167
I2C1_IRQn
@ I2C1_IRQn
Definition: NUC472_442.h:161
GPB_IRQn
@ GPB_IRQn
Definition: NUC472_442.h:100
SPI0_IRQn
@ SPI0_IRQn
Definition: NUC472_442.h:150
PWM1CH4_IRQn
@ PWM1CH4_IRQn
Definition: NUC472_442.h:137
PWM0CH5_IRQn
@ PWM0CH5_IRQn
Definition: NUC472_442.h:130
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: NUC472_442.h:28883
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: NUC472_442.h:28882
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: NUC472_442.h:28881
CLK_T::PLLCTL
__IO uint32_t PLLCTL
Definition: NUC472_442.h:3418
PWM_T::RCAPDAT5
__I uint32_t RCAPDAT5
Definition: NUC472_442.h:19711
SYS_T::IRCTIEN
__IO uint32_t IRCTIEN
Definition: NUC472_442.h:24114
SDH_T::GINTSTS
__I uint32_t GINTSTS
Definition: NUC472_442.h:22221
EADC_T::AD0DAT2
__I uint32_t AD0DAT2
Definition: NUC472_442.h:7481
SC_T::TMRCTL2
__IO uint32_t TMRCTL2
Definition: NUC472_442.h:21684
CAP_T::CWSP
__IO uint32_t CWSP
Definition: NUC472_442.h:1891
SYS_T::GPC_MFPL
__IO uint32_t GPC_MFPL
Definition: NUC472_442.h:23764
EMAC_T::CAM10L
__IO uint32_t CAM10L
Definition: NUC472_442.h:12178
SPI_T::RX
__I uint32_t RX
Definition: NUC472_442.h:23058
CAN_T::NDAT1
__IO uint32_t NDAT1
Definition: NUC472_442.h:1340
UART_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:25242
CRPT_T::TDES0_IVL
__IO uint32_t TDES0_IVL
Definition: NUC472_442.h:5889
FMC_T::ISPCTL
__IO uint32_t ISPCTL
Definition: NUC472_442.h:14628
CRPT_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:4201
CRPT_T::AES2_IV3
__IO uint32_t AES2_IV3
Definition: NUC472_442.h:5329
SPI_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:22774
USBD_EP_T::EPBUFEND
__IO uint32_t EPBUFEND
Definition: NUC472_442.h:27252
RTC_T::TAMP1PCTL
__IO uint32_t TAMP1PCTL
Definition: NUC472_442.h:20763
CRPT_T::TDES2_CNT
__IO uint32_t TDES2_CNT
Definition: NUC472_442.h:6341
PDMA_T::TRGSTS
__I uint32_t TRGSTS
Definition: NUC472_442.h:18302
I2C_T::ADDR3
__IO uint32_t ADDR3
Definition: NUC472_442.h:16983
ECAP_T::HOLD0
__IO uint32_t HOLD0
Definition: NUC472_442.h:2449
CRC_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:4034
PWM_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:19141
CRPT_T::TDES3_KEY3H
__IO uint32_t TDES3_KEY3H
Definition: NUC472_442.h:6420
CRPT_T::SHA_DGST4
__I uint32_t SHA_DGST4
Definition: NUC472_442.h:6656
UART_T::LINDEBUG
__IO uint32_t LINDEBUG
Definition: NUC472_442.h:25798
CRPT_T::AES0_IV1
__IO uint32_t AES0_IV1
Definition: NUC472_442.h:4761
USBD_T::BUSINTSTS
__IO uint32_t BUSINTSTS
Definition: NUC472_442.h:27448
CRPT_T::AES3_IV2
__IO uint32_t AES3_IV2
Definition: NUC472_442.h:5583
USBH_T::HcControl
__IO uint32_t HcControl
Definition: NUC472_442.h:26200
I2C_T::ADDR0
__IO uint32_t ADDR0
Definition: NUC472_442.h:16870
UART_T::BAUD
__IO uint32_t BAUD
Definition: NUC472_442.h:25573
PS2_T::TXDAT3
__IO uint32_t TXDAT3
Definition: NUC472_442.h:18847
EMAC_T::ALMSEC
__IO uint32_t ALMSEC
Definition: NUC472_442.h:13233
EMAC_T::TXDSA
__IO uint32_t TXDSA
Definition: NUC472_442.h:12357
PDMA_T::ABTSTS
__IO uint32_t ABTSTS
Definition: NUC472_442.h:18387
EADC_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:7793
UART_T::IRDA
__IO uint32_t IRDA
Definition: NUC472_442.h:25593
USBH_T::HcInterruptStatus
__IO uint32_t HcInterruptStatus
Definition: NUC472_442.h:26246
PDMA_T::PRISET
__IO uint32_t PRISET
Definition: NUC472_442.h:18317
RTC_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:20594
I2S_T::IEN
__IO uint32_t IEN
Definition: NUC472_442.h:17345
CRPT_T::AES1_KEY7
__IO uint32_t AES1_KEY7
Definition: NUC472_442.h:5000
SYS_T::GPD_MFPH
__IO uint32_t GPD_MFPH
Definition: NUC472_442.h:23818
CRPT_T::TDES0_KEY3L
__IO uint32_t TDES0_KEY3L
Definition: NUC472_442.h:5863
CRPT_T::AES0_IV3
__IO uint32_t AES0_IV3
Definition: NUC472_442.h:4791
CRPT_T::TDES0_IVH
__IO uint32_t TDES0_IVH
Definition: NUC472_442.h:5876
CRPT_T::AES3_DADDR
__IO uint32_t AES3_DADDR
Definition: NUC472_442.h:5642
EPWM_T::ASYMCTL
__IO uint32_t ASYMCTL
Definition: NUC472_442.h:14328
EMAC_T::TSINC
__IO uint32_t TSINC
Definition: NUC472_442.h:13177
CRPT_T::SHA_KEYCNT
__IO uint32_t SHA_KEYCNT
Definition: NUC472_442.h:6719
CRPT_T::SHA_DGST7
__I uint32_t SHA_DGST7
Definition: NUC472_442.h:6698
I2C_T::DAT
__IO uint32_t DAT
Definition: NUC472_442.h:16882
CRPT_T::AES3_KEY0
__IO uint32_t AES3_KEY0
Definition: NUC472_442.h:5412
EMAC_T::CAM3L
__IO uint32_t CAM3L
Definition: NUC472_442.h:11940
CLK_T::CLKDIV1
__IO uint32_t CLKDIV1
Definition: NUC472_442.h:3352
USBD_EP_T::EPDAT
__IO uint32_t EPDAT
Definition: NUC472_442.h:26967
EMAC_T::FRSTS
__IO uint32_t FRSTS
Definition: NUC472_442.h:13045
DSCT_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:18180
CRPT_T::AES2_IV2
__IO uint32_t AES2_IV2
Definition: NUC472_442.h:5314
CAP_T::POSTERIZE
__IO uint32_t POSTERIZE
Definition: NUC472_442.h:1820
USBH_T::HcCommandStatus
__IO uint32_t HcCommandStatus
Definition: NUC472_442.h:26222
GPIO_T::SMTEN
__IO uint32_t SMTEN
Definition: NUC472_442.h:16135
EMAC_T::CAM5M
__IO uint32_t CAM5M
Definition: NUC472_442.h:11992
CRPT_T::AES0_DADDR
__IO uint32_t AES0_DADDR
Definition: NUC472_442.h:4835
USBD_T::SETUP1_0
__I uint32_t SETUP1_0
Definition: NUC472_442.h:27816
CRPT_T::TDES0_KEY1L
__IO uint32_t TDES0_KEY1L
Definition: NUC472_442.h:5803
CAP_T::PKTBA1
__IO uint32_t PKTBA1
Definition: NUC472_442.h:2132
ECAP_T::CNTCMP
__IO uint32_t CNTCMP
Definition: NUC472_442.h:2488
PWM_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:19460
CRPT_T::TDES0_CNT
__IO uint32_t TDES0_CNT
Definition: NUC472_442.h:5951
CRPT_T::TDES0_SADDR
__IO uint32_t TDES0_SADDR
Definition: NUC472_442.h:5911
GPIO_T::DATMSK
__IO uint32_t DATMSK
Definition: NUC472_442.h:15435
EMAC_T::CAM1M
__IO uint32_t CAM1M
Definition: NUC472_442.h:11856
CRPT_T::AES2_KEY2
__IO uint32_t AES2_KEY2
Definition: NUC472_442.h:5179
RTC_T::FREQADJ
__IO uint32_t FREQADJ
Definition: NUC472_442.h:20450
TIMER_T::EINTSTS
__IO uint32_t EINTSTS
Definition: NUC472_442.h:25075
SDH_T::RESP0
__I uint32_t RESP0
Definition: NUC472_442.h:22450
CRPT_T::AES3_IV0
__IO uint32_t AES3_IV0
Definition: NUC472_442.h:5553
CLK_T::PLL2CTL
__IO uint32_t PLL2CTL
Definition: NUC472_442.h:3435
CAN_T::TXREQ1
__IO uint32_t TXREQ1
Definition: NUC472_442.h:1311
SDH_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:22437
EMAC_T::CAM9M
__IO uint32_t CAM9M
Definition: NUC472_442.h:12128
UART_T::DAT
__IO uint32_t DAT
Definition: NUC472_442.h:25188
USBH_T::HcBulkCurrentED
__IO uint32_t HcBulkCurrentED
Definition: NUC472_442.h:26383
SYS_T::SRAM0_ERRADDR
__I uint32_t SRAM0_ERRADDR
Definition: NUC472_442.h:24042
CRPT_T::AES3_CNT
__IO uint32_t AES3_CNT
Definition: NUC472_442.h:5663
EADC_T::SIMUSEL
__IO uint32_t SIMUSEL
Definition: NUC472_442.h:8713
FMC_T::MPADDR
__IO uint32_t MPADDR
Definition: NUC472_442.h:14903
EMAC_T::TXST
__O uint32_t TXST
Definition: NUC472_442.h:12583
I2C_T::ADDRMSK3
__IO uint32_t ADDRMSK3
Definition: NUC472_442.h:17047
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__IO uint32_t CMP
Definition: NUC472_442.h:24971
CAP_T::STRIDE
__IO uint32_t STRIDE
Definition: NUC472_442.h:1985
CRPT_T::TDES0_KEY3H
__IO uint32_t TDES0_KEY3H
Definition: NUC472_442.h:5848
EMAC_T::CAMCTL
__IO uint32_t CAMCTL
Definition: NUC472_442.h:11788
EMAC_T::ALMSUBSEC
__IO uint32_t ALMSUBSEC
Definition: NUC472_442.h:13247
SYS_T::GPF_MFPL
__IO uint32_t GPF_MFPL
Definition: NUC472_442.h:23872
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__IO uint32_t INTEN
Definition: NUC472_442.h:15971
ECAP_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:2657
SYS_T::SRAM_INTCTL
__IO uint32_t SRAM_INTCTL
Definition: NUC472_442.h:24015
CRPT_T::AES0_IV0
__IO uint32_t AES0_IV0
Definition: NUC472_442.h:4746
CRPT_T::AES3_KEY5
__IO uint32_t AES3_KEY5
Definition: NUC472_442.h:5502
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__IO uint32_t CAM0L
Definition: NUC472_442.h:11838
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__IO uint32_t MODEMSTS
Definition: NUC472_442.h:25363
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__IO uint32_t BRKCTL
Definition: NUC472_442.h:19411
EMAC_T::GENSTS
__IO uint32_t GENSTS
Definition: NUC472_442.h:12998
CRPT_T::TDES0_KEY1H
__IO uint32_t TDES0_KEY1H
Definition: NUC472_442.h:5788
SDH_T::DMASA
__IO uint32_t DMASA
Definition: NUC472_442.h:22122
EMAC_T::CAM8L
__IO uint32_t CAM8L
Definition: NUC472_442.h:12110
PDMA_T::REQSEL0_3
__IO uint32_t REQSEL0_3
Definition: NUC472_442.h:18511
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__IO uint32_t DAT
Definition: NUC472_442.h:4047
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__IO uint32_t STATUS
Definition: NUC472_442.h:28645
GPIO_T::INTTYPE
__IO uint32_t INTTYPE
Definition: NUC472_442.h:15801
EMAC_T::RPCNT
__I uint32_t RPCNT
Definition: NUC472_442.h:13027
USBH_T::HcPeriodicStart
__IO uint32_t HcPeriodicStart
Definition: NUC472_442.h:26453
USBD_T::DMACTL
__IO uint32_t DMACTL
Definition: NUC472_442.h:27912
USBH_T::HcRhDescriptorA
__IO uint32_t HcRhDescriptorA
Definition: NUC472_442.h:26509
PWM_T::POEN
__IO uint32_t POEN
Definition: NUC472_442.h:19517
SYS_T::PORCTL
__IO uint32_t PORCTL
Definition: NUC472_442.h:23632
EADC_T::AD1TRGEN0
__IO uint32_t AD1TRGEN0
Definition: NUC472_442.h:9648
EPWM_T::MSK
__IO uint32_t MSK
Definition: NUC472_442.h:14151
SYS_T::GPH_MFPL
__IO uint32_t GPH_MFPL
Definition: NUC472_442.h:23944
I2C_T::TOCTL
__IO uint32_t TOCTL
Definition: NUC472_442.h:16932
CRPT_T::AES3_KEY3
__IO uint32_t AES3_KEY3
Definition: NUC472_442.h:5466
CLK_T::CLKSEL3
__IO uint32_t CLKSEL3
Definition: NUC472_442.h:3314
EMAC_T::RXST
__O uint32_t RXST
Definition: NUC472_442.h:12598
CRPT_T::TDES1_IVL
__IO uint32_t TDES1_IVL
Definition: NUC472_442.h:6097
FMC_T::MPDAT2
__IO uint32_t MPDAT2
Definition: NUC472_442.h:14839
USBD_T::DMACNT
__IO uint32_t DMACNT
Definition: NUC472_442.h:27924
CRPT_T::AES1_IV2
__IO uint32_t AES1_IV2
Definition: NUC472_442.h:5045
USBH_T::HcMiscControl
__IO uint32_t HcMiscControl
Definition: NUC472_442.h:26691
CRPT_T::AES1_KEY2
__IO uint32_t AES1_KEY2
Definition: NUC472_442.h:4910
EADC_T::AD1DDAT2
__I uint32_t AD1DDAT2
Definition: NUC472_442.h:9010
OPA_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:17697
EMAC_T::RXDSA
__IO uint32_t RXDSA
Definition: NUC472_442.h:12373
USBH_T::HcRhStatus
__IO uint32_t HcRhStatus
Definition: NUC472_442.h:26561
UART_T::LINE
__IO uint32_t LINE
Definition: NUC472_442.h:25321
PDMA_T::SWREQ
__O uint32_t SWREQ
Definition: NUC472_442.h:18285
FMC_T::FBWP
__IO uint32_t FBWP
Definition: NUC472_442.h:14799
SYS_T::GPC_MFPH
__IO uint32_t GPC_MFPH
Definition: NUC472_442.h:23782
EADC_T::AD0TRGEN3
__IO uint32_t AD0TRGEN3
Definition: NUC472_442.h:9542
CRPT_T::PRNG_KEY4
__I uint32_t PRNG_KEY4
Definition: NUC472_442.h:4297
RTC_T::TAMP0PCTL
__IO uint32_t TAMP0PCTL
Definition: NUC472_442.h:20738
EADC_T::AD1DAT0
__I uint32_t AD1DAT0
Definition: NUC472_442.h:7607
PWM_T::RCAPDAT4
__I uint32_t RCAPDAT4
Definition: NUC472_442.h:19687
FMC_T::MPDAT3
__IO uint32_t MPDAT3
Definition: NUC472_442.h:14851
SPI_T::TX
__O uint32_t TX
Definition: NUC472_442.h:23039
EADC_T::AD0DAT3
__I uint32_t AD0DAT3
Definition: NUC472_442.h:7502
USBD_EP_T::EPCFG
__IO uint32_t EPCFG
Definition: NUC472_442.h:27228
CRPT_T::AES0_KEY2
__IO uint32_t AES0_KEY2
Definition: NUC472_442.h:4641
CRPT_T::PRNG_KEY3
__I uint32_t PRNG_KEY3
Definition: NUC472_442.h:4285
PDMA_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:18346
PWM_T::RCAPDAT2
__I uint32_t RCAPDAT2
Definition: NUC472_442.h:19639
RTC_T::TALM
__IO uint32_t TALM
Definition: NUC472_442.h:20531
CRPT_T::TDES_FDBCKL
__I uint32_t TDES_FDBCKL
Definition: NUC472_442.h:4443
I2S_T::TX
__O uint32_t TX
Definition: NUC472_442.h:17457
SYS_T::GPE_MFPL
__IO uint32_t GPE_MFPL
Definition: NUC472_442.h:23836
FMC_T::ISPADDR
__IO uint32_t ISPADDR
Definition: NUC472_442.h:14641
SC_T::UARTCTL
__IO uint32_t UARTCTL
Definition: NUC472_442.h:21714
EMAC_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:12481
PWM_T::RCAPDAT0
__I uint32_t RCAPDAT0
Definition: NUC472_442.h:19591
EMAC_T::TSADDEND
__IO uint32_t TSADDEND
Definition: NUC472_442.h:13191
USBD_EP_T::EPINTSTS
__IO uint32_t EPINTSTS
Definition: NUC472_442.h:27050
SC_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:21479
I2C_T::CLKDIV
__IO uint32_t CLKDIV
Definition: NUC472_442.h:16910
CAP_T::PAR
__IO uint32_t PAR
Definition: NUC472_442.h:1771
SYS_T::GPG_MFPL
__IO uint32_t GPG_MFPL
Definition: NUC472_442.h:23908
SYS_T::IRCTISTS
__IO uint32_t IRCTISTS
Definition: NUC472_442.h:24141
CRPT_T::AES3_KEY4
__IO uint32_t AES3_KEY4
Definition: NUC472_442.h:5484
EMAC_T::UPDSUBSEC
__IO uint32_t UPDSUBSEC
Definition: NUC472_442.h:13219
CRPT_T::AES0_KEY4
__IO uint32_t AES0_KEY4
Definition: NUC472_442.h:4677
EBI_T::KEY2
__IO uint32_t KEY2
Definition: NUC472_442.h:11673
I2C_T::STATUS
__I uint32_t STATUS
Definition: NUC472_442.h:16897
CAP_T::YBA
__IO uint32_t YBA
Definition: NUC472_442.h:2148
EADC_T::AD0TRGEN1
__IO uint32_t AD0TRGEN1
Definition: NUC472_442.h:9330
I2S_T::RX
__I uint32_t RX
Definition: NUC472_442.h:17471
OTG_T::PHYCTL
__IO uint32_t PHYCTL
Definition: NUC472_442.h:17820
EADC_T::ADIFOV
__IO uint32_t ADIFOV
Definition: NUC472_442.h:7861
CRPT_T::AES3_SADDR
__IO uint32_t AES3_SADDR
Definition: NUC472_442.h:5620
EMAC_T::CAM4M
__IO uint32_t CAM4M
Definition: NUC472_442.h:11958
SPI_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:23019
I2C_T::WKCTL
__IO uint32_t WKCTL
Definition: NUC472_442.h:17064
USBH_T::HcPeriodCurrentED
__IO uint32_t HcPeriodCurrentED
Definition: NUC472_442.h:26335
EMAC_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:12770
USBD_T::CEPCTL
__IO uint32_t CEPCTL
Definition: NUC472_442.h:27622
EPWM_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:14036
PWM_T::MSK
__IO uint32_t MSK
Definition: NUC472_442.h:19252
CAN_IF_T::DAT_B1
__IO uint32_t DAT_B1
Definition: NUC472_442.h:1105
TIMER_T::CAP
__I uint32_t CAP
Definition: NUC472_442.h:25018
CRC_T::CHECKSUM
__I uint32_t CHECKSUM
Definition: NUC472_442.h:4071
CRPT_T::PRNG_KEY2
__I uint32_t PRNG_KEY2
Definition: NUC472_442.h:4273
EADC_T::AD1SPCTL7
__IO uint32_t AD1SPCTL7
Definition: NUC472_442.h:8667
WWDT_T::RLDCNT
__O uint32_t RLDCNT
Definition: NUC472_442.h:28581
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: NUC472_442.h:3264
CAP_T::CWS
__IO uint32_t CWS
Definition: NUC472_442.h:1903
CRPT_T::AES2_CNT
__IO uint32_t AES2_CNT
Definition: NUC472_442.h:5394
CAN_T::NDAT2
__IO uint32_t NDAT2
Definition: NUC472_442.h:1353
CRC_T::SEED
__IO uint32_t SEED
Definition: NUC472_442.h:4059
SYS_T::GPH_MFPH
__IO uint32_t GPH_MFPH
Definition: NUC472_442.h:23962
SC_T::DAT
__IO uint32_t DAT
Definition: NUC472_442.h:21131
CRPT_T::AES1_CNT
__IO uint32_t AES1_CNT
Definition: NUC472_442.h:5125
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: NUC472_442.h:14666
I2C_T::WKSTS
__IO uint32_t WKSTS
Definition: NUC472_442.h:17078
SYS_T::GPI_MFPH
__IO uint32_t GPI_MFPH
Definition: NUC472_442.h:23998
SDH_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:22291
USBH_T::HcInterruptEnable
__IO uint32_t HcInterruptEnable
Definition: NUC472_442.h:26279
EPWM_T::ASYMCMP4
__IO uint32_t ASYMCMP4
Definition: NUC472_442.h:14187
PDMA_T::REQSEL4_7
__IO uint32_t REQSEL4_7
Definition: NUC472_442.h:18541
PWM_T::TRGADCSTS
__IO uint32_t TRGADCSTS
Definition: NUC472_442.h:19352
EBI_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:11598
EMAC_T::TSSUBSEC
__I uint32_t TSSUBSEC
Definition: NUC472_442.h:13164
EADC_T::AD0DAT4
__I uint32_t AD0DAT4
Definition: NUC472_442.h:7523
ADC_T::CURDAT
__I uint32_t CURDAT
Definition: NUC472_442.h:602
CRPT_T::TDES2_KEY1H
__IO uint32_t TDES2_KEY1H
Definition: NUC472_442.h:6178
CAN_IF_T::DAT_B2
__IO uint32_t DAT_B2
Definition: NUC472_442.h:1119
EPWM_T::EINTCTL
__IO uint32_t EINTCTL
Definition: NUC472_442.h:14369
CRPT_T::SHA_DATIN
__IO uint32_t SHA_DATIN
Definition: NUC472_442.h:6771
SYS_T::REGLCTL
__IO uint32_t REGLCTL
Definition: NUC472_442.h:24177
CRPT_T::SHA_DGST2
__I uint32_t SHA_DGST2
Definition: NUC472_442.h:6628
SYS_T::GPG_MFPH
__IO uint32_t GPG_MFPH
Definition: NUC472_442.h:23926
PS2_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:18948
EMAC_T::CAM7M
__IO uint32_t CAM7M
Definition: NUC472_442.h:12060
USBH_T::HcLSThreshold
__IO uint32_t HcLSThreshold
Definition: NUC472_442.h:26467
EMAC_T::CAM14L
__IO uint32_t CAM14L
Definition: NUC472_442.h:12314
I2S_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:17443
EMAC_T::CAM12L
__IO uint32_t CAM12L
Definition: NUC472_442.h:12246
CRPT_T::AES2_KEY6
__IO uint32_t AES2_KEY6
Definition: NUC472_442.h:5251
EADC_T::AD0DAT0
__I uint32_t AD0DAT0
Definition: NUC472_442.h:7439
CAN_IF_T::DAT_A2
__IO uint32_t DAT_A2
Definition: NUC472_442.h:1091
CAN_IF_T::MASK2
__IO uint32_t MASK2
Definition: NUC472_442.h:965
PS2_T::RXDAT
__I uint32_t RXDAT
Definition: NUC472_442.h:18860
EADC_T::AD1DDAT1
__I uint32_t AD1DDAT1
Definition: NUC472_442.h:8994
SC_T::ALTCTL
__IO uint32_t ALTCTL
Definition: NUC472_442.h:21325
CRPT_T::AES3_IV3
__IO uint32_t AES3_IV3
Definition: NUC472_442.h:5598
CRPT_T::TDES1_KEY2H
__IO uint32_t TDES1_KEY2H
Definition: NUC472_442.h:6026
SYS_T::GPA_MFPH
__IO uint32_t GPA_MFPH
Definition: NUC472_442.h:23710
CLK_T::APBCLK0
__IO uint32_t APBCLK0
Definition: NUC472_442.h:2984
CRPT_T::TDES2_KEY1L
__IO uint32_t TDES2_KEY1L
Definition: NUC472_442.h:6193
UART_T::FIFOSTS
__IO uint32_t FIFOSTS
Definition: NUC472_442.h:25425
USBH_T::HcRhDescriptorB
__IO uint32_t HcRhDescriptorB
Definition: NUC472_442.h:26527
WDT_T::ALTCTL
__IO uint32_t ALTCTL
Definition: NUC472_442.h:28514
PS2_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:18926
SYS_T::PDID
__I uint32_t PDID
Definition: NUC472_442.h:23277
EMAC_T::CAM9L
__IO uint32_t CAM9L
Definition: NUC472_442.h:12144
USBD_EP_T::EPDATCNT
__I uint32_t EPDATCNT
Definition: NUC472_442.h:27126
CRPT_T::AES1_IV0
__IO uint32_t AES1_IV0
Definition: NUC472_442.h:5015
EADC_T::AD0TRGEN2
__IO uint32_t AD0TRGEN2
Definition: NUC472_442.h:9436
CRPT_T::TDES_FDBCKH
__I uint32_t TDES_FDBCKH
Definition: NUC472_442.h:4424
CRPT_T::TDES1_KEY3H
__IO uint32_t TDES1_KEY3H
Definition: NUC472_442.h:6056
CRPT_T::TDES3_CNT
__IO uint32_t TDES3_CNT
Definition: NUC472_442.h:6523
USBH_T::HcHCCA
__IO uint32_t HcHCCA
Definition: NUC472_442.h:26323
EADC_T::AD1SPCTL5
__IO uint32_t AD1SPCTL5
Definition: NUC472_442.h:8585
SC_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:21226
EADC_T::AD1DAT2
__I uint32_t AD1DAT2
Definition: NUC472_442.h:7649
SYS_T::IPRST1
__IO uint32_t IPRST1
Definition: NUC472_442.h:23479
CRPT_T::TDES3_KEY1L
__IO uint32_t TDES3_KEY1L
Definition: NUC472_442.h:6375
CRPT_T::TDES3_KEY1H
__IO uint32_t TDES3_KEY1H
Definition: NUC472_442.h:6360
PDMA_T::CHCTL
__IO uint32_t CHCTL
Definition: NUC472_442.h:18248
CAP_T::PKTSL
__IO uint32_t PKTSL
Definition: NUC472_442.h:1929
EPWM_T::NPCTL
__IO uint32_t NPCTL
Definition: NUC472_442.h:14248
CRPT_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:4159
CRPT_T::PRNG_KEY6
__I uint32_t PRNG_KEY6
Definition: NUC472_442.h:4321
CRPT_T::TDES2_IVH
__IO uint32_t TDES2_IVH
Definition: NUC472_442.h:6266
CRPT_T::TDES_CTL
__IO uint32_t TDES_CTL
Definition: NUC472_442.h:5733
CAP_T::PKTSM
__IO uint32_t PKTSM
Definition: NUC472_442.h:2042
EMAC_T::CAM13M
__IO uint32_t CAM13M
Definition: NUC472_442.h:12264
USBD_T::CEPINTEN
__IO uint32_t CEPINTEN
Definition: NUC472_442.h:27671
PWM_T::CAPSTS
__I uint32_t CAPSTS
Definition: NUC472_442.h:19575
SC_T::EGT
__IO uint32_t EGT
Definition: NUC472_442.h:21338
EMAC_T::TSSEC
__I uint32_t TSSEC
Definition: NUC472_442.h:13151
CRPT_T::AES1_DADDR
__IO uint32_t AES1_DADDR
Definition: NUC472_442.h:5104
CRPT_T::AES_FDBCK0
__I uint32_t AES_FDBCK0
Definition: NUC472_442.h:4354
EMAC_T::CAM11L
__IO uint32_t CAM11L
Definition: NUC472_442.h:12212
CAP_T::INT
__IO uint32_t INT
Definition: NUC472_442.h:1804
EADC_T::AD1DAT1
__I uint32_t AD1DAT1
Definition: NUC472_442.h:7628
ACMP_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:288
SDH_T::CMDARG
__IO uint32_t CMDARG
Definition: NUC472_442.h:22304
EADC_T::AD1DDAT3
__I uint32_t AD1DDAT3
Definition: NUC472_442.h:9026
ADC_T::STATUS0
__IO uint32_t STATUS0
Definition: NUC472_442.h:572
EMAC_T::CAM11M
__IO uint32_t CAM11M
Definition: NUC472_442.h:12196
CRPT_T::PRNG_KEY1
__I uint32_t PRNG_KEY1
Definition: NUC472_442.h:4261
FMC_T::ISPSTS
__IO uint32_t ISPSTS
Definition: NUC472_442.h:14750
EADC_T::AD0SPCTL1
__IO uint32_t AD0SPCTL1
Definition: NUC472_442.h:7997
CRPT_T::TDES3_KEY3L
__IO uint32_t TDES3_KEY3L
Definition: NUC472_442.h:6435
RTC_T::TICK
__IO uint32_t TICK
Definition: NUC472_442.h:20615
CAP_T::CURADDRU
__I uint32_t CURADDRU
Definition: NUC472_442.h:2097
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: NUC472_442.h:22789
CAP_T::VBA
__IO uint32_t VBA
Definition: NUC472_442.h:2172
CAP_T::UBA
__IO uint32_t UBA
Definition: NUC472_442.h:2160
CRPT_T::TDES_STS
__I uint32_t TDES_STS
Definition: NUC472_442.h:5773
CAN_T::WU_EN
__IO uint32_t WU_EN
Definition: NUC472_442.h:1428
EPWM_T::ASYMCMP2
__IO uint32_t ASYMCMP2
Definition: NUC472_442.h:14175
USBH_T::HcFmRemaining
__I uint32_t HcFmRemaining
Definition: NUC472_442.h:26428
CAN_T::ERR
__IO uint32_t ERR
Definition: NUC472_442.h:1205
USBD_T::SETUP5_4
__I uint32_t SETUP5_4
Definition: NUC472_442.h:27848
EMAC_T::CAM4L
__IO uint32_t CAM4L
Definition: NUC472_442.h:11974
EMAC_T::CAM3M
__IO uint32_t CAM3M
Definition: NUC472_442.h:11924
RTC_T::LEAPYEAR
__I uint32_t LEAPYEAR
Definition: NUC472_442.h:20560
RTC_T::TIME
__IO uint32_t TIME
Definition: NUC472_442.h:20466
CRPT_T::SHA_DGST3
__I uint32_t SHA_DGST3
Definition: NUC472_442.h:6642
EADC_T::AD0DDAT0
__I uint32_t AD0DDAT0
Definition: NUC472_442.h:8910
EMAC_T::CAM2M
__IO uint32_t CAM2M
Definition: NUC472_442.h:11890
OTG_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:17871
SDH_T::RESP1
__I uint32_t RESP1
Definition: NUC472_442.h:22463
CRPT_T::TDES_DATOUT
__I uint32_t TDES_DATOUT
Definition: NUC472_442.h:5977
CAP_T::SEPIA
__IO uint32_t SEPIA
Definition: NUC472_442.h:1879
PDMA_T::SCATBA
__IO uint32_t SCATBA
Definition: NUC472_442.h:18450
QEI_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:20287
USBD_T::PHYCTL
__IO uint32_t PHYCTL
Definition: NUC472_442.h:27965
PS2_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:18795
GPIO_T::INTSRC
__IO uint32_t INTSRC
Definition: NUC472_442.h:16093
EPWM_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:14086
CRPT_T::PRNG_SEED
__O uint32_t PRNG_SEED
Definition: NUC472_442.h:4237
CRPT_T::TDES_DATIN
__IO uint32_t TDES_DATIN
Definition: NUC472_442.h:5964
CRPT_T::TDES0_KEY2L
__IO uint32_t TDES0_KEY2L
Definition: NUC472_442.h:5833
USBD_T::FRAMECNT
__I uint32_t FRAMECNT
Definition: NUC472_442.h:27524
CAN_T::WU_STATUS
__IO uint32_t WU_STATUS
Definition: NUC472_442.h:1442
RTC_T::CLKFMT
__IO uint32_t CLKFMT
Definition: NUC472_442.h:20496
I2C_T::ADDRMSK1
__IO uint32_t ADDRMSK1
Definition: NUC472_442.h:17015
CLK_T::APBCLK1
__IO uint32_t APBCLK1
Definition: NUC472_442.h:3057
RTC_T::LXTIPCTL
__IO uint32_t LXTIPCTL
Definition: NUC472_442.h:20788
CRPT_T::SHA_DGST5
__I uint32_t SHA_DGST5
Definition: NUC472_442.h:6670
CRPT_T::AES_FDBCK3
__I uint32_t AES_FDBCK3
Definition: NUC472_442.h:4405
CRPT_T::PRNG_KEY7
__I uint32_t PRNG_KEY7
Definition: NUC472_442.h:4333
CAP_T::CURVADDR
__I uint32_t CURVADDR
Definition: NUC472_442.h:2108
EADC_T::AD1DAT4
__I uint32_t AD1DAT4
Definition: NUC472_442.h:7691
FMC_T::FTCTL
__IO uint32_t FTCTL
Definition: NUC472_442.h:14717
FMC_T::MPSTS
__IO uint32_t MPSTS
Definition: NUC472_442.h:14889
CRPT_T::AES0_KEY7
__IO uint32_t AES0_KEY7
Definition: NUC472_442.h:4731
EMAC_T::CRXDSA
__I uint32_t CRXDSA
Definition: NUC472_442.h:13084
USBH_T::HcControlCurrentED
__IO uint32_t HcControlCurrentED
Definition: NUC472_442.h:26359
RTC_T::CAL
__IO uint32_t CAL
Definition: NUC472_442.h:20482
CRPT_T::AES_FDBCK1
__I uint32_t AES_FDBCK1
Definition: NUC472_442.h:4371
RTC_T::CALM
__IO uint32_t CALM
Definition: NUC472_442.h:20547
CAP_T::MDYADDR
__IO uint32_t MDYADDR
Definition: NUC472_442.h:1867
EADC_T::EXTSMPT
__IO uint32_t EXTSMPT
Definition: NUC472_442.h:8890
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: NUC472_442.h:2884
CRPT_T::TDES1_KEY1H
__IO uint32_t TDES1_KEY1H
Definition: NUC472_442.h:5996
CAP_T::CURADDRP
__I uint32_t CURADDRP
Definition: NUC472_442.h:2075
EBI_T::KEY1
__IO uint32_t KEY1
Definition: NUC472_442.h:11662
FMC_T::DFBA
__I uint32_t DFBA
Definition: NUC472_442.h:14695
CAN_IF_T::CREQ
__IO uint32_t CREQ
Definition: NUC472_442.h:868
CAN_T::IIDR
__IO uint32_t IIDR
Definition: NUC472_442.h:1248
CAN_T::TXREQ2
__IO uint32_t TXREQ2
Definition: NUC472_442.h:1325
USBH_T::HcPhyControl
__IO uint32_t HcPhyControl
Definition: NUC472_442.h:26652
ECAP_T::CNT
__IO uint32_t CNT
Definition: NUC472_442.h:2436
CAN_T::MVLD1
__IO uint32_t MVLD1
Definition: NUC472_442.h:1399
CRPT_T::AES2_KEY0
__IO uint32_t AES2_KEY0
Definition: NUC472_442.h:5143
I2C_T::ADDR1
__IO uint32_t ADDR1
Definition: NUC472_442.h:16949
CRPT_T::AES2_IV1
__IO uint32_t AES2_IV1
Definition: NUC472_442.h:5299
CRPT_T::TDES3_KEY2L
__IO uint32_t TDES3_KEY2L
Definition: NUC472_442.h:6405
EPWM_T::OUTEN0
__IO uint32_t OUTEN0
Definition: NUC472_442.h:14385
GPIO_DB_T::DBCTL
__IO uint32_t DBCTL
Definition: NUC472_442.h:16216
EMAC_T::MPCNT
__IO uint32_t MPCNT
Definition: NUC472_442.h:13014
DSCT_T::NEXT
__IO uint32_t NEXT
Definition: NUC472_442.h:18223
USBD_EP_T::EPINTEN
__IO uint32_t EPINTEN
Definition: NUC472_442.h:27112
EMAC_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: NUC472_442.h:12568
UART_T::TOUT
__IO uint32_t TOUT
Definition: NUC472_442.h:25548
SYS_T::GPB_MFPH
__IO uint32_t GPB_MFPH
Definition: NUC472_442.h:23746
QEI_T::CNTCMP
__IO uint32_t CNTCMP
Definition: NUC472_442.h:20143
USBD_T::FADDR
__IO uint32_t FADDR
Definition: NUC472_442.h:27537
CAP_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:1714
EPWM_T::PERIOD
__IO uint32_t PERIOD
Definition: NUC472_442.h:14103
PWM_T::INTCTL
__IO uint32_t INTCTL
Definition: NUC472_442.h:19431
CLK_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:3480
UART_T::LINCTL
__IO uint32_t LINCTL
Definition: NUC472_442.h:25731
EPWM_T::BRKOUT
__IO uint32_t BRKOUT
Definition: NUC472_442.h:14233
UART_T::FIFO
__IO uint32_t FIFO
Definition: NUC472_442.h:25288
CRPT_T::AES3_KEY2
__IO uint32_t AES3_KEY2
Definition: NUC472_442.h:5448
ADC_T::CHEN
__IO uint32_t CHEN
Definition: NUC472_442.h:493
USBD_T::CEPRXCNT
__I uint32_t CEPRXCNT
Definition: NUC472_442.h:27761
PWM_T::CNTEN
__IO uint32_t CNTEN
Definition: NUC472_442.h:19155
EADC_T::AD1DAT6
__I uint32_t AD1DAT6
Definition: NUC472_442.h:7733
EMAC_T::CRXBSA
__I uint32_t CRXBSA
Definition: NUC472_442.h:13097
CRPT_T::AES0_KEY5
__IO uint32_t AES0_KEY5
Definition: NUC472_442.h:4695
EMAC_T::CAM15MSB
__IO uint32_t CAM15MSB
Definition: NUC472_442.h:12328
SC_T::PINCTL
__IO uint32_t PINCTL
Definition: NUC472_442.h:21639
USBD_T::CEPDATCNT
__I uint32_t CEPDATCNT
Definition: NUC472_442.h:27773
USBD_T::GINTEN
__IO uint32_t GINTEN
Definition: NUC472_442.h:27397
CLK_T::PWRCTL
__IO uint32_t PWRCTL
Definition: NUC472_442.h:2841
GPIO_T::SLEWCTL
__IO uint32_t SLEWCTL
Definition: NUC472_442.h:16177
EADC_T::AD1SPCTL2
__IO uint32_t AD1SPCTL2
Definition: NUC472_442.h:8446
EMAC_T::CAM1L
__IO uint32_t CAM1L
Definition: NUC472_442.h:11872
SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: NUC472_442.h:22919
EMAC_T::CAM10M
__IO uint32_t CAM10M
Definition: NUC472_442.h:12162
SC_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:21569
CRPT_T::AES1_KEY0
__IO uint32_t AES1_KEY0
Definition: NUC472_442.h:4874
PWM_T::RCAPDAT1
__I uint32_t RCAPDAT1
Definition: NUC472_442.h:19615
CAP_T::CMPADDR
__IO uint32_t CMPADDR
Definition: NUC472_442.h:2016
CRPT_T::AES_DATIN
__IO uint32_t AES_DATIN
Definition: NUC472_442.h:4574
PDMA_T::PRICLR
__O uint32_t PRICLR
Definition: NUC472_442.h:18332
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: NUC472_442.h:14654
USBD_T::CEPDAT
__IO uint32_t CEPDAT
Definition: NUC472_442.h:27572
SDH_T::GINTEN
__IO uint32_t GINTEN
Definition: NUC472_442.h:22205
EADC_T::OVSTS
__IO uint32_t OVSTS
Definition: NUC472_442.h:7883
USBD_T::SETUP7_6
__I uint32_t SETUP7_6
Definition: NUC472_442.h:27864
PWM_T::FCAPDAT3
__I uint32_t FCAPDAT3
Definition: NUC472_442.h:19675
EBI_T::KEY3
__IO uint32_t KEY3
Definition: NUC472_442.h:11684
CRPT_T::AES1_KEY5
__IO uint32_t AES1_KEY5
Definition: NUC472_442.h:4964
USBD_T::BUSINTEN
__IO uint32_t BUSINTEN
Definition: NUC472_442.h:27490
CRPT_T::AES2_KEY1
__IO uint32_t AES2_KEY1
Definition: NUC472_442.h:5161
SYS_T::IPRST2
__IO uint32_t IPRST2
Definition: NUC472_442.h:23522
CRPT_T::TDES2_SADDR
__IO uint32_t TDES2_SADDR
Definition: NUC472_442.h:6301
SYS_T::SRAM_STATUS
__IO uint32_t SRAM_STATUS
Definition: NUC472_442.h:24031
CAN_IF_T::CMASK
__IO uint32_t CMASK
Definition: NUC472_442.h:931
OTG_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:17935
FMC_T::MPDAT0
__IO uint32_t MPDAT0
Definition: NUC472_442.h:14815
EADC_T::AD1SPCTL4
__IO uint32_t AD1SPCTL4
Definition: NUC472_442.h:8544
EPWM_T::DTCTL
__IO uint32_t DTCTL
Definition: NUC472_442.h:14218
CRPT_T::AES2_KEY5
__IO uint32_t AES2_KEY5
Definition: NUC472_442.h:5233
DSCT_T::ENDDA
__IO uint32_t ENDDA
Definition: NUC472_442.h:18208
EMAC_T::CAM8M
__IO uint32_t CAM8M
Definition: NUC472_442.h:12094
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: NUC472_442.h:3200
WWDT_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:28625
CRPT_T::AES2_KEY7
__IO uint32_t AES2_KEY7
Definition: NUC472_442.h:5269
CLK_T::CLKOCTL
__IO uint32_t CLKOCTL
Definition: NUC472_442.h:3506
CRPT_T::AES0_KEY0
__IO uint32_t AES0_KEY0
Definition: NUC472_442.h:4605
EADC_T::AD0DDAT3
__I uint32_t AD0DDAT3
Definition: NUC472_442.h:8958
EMAC_T::TSCTL
__IO uint32_t TSCTL
Definition: NUC472_442.h:13134
PS2_T::TXDAT0
__IO uint32_t TXDAT0
Definition: NUC472_442.h:18808
EADC_T::PENDSTS
__I uint32_t PENDSTS
Definition: NUC472_442.h:7835
SYS_T::SRAM1_ERRADDR
__I uint32_t SRAM1_ERRADDR
Definition: NUC472_442.h:24054
QEI_T::CNTMAX
__IO uint32_t CNTMAX
Definition: NUC472_442.h:20159
CRPT_T::AES1_IV1
__IO uint32_t AES1_IV1
Definition: NUC472_442.h:5030
USBD_T::SETUP3_2
__I uint32_t SETUP3_2
Definition: NUC472_442.h:27832
SYS_T::USBPHY
__IO uint32_t USBPHY
Definition: NUC472_442.h:23674
OPA_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:17675
EADC_T::AD0DDAT1
__I uint32_t AD0DDAT1
Definition: NUC472_442.h:8926
CAN_IF_T::MASK1
__IO uint32_t MASK1
Definition: NUC472_442.h:944
EADC_T::AD0SPCTL4
__IO uint32_t AD0SPCTL4
Definition: NUC472_442.h:8152
USBD_EP_T::EPRSPCTL
__IO uint32_t EPRSPCTL
Definition: NUC472_442.h:27176
EMAC_T::CAM5L
__IO uint32_t CAM5L
Definition: NUC472_442.h:12008
CRPT_T::SHA_CTL
__IO uint32_t SHA_CTL
Definition: NUC472_442.h:6564
CRPT_T::AES1_SADDR
__IO uint32_t AES1_SADDR
Definition: NUC472_442.h:5082
USBD_T::CEPINTSTS
__IO uint32_t CEPINTSTS
Definition: NUC472_442.h:27735
SDH_T::BLEN
__IO uint32_t BLEN
Definition: NUC472_442.h:22477
OTG_T::STATUS
__I uint32_t STATUS
Definition: NUC472_442.h:17964
CRPT_T::TDES3_IVL
__IO uint32_t TDES3_IVL
Definition: NUC472_442.h:6461
EMAC_T::CAM7L
__IO uint32_t CAM7L
Definition: NUC472_442.h:12076
SC_T::TMRDAT1_2
__I uint32_t TMRDAT1_2
Definition: NUC472_442.h:21740
EMAC_T::CAM13L
__IO uint32_t CAM13L
Definition: NUC472_442.h:12280
CRPT_T::AES1_IV3
__IO uint32_t AES1_IV3
Definition: NUC472_442.h:5060
CAP_T::CURADDRY
__I uint32_t CURADDRY
Definition: NUC472_442.h:2086
ADC_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:470
EMAC_T::CTXDSA
__I uint32_t CTXDSA
Definition: NUC472_442.h:13058
CRPT_T::TDES3_IVH
__IO uint32_t TDES3_IVH
Definition: NUC472_442.h:6448
CRPT_T::AES_FDBCK2
__I uint32_t AES_FDBCK2
Definition: NUC472_442.h:4388
EADC_T::AD1DDAT0
__I uint32_t AD1DDAT0
Definition: NUC472_442.h:8978
GPIO_T::DINOFF
__IO uint32_t DINOFF
Definition: NUC472_442.h:15255
USBD_T::CEPTXCNT
__IO uint32_t CEPTXCNT
Definition: NUC472_442.h:27749
CRPT_T::AES2_KEY4
__IO uint32_t AES2_KEY4
Definition: NUC472_442.h:5215
CAN_T::CON
__IO uint32_t CON
Definition: NUC472_442.h:1156
CRPT_T::TDES2_KEY3H
__IO uint32_t TDES2_KEY3H
Definition: NUC472_442.h:6238
PWM_T::CAPINEN
__IO uint32_t CAPINEN
Definition: NUC472_442.h:19559
I2S_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:17280
DSCT_T::ENDSA
__IO uint32_t ENDSA
Definition: NUC472_442.h:18194
SYS_T::GPI_MFPL
__IO uint32_t GPI_MFPL
Definition: NUC472_442.h:23980
EADC_T::STATUS0
__I uint32_t STATUS0
Definition: NUC472_442.h:8773
PWM_T::FCAPDAT0
__I uint32_t FCAPDAT0
Definition: NUC472_442.h:19603
CRPT_T::AES1_KEY1
__IO uint32_t AES1_KEY1
Definition: NUC472_442.h:4892
CRPT_T::AES2_SADDR
__IO uint32_t AES2_SADDR
Definition: NUC472_442.h:5351
SC_T::TMRDAT0
__I uint32_t TMRDAT0
Definition: NUC472_442.h:21726
UART_T::MODEM
__IO uint32_t MODEM
Definition: NUC472_442.h:25344
CRPT_T::AES3_KEY6
__IO uint32_t AES3_KEY6
Definition: NUC472_442.h:5520
SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: NUC472_442.h:22848
RTC_T::TAMSK
__IO uint32_t TAMSK
Definition: NUC472_442.h:20833
QEI_T::CNTHOLD
__IO uint32_t CNTHOLD
Definition: NUC472_442.h:20118
USBH_T::HcRevision
__I uint32_t HcRevision
Definition: NUC472_442.h:26161
EADC_T::AD1DAT7
__I uint32_t AD1DAT7
Definition: NUC472_442.h:7754
ECAP_T::CTL0
__IO uint32_t CTL0
Definition: NUC472_442.h:2573
EADC_T::AD0TRGEN0
__IO uint32_t AD0TRGEN0
Definition: NUC472_442.h:9224
SYS_T::GPA_MFPL
__IO uint32_t GPA_MFPL
Definition: NUC472_442.h:23692
FMC_T::MPDAT1
__IO uint32_t MPDAT1
Definition: NUC472_442.h:14827
I2C_T::ADDR2
__IO uint32_t ADDR2
Definition: NUC472_442.h:16966
CRPT_T::SHA_STS
__I uint32_t SHA_STS
Definition: NUC472_442.h:6586
EADC_T::AD1TRGEN3
__IO uint32_t AD1TRGEN3
Definition: NUC472_442.h:9966
USBD_T::CEPBUFSTART
__IO uint32_t CEPBUFSTART
Definition: NUC472_442.h:27876
CRPT_T::AES1_KEY3
__IO uint32_t AES1_KEY3
Definition: NUC472_442.h:4928
EMAC_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:12948
EMAC_T::CAM6L
__IO uint32_t CAM6L
Definition: NUC472_442.h:12042
EADC_T::AD1SPCTL0
__IO uint32_t AD1SPCTL0
Definition: NUC472_442.h:8332
CAP_T::MDADDR
__IO uint32_t MDADDR
Definition: NUC472_442.h:1856
EADC_T::DBMEN
__IO uint32_t DBMEN
Definition: NUC472_442.h:9060
SYS_T::GPB_MFPL
__IO uint32_t GPB_MFPL
Definition: NUC472_442.h:23728
EMAC_T::CAM2L
__IO uint32_t CAM2L
Definition: NUC472_442.h:11906
EADC_T::AD0SPCTL5
__IO uint32_t AD0SPCTL5
Definition: NUC472_442.h:8193
CRPT_T::SHA_DMACNT
__IO uint32_t SHA_DMACNT
Definition: NUC472_442.h:6759
CRPT_T::AES3_KEY7
__IO uint32_t AES3_KEY7
Definition: NUC472_442.h:5538
USBD_EP_T::EPDAT_BYTE
__IO uint8_t EPDAT_BYTE
Definition: NUC472_442.h:26979
SDH_T::DMABCNT
__I uint32_t DMABCNT
Definition: NUC472_442.h:22135
EADC_T::AD0DDAT2
__I uint32_t AD0DDAT2
Definition: NUC472_442.h:8942
CRPT_T::AES_STS
__I uint32_t AES_STS
Definition: NUC472_442.h:4562
CRPT_T::AES0_IV2
__IO uint32_t AES0_IV2
Definition: NUC472_442.h:4776
USBD_T::CEPBUFEND
__IO uint32_t CEPBUFEND
Definition: NUC472_442.h:27888
CAP_T::FRCTL
__IO uint32_t FRCTL
Definition: NUC472_442.h:1971
EADC_T::SWTRG
__O uint32_t SWTRG
Definition: NUC472_442.h:7815
CRPT_T::AES0_SADDR
__IO uint32_t AES0_SADDR
Definition: NUC472_442.h:4813
CRPT_T::TDES3_DADDR
__IO uint32_t TDES3_DADDR
Definition: NUC472_442.h:6505
CRPT_T::TDES1_CNT
__IO uint32_t TDES1_CNT
Definition: NUC472_442.h:6159
QEI_T::CNT
__IO uint32_t CNT
Definition: NUC472_442.h:20106
EADC_T::AD1TRGEN2
__IO uint32_t AD1TRGEN2
Definition: NUC472_442.h:9860
EADC_T::AD0DAT1
__I uint32_t AD0DAT1
Definition: NUC472_442.h:7460
CAP_T::PLNSM
__IO uint32_t PLNSM
Definition: NUC472_442.h:2064
USBD_EP_T::EPMPS
__IO uint32_t EPMPS
Definition: NUC472_442.h:27188
EMAC_T::CTXBSA
__I uint32_t CTXBSA
Definition: NUC472_442.h:13071
CLK_T::CLKDIV2
__IO uint32_t CLKDIV2
Definition: NUC472_442.h:3366
CRPT_T::AES0_CNT
__IO uint32_t AES0_CNT
Definition: NUC472_442.h:4856
TIMER_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:24954
QEI_T::CTR
__IO uint32_t CTR
Definition: NUC472_442.h:20247
PWM_T::CLKDIV
__IO uint32_t CLKDIV
Definition: NUC472_442.h:19096
SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: NUC472_442.h:23584
CRPT_T::SHA_DGST1
__I uint32_t SHA_DGST1
Definition: NUC472_442.h:6614
EMAC_T::CAM12M
__IO uint32_t CAM12M
Definition: NUC472_442.h:12230
EADC_T::AD0DAT6
__I uint32_t AD0DAT6
Definition: NUC472_442.h:7565
SDH_T::GCTL
__IO uint32_t GCTL
Definition: NUC472_442.h:22192
SYS_T::IPRST0
__IO uint32_t IPRST0
Definition: NUC472_442.h:23394
I2C_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:16853
EADC_T::AD1SPCTL1
__IO uint32_t AD1SPCTL1
Definition: NUC472_442.h:8389
PDMA_T::REQSEL12_15
__IO uint32_t REQSEL12_15
Definition: NUC472_442.h:18601
EADC_T::AD0DAT5
__I uint32_t AD0DAT5
Definition: NUC472_442.h:7544
TIMER_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:24991
EADC_T::AD0SPCTL2
__IO uint32_t AD0SPCTL2
Definition: NUC472_442.h:8054
CRPT_T::PRNG_KEY0
__I uint32_t PRNG_KEY0
Definition: NUC472_442.h:4249
PWM_T::CLKPSC
__IO uint32_t CLKPSC
Definition: NUC472_442.h:19068
CAP_T::MD
__IO uint32_t MD
Definition: NUC472_442.h:1845
RTC_T::SPRCTL
__IO uint32_t SPRCTL
Definition: NUC472_442.h:20639
ECAP_T::HOLD2
__IO uint32_t HOLD2
Definition: NUC472_442.h:2475
CAN_IF_T::MCON
__IO uint32_t MCON
Definition: NUC472_442.h:1063
USBH_T::HcDoneHead
__IO uint32_t HcDoneHead
Definition: NUC472_442.h:26395
CAP_T::PLNSL
__IO uint32_t PLNSL
Definition: NUC472_442.h:1955
PWM_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:19503
CLK_T::CLKDIV3
__IO uint32_t CLKDIV3
Definition: NUC472_442.h:3382
EMAC_T::CAM6M
__IO uint32_t CAM6M
Definition: NUC472_442.h:12026
UART_T::LINSTS
__IO uint32_t LINSTS
Definition: NUC472_442.h:25780
CRPT_T::AES_DATOUT
__I uint32_t AES_DATOUT
Definition: NUC472_442.h:4587
CRPT_T::TDES0_KEY2H
__IO uint32_t TDES0_KEY2H
Definition: NUC472_442.h:5818
CRPT_T::TDES1_KEY3L
__IO uint32_t TDES1_KEY3L
Definition: NUC472_442.h:6071
CRPT_T::TDES2_KEY2L
__IO uint32_t TDES2_KEY2L
Definition: NUC472_442.h:6223
EADC_T::AD0SPCTL3
__IO uint32_t AD0SPCTL3
Definition: NUC472_442.h:8111
QEI_T::CNTLATCH
__IO uint32_t CNTLATCH
Definition: NUC472_442.h:20130
EPWM_T::PERIODCNT
__IO uint32_t PERIODCNT
Definition: NUC472_442.h:14341
CRPT_T::TDES0_DADDR
__IO uint32_t TDES0_DADDR
Definition: NUC472_442.h:5933
CRPT_T::TDES1_KEY2L
__IO uint32_t TDES1_KEY2L
Definition: NUC472_442.h:6041
PWM_T::FCAPDAT2
__I uint32_t FCAPDAT2
Definition: NUC472_442.h:19651
RTC_T::CAMSK
__IO uint32_t CAMSK
Definition: NUC472_442.h:20849
RTC_T::TAMPCTL
__IO uint32_t TAMPCTL
Definition: NUC472_442.h:20691
CRPT_T::AES0_KEY3
__IO uint32_t AES0_KEY3
Definition: NUC472_442.h:4659
WWDT_T::CNT
__I uint32_t CNT
Definition: NUC472_442.h:28657
EMAC_T::UPDSEC
__IO uint32_t UPDSEC
Definition: NUC472_442.h:13205
CAP_T::FIFOTH
__IO uint32_t FIFOTH
Definition: NUC472_442.h:2004
CRPT_T::SHA_DGST6
__I uint32_t SHA_DGST6
Definition: NUC472_442.h:6684
EADC_T::STATUS1
__IO uint32_t STATUS1
Definition: NUC472_442.h:8874
EADC_T::AD0SPCTL0
__IO uint32_t AD0SPCTL0
Definition: NUC472_442.h:7940
GPIO_T::PIN
__I uint32_t PIN
Definition: NUC472_442.h:15493
EMAC_T::CAM14M
__IO uint32_t CAM14M
Definition: NUC472_442.h:12298
I2C_T::ADDRMSK0
__IO uint32_t ADDRMSK0
Definition: NUC472_442.h:16999
SYS_T::IRCTCTL
__IO uint32_t IRCTCTL
Definition: NUC472_442.h:24094
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: NUC472_442.h:15329
PWM_T::RCAPDAT3
__I uint32_t RCAPDAT3
Definition: NUC472_442.h:19663
EADC_T::AD1DAT5
__I uint32_t AD1DAT5
Definition: NUC472_442.h:7712
UART_T::ALTCTL
__IO uint32_t ALTCTL
Definition: NUC472_442.h:25635
SYS_T::GPF_MFPH
__IO uint32_t GPF_MFPH
Definition: NUC472_442.h:23890
CRPT_T::AES1_KEY6
__IO uint32_t AES1_KEY6
Definition: NUC472_442.h:4982
CRPT_T::TDES1_IVH
__IO uint32_t TDES1_IVH
Definition: NUC472_442.h:6084
SC_T::RXTOUT
__IO uint32_t RXTOUT
Definition: NUC472_442.h:21353
PS2_T::TXDAT2
__IO uint32_t TXDAT2
Definition: NUC472_442.h:18834
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: NUC472_442.h:15615
SC_T::TMRCTL0
__IO uint32_t TMRCTL0
Definition: NUC472_442.h:21654
PDMA_T::TACTSTS
__I uint32_t TACTSTS
Definition: NUC472_442.h:18431
OTG_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:17778
CAN_T::MVLD2
__IO uint32_t MVLD2
Definition: NUC472_442.h:1414
USBD_EP_T::EPTXCNT
__IO uint32_t EPTXCNT
Definition: NUC472_442.h:27201
CRPT_T::PRNG_KEY5
__I uint32_t PRNG_KEY5
Definition: NUC472_442.h:4309
EADC_T::AD0DAT7
__I uint32_t AD0DAT7
Definition: NUC472_442.h:7586
CRPT_T::TDES1_SADDR
__IO uint32_t TDES1_SADDR
Definition: NUC472_442.h:6119
ECAP_T::HOLD1
__IO uint32_t HOLD1
Definition: NUC472_442.h:2462
PDMA_T::SCATSTS
__IO uint32_t SCATSTS
Definition: NUC472_442.h:18417
RTC_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:20576
ACMP_T::VREF
__IO uint32_t VREF
Definition: NUC472_442.h:306
USBH_T::HcBulkHeadED
__IO uint32_t HcBulkHeadED
Definition: NUC472_442.h:26371
RTC_T::INIT
__IO uint32_t INIT
Definition: NUC472_442.h:20420
EMAC_T::CAM15LSB
__IO uint32_t CAM15LSB
Definition: NUC472_442.h:12341
CRPT_T::AES2_KEY3
__IO uint32_t AES2_KEY3
Definition: NUC472_442.h:5197
CAN_T::BTIME
__IO uint32_t BTIME
Definition: NUC472_442.h:1229
SDH_T::DMACTL
__IO uint32_t DMACTL
Definition: NUC472_442.h:22101
EMAC_T::MRFL
__IO uint32_t MRFL
Definition: NUC472_442.h:12612
EMAC_T::CAM0M
__IO uint32_t CAM0M
Definition: NUC472_442.h:11822
CRPT_T::TDES2_IVL
__IO uint32_t TDES2_IVL
Definition: NUC472_442.h:6279
CRPT_T::PRNG_CTL
__IO uint32_t PRNG_CTL
Definition: NUC472_442.h:4225
PWM_T::MSKEN
__IO uint32_t MSKEN
Definition: NUC472_442.h:19237
CRPT_T::TDES1_DADDR
__IO uint32_t TDES1_DADDR
Definition: NUC472_442.h:6141
PWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: NUC472_442.h:19543
CRPT_T::TDES2_DADDR
__IO uint32_t TDES2_DADDR
Definition: NUC472_442.h:6323
EMAC_T::CAMEN
__IO uint32_t CAMEN
Definition: NUC472_442.h:11804
SYS_T::RSTSTS
__IO uint32_t RSTSTS
Definition: NUC472_442.h:23315
PDMA_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:18372
USBH_T::HcFmNumber
__I uint32_t HcFmNumber
Definition: NUC472_442.h:26441
GPIO_T::MODE
__IO uint32_t MODE
Definition: NUC472_442.h:15165
CAN_IF_T::ARB1
__IO uint32_t ARB1
Definition: NUC472_442.h:978
PWM_T::FCAPDAT4
__I uint32_t FCAPDAT4
Definition: NUC472_442.h:19699
SDH_T::DMAINTSTS
__IO uint32_t DMAINTSTS
Definition: NUC472_442.h:22170
EMAC_T::MIIMCTL
__IO uint32_t MIIMCTL
Definition: NUC472_442.h:12529
PWM_T::DTCTL
__IO uint32_t DTCTL
Definition: NUC472_442.h:19291
EADC_T::AD1DAT3
__I uint32_t AD1DAT3
Definition: NUC472_442.h:7670
CRPT_T::TDES2_KEY3L
__IO uint32_t TDES2_KEY3L
Definition: NUC472_442.h:6253
EADC_T::AD0SPCTL7
__IO uint32_t AD0SPCTL7
Definition: NUC472_442.h:8275
EPWM_T::ASYMCMP0
__IO uint32_t ASYMCMP0
Definition: NUC472_442.h:14163
CAN_T::IPND2
__IO uint32_t IPND2
Definition: NUC472_442.h:1381
EADC_T::AD0SPCTL6
__IO uint32_t AD0SPCTL6
Definition: NUC472_442.h:8234
TIMER_T::EXTCTL
__IO uint32_t EXTCTL
Definition: NUC472_442.h:25059
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: NUC472_442.h:3120
UART_T::FUNCSEL
__IO uint32_t FUNCSEL
Definition: NUC472_442.h:25651
CRPT_T::TDES3_SADDR
__IO uint32_t TDES3_SADDR
Definition: NUC472_442.h:6483
CRPT_T::AES2_IV0
__IO uint32_t AES2_IV0
Definition: NUC472_442.h:5284
CRPT_T::AES3_IV1
__IO uint32_t AES3_IV1
Definition: NUC472_442.h:5568
UART_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:25529
USBH_T::HcFmInterval
__IO uint32_t HcFmInterval
Definition: NUC472_442.h:26412
CAP_T::PKTBA0
__IO uint32_t PKTBA0
Definition: NUC472_442.h:2120
CRPT_T::TDES3_KEY2H
__IO uint32_t TDES3_KEY2H
Definition: NUC472_442.h:6390
RTC_T::WEEKDAY
__IO uint32_t WEEKDAY
Definition: NUC472_442.h:20515
RTC_T::TAMPSTS
__IO uint32_t TAMPSTS
Definition: NUC472_442.h:20709
SYS_T::VREFCTL
__IO uint32_t VREFCTL
Definition: NUC472_442.h:23655
CRPT_T::TDES1_KEY1L
__IO uint32_t TDES1_KEY1L
Definition: NUC472_442.h:6011
CAN_T::IPND1
__IO uint32_t IPND1
Definition: NUC472_442.h:1368
PDMA_T::STOP
__O uint32_t STOP
Definition: NUC472_442.h:18267
CLK_T::CLKDCTL
__IO uint32_t CLKDCTL
Definition: NUC472_442.h:3538
EMAC_T::MIIMDAT
__IO uint32_t MIIMDAT
Definition: NUC472_442.h:12493
USBD_T::GINTSTS
__I uint32_t GINTSTS
Definition: NUC472_442.h:27327
CAN_IF_T::ARB2
__IO uint32_t ARB2
Definition: NUC472_442.h:1006
CRPT_T::AES3_KEY1
__IO uint32_t AES3_KEY1
Definition: NUC472_442.h:5430
CLK_T::CLKDIV0
__IO uint32_t CLKDIV0
Definition: NUC472_442.h:3334
SDH_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:22352
EPWM_T::MSKEN
__IO uint32_t MSKEN
Definition: NUC472_442.h:14136
SC_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:21427
WDT_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:28496
CAN_T::TEST
__IO uint32_t TEST
Definition: NUC472_442.h:1278
SYS_T::GPD_MFPL
__IO uint32_t GPD_MFPL
Definition: NUC472_442.h:23800
USBH_T::HcInterruptDisable
__IO uint32_t HcInterruptDisable
Definition: NUC472_442.h:26311
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: NUC472_442.h:14682
SC_T::ETUCTL
__IO uint32_t ETUCTL
Definition: NUC472_442.h:21372
CAN_T::BRPE
__IO uint32_t BRPE
Definition: NUC472_442.h:1291
CRPT_T::AES_CTL
__IO uint32_t AES_CTL
Definition: NUC472_442.h:4518
CRPT_T::AES1_KEY4
__IO uint32_t AES1_KEY4
Definition: NUC472_442.h:4946
USBD_EP_T::EPBUFSTART
__IO uint32_t EPBUFSTART
Definition: NUC472_442.h:27240
PWM_T::FCAPDAT5
__I uint32_t FCAPDAT5
Definition: NUC472_442.h:19723
I2S_T::CLKDIV
__IO uint32_t CLKDIV
Definition: NUC472_442.h:17302
TIMER_T::CNT
__I uint32_t CNT
Definition: NUC472_442.h:25006
SC_T::TMRCTL1
__IO uint32_t TMRCTL1
Definition: NUC472_442.h:21669
SYS_T::TEMPCTL
__IO uint32_t TEMPCTL
Definition: NUC472_442.h:23600
PDMA_T::TDSTS
__IO uint32_t TDSTS
Definition: NUC472_442.h:18402
PWM_T::TRGADCTL
__IO uint32_t TRGADCTL
Definition: NUC472_442.h:19322
SYS_T::VCID
__I uint32_t VCID
Definition: NUC472_442.h:23615
EADC_T::AD1SPCTL6
__IO uint32_t AD1SPCTL6
Definition: NUC472_442.h:8626
CRPT_T::AES0_KEY6
__IO uint32_t AES0_KEY6
Definition: NUC472_442.h:4713
RTC_T::RWEN
__O uint32_t RWEN
Definition: NUC472_442.h:20436
CAN_T::STATUS
__IO uint32_t STATUS
Definition: NUC472_442.h:1188
USBD_T::DMAADDR
__IO uint32_t DMAADDR
Definition: NUC472_442.h:27943
USBD_T::OPER
__IO uint32_t OPER
Definition: NUC472_442.h:27510
SYS_T::GPE_MFPH
__IO uint32_t GPE_MFPH
Definition: NUC472_442.h:23854
ECAP_T::CTL1
__IO uint32_t CTL1
Definition: NUC472_442.h:2622
PDMA_T::REQSEL8_11
__IO uint32_t REQSEL8_11
Definition: NUC472_442.h:18571
EADC_T::AD1TRGEN1
__IO uint32_t AD1TRGEN1
Definition: NUC472_442.h:9754
USBD_T::CEPDAT_BYTE
__IO uint8_t CEPDAT_BYTE
Definition: NUC472_442.h:27584
CRPT_T::AES0_KEY1
__IO uint32_t AES0_KEY1
Definition: NUC472_442.h:4623
SPI_T::PDMACTL
__IO uint32_t PDMACTL
Definition: NUC472_442.h:22873
USBD_T::TEST
__IO uint32_t TEST
Definition: NUC472_442.h:27557
EBI_T::KEY0
__IO uint32_t KEY0
Definition: NUC472_442.h:11651
EADC_T::AD1SPCTL3
__IO uint32_t AD1SPCTL3
Definition: NUC472_442.h:8503
SDH_T::TOUT
__IO uint32_t TOUT
Definition: NUC472_442.h:22493
ADC_T::STATUS1
__I uint32_t STATUS1
Definition: NUC472_442.h:586
USBH_T::HcControlHeadED
__IO uint32_t HcControlHeadED
Definition: NUC472_442.h:26347
CRPT_T::SHA_DGST0
__I uint32_t SHA_DGST0
Definition: NUC472_442.h:6600
CAN_IF_T::DAT_A1
__IO uint32_t DAT_A1
Definition: NUC472_442.h:1077
CRPT_T::SHA_SADDR
__IO uint32_t SHA_SADDR
Definition: NUC472_442.h:6741
CRPT_T::AES2_DADDR
__IO uint32_t AES2_DADDR
Definition: NUC472_442.h:5373
I2C_T::ADDRMSK2
__IO uint32_t ADDRMSK2
Definition: NUC472_442.h:17031
PS2_T::TXDAT1
__IO uint32_t TXDAT1
Definition: NUC472_442.h:18821
RTC_T::LXTOPCTL
__IO uint32_t LXTOPCTL
Definition: NUC472_442.h:20813
PWM_T::FCAPDAT1
__I uint32_t FCAPDAT1
Definition: NUC472_442.h:19627
SDH_T::DMAINTEN
__IO uint32_t DMAINTEN
Definition: NUC472_442.h:22151
CRPT_T::TDES2_KEY2H
__IO uint32_t TDES2_KEY2H
Definition: NUC472_442.h:6208
i2c.h
NUC472/NUC442 I2C driver header file.
i2s.h
pdma.h
NUC472/NUC442 PDMA driver header file.
ps2.h
NUC472/NUC442 PS2 Driver Header File.
pwm.h
NUC472/NUC442 PWM driver header file.
rtc.h
NUC472/NUC442 RTC driver header file.
sc.h
NUC472/NUC442 Smartcard (SC) driver header file.
scuart.h
sd.h
NUC472/NUC442 SD driver header file.
spi.h
NUC472/NUC442 SPI driver header file.
ACMP_T
Definition: NUC472_442.h:223
ADC_T
Definition: NUC472_442.h:370
CAN_IF_T
Definition: NUC472_442.h:849
CAN_T
Definition: NUC472_442.h:1125
CAP_T
Definition: NUC472_442.h:1682
CLK_T
Definition: NUC472_442.h:2781
CRC_T
Definition: NUC472_442.h:3989
CRPT_T
Definition: NUC472_442.h:4123
DSCT_T
Definition: NUC472_442.h:18121
EADC_T
Definition: NUC472_442.h:7417
EBI_T
Definition: NUC472_442.h:11569
ECAP_T
Definition: NUC472_442.h:2422
EMAC_T
Definition: NUC472_442.h:11751
EPWM_T
Definition: NUC472_442.h:13932
FMC_T
Definition: NUC472_442.h:14590
GPIO_DB_T
Definition: NUC472_442.h:16182
GPIO_T
Definition: NUC472_442.h:15010
I2C_T
Definition: NUC472_442.h:16820
I2S_T
Definition: NUC472_442.h:17175
OPA_T
Definition: NUC472_442.h:17640
OTG_T
Definition: NUC472_442.h:17746
PDMA_T
Definition: NUC472_442.h:18227
PS2_T
Definition: NUC472_442.h:18746
PWM_T
Definition: NUC472_442.h:19042
QEI_T
Definition: NUC472_442.h:20087
RTC_T
Definition: NUC472_442.h:20402
SC_T
Definition: NUC472_442.h:21114
SDH_T
Definition: NUC472_442.h:22056
SPI_T
Definition: NUC472_442.h:22695
SYS_T
Definition: NUC472_442.h:23263
TIMER_T
Definition: NUC472_442.h:24889
UART_T
Definition: NUC472_442.h:25170
USBD_EP_T
USBD endpoints register.
Definition: NUC472_442.h:26952
USBD_T
Definition: NUC472_442.h:27258
USBH_T
Definition: NUC472_442.h:26148
WDT_T
Definition: NUC472_442.h:28434
WWDT_T
Definition: NUC472_442.h:28566
sys.h
NUC472/NUC442 SYS Header File.
system_NUC472_442.h
NUC472/NUC442 system clock definition file.
timer.h
NUC472/NUC442 TIMER driver header file.
uart.h
NUC472/NUC442 UART driver header file.
usbd.h
NUC472/NUC442 USBD driver header file.
wdt.h
NUC472/NUC442 WDT driver header file.
wwdt.h
NUC472/NUC442 WWDT driver header file.