NUC472_NUC442_BSP V3.03.004
The Board Support Package for NUC472/NUC442
adc.c
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1/**************************************************************************/
12#include "NUC472_442.h"
13
55void ADC_Open(ADC_T *adc,
56 uint32_t u32InputMode,
57 uint32_t u32OpMode,
58 uint32_t u32ChMask)
59{
60
61 ADC->CTL |= u32InputMode;
62 ADC->CTL |= u32OpMode;
63 ADC->CHEN = (ADC->CHEN & ~(ADC_CHEN_CHEN_Msk | ADC_CHEN_ADBGEN_Msk | ADC_CHEN_ADTSEN_Msk)) | u32ChMask;
64 return;
65}
66
72void ADC_Close(ADC_T *adc)
73{
74 SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
75 SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
76 return;
77
78}
79
97 uint32_t u32Source,
98 uint32_t u32Param)
99{
101 if(u32Source == ADC_TRIGGER_BY_EXT_PIN)
102 {
104 ADC->CTL |= u32Source | u32Param | ADC_CTL_HWTRGEN_Msk;
105 }
106 else
107 {
109 ADC->CTL |= u32Source | (u32Param << ADC_CTL_PWMTRGDLY_Pos) | ADC_CTL_HWTRGEN_Msk;
110 }
111
112 return;
113}
114
121{
123 return;
124}
125
137void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
138{
139 if(u32Mask & ADC_ADF_INT)
140 ADC->CTL |= ADC_CTL_ADCIEN_Msk;
141 if(u32Mask & ADC_CMP0_INT)
142 ADC->CMP[0] |= ADC_CMP0_ADCMPIE_Msk;
143 if(u32Mask & ADC_CMP1_INT)
144 ADC->CMP[1] |= ADC_CMP1_ADCMPIE_Msk;
145
146 return;
147}
148
160void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
161{
162 if(u32Mask & ADC_ADF_INT)
163 ADC->CTL &= ~ADC_CTL_ADCIEN_Msk;
164 if(u32Mask & ADC_CMP0_INT)
165 ADC->CMP[0] &= ~ADC_CMP0_ADCMPIE_Msk;
166 if(u32Mask & ADC_CMP1_INT)
167 ADC->CMP[1] &= ~ADC_CMP1_ADCMPIE_Msk;
168
169 return;
170}
171
172
173 /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */
175 /* end of group NUC472_442_ADC_Driver */
177 /* end of group NUC472_442_Device_Driver */
179
180/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's d...
#define SYS_IPRST1_ADCRST_Msk
Definition: NUC472_442.h:24310
#define ADC_ADF_INT
Definition: adc.h:55
#define ADC_CMP0_INT
Definition: adc.h:56
#define ADC_TRIGGER_BY_PWM
Definition: adc.h:50
#define ADC_TRIGGER_BY_EXT_PIN
Definition: adc.h:49
#define ADC_CMP1_INT
Definition: adc.h:57
#define ADC_RISING_EDGE_TRIGGER
Definition: adc.h:54
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:96
void ADC_Close(ADC_T *adc)
Disable ADC module.
Definition: adc.c:72
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
Definition: adc.c:55
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:160
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
Definition: adc.c:120
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:137
#define ADC_CTL_HWTRGSEL_Msk
Definition: NUC472_442.h:747
#define ADC_CHEN_ADBGEN_Msk
Definition: NUC472_442.h:777
#define ADC_CMP1_ADCMPIE_Msk
Definition: NUC472_442.h:801
#define ADC_CMP0_ADCMPIE_Msk
Definition: NUC472_442.h:783
#define ADC_CTL_PWMTRGDLY_Msk
Definition: NUC472_442.h:765
#define ADC_CTL_PWMTRGDLY_Pos
Definition: NUC472_442.h:764
#define ADC_CHEN_ADTSEN_Msk
Definition: NUC472_442.h:774
#define ADC_CHEN_CHEN_Msk
Definition: NUC472_442.h:771
#define ADC_CTL_HWTRGEN_Msk
Definition: NUC472_442.h:753
#define ADC_CTL_ADCIEN_Msk
Definition: NUC472_442.h:741
#define ADC_CTL_HWTRGCOND_Msk
Definition: NUC472_442.h:750
#define ADC
Definition: NUC472_442.h:28829
#define SYS
Definition: NUC472_442.h:28797