| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

clk.h
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1/**************************************************************************/
12#ifndef __CLK_H__
13#define __CLK_H__
14
15#ifdef __cplusplus
16extern "C"
17{
18#endif
19
20
34#define FREQ_500MHZ 500000000
35#define FREQ_250MHZ 250000000
36#define FREQ_200MHZ 200000000
37#define FREQ_125MHZ 125000000
38#define FREQ_72MHZ 72000000
39#define FREQ_50MHZ 50000000
40#define FREQ_25MHZ 25000000
41#define FREQ_24MHZ 24000000
42#define FREQ_22MHZ 22000000
43#define FREQ_32KHZ 32000
44#define FREQ_10KHZ 10000
45
46/*---------------------------------------------------------------------------------------------------------*/
47/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
48/*---------------------------------------------------------------------------------------------------------*/
49#define CLK_PLLCTL_PLLSRC_HIRC (0x1UL<<CLK_PLLCTL_PLLSRC_Pos)
50#define CLK_PLLCTL_PLLSRC_HXT (0x0UL<<CLK_PLLCTL_PLLSRC_Pos)
52#define CLK_PLLCTL_NR(x) (((x)-2)<<9)
53#define CLK_PLLCTL_NF(x) ((x)-2)
55#define CLK_PLLCTL_NO_1 (0x0UL<<CLK_PLLCTL_OUTDV_Pos)
56#define CLK_PLLCTL_NO_2 (0x1UL<<CLK_PLLCTL_OUTDV_Pos)
57#define CLK_PLLCTL_NO_4 (0x3UL<<CLK_PLLCTL_OUTDV_Pos)
59#if (__HXT == 12000000)
60#define CLK_PLLCTL_FOR_I2S (0xA54)
61#define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 28) | CLK_PLLCTL_NO_2)
62#define CLK_PLLCTL_50MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 25) | CLK_PLLCTL_NO_2)
63#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF(112) | CLK_PLLCTL_NO_4)
64#define CLK_PLLCTL_36MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF( 84) | CLK_PLLCTL_NO_4)
65#define CLK_PLLCTL_32MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(6) | CLK_PLLCTL_NF( 64) | CLK_PLLCTL_NO_4)
66#define CLK_PLLCTL_24MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 16) | CLK_PLLCTL_NO_4)
67#else
68# error "The PLL pre-definitions are only valid when external crystal is 12MHz"
69#endif
70
71#define CLK_PLLCTL_50MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF( 59) | CLK_PLLCTL_NO_2)
72#define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_4)
73#define CLK_PLLCTL_36MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(12) | CLK_PLLCTL_NF( 78) | CLK_PLLCTL_NO_4)
74#define CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 9) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4)
75#define CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 3) | CLK_PLLCTL_NF( 13) | CLK_PLLCTL_NO_4)
77/*---------------------------------------------------------------------------------------------------------*/
78/* PLL2CTL constant definitions. */
79/*---------------------------------------------------------------------------------------------------------*/
80#define CLK_PLL2CTL_PLL2DIV(x) (((x)-1) << CLK_PLL2CTL_PLL2DIV_Pos)
82/*---------------------------------------------------------------------------------------------------------*/
83/* CLKSEL0 constant definitions. (Write-protection) */
84/*---------------------------------------------------------------------------------------------------------*/
85#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos)
86#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos)
87#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos)
88#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos)
89#define CLK_CLKSEL0_HCLKSEL_PLL2 (0x04UL<<CLK_CLKSEL0_HCLKSEL_Pos)
90#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos)
92#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos)
93#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos)
94#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos)
95#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos)
96#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos)
97#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)
99#define CLK_CLKSEL0_PCLKSEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos)
100#define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos)
102#define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos)
103#define CLK_CLKSEL0_USBHSEL_PLL2 (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos)
105#define CLK_CLKSEL0_CAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos)
106#define CLK_CLKSEL0_CAPSEL_PLL (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos)
107#define CLK_CLKSEL0_CAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos)
108#define CLK_CLKSEL0_CAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos)
110#define CLK_CLKSEL0_ICAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos)
111#define CLK_CLKSEL0_ICAPSEL_PLL (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos)
112#define CLK_CLKSEL0_ICAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos)
113#define CLK_CLKSEL0_ICAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos)
115#define CLK_CLKSEL0_SDHSEL_HXT (0x00UL<<CLK_CLKSEL0_SDHSEL_Pos)
116#define CLK_CLKSEL0_SDHSEL_PLL (0x01UL<<CLK_CLKSEL0_SDHSEL_Pos)
117#define CLK_CLKSEL0_SDHSEL_HCLK (0x02UL<<CLK_CLKSEL0_SDHSEL_Pos)
118#define CLK_CLKSEL0_SDHSEL_HIRC (0x03UL<<CLK_CLKSEL0_SDHSEL_Pos)
120/*---------------------------------------------------------------------------------------------------------*/
121/* CLKSEL1 constant definitions. */
122/*---------------------------------------------------------------------------------------------------------*/
123#define CLK_CLKSEL1_WDTSEL_HXT (0x0UL<<CLK_CLKSEL1_WDTSEL_Pos)
124#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)
125#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)
126#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)
128#define CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)
129#define CLK_CLKSEL1_ADCSEL_PLL (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)
130#define CLK_CLKSEL1_ADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos)
131#define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)
133#define CLK_CLKSEL1_EADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)
134#define CLK_CLKSEL1_EADCSEL_PLL (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)
135#define CLK_CLKSEL1_EADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos)
136#define CLK_CLKSEL1_EADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)
138#define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos)
139#define CLK_CLKSEL1_SPI0SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos)
141#define CLK_CLKSEL1_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI1SEL_Pos)
142#define CLK_CLKSEL1_SPI1SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI1SEL_Pos)
144#define CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos)
145#define CLK_CLKSEL1_SPI2SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos)
147#define CLK_CLKSEL1_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI3SEL_Pos)
148#define CLK_CLKSEL1_SPI3SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI3SEL_Pos)
150#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)
151#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)
152#define CLK_CLKSEL1_TMR0SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)
153#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)
154#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)
155#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos)
157#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)
158#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)
159#define CLK_CLKSEL1_TMR1SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)
160#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)
161#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)
162#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos)
164#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos)
165#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos)
166#define CLK_CLKSEL1_TMR2SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos)
167#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos)
168#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos)
169#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos)
171#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos)
172#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos)
173#define CLK_CLKSEL1_TMR3SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos)
174#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos)
175#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos)
176#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos)
178#define CLK_CLKSEL1_UARTSEL_HXT (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos)
179#define CLK_CLKSEL1_UARTSEL_PLL (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos)
180#define CLK_CLKSEL1_UARTSEL_HIRC (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos)
182#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos)
183#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos)
184#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos)
185#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos)
187#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)
188#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)
191/*---------------------------------------------------------------------------------------------------------*/
192/* CLKSEL2 constant definitions. */
193/*---------------------------------------------------------------------------------------------------------*/
194#define CLK_CLKSEL2_PWM0CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)
195#define CLK_CLKSEL2_PWM0CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)
196#define CLK_CLKSEL2_PWM0CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)
197#define CLK_CLKSEL2_PWM0CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)
198#define CLK_CLKSEL2_PWM0CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos)
200#define CLK_CLKSEL2_PWM0CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)
201#define CLK_CLKSEL2_PWM0CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)
202#define CLK_CLKSEL2_PWM0CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)
203#define CLK_CLKSEL2_PWM0CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)
204#define CLK_CLKSEL2_PWM0CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos)
206#define CLK_CLKSEL2_PWM0CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)
207#define CLK_CLKSEL2_PWM0CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)
208#define CLK_CLKSEL2_PWM0CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)
209#define CLK_CLKSEL2_PWM0CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)
210#define CLK_CLKSEL2_PWM0CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos)
212#define CLK_CLKSEL2_PWM1CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)
213#define CLK_CLKSEL2_PWM1CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)
214#define CLK_CLKSEL2_PWM1CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)
215#define CLK_CLKSEL2_PWM1CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)
216#define CLK_CLKSEL2_PWM1CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos)
218#define CLK_CLKSEL2_PWM1CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)
219#define CLK_CLKSEL2_PWM1CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)
220#define CLK_CLKSEL2_PWM1CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)
221#define CLK_CLKSEL2_PWM1CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)
222#define CLK_CLKSEL2_PWM1CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos)
224#define CLK_CLKSEL2_PWM1CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)
225#define CLK_CLKSEL2_PWM1CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)
226#define CLK_CLKSEL2_PWM1CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)
227#define CLK_CLKSEL2_PWM1CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)
228#define CLK_CLKSEL2_PWM1CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos)
230/*---------------------------------------------------------------------------------------------------------*/
231/* CLKSEL3 constant definitions. */
232/*---------------------------------------------------------------------------------------------------------*/
233#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos)
234#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos)
235#define CLK_CLKSEL3_SC0SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos)
236#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos)
238#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos)
239#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos)
240#define CLK_CLKSEL3_SC1SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos)
241#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos)
243#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos)
244#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos)
245#define CLK_CLKSEL3_SC2SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos)
246#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos)
248#define CLK_CLKSEL3_SC3SEL_HXT (0x0UL<<CLK_CLKSEL3_SC3SEL_Pos)
249#define CLK_CLKSEL3_SC3SEL_PLL (0x1UL<<CLK_CLKSEL3_SC3SEL_Pos)
250#define CLK_CLKSEL3_SC3SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC3SEL_Pos)
251#define CLK_CLKSEL3_SC3SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC3SEL_Pos)
253#define CLK_CLKSEL3_SC4SEL_HXT (0x0UL<<CLK_CLKSEL3_SC4SEL_Pos)
254#define CLK_CLKSEL3_SC4SEL_PLL (0x1UL<<CLK_CLKSEL3_SC4SEL_Pos)
255#define CLK_CLKSEL3_SC4SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC4SEL_Pos)
256#define CLK_CLKSEL3_SC4SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC4SEL_Pos)
258#define CLK_CLKSEL3_SC5SEL_HXT (0x0UL<<CLK_CLKSEL3_SC5SEL_Pos)
259#define CLK_CLKSEL3_SC5SEL_PLL (0x1UL<<CLK_CLKSEL3_SC5SEL_Pos)
260#define CLK_CLKSEL3_SC5SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC5SEL_Pos)
261#define CLK_CLKSEL3_SC5SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC5SEL_Pos)
263#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos)
264#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos)
265#define CLK_CLKSEL3_I2S0SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos)
266#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos)
268#define CLK_CLKSEL3_I2S1SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S1SEL_Pos)
269#define CLK_CLKSEL3_I2S1SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S1SEL_Pos)
270#define CLK_CLKSEL3_I2S1SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S1SEL_Pos)
271#define CLK_CLKSEL3_I2S1SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S1SEL_Pos)
273/*---------------------------------------------------------------------------------------------------------*/
274/* CLKDIV0 constant definitions. */
275/*---------------------------------------------------------------------------------------------------------*/
276#define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos)
277#define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBHDIV_Pos)
278#define CLK_CLKDIV0_UART(x) (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos)
279#define CLK_CLKDIV0_ADC(x) (((x)-1) << CLK_CLKDIV0_ADCDIV_Pos)
280#define CLK_CLKDIV0_SDH(x) (((x)-1) << CLK_CLKDIV0_SDHDIV_Pos)
282/*---------------------------------------------------------------------------------------------------------*/
283/* CLKDIV1 constant definitions. */
284/*---------------------------------------------------------------------------------------------------------*/
285#define CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos)
286#define CLK_CLKDIV1_SC1(x) (((x)-1) << CLK_CLKDIV1_SC1DIV_Pos)
287#define CLK_CLKDIV1_SC2(x) (((x)-1) << CLK_CLKDIV1_SC2DIV_Pos)
288#define CLK_CLKDIV1_SC3(x) (((x)-1) << CLK_CLKDIV1_SC3DIV_Pos)
290/*---------------------------------------------------------------------------------------------------------*/
291/* CLKDIV2 constant definitions. */
292/*---------------------------------------------------------------------------------------------------------*/
293#define CLK_CLKDIV2_SC4(x) (((x)-1) << CLK_CLKDIV2_SC4DIV_Pos)
294#define CLK_CLKDIV2_SC5(x) (((x)-1) << CLK_CLKDIV2_SC5DIV_Pos)
296/*---------------------------------------------------------------------------------------------------------*/
297/* CLKDIV3 constant definitions. */
298/*---------------------------------------------------------------------------------------------------------*/
299#define CLK_CLKDIV3_CAP(x) (((x)-1) << CLK_CLKDIV3_CAPDIV_Pos)
300#define CLK_CLKDIV3_VSENSE(x) (((x)-1) << CLK_CLKDIV3_VSENSEDIV_Pos)
301#define CLK_CLKDIV3_EMAC(x) (((x)-1) << CLK_CLKDIV3_EMACDIV_Pos)
304/*---------------------------------------------------------------------------------------------------------*/
305/* MODULE constant definitions. */
306/*---------------------------------------------------------------------------------------------------------*/
307#define MODULE_APBCLK(x) ((x >>30) & 0x3)
308#define MODULE_CLKSEL(x) ((x >>28) & 0x3)
309#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0x7)
310#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
311#define MODULE_CLKDIV(x) ((x >>18) & 0x3)
312#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
313#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
314#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
315#define MODULE_NoMsk 0x0
316#define NA MODULE_NoMsk
318#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30)
319#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28)
320#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25)
321#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
322#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
323#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
324#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
325#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
326/*--------------------------------------------------------------------------------------------------------------------------------------*/
327/* AHBCLK/APBCLK(2) | CLKSEL(2) | CLKSEL_Msk(3) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
328/*--------------------------------------------------------------------------------------------------------------------------------------*/
329#define PDMA_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_PDMACKEN_Pos)
330#define ISP_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos)
331#define EBI_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBICKEN_Pos)
332#define USBH_MODULE ((0UL<<30)|(0<<28)|(1<<25) |( 8<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_AHBCLK_USBHCKEN_Pos)
333#define EMAC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|(10<<20)|(3<<18)|(0xFF<<10) |(16<<5)|CLK_AHBCLK_EMACCKEN_Pos)
334#define SDH_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(20<<20)|(0<<18)|(0xFF<<10) |(24<<5)|CLK_AHBCLK_SDHCKEN_Pos)
335#define CRC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRCCKEN_Pos)
336#define CAP_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(16<<20)|(3<<18)|(0xFF<<10) |( 0<<5)|CLK_AHBCLK_CAPCKEN_Pos)
337#define SEN_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(3<<18)|(0xFF<<10) |( 8<<5)|CLK_AHBCLK_SENCKEN_Pos)
338#define USBD_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_USBDCKEN_Pos)
339#define CRPT_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRPTCKEN_Pos)
341#define WDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos)
342#define WWDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(30<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos)
343#define RTC_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_RTCCKEN_Pos)
344#define TMR0_MODULE ((1UL<<30)|(1<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR0CKEN_Pos)
345#define TMR1_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR1CKEN_Pos)
346#define TMR2_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR2CKEN_Pos)
347#define TMR3_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR3CKEN_Pos)
348#define CLKO_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(28<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CLKOCKEN_Pos)
349#define ACMP_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_ACMPCKEN_Pos)
350#define I2C0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C0CKEN_Pos)
351#define I2C1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C1CKEN_Pos)
352#define I2C2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C2CKEN_Pos)
353#define I2C3_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C3CKEN_Pos)
354#define SPI0_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI0CKEN_Pos)
355#define SPI1_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 5<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI1CKEN_Pos)
356#define SPI2_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI2CKEN_Pos)
357#define SPI3_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 7<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI3CKEN_Pos)
358#define UART0_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART0CKEN_Pos)
359#define UART1_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART1CKEN_Pos)
360#define UART2_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART2CKEN_Pos)
361#define UART3_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART3CKEN_Pos)
362#define UART4_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART4CKEN_Pos)
363#define UART5_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART5CKEN_Pos)
364#define CAN0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN0CKEN_Pos)
365#define CAN1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN1CKEN_Pos)
366#define OTG_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_OTGCKEN_Pos)
367#define ADC_MODULE ((1UL<<30)|(1<<28)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK0_ADCCKEN_Pos)
368#define I2S0_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S0CKEN_Pos)
369#define I2S1_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S1CKEN_Pos)
370#define PS2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_PS2CKEN_Pos)
372#define SC0_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 0<<20)|(1<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC0CKEN_Pos)
373#define SC1_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 2<<20)|(1<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC1CKEN_Pos)
374#define SC2_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 4<<20)|(1<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK1_SC2CKEN_Pos)
375#define SC3_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 6<<20)|(1<<18)|(0xFF<<10) |(24<<5)|CLK_APBCLK1_SC3CKEN_Pos)
376#define SC4_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 8<<20)|(2<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC4CKEN_Pos)
377#define SC5_MODULE ((2UL<<30)|(3<<28)|(3<<25) |(10<<20)|(2<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC5CKEN_Pos)
378#define I2C4_MODULE ((2UL<<30)|(0<<28)|(0<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos)
379#define PWM0CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH01CKEN_Pos)
380#define PWM0CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH23CKEN_Pos)
381#define PWM0CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH45CKEN_Pos)
382#define PWM1CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH01CKEN_Pos)
383#define PWM1CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH2345CKEN_Pos)
384#define PWM1CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH2345CKEN_Pos)
385#define QEI0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI0CKEN_Pos)
386#define QEI1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI1CKEN_Pos)
387#define ECAP0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP0CKEN_Pos)
388#define ECAP1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP1CKEN_Pos)
389#define EPWM0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM0CKEN_Pos)
390#define EPWM1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM1CKEN_Pos)
391#define OPA_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_OPACKEN_Pos)
392#define EADC_MODULE ((2UL<<30)|(1<<28)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK1_EADCCKEN_Pos)
394#define CLK_TIMEOUT_ERR (-1) /* end of group NUC472_442_CLK_EXPORTED_CONSTANTS */
397
398extern int32_t g_CLK_i32ErrCode;
399
404void CLK_DisableCKO(void);
405void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
406void CLK_PowerDown(void);
407void CLK_Idle(void);
408uint32_t CLK_GetHXTFreq(void);
409uint32_t CLK_GetLXTFreq(void);
410uint32_t CLK_GetHCLKFreq(void);
411uint32_t CLK_GetPCLKFreq(void);
412uint32_t CLK_GetCPUFreq(void);
413uint32_t CLK_GetPLLClockFreq(void);
414uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
415void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
416void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
417void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
418void CLK_EnableXtalRC(uint32_t u32ClkMask);
419void CLK_DisableXtalRC(uint32_t u32ClkMask);
420void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
421void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
422uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
423void CLK_DisablePLL(void);
424int32_t CLK_SysTickDelay(uint32_t us);
425uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
426void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
427void CLK_DisableSysTick(void);
428 /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
430 /* end of group NUC472_442_CLK_Driver */
432 /* end of group NUC472_442_Device_Driver */
434
435#ifdef __cplusplus
436}
437#endif
438
439#endif //__CLK_H__
440
441/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
g_CLK_i32ErrCode
int32_t g_CLK_i32ErrCode
Definition: clk.c:22
CLK_Idle
void CLK_Idle(void)
Enter to Idle mode.
Definition: clk.c:87
CLK_GetPCLKFreq
uint32_t CLK_GetPCLKFreq(void)
This function get PCLK frequency. The frequency unit is Hz.
Definition: clk.c:104
CLK_SetSysTickClockSrc
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
This function set SysTick clock source.
Definition: clk.c:790
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
Definition: clk.c:145
CLK_EnablePLL
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
Definition: clk.c:655
CLK_DisableCKO
void CLK_DisableCKO(void)
Disable frequency output function.
Definition: clk.c:34
CLK_EnableModuleClock
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
Definition: clk.c:571
CLK_EnableCKO
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:58
CLK_DisableModuleClock
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
Definition: clk.c:642
CLK_WaitClockReady
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:847
CLK_GetLXTFreq
uint32_t CLK_GetLXTFreq(void)
Get external low speed crystal clock frequency.
Definition: clk.c:131
CLK_PowerDown
void CLK_PowerDown(void)
Enter to Power-down mode.
Definition: clk.c:75
CLK_DisablePLL
void CLK_DisablePLL(void)
This function disable PLL.
Definition: clk.c:775
CLK_GetCPUFreq
uint32_t CLK_GetCPUFreq(void)
Get CPU frequency.
Definition: clk.c:156
CLK_SysTickDelay
int32_t CLK_SysTickDelay(uint32_t us)
This function execute delay function.
Definition: clk.c:804
CLK_SetHCLK
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:269
CLK_DisableXtalRC
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
Definition: clk.c:500
CLK_DisableSysTick
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:910
CLK_SetModuleClock
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:456
CLK_EnableXtalRC
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
Definition: clk.c:486
CLK_EnableSysTick
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:883
CLK_SetCoreClock
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
Definition: clk.c:210
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:166
CLK_GetHXTFreq
uint32_t CLK_GetHXTFreq(void)
Get external high speed crystal clock frequency.
Definition: clk.c:118