NUC472_NUC442_BSP V3.03.004
The Board Support Package for NUC472/NUC442
Functions
Collaboration diagram for CLK Exported Functions:

Functions

void CLK_DisableCKO (void)
 Disable frequency output function. More...
 
void CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More...
 
void CLK_PowerDown (void)
 Enter to Power-down mode. More...
 
void CLK_Idle (void)
 Enter to Idle mode. More...
 
uint32_t CLK_GetHXTFreq (void)
 Get external high speed crystal clock frequency. More...
 
uint32_t CLK_GetLXTFreq (void)
 Get external low speed crystal clock frequency. More...
 
uint32_t CLK_GetHCLKFreq (void)
 Get HCLK frequency. More...
 
uint32_t CLK_GetPCLKFreq (void)
 This function get PCLK frequency. The frequency unit is Hz. More...
 
uint32_t CLK_GetCPUFreq (void)
 Get CPU frequency. More...
 
uint32_t CLK_GetPLLClockFreq (void)
 This function get PLL frequency. The frequency unit is Hz. More...
 
uint32_t CLK_SetCoreClock (uint32_t u32Hclk)
 Set HCLK frequency. More...
 
void CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set HCLK clock source and HCLK clock divider. More...
 
void CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set selected module clock source and module clock divider. More...
 
void CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
 This function set SysTick clock source. More...
 
void CLK_EnableXtalRC (uint32_t u32ClkMask)
 This function enable clock source. More...
 
void CLK_DisableXtalRC (uint32_t u32ClkMask)
 This function disable clock source. More...
 
void CLK_EnableModuleClock (uint32_t u32ModuleIdx)
 This function enable module clock. More...
 
void CLK_DisableModuleClock (uint32_t u32ModuleIdx)
 This function disable module clock. More...
 
uint32_t CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
 This function set PLL frequency. More...
 
void CLK_DisablePLL (void)
 This function disable PLL. More...
 
int32_t CLK_SysTickDelay (uint32_t us)
 This function execute delay function. More...
 
uint32_t CLK_WaitClockReady (uint32_t u32ClkMask)
 This function check selected clock source status. More...
 
void CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
 Enable System Tick counter. More...
 
void CLK_DisableSysTick (void)
 Disable System Tick counter. More...
 

Detailed Description

Function Documentation

◆ CLK_DisableCKO()

void CLK_DisableCKO ( void  )

Disable frequency output function.

Returns
None

This function disable frequency output function.

Definition at line 34 of file clk.c.

◆ CLK_DisableModuleClock()

void CLK_DisableModuleClock ( uint32_t  u32ModuleIdx)

◆ CLK_DisablePLL()

void CLK_DisablePLL ( void  )

This function disable PLL.

Returns
None

Definition at line 775 of file clk.c.

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◆ CLK_DisableSysTick()

void CLK_DisableSysTick ( void  )

Disable System Tick counter.

Parameters
None
Returns
None

This function disable System Tick counter.

Definition at line 910 of file clk.c.

◆ CLK_DisableXtalRC()

void CLK_DisableXtalRC ( uint32_t  u32ClkMask)

This function disable clock source.

Parameters
u32ClkMaskis clock source mask. Including:
Returns
None

Definition at line 500 of file clk.c.

◆ CLK_EnableCKO()

void CLK_EnableCKO ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv,
uint32_t  u32ClkDivBy1En 
)

This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider.

Parameters
[in]u32ClkSrcis frequency divider function clock source
[in]u32ClkDivis system reset source
[in]u32ClkDivBy1Enis frequency divided by one enable.
Returns
None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. The formula is: CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 58 of file clk.c.

◆ CLK_EnableModuleClock()

void CLK_EnableModuleClock ( uint32_t  u32ModuleIdx)

◆ CLK_EnablePLL()

uint32_t CLK_EnablePLL ( uint32_t  u32PllClkSrc,
uint32_t  u32PllFreq 
)

This function set PLL frequency.

Parameters
[in]u32PllClkSrcis PLL clock source. Including :
[in]u32PllFreqis PLL frequency
Returns
None

Definition at line 655 of file clk.c.

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◆ CLK_EnableSysTick()

void CLK_EnableSysTick ( uint32_t  u32ClkSrc,
uint32_t  u32Count 
)

Enable System Tick counter.

Parameters
[in]u32ClkSrcis System Tick clock source. Including:
[in]u32Countis System Tick reload value. It could be 0~0xFFFFFF.
Returns
None

This function set System Tick clock source, reload value, enable System Tick counter and interrupt.
The register write-protection function should be disabled before using this function.

Definition at line 883 of file clk.c.

◆ CLK_EnableXtalRC()

void CLK_EnableXtalRC ( uint32_t  u32ClkMask)

This function enable clock source.

Parameters
u32ClkMaskis clock source mask. Including:
Returns
None

Definition at line 486 of file clk.c.

◆ CLK_GetCPUFreq()

uint32_t CLK_GetCPUFreq ( void  )

Get CPU frequency.

Returns
CPU frequency

This function get CPU frequency. The frequency unit is Hz.

Definition at line 156 of file clk.c.

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◆ CLK_GetHCLKFreq()

uint32_t CLK_GetHCLKFreq ( void  )

Get HCLK frequency.

Returns
HCLK frequency

This function get HCLK frequency. The frequency unit is Hz.

Definition at line 145 of file clk.c.

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◆ CLK_GetHXTFreq()

uint32_t CLK_GetHXTFreq ( void  )

Get external high speed crystal clock frequency.

Returns
External high frequency crystal frequency

This function get external high frequency crystal frequency. The frequency unit is Hz.

Definition at line 118 of file clk.c.

◆ CLK_GetLXTFreq()

uint32_t CLK_GetLXTFreq ( void  )

Get external low speed crystal clock frequency.

Returns
External low speed crystal clock frequency

This function get external low frequency crystal frequency. The frequency unit is Hz.

Definition at line 131 of file clk.c.

◆ CLK_GetPCLKFreq()

uint32_t CLK_GetPCLKFreq ( void  )

This function get PCLK frequency. The frequency unit is Hz.

Returns
PCLK frequency

Definition at line 104 of file clk.c.

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◆ CLK_GetPLLClockFreq()

uint32_t CLK_GetPLLClockFreq ( void  )

This function get PLL frequency. The frequency unit is Hz.

Returns
PLL frequency

Definition at line 166 of file clk.c.

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◆ CLK_Idle()

void CLK_Idle ( void  )

Enter to Idle mode.

Returns
None

This function let system enter to Idle mode.

Definition at line 87 of file clk.c.

◆ CLK_PowerDown()

void CLK_PowerDown ( void  )

Enter to Power-down mode.

Returns
None

This function let system enter to Power-down mode.

Definition at line 75 of file clk.c.

◆ CLK_SetCoreClock()

uint32_t CLK_SetCoreClock ( uint32_t  u32Hclk)

Set HCLK frequency.

Parameters
[in]u32Hclkis HCLK frequency
Returns
HCLK frequency

This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 MHz ~ 96 MHz.

Definition at line 210 of file clk.c.

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◆ CLK_SetHCLK()

void CLK_SetHCLK ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set HCLK clock source and HCLK clock divider.

Parameters
[in]u32ClkSrcis HCLK clock source. Including :
[in]u32ClkDivis HCLK clock divider. Including :
Returns
None

Definition at line 269 of file clk.c.

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◆ CLK_SetModuleClock()

void CLK_SetModuleClock ( uint32_t  u32ModuleIdx,
uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set selected module clock source and module clock divider.

Parameters
[in]u32ModuleIdxis module index.
[in]u32ClkSrcis module clock source.
[in]u32ClkDivis module clock divider.
Returns
None

Valid parameter combinations listed in following table:

Module index Clock source Divider
PDMA_MODULE x x
ISP_MODULE x x
EBI_MODULE x x
USBH_MODULE CLK_CLKSEL0_USBHSEL_PLL CLK_CLKDIV0_USB(x)
USBH_MODULE CLK_CLKSEL0_USBHSEL_PLL2 CLK_CLKDIV0_USB(x)
EMAC_MODULE x CLK_CLKDIV3_EMAC(x)
SDH_MODULE CLK_CLKSEL0_SDHSEL_HXT CLK_CLKDIV0_SDH(x)
SDH_MODULE CLK_CLKSEL0_SDHSEL_PLL CLK_CLKDIV0_SDH(x)
SDH_MODULE CLK_CLKSEL0_SDHSEL_HCLK CLK_CLKDIV0_SDH(x)
SDH_MODULE CLK_CLKSEL0_SDHSEL_HIRC CLK_CLKDIV0_SDH(x)
CRC_MODULE x x
CAP_MODULE CLK_CLKSEL0_CAPSEL_HXT CLK_CLKDIV3_CAP(x)
CAP_MODULE CLK_CLKSEL0_CAPSEL_PLL CLK_CLKDIV3_CAP(x)
CAP_MODULE CLK_CLKSEL0_CAPSEL_HCLK CLK_CLKDIV3_CAP(x)
CAP_MODULE CLK_CLKSEL0_CAPSEL_HIRC CLK_CLKDIV3_CAP(x)
SEN_MODULE x x
USBD_MODULE x x
CRPT_MODULE x x
ECAP1_MODULE x x
ECAP0_MODULE x x
EADC_MODULE CLK_CLKSEL1_ADCSEL_HXT CLK_CLKDIV0_ADC(x)
EADC_MODULE CLK_CLKSEL1_ADCSEL_PLL CLK_CLKDIV0_ADC(x)
EADC_MODULE CLK_CLKSEL1_ADCSEL_PCLK CLK_CLKDIV0_ADC(x)
EADC_MODULE CLK_CLKSEL1_ADCSEL_HIRC CLK_CLKDIV0_ADC(x)
OPA_MODULE x x
QEI1_MODULE x x
QEI0_MODULE x x
PWM1CH45_MODULE CLK_CLKSEL2_PWM1CH45SEL_HXT x
PWM1CH45_MODULE CLK_CLKSEL2_PWM1CH45SEL_LXT x
PWM1CH45_MODULE CLK_CLKSEL2_PWM1CH45SEL_PCLK x
PWM1CH45_MODULE CLK_CLKSEL2_PWM1CH45SEL_LIRC x
PWM1CH45_MODULE CLK_CLKSEL2_PWM1CH45SEL_HIRC x
PWM1CH23_MODULE CLK_CLKSEL2_PWM1CH23SEL_HXT x
PWM1CH23_MODULE CLK_CLKSEL2_PWM1CH23SEL_LXT x
PWM1CH23_MODULE CLK_CLKSEL2_PWM1CH23SEL_PCLK x
PWM1CH23_MODULE CLK_CLKSEL2_PWM1CH23SEL_LIRC x
PWM1CH23_MODULE CLK_CLKSEL2_PWM1CH23SEL_HIRC x
PWM1CH01_MODULE CLK_CLKSEL2_PWM1CH01SEL_HXT x
PWM1CH01_MODULE CLK_CLKSEL2_PWM1CH01SEL_LXT x
PWM1CH01_MODULE CLK_CLKSEL2_PWM1CH01SEL_PCLK x
PWM1CH01_MODULE CLK_CLKSEL2_PWM1CH01SEL_LIRC x
PWM1CH01_MODULE CLK_CLKSEL2_PWM1CH01SEL_HIRC x
PWM0CH45_MODULE CLK_CLKSEL2_PWM0CH45SEL_HXT x
PWM0CH45_MODULE CLK_CLKSEL2_PWM0CH45SEL_LXT x
PWM0CH45_MODULE CLK_CLKSEL2_PWM0CH45SEL_PCLK x
PWM0CH45_MODULE CLK_CLKSEL2_PWM0CH45SEL_LIRC x
PWM0CH45_MODULE CLK_CLKSEL2_PWM0CH45SEL_HIRC x
PWM0CH23_MODULE CLK_CLKSEL2_PWM0CH23SEL_HXT x
PWM0CH23_MODULE CLK_CLKSEL2_PWM0CH23SEL_LXT x
PWM0CH23_MODULE CLK_CLKSEL2_PWM0CH23SEL_PCLK x
PWM0CH23_MODULE CLK_CLKSEL2_PWM0CH23SEL_LIRC x
PWM0CH23_MODULE CLK_CLKSEL2_PWM0CH23SEL_HIRC x
PWM0CH01_MODULE CLK_CLKSEL2_PWM0CH01SEL_HXT x
PWM0CH01_MODULE CLK_CLKSEL2_PWM0CH01SEL_LXT x
PWM0CH01_MODULE CLK_CLKSEL2_PWM0CH01SEL_PCLK x
PWM0CH01_MODULE CLK_CLKSEL2_PWM0CH01SEL_LIRC x
PWM0CH01_MODULE CLK_CLKSEL2_PWM0CH01SEL_HIRC x
I2C4_MODULE x x
SC5_MODULE x x
SC4_MODULE x x
SC3_MODULE x x
SC2_MODULE x x
SC5_MODULE CLK_CLKSEL3_SC5SEL_HXT CLK_CLKDIV2_SC5(x)
SC5_MODULE CLK_CLKSEL3_SC5SEL_PLL CLK_CLKDIV2_SC5(x)
SC5_MODULE CLK_CLKSEL3_SC5SEL_PCLK CLK_CLKDIV2_SC5(x)
SC5_MODULE CLK_CLKSEL3_SC5SEL_HIRC CLK_CLKDIV2_SC5(x)
SC4_MODULE CLK_CLKSEL3_SC4SEL_HXT CLK_CLKDIV2_SC4(x)
SC4_MODULE CLK_CLKSEL3_SC4SEL_PLL CLK_CLKDIV2_SC4(x)
SC4_MODULE CLK_CLKSEL3_SC4SEL_PCLK CLK_CLKDIV2_SC4(x)
SC4_MODULE CLK_CLKSEL3_SC4SEL_HIRC CLK_CLKDIV2_SC4(x)
SC3_MODULE CLK_CLKSEL3_SC3SEL_HXT CLK_CLKDIV1_SC3(x)
SC3_MODULE CLK_CLKSEL3_SC3SEL_PLL CLK_CLKDIV1_SC3(x)
SC3_MODULE CLK_CLKSEL3_SC3SEL_PCLK CLK_CLKDIV1_SC3(x)
SC3_MODULE CLK_CLKSEL3_SC3SEL_HIRC CLK_CLKDIV1_SC3(x)
SC2_MODULE CLK_CLKSEL3_SC2SEL_HXT CLK_CLKDIV1_SC2(x)
SC2_MODULE CLK_CLKSEL3_SC2SEL_PLL CLK_CLKDIV1_SC2(x)
SC2_MODULE CLK_CLKSEL3_SC2SEL_PCLK CLK_CLKDIV1_SC2(x)
SC2_MODULE CLK_CLKSEL3_SC2SEL_HIRC CLK_CLKDIV1_SC2(x)
SC1_MODULE CLK_CLKSEL3_SC1SEL_HXT CLK_CLKDIV1_SC1(x)
SC1_MODULE CLK_CLKSEL3_SC1SEL_PLL CLK_CLKDIV1_SC1(x)
SC1_MODULE CLK_CLKSEL3_SC1SEL_PCLK CLK_CLKDIV1_SC1(x)
SC1_MODULE CLK_CLKSEL3_SC1SEL_HIRC CLK_CLKDIV1_SC1(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_HXT CLK_CLKDIV1_SC0(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_PLL CLK_CLKDIV1_SC0(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_PCLK CLK_CLKDIV1_SC0(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_HIRC CLK_CLKDIV1_SC0(x)
PS2_MODULE CLK_CLKSEL3_I2S1SEL_HXT x
I2S1_MODULE CLK_CLKSEL3_I2S1SEL_HXT x
I2S1_MODULE CLK_CLKSEL3_I2S1SEL_PLL x
I2S1_MODULE CLK_CLKSEL3_I2S1SEL_PCLK x
I2S1_MODULE CLK_CLKSEL3_I2S1SEL_HIRC x
I2S0_MODULE CLK_CLKSEL3_I2S0SEL_HXT x
I2S0_MODULE CLK_CLKSEL3_I2S0SEL_PLL x
I2S0_MODULE CLK_CLKSEL3_I2S0SEL_PCLK x
I2S0_MODULE CLK_CLKSEL3_I2S0SEL_HIRC x
ADC_MODULE CLK_CLKSEL1_ADCSEL_HXT CLK_CLKDIV0_ADC(x)
ADC_MODULE CLK_CLKSEL1_ADCSEL_PLL CLK_CLKDIV0_ADC(x)
ADC_MODULE CLK_CLKSEL1_ADCSEL_PCLK CLK_CLKDIV0_ADC(x)
ADC_MODULE CLK_CLKSEL1_ADCSEL_HIRC CLK_CLKDIV0_ADC(x)
OTG_MODULE x x
CAN1_MODULE x x
CAN0_MODULE x x
UART5_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART5_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART5_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART4_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART4_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART4_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART3_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART3_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART3_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART2_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART2_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART2_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART1_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART1_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART1_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART0_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART0_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART0_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
SPI3_MODULE CLK_CLKSEL1_SPI3SEL_PLL x
SPI3_MODULE CLK_CLKSEL1_SPI3SEL_PCLK x
SPI2_MODULE CLK_CLKSEL1_SPI2SEL_PLL x
SPI2_MODULE CLK_CLKSEL1_SPI2SEL_PCLK x
SPI1_MODULE CLK_CLKSEL1_SPI1SEL_PLL x
SPI1_MODULE CLK_CLKSEL1_SPI1SEL_PCLK x
SPI0_MODULE CLK_CLKSEL1_SPI0SEL_PLL x
SPI0_MODULE CLK_CLKSEL1_SPI0SEL_PCLK x
I2C3_MODULE x x
I2C2_MODULE x x
I2C1_MODULE x x
I2C0_MODULE x x
ACMP_MODULE x x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_HXT x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_LXT x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_HCLK x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_HIRC x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_HXT x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_LXT x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_PCLK x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_LIRC x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_EXT x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_HIRC x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_HXT x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_LXT x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_PCLK x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_LIRC x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_EXT x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_HIRC x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_HXT x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_LXT x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_PCLK x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_LIRC x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_EXT x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_HIRC x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_HXT x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_LXT x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_PCLK x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_LIRC x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_EXT x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_HIRC x
RTC_MODULE x x
WWDT_MODULE CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 x
WWDT_MODULE CLK_CLKSEL1_WWDTSEL_LIRC x
WDT_MODULE CLK_CLKSEL1_WDTSEL_LXT x
WDT_MODULE CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 x
WDT_MODULE CLK_CLKSEL1_WDTSEL_LIRC x

Definition at line 456 of file clk.c.

◆ CLK_SetSysTickClockSrc()

void CLK_SetSysTickClockSrc ( uint32_t  u32ClkSrc)

This function set SysTick clock source.

Parameters
[in]u32ClkSrcis SysTick clock source. Including :
Returns
None

Definition at line 790 of file clk.c.

◆ CLK_SysTickDelay()

int32_t CLK_SysTickDelay ( uint32_t  us)

This function execute delay function.

Parameters
[in]usDelay time. The Max value is 2^24 / CPU Clock(MHz). Ex: 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
Returns
Delay success or not
Return values
0Success, target delay time reached

Use the SysTick to generate the delay time and the UNIT is in us. The SysTick clock source is from HCLK, i.e the same as system core clock. User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.

Definition at line 804 of file clk.c.

◆ CLK_WaitClockReady()

uint32_t CLK_WaitClockReady ( uint32_t  u32ClkMask)

This function check selected clock source status.

Parameters
[in]u32ClkMaskis selected clock source. Including
Returns
0 clock is not stable 1 clock is stable

To wait for clock ready by specified CLKSTATUS bit or timeout (~500ms)

Note
This function sets g_CLK_i32ErrCode to CLK_TIMEOUT_ERR if clock source status is not stable

Definition at line 847 of file clk.c.

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