| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

Modules | Macros | Variables
CLK Exported Constants
NUC472/NUC442 Device Driver » CLK Driver
Collaboration diagram for CLK Exported Constants:

## Modules
| CLK Exported Functions

## Macros
#define | FREQ_500MHZ 500000000
#define | FREQ_250MHZ 250000000
#define | FREQ_200MHZ 200000000
#define | FREQ_125MHZ 125000000
#define | FREQ_72MHZ 72000000
#define | FREQ_50MHZ 50000000
#define | FREQ_25MHZ 25000000
#define | FREQ_24MHZ 24000000
#define | FREQ_22MHZ 22000000
#define | FREQ_32KHZ 32000
#define | FREQ_10KHZ 10000
#define | CLK_PLLCTL_PLLSRC_HIRC
#define | CLK_PLLCTL_PLLSRC_HXT
#define | CLK_PLLCTL_NR(x)
#define | CLK_PLLCTL_NF(x)
#define | CLK_PLLCTL_NO_1
#define | CLK_PLLCTL_NO_2
#define | CLK_PLLCTL_NO_4
#define | CLK_PLLCTL_50MHz_HIRC
#define | CLK_PLLCTL_48MHz_HIRC
#define | CLK_PLLCTL_36MHz_HIRC
#define | CLK_PLLCTL_32MHz_HIRC
#define | CLK_PLLCTL_24MHz_HIRC
#define | CLK_PLL2CTL_PLL2DIV(x)
#define | CLK_CLKSEL0_HCLKSEL_HXT
#define | CLK_CLKSEL0_HCLKSEL_LXT
#define | CLK_CLKSEL0_HCLKSEL_PLL
#define | CLK_CLKSEL0_HCLKSEL_LIRC
#define | CLK_CLKSEL0_HCLKSEL_PLL2
#define | CLK_CLKSEL0_HCLKSEL_HIRC
#define | CLK_CLKSEL0_STCLKSEL_HXT
#define | CLK_CLKSEL0_STCLKSEL_LXT
#define | CLK_CLKSEL0_STCLKSEL_HXT_DIV2
#define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
#define | CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
#define | CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)
#define | CLK_CLKSEL0_PCLKSEL_HCLK
#define | CLK_CLKSEL0_PCLKSEL_HCLK_DIV2
#define | CLK_CLKSEL0_USBHSEL_PLL
#define | CLK_CLKSEL0_USBHSEL_PLL2
#define | CLK_CLKSEL0_CAPSEL_HXT
#define | CLK_CLKSEL0_CAPSEL_PLL
#define | CLK_CLKSEL0_CAPSEL_HCLK
#define | CLK_CLKSEL0_CAPSEL_HIRC
#define | CLK_CLKSEL0_ICAPSEL_HXT
#define | CLK_CLKSEL0_ICAPSEL_PLL
#define | CLK_CLKSEL0_ICAPSEL_HCLK
#define | CLK_CLKSEL0_ICAPSEL_HIRC
#define | CLK_CLKSEL0_SDHSEL_HXT
#define | CLK_CLKSEL0_SDHSEL_PLL
#define | CLK_CLKSEL0_SDHSEL_HCLK
#define | CLK_CLKSEL0_SDHSEL_HIRC
#define | CLK_CLKSEL1_WDTSEL_HXT
#define | CLK_CLKSEL1_WDTSEL_LXT
#define | CLK_CLKSEL1_WDTSEL_HCLK_DIV2048
#define | CLK_CLKSEL1_WDTSEL_LIRC
#define | CLK_CLKSEL1_ADCSEL_HXT
#define | CLK_CLKSEL1_ADCSEL_PLL
#define | CLK_CLKSEL1_ADCSEL_PCLK
#define | CLK_CLKSEL1_ADCSEL_HIRC
#define | CLK_CLKSEL1_EADCSEL_HXT
#define | CLK_CLKSEL1_EADCSEL_PLL
#define | CLK_CLKSEL1_EADCSEL_PCLK
#define | CLK_CLKSEL1_EADCSEL_HIRC
#define | CLK_CLKSEL1_SPI0SEL_PLL
#define | CLK_CLKSEL1_SPI0SEL_PCLK
#define | CLK_CLKSEL1_SPI1SEL_PLL
#define | CLK_CLKSEL1_SPI1SEL_PCLK
#define | CLK_CLKSEL1_SPI2SEL_PLL
#define | CLK_CLKSEL1_SPI2SEL_PCLK
#define | CLK_CLKSEL1_SPI3SEL_PLL
#define | CLK_CLKSEL1_SPI3SEL_PCLK
#define | CLK_CLKSEL1_TMR0SEL_HXT
#define | CLK_CLKSEL1_TMR0SEL_LXT
#define | CLK_CLKSEL1_TMR0SEL_PCLK
#define | CLK_CLKSEL1_TMR0SEL_EXT
#define | CLK_CLKSEL1_TMR0SEL_LIRC
#define | CLK_CLKSEL1_TMR0SEL_HIRC
#define | CLK_CLKSEL1_TMR1SEL_HXT
#define | CLK_CLKSEL1_TMR1SEL_LXT
#define | CLK_CLKSEL1_TMR1SEL_PCLK
#define | CLK_CLKSEL1_TMR1SEL_EXT
#define | CLK_CLKSEL1_TMR1SEL_LIRC
#define | CLK_CLKSEL1_TMR1SEL_HIRC
#define | CLK_CLKSEL1_TMR2SEL_HXT
#define | CLK_CLKSEL1_TMR2SEL_LXT
#define | CLK_CLKSEL1_TMR2SEL_PCLK
#define | CLK_CLKSEL1_TMR2SEL_EXT
#define | CLK_CLKSEL1_TMR2SEL_LIRC
#define | CLK_CLKSEL1_TMR2SEL_HIRC
#define | CLK_CLKSEL1_TMR3SEL_HXT
#define | CLK_CLKSEL1_TMR3SEL_LXT
#define | CLK_CLKSEL1_TMR3SEL_PCLK
#define | CLK_CLKSEL1_TMR3SEL_EXT
#define | CLK_CLKSEL1_TMR3SEL_LIRC
#define | CLK_CLKSEL1_TMR3SEL_HIRC
#define | CLK_CLKSEL1_UARTSEL_HXT
#define | CLK_CLKSEL1_UARTSEL_PLL
#define | CLK_CLKSEL1_UARTSEL_HIRC
#define | CLK_CLKSEL1_CLKOSEL_HXT
#define | CLK_CLKSEL1_CLKOSEL_LXT
#define | CLK_CLKSEL1_CLKOSEL_HCLK
#define | CLK_CLKSEL1_CLKOSEL_HIRC
#define | CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048
#define | CLK_CLKSEL1_WWDTSEL_LIRC
#define | CLK_CLKSEL2_PWM0CH01SEL_HXT
#define | CLK_CLKSEL2_PWM0CH01SEL_LXT
#define | CLK_CLKSEL2_PWM0CH01SEL_PCLK
#define | CLK_CLKSEL2_PWM0CH01SEL_HIRC
#define | CLK_CLKSEL2_PWM0CH01SEL_LIRC
#define | CLK_CLKSEL2_PWM0CH23SEL_HXT
#define | CLK_CLKSEL2_PWM0CH23SEL_LXT
#define | CLK_CLKSEL2_PWM0CH23SEL_PCLK
#define | CLK_CLKSEL2_PWM0CH23SEL_HIRC
#define | CLK_CLKSEL2_PWM0CH23SEL_LIRC
#define | CLK_CLKSEL2_PWM0CH45SEL_HXT
#define | CLK_CLKSEL2_PWM0CH45SEL_LXT
#define | CLK_CLKSEL2_PWM0CH45SEL_PCLK
#define | CLK_CLKSEL2_PWM0CH45SEL_HIRC
#define | CLK_CLKSEL2_PWM0CH45SEL_LIRC
#define | CLK_CLKSEL2_PWM1CH01SEL_HXT
#define | CLK_CLKSEL2_PWM1CH01SEL_LXT
#define | CLK_CLKSEL2_PWM1CH01SEL_PCLK
#define | CLK_CLKSEL2_PWM1CH01SEL_HIRC
#define | CLK_CLKSEL2_PWM1CH01SEL_LIRC
#define | CLK_CLKSEL2_PWM1CH23SEL_HXT
#define | CLK_CLKSEL2_PWM1CH23SEL_LXT
#define | CLK_CLKSEL2_PWM1CH23SEL_PCLK
#define | CLK_CLKSEL2_PWM1CH23SEL_HIRC
#define | CLK_CLKSEL2_PWM1CH23SEL_LIRC
#define | CLK_CLKSEL2_PWM1CH45SEL_HXT
#define | CLK_CLKSEL2_PWM1CH45SEL_LXT
#define | CLK_CLKSEL2_PWM1CH45SEL_PCLK
#define | CLK_CLKSEL2_PWM1CH45SEL_HIRC
#define | CLK_CLKSEL2_PWM1CH45SEL_LIRC
#define | CLK_CLKSEL3_SC0SEL_HXT
#define | CLK_CLKSEL3_SC0SEL_PLL
#define | CLK_CLKSEL3_SC0SEL_PCLK
#define | CLK_CLKSEL3_SC0SEL_HIRC
#define | CLK_CLKSEL3_SC1SEL_HXT
#define | CLK_CLKSEL3_SC1SEL_PLL
#define | CLK_CLKSEL3_SC1SEL_PCLK
#define | CLK_CLKSEL3_SC1SEL_HIRC
#define | CLK_CLKSEL3_SC2SEL_HXT
#define | CLK_CLKSEL3_SC2SEL_PLL
#define | CLK_CLKSEL3_SC2SEL_PCLK
#define | CLK_CLKSEL3_SC2SEL_HIRC
#define | CLK_CLKSEL3_SC3SEL_HXT
#define | CLK_CLKSEL3_SC3SEL_PLL
#define | CLK_CLKSEL3_SC3SEL_PCLK
#define | CLK_CLKSEL3_SC3SEL_HIRC
#define | CLK_CLKSEL3_SC4SEL_HXT
#define | CLK_CLKSEL3_SC4SEL_PLL
#define | CLK_CLKSEL3_SC4SEL_PCLK
#define | CLK_CLKSEL3_SC4SEL_HIRC
#define | CLK_CLKSEL3_SC5SEL_HXT
#define | CLK_CLKSEL3_SC5SEL_PLL
#define | CLK_CLKSEL3_SC5SEL_PCLK
#define | CLK_CLKSEL3_SC5SEL_HIRC
#define | CLK_CLKSEL3_I2S0SEL_HXT
#define | CLK_CLKSEL3_I2S0SEL_PLL
#define | CLK_CLKSEL3_I2S0SEL_PCLK
#define | CLK_CLKSEL3_I2S0SEL_HIRC
#define | CLK_CLKSEL3_I2S1SEL_HXT
#define | CLK_CLKSEL3_I2S1SEL_PLL
#define | CLK_CLKSEL3_I2S1SEL_PCLK
#define | CLK_CLKSEL3_I2S1SEL_HIRC
#define | CLK_CLKDIV0_HCLK(x)
#define | CLK_CLKDIV0_USB(x)
#define | CLK_CLKDIV0_UART(x)
#define | CLK_CLKDIV0_ADC(x)
#define | CLK_CLKDIV0_SDH(x)
#define | CLK_CLKDIV1_SC0(x)
#define | CLK_CLKDIV1_SC1(x)
#define | CLK_CLKDIV1_SC2(x)
#define | CLK_CLKDIV1_SC3(x)
#define | CLK_CLKDIV2_SC4(x)
#define | CLK_CLKDIV2_SC5(x)
#define | CLK_CLKDIV3_CAP(x)
#define | CLK_CLKDIV3_VSENSE(x)
#define | CLK_CLKDIV3_EMAC(x)
#define | MODULE_APBCLK(x)
#define | MODULE_CLKSEL(x)
#define | MODULE_CLKSEL_Msk(x)
#define | MODULE_CLKSEL_Pos(x)
#define | MODULE_CLKDIV(x)
#define | MODULE_CLKDIV_Msk(x)
#define | MODULE_CLKDIV_Pos(x)
#define | MODULE_IP_EN_Pos(x)
#define | MODULE_NoMsk
#define | NA
#define | MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30)
#define | MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28)
#define | MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25)
#define | MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
#define | MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
#define | MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
#define | MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
#define | MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
#define | PDMA_MODULE
#define | ISP_MODULE
#define | EBI_MODULE
#define | USBH_MODULE
#define | EMAC_MODULE
#define | SDH_MODULE
#define | CRC_MODULE
#define | CAP_MODULE
#define | SEN_MODULE
#define | USBD_MODULE
#define | CRPT_MODULE
#define | WDT_MODULE
#define | WWDT_MODULE
#define | RTC_MODULE
#define | TMR0_MODULE
#define | TMR1_MODULE
#define | TMR2_MODULE
#define | TMR3_MODULE
#define | CLKO_MODULE
#define | ACMP_MODULE
#define | I2C0_MODULE
#define | I2C1_MODULE
#define | I2C2_MODULE
#define | I2C3_MODULE
#define | SPI0_MODULE
#define | SPI1_MODULE
#define | SPI2_MODULE
#define | SPI3_MODULE
#define | UART0_MODULE
#define | UART1_MODULE
#define | UART2_MODULE
#define | UART3_MODULE
#define | UART4_MODULE
#define | UART5_MODULE
#define | CAN0_MODULE
#define | CAN1_MODULE
#define | OTG_MODULE
#define | ADC_MODULE
#define | I2S0_MODULE
#define | I2S1_MODULE
#define | PS2_MODULE
#define | SC0_MODULE
#define | SC1_MODULE
#define | SC2_MODULE
#define | SC3_MODULE
#define | SC4_MODULE
#define | SC5_MODULE
#define | I2C4_MODULE ((2UL<<30)|(0<<28)|(0<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos)
#define | PWM0CH01_MODULE
#define | PWM0CH23_MODULE
#define | PWM0CH45_MODULE
#define | PWM1CH01_MODULE
#define | PWM1CH23_MODULE
#define | PWM1CH45_MODULE
#define | QEI0_MODULE
#define | QEI1_MODULE
#define | ECAP0_MODULE
#define | ECAP1_MODULE
#define | EPWM0_MODULE
#define | EPWM1_MODULE
#define | OPA_MODULE
#define | EADC_MODULE
#define | CLK_TIMEOUT_ERR

## Variables
int32_t | g_CLK_i32ErrCode

## Detailed Description

## Macro Definition Documentation

## ◆ ACMP_MODULE

#define ACMP_MODULE

ACMP Module

Definition at line 349 of file clk.h.

## ◆ ADC_MODULE

#define ADC_MODULE

ADC Module

Definition at line 367 of file clk.h.

## ◆ CAN0_MODULE

#define CAN0_MODULE

CAN0 Module

Definition at line 364 of file clk.h.

## ◆ CAN1_MODULE

#define CAN1_MODULE

CAN1 Module

Definition at line 365 of file clk.h.

## ◆ CAP_MODULE

#define CAP_MODULE

CAP Module

Definition at line 336 of file clk.h.

## ◆ CLK_CLKDIV0_ADC

#define CLK_CLKDIV0_ADC | ( |  | x | ) |

CLKDIV Setting for ADC clock divider. It could be 1~256

Definition at line 279 of file clk.h.

## ◆ CLK_CLKDIV0_HCLK

#define CLK_CLKDIV0_HCLK | ( |  | x | ) |

CLKDIV Setting for HCLK clock divider. It could be 1~16

Definition at line 276 of file clk.h.

## ◆ CLK_CLKDIV0_SDH

#define CLK_CLKDIV0_SDH | ( |  | x | ) |

CLKDIV Setting for SDIO clock divider. It could be 1~256

Definition at line 280 of file clk.h.

## ◆ CLK_CLKDIV0_UART

#define CLK_CLKDIV0_UART | ( |  | x | ) |

CLKDIV Setting for UR clock divider. It could be 1~16

Definition at line 278 of file clk.h.

## ◆ CLK_CLKDIV0_USB

#define CLK_CLKDIV0_USB | ( |  | x | ) |

CLKDIV Setting for USB clock divider. It could be 1~16

Definition at line 277 of file clk.h.

## ◆ CLK_CLKDIV1_SC0

#define CLK_CLKDIV1_SC0 | ( |  | x | ) |

CLKDIV Setting for SC0 clock divider. It could be 1~256

Definition at line 285 of file clk.h.

## ◆ CLK_CLKDIV1_SC1

#define CLK_CLKDIV1_SC1 | ( |  | x | ) |

CLKDIV Setting for SC1 clock divider. It could be 1~256

Definition at line 286 of file clk.h.

## ◆ CLK_CLKDIV1_SC2

#define CLK_CLKDIV1_SC2 | ( |  | x | ) |

CLKDIV Setting for SC2 clock divider. It could be 1~256

Definition at line 287 of file clk.h.

## ◆ CLK_CLKDIV1_SC3

#define CLK_CLKDIV1_SC3 | ( |  | x | ) |

CLKDIV Setting for SC3 clock divider. It could be 1~256

Definition at line 288 of file clk.h.

## ◆ CLK_CLKDIV2_SC4

#define CLK_CLKDIV2_SC4 | ( |  | x | ) |

CLKDIV Setting for SC4 clock divider. It could be 1~256

Definition at line 293 of file clk.h.

## ◆ CLK_CLKDIV2_SC5

#define CLK_CLKDIV2_SC5 | ( |  | x | ) |

CLKDIV Setting for SC5 clock divider. It could be 1~256

Definition at line 294 of file clk.h.

## ◆ CLK_CLKDIV3_CAP

#define CLK_CLKDIV3_CAP | ( |  | x | ) |

CLKDIV Setting for CAP Engine clock divider. It could be 1~256

Definition at line 299 of file clk.h.

## ◆ CLK_CLKDIV3_EMAC

#define CLK_CLKDIV3_EMAC | ( |  | x | ) |

CLKDIV Setting for EMAC_MDCLK clock divider. It could be 1~256

Definition at line 301 of file clk.h.

## ◆ CLK_CLKDIV3_VSENSE

#define CLK_CLKDIV3_VSENSE | ( |  | x | ) |

CLKDIV Setting for Video Pixel clock divider. It could be 1~256

Definition at line 300 of file clk.h.

## ◆ CLK_CLKSEL0_CAPSEL_HCLK

#define CLK_CLKSEL0_CAPSEL_HCLK

Setting clock source as HCLK

Definition at line 107 of file clk.h.

## ◆ CLK_CLKSEL0_CAPSEL_HIRC

#define CLK_CLKSEL0_CAPSEL_HIRC

Setting clock source as internal 22.1184MHz RC clock

Definition at line 108 of file clk.h.

## ◆ CLK_CLKSEL0_CAPSEL_HXT

#define CLK_CLKSEL0_CAPSEL_HXT

Setting clock source as external XTAL

Definition at line 105 of file clk.h.

## ◆ CLK_CLKSEL0_CAPSEL_PLL

#define CLK_CLKSEL0_CAPSEL_PLL

Setting clock source as PLL

Definition at line 106 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HIRC

#define CLK_CLKSEL0_HCLKSEL_HIRC

Setting clock source as internal 22.1184MHz RC clock

Definition at line 90 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HXT

#define CLK_CLKSEL0_HCLKSEL_HXT

Setting clock source as external XTAL

Definition at line 85 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LIRC

#define CLK_CLKSEL0_HCLKSEL_LIRC

Setting clock source as internal 10KHz RC clock

Definition at line 88 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LXT

#define CLK_CLKSEL0_HCLKSEL_LXT

Setting clock source as external XTAL 32.768KHz

Definition at line 86 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_PLL

#define CLK_CLKSEL0_HCLKSEL_PLL

Setting clock source as PLL output

Definition at line 87 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_PLL2

#define CLK_CLKSEL0_HCLKSEL_PLL2

Setting clock source as USBPLL clock

Definition at line 89 of file clk.h.

## ◆ CLK_CLKSEL0_ICAPSEL_HCLK

#define CLK_CLKSEL0_ICAPSEL_HCLK

Setting clock source as HCLK

Definition at line 112 of file clk.h.

## ◆ CLK_CLKSEL0_ICAPSEL_HIRC

#define CLK_CLKSEL0_ICAPSEL_HIRC

Setting clock source as internal 22.1184MHz RC clock

Definition at line 113 of file clk.h.

## ◆ CLK_CLKSEL0_ICAPSEL_HXT

#define CLK_CLKSEL0_ICAPSEL_HXT

Setting clock source as external XTAL

Definition at line 110 of file clk.h.

## ◆ CLK_CLKSEL0_ICAPSEL_PLL

#define CLK_CLKSEL0_ICAPSEL_PLL

Setting clock source as PLL

Definition at line 111 of file clk.h.

## ◆ CLK_CLKSEL0_PCLKSEL_HCLK

#define CLK_CLKSEL0_PCLKSEL_HCLK

Setting clock source as HCLK

Definition at line 99 of file clk.h.

## ◆ CLK_CLKSEL0_PCLKSEL_HCLK_DIV2

#define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2

Setting clock source as HCLK/2

Definition at line 100 of file clk.h.

## ◆ CLK_CLKSEL0_SDHSEL_HCLK

#define CLK_CLKSEL0_SDHSEL_HCLK

Setting clock source as HCLK

Definition at line 117 of file clk.h.

## ◆ CLK_CLKSEL0_SDHSEL_HIRC

#define CLK_CLKSEL0_SDHSEL_HIRC

Setting clock source as internal 22.1184MHz RC clock

Definition at line 118 of file clk.h.

## ◆ CLK_CLKSEL0_SDHSEL_HXT

#define CLK_CLKSEL0_SDHSEL_HXT

Setting clock source as external XTAL

Definition at line 115 of file clk.h.

## ◆ CLK_CLKSEL0_SDHSEL_PLL

#define CLK_CLKSEL0_SDHSEL_PLL

Setting clock source as PLL2

Definition at line 116 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK

#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)

Setting SysTick clock source as HCLK

Definition at line 97 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK_DIV2

#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2

Setting clock source as HCLK/2

Definition at line 95 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

Setting clock source as internal 22.1184MHz RC clock/2

Definition at line 96 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HXT

#define CLK_CLKSEL0_STCLKSEL_HXT

Setting clock source as external XTAL

Definition at line 92 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HXT_DIV2

#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2

Setting clock source as external XTAL/2

Definition at line 94 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_LXT

#define CLK_CLKSEL0_STCLKSEL_LXT

Setting clock source as external XTAL 32.768KHz

Definition at line 93 of file clk.h.

## ◆ CLK_CLKSEL0_USBHSEL_PLL

#define CLK_CLKSEL0_USBHSEL_PLL

Setting clock source as PLL

Definition at line 102 of file clk.h.

## ◆ CLK_CLKSEL0_USBHSEL_PLL2

#define CLK_CLKSEL0_USBHSEL_PLL2

Setting clock source as PLL2

Definition at line 103 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_HIRC

#define CLK_CLKSEL1_ADCSEL_HIRC

Setting ADC clock source as internal 22.1184MHz RC clock

Definition at line 131 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_HXT

#define CLK_CLKSEL1_ADCSEL_HXT

Setting ADC clock source as external XTAL

Definition at line 128 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_PCLK

#define CLK_CLKSEL1_ADCSEL_PCLK

Setting ADC clock source as PCLK

Definition at line 130 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_PLL

#define CLK_CLKSEL1_ADCSEL_PLL

Setting ADC clock source as PLL

Definition at line 129 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_HCLK

#define CLK_CLKSEL1_CLKOSEL_HCLK

Setting CLKO clock source as HCLK

Definition at line 184 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_HIRC

#define CLK_CLKSEL1_CLKOSEL_HIRC

Setting CLKO clock source as external internal 22.1184MHz RC clock

Definition at line 185 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_HXT

#define CLK_CLKSEL1_CLKOSEL_HXT

Setting CLKO clock source as external XTAL

Definition at line 182 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_LXT

#define CLK_CLKSEL1_CLKOSEL_LXT

Setting CLKO clock source as external XTAL 32.768KHz

Definition at line 183 of file clk.h.

## ◆ CLK_CLKSEL1_EADCSEL_HIRC

#define CLK_CLKSEL1_EADCSEL_HIRC

Setting EADC clock source as internal 22.1184MHz RC clock

Definition at line 136 of file clk.h.

## ◆ CLK_CLKSEL1_EADCSEL_HXT

#define CLK_CLKSEL1_EADCSEL_HXT

Setting EADC clock source as external XTAL

Definition at line 133 of file clk.h.

## ◆ CLK_CLKSEL1_EADCSEL_PCLK

#define CLK_CLKSEL1_EADCSEL_PCLK

Setting EADC clock source as PCLK

Definition at line 135 of file clk.h.

## ◆ CLK_CLKSEL1_EADCSEL_PLL

#define CLK_CLKSEL1_EADCSEL_PLL

Setting EADC clock source as PLL

Definition at line 134 of file clk.h.

## ◆ CLK_CLKSEL1_SPI0SEL_PCLK

#define CLK_CLKSEL1_SPI0SEL_PCLK

Setting SPI0 clock source as PCLK

Definition at line 139 of file clk.h.

## ◆ CLK_CLKSEL1_SPI0SEL_PLL

#define CLK_CLKSEL1_SPI0SEL_PLL

Setting SPI0 clock source as PLL

Definition at line 138 of file clk.h.

## ◆ CLK_CLKSEL1_SPI1SEL_PCLK

#define CLK_CLKSEL1_SPI1SEL_PCLK

Setting SPI1 clock source as PCLK

Definition at line 142 of file clk.h.

## ◆ CLK_CLKSEL1_SPI1SEL_PLL

#define CLK_CLKSEL1_SPI1SEL_PLL

Setting SPI1 clock source as PLL

Definition at line 141 of file clk.h.

## ◆ CLK_CLKSEL1_SPI2SEL_PCLK

#define CLK_CLKSEL1_SPI2SEL_PCLK

Setting SPI2 clock source as PCLK

Definition at line 145 of file clk.h.

## ◆ CLK_CLKSEL1_SPI2SEL_PLL

#define CLK_CLKSEL1_SPI2SEL_PLL

Setting SPI2 clock source as PLL

Definition at line 144 of file clk.h.

## ◆ CLK_CLKSEL1_SPI3SEL_PCLK

#define CLK_CLKSEL1_SPI3SEL_PCLK

Setting SPI3 clock source as PCLK

Definition at line 148 of file clk.h.

## ◆ CLK_CLKSEL1_SPI3SEL_PLL

#define CLK_CLKSEL1_SPI3SEL_PLL

Setting SPI3 clock source as PLL

Definition at line 147 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_EXT

#define CLK_CLKSEL1_TMR0SEL_EXT

Setting Timer 0 clock source as external trigger

Definition at line 153 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HIRC

#define CLK_CLKSEL1_TMR0SEL_HIRC

Setting Timer 0 clock source as internal 22.1184MHz RC clock

Definition at line 155 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HXT

#define CLK_CLKSEL1_TMR0SEL_HXT

Setting Timer 0 clock source as external XTAL

Definition at line 150 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_LIRC

#define CLK_CLKSEL1_TMR0SEL_LIRC

Setting Timer 0 clock source as internal 10KHz RC clock

Definition at line 154 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_LXT

#define CLK_CLKSEL1_TMR0SEL_LXT

Setting Timer 0 clock source as external XTAL 32.768KHz

Definition at line 151 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_PCLK

#define CLK_CLKSEL1_TMR0SEL_PCLK

Setting Timer 0 clock source as PCLK

Definition at line 152 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_EXT

#define CLK_CLKSEL1_TMR1SEL_EXT

Setting Timer 1 clock source as external trigger

Definition at line 160 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HIRC

#define CLK_CLKSEL1_TMR1SEL_HIRC

Setting Timer 1 clock source as internal 22.1184MHz RC clock

Definition at line 162 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HXT

#define CLK_CLKSEL1_TMR1SEL_HXT

Setting Timer 1 clock source as external XTAL

Definition at line 157 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_LIRC

#define CLK_CLKSEL1_TMR1SEL_LIRC

Setting Timer 1 clock source as internal 10KHz RC clock

Definition at line 161 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_LXT

#define CLK_CLKSEL1_TMR1SEL_LXT

Setting Timer 1 clock source as external XTAL 32.768KHz

Definition at line 158 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_PCLK

#define CLK_CLKSEL1_TMR1SEL_PCLK

Setting Timer 1 clock source as PCLK

Definition at line 159 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_EXT

#define CLK_CLKSEL1_TMR2SEL_EXT

Setting Timer 2 clock source as external trigger

Definition at line 167 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_HIRC

#define CLK_CLKSEL1_TMR2SEL_HIRC

Setting Timer 2 clock source as internal 22.1184MHz RC clock

Definition at line 169 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_HXT

#define CLK_CLKSEL1_TMR2SEL_HXT

Setting Timer 2 clock source as external XTAL

Definition at line 164 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_LIRC

#define CLK_CLKSEL1_TMR2SEL_LIRC

Setting Timer 2 clock source as internal 10KHz RC clock

Definition at line 168 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_LXT

#define CLK_CLKSEL1_TMR2SEL_LXT

Setting Timer 2 clock source as external XTAL 32.768KHz

Definition at line 165 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_PCLK

#define CLK_CLKSEL1_TMR2SEL_PCLK

Setting Timer 2 clock source as PCLK

Definition at line 166 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_EXT

#define CLK_CLKSEL1_TMR3SEL_EXT

Setting Timer 3 clock source as external trigger

Definition at line 174 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_HIRC

#define CLK_CLKSEL1_TMR3SEL_HIRC

Setting Timer 3 clock source as internal 22.1184MHz RC clock

Definition at line 176 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_HXT

#define CLK_CLKSEL1_TMR3SEL_HXT

Setting Timer 3 clock source as external XTAL

Definition at line 171 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_LIRC

#define CLK_CLKSEL1_TMR3SEL_LIRC

Setting Timer 3 clock source as internal 10KHz RC clock

Definition at line 175 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_LXT

#define CLK_CLKSEL1_TMR3SEL_LXT

Setting Timer 3 clock source as external XTAL 32.768KHz

Definition at line 172 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_PCLK

#define CLK_CLKSEL1_TMR3SEL_PCLK

Setting Timer 3 clock source as PCLK

Definition at line 173 of file clk.h.

## ◆ CLK_CLKSEL1_UARTSEL_HIRC

#define CLK_CLKSEL1_UARTSEL_HIRC

Setting UR clock source as external internal 22.1184MHz RC clock

Definition at line 180 of file clk.h.

## ◆ CLK_CLKSEL1_UARTSEL_HXT

#define CLK_CLKSEL1_UARTSEL_HXT

Setting UR clock source as external XTAL

Definition at line 178 of file clk.h.

## ◆ CLK_CLKSEL1_UARTSEL_PLL

#define CLK_CLKSEL1_UARTSEL_PLL

Setting UR clock source as external PLL

Definition at line 179 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_HCLK_DIV2048

#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048

Setting WDT clock source as HCLK/2048

Definition at line 125 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_HXT

#define CLK_CLKSEL1_WDTSEL_HXT

Setting WDT clock source as external XTAL

Definition at line 123 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_LIRC

#define CLK_CLKSEL1_WDTSEL_LIRC

Setting WDT clock source as internal 10KHz RC clock

Definition at line 126 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_LXT

#define CLK_CLKSEL1_WDTSEL_LXT

Setting WDT clock source as external XTAL 32.768KHz

Definition at line 124 of file clk.h.

## ◆ CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048

#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048

Setting CLKO clock source as HCLK/2048

Definition at line 187 of file clk.h.

## ◆ CLK_CLKSEL1_WWDTSEL_LIRC

#define CLK_CLKSEL1_WWDTSEL_LIRC

Setting CLKO clock source as internal 10KHz RC clock

Definition at line 188 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH01SEL_HIRC

#define CLK_CLKSEL2_PWM0CH01SEL_HIRC

Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock

Definition at line 197 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH01SEL_HXT

#define CLK_CLKSEL2_PWM0CH01SEL_HXT

Setting PWM0 and PWM1 clock source as external XTAL

Definition at line 194 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH01SEL_LIRC

#define CLK_CLKSEL2_PWM0CH01SEL_LIRC

Setting PWM0 and PWM1 clock source as internal 10KHz RC clock

Definition at line 198 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH01SEL_LXT

#define CLK_CLKSEL2_PWM0CH01SEL_LXT

Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz

Definition at line 195 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH01SEL_PCLK

#define CLK_CLKSEL2_PWM0CH01SEL_PCLK

Setting PWM0 and PWM1 clock source as PCLK

Definition at line 196 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH23SEL_HIRC

#define CLK_CLKSEL2_PWM0CH23SEL_HIRC

Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock

Definition at line 203 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH23SEL_HXT

#define CLK_CLKSEL2_PWM0CH23SEL_HXT

Setting PWM2 and PWM3 clock source as external XTAL

Definition at line 200 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH23SEL_LIRC

#define CLK_CLKSEL2_PWM0CH23SEL_LIRC

Setting PWM2 and PWM3 clock source as internal 10KHz RC clock

Definition at line 204 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH23SEL_LXT

#define CLK_CLKSEL2_PWM0CH23SEL_LXT

Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz

Definition at line 201 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH23SEL_PCLK

#define CLK_CLKSEL2_PWM0CH23SEL_PCLK

Setting PWM2 and PWM3 clock source as PCLK

Definition at line 202 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH45SEL_HIRC

#define CLK_CLKSEL2_PWM0CH45SEL_HIRC

Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock

Definition at line 209 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH45SEL_HXT

#define CLK_CLKSEL2_PWM0CH45SEL_HXT

Setting PWM4 and PWM5 clock source as external XTAL

Definition at line 206 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH45SEL_LIRC

#define CLK_CLKSEL2_PWM0CH45SEL_LIRC

Setting PWM4 and PWM5 clock source as internal 10KHz RC clock

Definition at line 210 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH45SEL_LXT

#define CLK_CLKSEL2_PWM0CH45SEL_LXT

Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz

Definition at line 207 of file clk.h.

## ◆ CLK_CLKSEL2_PWM0CH45SEL_PCLK

#define CLK_CLKSEL2_PWM0CH45SEL_PCLK

Setting PWM4 and PWM5 clock source as PCLK

Definition at line 208 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH01SEL_HIRC

#define CLK_CLKSEL2_PWM1CH01SEL_HIRC

Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock

Definition at line 215 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH01SEL_HXT

#define CLK_CLKSEL2_PWM1CH01SEL_HXT

Setting PWM0 and PWM1 clock source as external XTAL

Definition at line 212 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH01SEL_LIRC

#define CLK_CLKSEL2_PWM1CH01SEL_LIRC

Setting PWM0 and PWM1 clock source as internal 10KHz RC clock

Definition at line 216 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH01SEL_LXT

#define CLK_CLKSEL2_PWM1CH01SEL_LXT

Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz

Definition at line 213 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH01SEL_PCLK

#define CLK_CLKSEL2_PWM1CH01SEL_PCLK

Setting PWM0 and PWM1 clock source as PCLK

Definition at line 214 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH23SEL_HIRC

#define CLK_CLKSEL2_PWM1CH23SEL_HIRC

Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock

Definition at line 221 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH23SEL_HXT

#define CLK_CLKSEL2_PWM1CH23SEL_HXT

Setting PWM2 and PWM3 clock source as external XTAL

Definition at line 218 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH23SEL_LIRC

#define CLK_CLKSEL2_PWM1CH23SEL_LIRC

Setting PWM2 and PWM3 clock source as internal 10KHz RC clock

Definition at line 222 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH23SEL_LXT

#define CLK_CLKSEL2_PWM1CH23SEL_LXT

Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz

Definition at line 219 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH23SEL_PCLK

#define CLK_CLKSEL2_PWM1CH23SEL_PCLK

Setting PWM2 and PWM3 clock source as PCLK

Definition at line 220 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH45SEL_HIRC

#define CLK_CLKSEL2_PWM1CH45SEL_HIRC

Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock

Definition at line 227 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH45SEL_HXT

#define CLK_CLKSEL2_PWM1CH45SEL_HXT

Setting PWM4 and PWM5 clock source as external XTAL

Definition at line 224 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH45SEL_LIRC

#define CLK_CLKSEL2_PWM1CH45SEL_LIRC

Setting PWM4 and PWM5 clock source as internal 10KHz RC clock

Definition at line 228 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH45SEL_LXT

#define CLK_CLKSEL2_PWM1CH45SEL_LXT

Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz

Definition at line 225 of file clk.h.

## ◆ CLK_CLKSEL2_PWM1CH45SEL_PCLK

#define CLK_CLKSEL2_PWM1CH45SEL_PCLK

Setting PWM4 and PWM5 clock source as PCLK

Definition at line 226 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_HIRC

#define CLK_CLKSEL3_I2S0SEL_HIRC

Setting I2S0 clock source as internal 22.1184MHz RC clock

Definition at line 266 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_HXT

#define CLK_CLKSEL3_I2S0SEL_HXT

Setting I2S0 clock source as external XTAL

Definition at line 263 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_PCLK

#define CLK_CLKSEL3_I2S0SEL_PCLK

Setting I2S0 clock source as PCLK

Definition at line 265 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_PLL

#define CLK_CLKSEL3_I2S0SEL_PLL

Setting I2S0 clock source as PLL

Definition at line 264 of file clk.h.

## ◆ CLK_CLKSEL3_I2S1SEL_HIRC

#define CLK_CLKSEL3_I2S1SEL_HIRC

Setting I2S1 clock source as internal 22.1184MHz RC clock

Definition at line 271 of file clk.h.

## ◆ CLK_CLKSEL3_I2S1SEL_HXT

#define CLK_CLKSEL3_I2S1SEL_HXT

Setting I2S1 clock source as external XTAL

Definition at line 268 of file clk.h.

## ◆ CLK_CLKSEL3_I2S1SEL_PCLK

#define CLK_CLKSEL3_I2S1SEL_PCLK

Setting I2S1 clock source as PCLK

Definition at line 270 of file clk.h.

## ◆ CLK_CLKSEL3_I2S1SEL_PLL

#define CLK_CLKSEL3_I2S1SEL_PLL

Setting I2S1 clock source as PLL

Definition at line 269 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_HIRC

#define CLK_CLKSEL3_SC0SEL_HIRC

Setting SC0 clock source as internal 22.1184MHz RC clock

Definition at line 236 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_HXT

#define CLK_CLKSEL3_SC0SEL_HXT

Setting SC0 clock source as external XTAL

Definition at line 233 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_PCLK

#define CLK_CLKSEL3_SC0SEL_PCLK

Setting SC0 clock source as PCLK

Definition at line 235 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_PLL

#define CLK_CLKSEL3_SC0SEL_PLL

Setting SC0 clock source as PLL

Definition at line 234 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_HIRC

#define CLK_CLKSEL3_SC1SEL_HIRC

Setting SC1 clock source as internal 22.1184MHz RC clock

Definition at line 241 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_HXT

#define CLK_CLKSEL3_SC1SEL_HXT

Setting SC1 clock source as external XTAL

Definition at line 238 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_PCLK

#define CLK_CLKSEL3_SC1SEL_PCLK

Setting SC1 clock source as PCLK

Definition at line 240 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_PLL

#define CLK_CLKSEL3_SC1SEL_PLL

Setting SC1 clock source as PLL

Definition at line 239 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_HIRC

#define CLK_CLKSEL3_SC2SEL_HIRC

Setting SC2 clock source as internal 22.1184MHz RC clock

Definition at line 246 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_HXT

#define CLK_CLKSEL3_SC2SEL_HXT

Setting SC2 clock source as external XTAL

Definition at line 243 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_PCLK

#define CLK_CLKSEL3_SC2SEL_PCLK

Setting SC2 clock source as PCLK

Definition at line 245 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_PLL

#define CLK_CLKSEL3_SC2SEL_PLL

Setting SC2 clock source as PLL

Definition at line 244 of file clk.h.

## ◆ CLK_CLKSEL3_SC3SEL_HIRC

#define CLK_CLKSEL3_SC3SEL_HIRC

Setting SC3 clock source as internal 22.1184MHz RC clock

Definition at line 251 of file clk.h.

## ◆ CLK_CLKSEL3_SC3SEL_HXT

#define CLK_CLKSEL3_SC3SEL_HXT

Setting SC3 clock source as external XTAL

Definition at line 248 of file clk.h.

## ◆ CLK_CLKSEL3_SC3SEL_PCLK

#define CLK_CLKSEL3_SC3SEL_PCLK

Setting SC3 clock source as PCLK

Definition at line 250 of file clk.h.

## ◆ CLK_CLKSEL3_SC3SEL_PLL

#define CLK_CLKSEL3_SC3SEL_PLL

Setting SC3 clock source as PLL

Definition at line 249 of file clk.h.

## ◆ CLK_CLKSEL3_SC4SEL_HIRC

#define CLK_CLKSEL3_SC4SEL_HIRC

Setting SC4 clock source as internal 22.1184MHz RC clock

Definition at line 256 of file clk.h.

## ◆ CLK_CLKSEL3_SC4SEL_HXT

#define CLK_CLKSEL3_SC4SEL_HXT

Setting SC4 clock source as external XTAL

Definition at line 253 of file clk.h.

## ◆ CLK_CLKSEL3_SC4SEL_PCLK

#define CLK_CLKSEL3_SC4SEL_PCLK

Setting SC4 clock source as PCLK

Definition at line 255 of file clk.h.

## ◆ CLK_CLKSEL3_SC4SEL_PLL

#define CLK_CLKSEL3_SC4SEL_PLL

Setting SC4 clock source as PLL

Definition at line 254 of file clk.h.

## ◆ CLK_CLKSEL3_SC5SEL_HIRC

#define CLK_CLKSEL3_SC5SEL_HIRC

Setting SC5 clock source as internal 22.1184MHz RC clock

Definition at line 261 of file clk.h.

## ◆ CLK_CLKSEL3_SC5SEL_HXT

#define CLK_CLKSEL3_SC5SEL_HXT

Setting SC5 clock source as external XTAL

Definition at line 258 of file clk.h.

## ◆ CLK_CLKSEL3_SC5SEL_PCLK

#define CLK_CLKSEL3_SC5SEL_PCLK

Setting SC5 clock source as PCLK

Definition at line 260 of file clk.h.

## ◆ CLK_CLKSEL3_SC5SEL_PLL

#define CLK_CLKSEL3_SC5SEL_PLL

Setting SC5 clock source as PLL

Definition at line 259 of file clk.h.

## ◆ CLK_PLL2CTL_PLL2DIV

#define CLK_PLL2CTL_PLL2DIV | ( |  | x | ) |

USBPLL clock frequency = (480 MHz) / 2 / (USB_N + 1). It could be 1~256, Max. PLL frequency :480MHz / 2 when XTL12M.

Definition at line 80 of file clk.h.

## ◆ CLK_PLLCTL_24MHz_HIRC

#define CLK_PLLCTL_24MHz_HIRC

Predefined PLLCTL setting for 23.9616MHz PLL output with 22.1184MHz IRC

Definition at line 75 of file clk.h.

## ◆ CLK_PLLCTL_32MHz_HIRC

#define CLK_PLLCTL_32MHz_HIRC

Predefined PLLCTL setting for 31.9488MHz PLL output with 22.1184MHz IRC

Definition at line 74 of file clk.h.

## ◆ CLK_PLLCTL_36MHz_HIRC

#define CLK_PLLCTL_36MHz_HIRC

Predefined PLLCTL setting for 35.9424MHz PLL output with 22.1184MHz IRC

Definition at line 73 of file clk.h.

## ◆ CLK_PLLCTL_48MHz_HIRC

#define CLK_PLLCTL_48MHz_HIRC

Predefined PLLCTL setting for 48.064985MHz PLL output with 22.1184MHz IRC

Definition at line 72 of file clk.h.

## ◆ CLK_PLLCTL_50MHz_HIRC

#define CLK_PLLCTL_50MHz_HIRC

Predefined PLLCTL setting for 50.1918MHz PLL output with 22.1184MHz IRC

Definition at line 71 of file clk.h.

## ◆ CLK_PLLCTL_NF

#define CLK_PLLCTL_NF | ( |  | x | ) |

x must be constant and 2 <= x <= 513. 100MHz < FIN*NF/NR < 200MHz. (120MHz < FIN*NF/NR < 200MHz is preferred.)

Definition at line 53 of file clk.h.

## ◆ CLK_PLLCTL_NO_1

#define CLK_PLLCTL_NO_1

For output divider is 1

Definition at line 55 of file clk.h.

## ◆ CLK_PLLCTL_NO_2

#define CLK_PLLCTL_NO_2

For output divider is 2

Definition at line 56 of file clk.h.

## ◆ CLK_PLLCTL_NO_4

#define CLK_PLLCTL_NO_4

For output divider is 4

Definition at line 57 of file clk.h.

## ◆ CLK_PLLCTL_NR

#define CLK_PLLCTL_NR | ( |  | x | ) |

x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 15MHz

Definition at line 52 of file clk.h.

## ◆ CLK_PLLCTL_PLLSRC_HIRC

#define CLK_PLLCTL_PLLSRC_HIRC

For PLL clock source is internal RC clock. 4MHz < FIN < 24MHz

Definition at line 49 of file clk.h.

## ◆ CLK_PLLCTL_PLLSRC_HXT

#define CLK_PLLCTL_PLLSRC_HXT

For PLL clock source is external crystal. 4MHz < FIN < 24MHz

Definition at line 50 of file clk.h.

## ◆ CLK_TIMEOUT_ERR

#define CLK_TIMEOUT_ERR

Clock timeout error value

Definition at line 394 of file clk.h.

## ◆ CLKO_MODULE

#define CLKO_MODULE

CLKO Module

Definition at line 348 of file clk.h.

## ◆ CRC_MODULE

#define CRC_MODULE

CRC Module

Definition at line 335 of file clk.h.

## ◆ CRPT_MODULE

#define CRPT_MODULE

CRYPTO Module

Definition at line 339 of file clk.h.

## ◆ EADC_MODULE

#define EADC_MODULE

EADC Module

Definition at line 392 of file clk.h.

## ◆ EBI_MODULE

#define EBI_MODULE

EBI Module

Definition at line 331 of file clk.h.

## ◆ ECAP0_MODULE

#define ECAP0_MODULE

ECAP0 Module

Definition at line 387 of file clk.h.

## ◆ ECAP1_MODULE

#define ECAP1_MODULE

ECAP1 Module

Definition at line 388 of file clk.h.

## ◆ EMAC_MODULE

#define EMAC_MODULE

EMAC Module

Definition at line 333 of file clk.h.

## ◆ EPWM0_MODULE

#define EPWM0_MODULE

EPWM0 Module

Definition at line 389 of file clk.h.

## ◆ EPWM1_MODULE

#define EPWM1_MODULE

EPWM1 Module

Definition at line 390 of file clk.h.

## ◆ FREQ_10KHZ

#define FREQ_10KHZ 10000

Definition at line 44 of file clk.h.

## ◆ FREQ_125MHZ

#define FREQ_125MHZ 125000000

Definition at line 37 of file clk.h.

## ◆ FREQ_200MHZ

#define FREQ_200MHZ 200000000

Definition at line 36 of file clk.h.

## ◆ FREQ_22MHZ

#define FREQ_22MHZ 22000000

Definition at line 42 of file clk.h.

## ◆ FREQ_24MHZ

#define FREQ_24MHZ 24000000

Definition at line 41 of file clk.h.

## ◆ FREQ_250MHZ

#define FREQ_250MHZ 250000000

Definition at line 35 of file clk.h.

## ◆ FREQ_25MHZ

#define FREQ_25MHZ 25000000

Definition at line 40 of file clk.h.

## ◆ FREQ_32KHZ

#define FREQ_32KHZ 32000

Definition at line 43 of file clk.h.

## ◆ FREQ_500MHZ

#define FREQ_500MHZ 500000000

Definition at line 34 of file clk.h.

## ◆ FREQ_50MHZ

#define FREQ_50MHZ 50000000

Definition at line 39 of file clk.h.

## ◆ FREQ_72MHZ

#define FREQ_72MHZ 72000000

Definition at line 38 of file clk.h.

## ◆ I2C0_MODULE

#define I2C0_MODULE

I2C0 Module

Definition at line 350 of file clk.h.

## ◆ I2C1_MODULE

#define I2C1_MODULE

I2C1 Module

Definition at line 351 of file clk.h.

## ◆ I2C2_MODULE

#define I2C2_MODULE

I2C2 Module

Definition at line 352 of file clk.h.

## ◆ I2C3_MODULE

#define I2C3_MODULE

I2C3 Module

Definition at line 353 of file clk.h.

## ◆ I2C4_MODULE

#define I2C4_MODULE ((2UL<<30)|(0<<28)|(0<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos)

I2C4 Module

Definition at line 378 of file clk.h.

## ◆ I2S0_MODULE

#define I2S0_MODULE

I2S0 Module

Definition at line 368 of file clk.h.

## ◆ I2S1_MODULE

#define I2S1_MODULE

I2S1 Module

Definition at line 369 of file clk.h.

## ◆ ISP_MODULE

#define ISP_MODULE

ISP Module

Definition at line 330 of file clk.h.

## ◆ MODULE_APBCLK

#define MODULE_APBCLK | ( |  | x | ) |

Calculate AHBCLK/APBCLK offset on MODULE index

Definition at line 307 of file clk.h.

## ◆ MODULE_APBCLK_ENC

#define MODULE_APBCLK_ENC | ( |  | x | ) | (((x) & 0x03) << 30)

MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1

Definition at line 318 of file clk.h.

## ◆ MODULE_CLKDIV

#define MODULE_CLKDIV | ( |  | x | ) |

Calculate APBCLK CLKDIV on MODULE index

Definition at line 311 of file clk.h.

## ◆ MODULE_CLKDIV_ENC

#define MODULE_CLKDIV_ENC | ( |  | x | ) | (((x) & 0x03) << 18)

APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1

Definition at line 322 of file clk.h.

## ◆ MODULE_CLKDIV_Msk

#define MODULE_CLKDIV_Msk | ( |  | x | ) |

Calculate CLKDIV mask offset on MODULE index

Definition at line 312 of file clk.h.

## ◆ MODULE_CLKDIV_Msk_ENC

#define MODULE_CLKDIV_Msk_ENC | ( |  | x | ) | (((x) & 0xff) << 10)

CLKDIV mask offset on MODULE index

Definition at line 323 of file clk.h.

## ◆ MODULE_CLKDIV_Pos

#define MODULE_CLKDIV_Pos | ( |  | x | ) |

Calculate CLKDIV position offset on MODULE index

Definition at line 313 of file clk.h.

## ◆ MODULE_CLKDIV_Pos_ENC

#define MODULE_CLKDIV_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 5)

CLKDIV position offset on MODULE index

Definition at line 324 of file clk.h.

## ◆ MODULE_CLKSEL

#define MODULE_CLKSEL | ( |  | x | ) |

Calculate CLKSEL offset on MODULE index

Definition at line 308 of file clk.h.

## ◆ MODULE_CLKSEL_ENC

#define MODULE_CLKSEL_ENC | ( |  | x | ) | (((x) & 0x03) << 28)

CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3

Definition at line 319 of file clk.h.

## ◆ MODULE_CLKSEL_Msk

#define MODULE_CLKSEL_Msk | ( |  | x | ) |

Calculate CLKSEL mask offset on MODULE index

Definition at line 309 of file clk.h.

## ◆ MODULE_CLKSEL_Msk_ENC

#define MODULE_CLKSEL_Msk_ENC | ( |  | x | ) | (((x) & 0x07) << 25)

CLKSEL mask offset on MODULE index

Definition at line 320 of file clk.h.

## ◆ MODULE_CLKSEL_Pos

#define MODULE_CLKSEL_Pos | ( |  | x | ) |

Calculate CLKSEL position offset on MODULE index

Definition at line 310 of file clk.h.

## ◆ MODULE_CLKSEL_Pos_ENC

#define MODULE_CLKSEL_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 20)

CLKSEL position offset on MODULE index

Definition at line 321 of file clk.h.

## ◆ MODULE_IP_EN_Pos

#define MODULE_IP_EN_Pos | ( |  | x | ) |

Calculate APBCLK offset on MODULE index

Definition at line 314 of file clk.h.

## ◆ MODULE_IP_EN_Pos_ENC

#define MODULE_IP_EN_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 0)

AHBCLK/APBCLK offset on MODULE index

Definition at line 325 of file clk.h.

## ◆ MODULE_NoMsk

#define MODULE_NoMsk

Not mask on MODULE index

Definition at line 315 of file clk.h.

## ◆ NA

#define NA

Not Available

Definition at line 316 of file clk.h.

## ◆ OPA_MODULE

#define OPA_MODULE

OPA Module

Definition at line 391 of file clk.h.

## ◆ OTG_MODULE

#define OTG_MODULE

OTG Module

Definition at line 366 of file clk.h.

## ◆ PDMA_MODULE

#define PDMA_MODULE

PDMA Module

Definition at line 329 of file clk.h.

## ◆ PS2_MODULE

#define PS2_MODULE

PS2 Module

Definition at line 370 of file clk.h.

## ◆ PWM0CH01_MODULE

#define PWM0CH01_MODULE

PWM0CH01 Module

Definition at line 379 of file clk.h.

## ◆ PWM0CH23_MODULE

#define PWM0CH23_MODULE

PWM0CH23 Module

Definition at line 380 of file clk.h.

## ◆ PWM0CH45_MODULE

#define PWM0CH45_MODULE

PWM0CH45 Module

Definition at line 381 of file clk.h.

## ◆ PWM1CH01_MODULE

#define PWM1CH01_MODULE

PWM1CH01 Module

Definition at line 382 of file clk.h.

## ◆ PWM1CH23_MODULE

#define PWM1CH23_MODULE

PWM1CH23 Module

Definition at line 383 of file clk.h.

## ◆ PWM1CH45_MODULE

#define PWM1CH45_MODULE

PWM1CH45 Module

Definition at line 384 of file clk.h.

## ◆ QEI0_MODULE

#define QEI0_MODULE

QEI0 Module

Definition at line 385 of file clk.h.

## ◆ QEI1_MODULE

#define QEI1_MODULE

QEI1 Module

Definition at line 386 of file clk.h.

## ◆ RTC_MODULE

#define RTC_MODULE

RTC Module

Definition at line 343 of file clk.h.

## ◆ SC0_MODULE

#define SC0_MODULE

SmartCard0 Module

Definition at line 372 of file clk.h.

## ◆ SC1_MODULE

#define SC1_MODULE

SmartCard1 Module

Definition at line 373 of file clk.h.

## ◆ SC2_MODULE

#define SC2_MODULE

SmartCard2 Module

Definition at line 374 of file clk.h.

## ◆ SC3_MODULE

#define SC3_MODULE

SmartCard3 Module

Definition at line 375 of file clk.h.

## ◆ SC4_MODULE

#define SC4_MODULE

SmartCard4 Module

Definition at line 376 of file clk.h.

## ◆ SC5_MODULE

#define SC5_MODULE

SmartCard5 Module

Definition at line 377 of file clk.h.

## ◆ SDH_MODULE

#define SDH_MODULE

SDH Module

Definition at line 334 of file clk.h.

## ◆ SEN_MODULE

#define SEN_MODULE

Sensor Clock Module

Definition at line 337 of file clk.h.

## ◆ SPI0_MODULE

#define SPI0_MODULE

SPI0 Module

Definition at line 354 of file clk.h.

## ◆ SPI1_MODULE

#define SPI1_MODULE

SPI1 Module

Definition at line 355 of file clk.h.

## ◆ SPI2_MODULE

#define SPI2_MODULE

SPI2 Module

Definition at line 356 of file clk.h.

## ◆ SPI3_MODULE

#define SPI3_MODULE

SPI3 Module

Definition at line 357 of file clk.h.

## ◆ TMR0_MODULE

#define TMR0_MODULE

Timer0 Module

Definition at line 344 of file clk.h.

## ◆ TMR1_MODULE

#define TMR1_MODULE

Timer1 Module

Definition at line 345 of file clk.h.

## ◆ TMR2_MODULE

#define TMR2_MODULE

Timer2 Module

Definition at line 346 of file clk.h.

## ◆ TMR3_MODULE

#define TMR3_MODULE

Timer3 Module

Definition at line 347 of file clk.h.

## ◆ UART0_MODULE

#define UART0_MODULE

UART0 Module

Definition at line 358 of file clk.h.

## ◆ UART1_MODULE

#define UART1_MODULE

UART1 Module

Definition at line 359 of file clk.h.

## ◆ UART2_MODULE

#define UART2_MODULE

UART2 Module

Definition at line 360 of file clk.h.

## ◆ UART3_MODULE

#define UART3_MODULE

UART3 Module

Definition at line 361 of file clk.h.

## ◆ UART4_MODULE

#define UART4_MODULE

UART4 Module

Definition at line 362 of file clk.h.

## ◆ UART5_MODULE

#define UART5_MODULE

UART5 Module

Definition at line 363 of file clk.h.

## ◆ USBD_MODULE

#define USBD_MODULE

USBD Module

Definition at line 338 of file clk.h.

## ◆ USBH_MODULE

#define USBH_MODULE

USBH Module

Definition at line 332 of file clk.h.

## ◆ WDT_MODULE

#define WDT_MODULE

Watchdog Timer Module

Definition at line 341 of file clk.h.

## ◆ WWDT_MODULE

#define WWDT_MODULE

Window Watchdog Timer Module

Definition at line 342 of file clk.h.

## Variable Documentation

## ◆ g_CLK_i32ErrCode

int32_t g_CLK_i32ErrCode
| extern

CLK global error code

Definition at line 22 of file clk.c.