| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

spi.h
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1/****************************************************************************/
12#ifndef __SPI_H__
13#define __SPI_H__
14
15#ifdef __cplusplus
16extern "C"
17{
18#endif
19
20
33#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
34#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
35#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
36#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
38#define SPI_SLAVE (SPI_CTL_SLAVE_Msk)
39#define SPI_MASTER (0x0)
41#define SPI_SS0 (0x1)
42#define SPI_SS1 (0x2)
43#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
44#define SPI_SS_ACTIVE_LOW (0x0)
46#define SPI_UNITIEN_MASK (0x001)
47#define SPI_SSINAIEN_MASK (0x002)
48#define SPI_SSACTIEN_MASK (0x004)
49#define SPI_SLVURIEN_MASK (0x008)
50#define SPI_SLVBEIEN_MASK (0x010)
51#define SPI_SLVTOIEN_MASK (0x020)
52#define SPI_FIFO_TXTHIEN_MASK (0x040)
53#define SPI_FIFO_RXTHIEN_MASK (0x080)
54#define SPI_FIFO_RXOVIEN_MASK (0x100)
55#define SPI_FIFO_TXUFIEN_MASK (0x200)
56#define SPI_FIFO_RXTOIEN_MASK (0x400) /* end of group NUC472_442_SPI_EXPORTED_CONSTANTS */
60
61
74#define SPI_SET_SLAVE_TIMEOUT_PERIOD(spi, u32TimeoutPeriod) ( (spi)->SSCTL = ((spi)->SSCTL & ~SPI_SSCTL_SLVTOCNT_Msk) | (((uint32_t)u32TimeoutPeriod & 0xFFFF) << SPI_SSCTL_SLVTOCNT_Pos) )
75
82#define SPI_ENABLE_TIMEOUT_FIFO_CLEAR(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLVTORST_Msk )
83
90#define SPI_DISABLE_TIMEOUT_FIFO_CLEAR(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLVTORST_Msk )
91
98#define SPI_SET_TX_UNDERRUN_DATA_LOW(spi) ( (spi)->FIFOCTL &= ~SPI_FIFOCTL_TXUFPOL_Msk )
99
106#define SPI_SET_TX_UNDERRUN_DATA_HIGH(spi) ( (spi)->FIFOCTL |= SPI_FIFOCTL_TXUFPOL_Msk )
107
114#define SPI_GET_STATUS(spi) ( (spi)->STATUS )
115
122#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
123
131#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk )
132
140#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk )
141
148#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
149
158#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
159
168#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
169
178#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
179
186#define SPI_READ_RX(spi) ((spi)->RX)
187
195#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
196
204#define SPI_SET_SS0_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS0)))
205
213#define SPI_SET_SS0_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS0)) | SPI_SS0)
214
222#define SPI_SET_SS1_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS1)))
223
231#define SPI_SET_SS1_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI_SSCTL_AUTOSS_Msk|SPI_SSCTL_SSACTPOL_Msk|SPI_SS1)) | SPI_SS1)
232
233
241#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
242
250#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
251
260#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
261
269#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
270
278#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
279
288 static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
289{
290 if(u32Width == 32)
291 u32Width = 0;
292
293 spi->CTL = (spi->CTL & ~SPI_CTL_DWIDTH_Msk) | (u32Width << SPI_CTL_DWIDTH_Pos);
294}
295
304#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) == SPI_STATUS_BUSY_Msk ? 1:0 )
305
312#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
313
320#define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
321
328#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )
329
336#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk )
337
344#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_QDIODIR_Msk) | SPI_CTL_DUALIOEN_Msk )
345
352#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk )
353
360#define SPI_DISABLE_QUAD_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk )
361
368#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_QDIODIR_Msk) | SPI_CTL_QUADIOEN_Msk )
369
376#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk )
377
384#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
385
392#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
393
400#define SPI_TRIGGER_TXRX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
401
408#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
409
416#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
417
425#define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOBIT_Msk )
426
434#define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOBIT_Msk )
435
436uint32_t SPI_Open(SPI_T *spi,uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
437void SPI_Close(SPI_T *spi);
438void SPI_ClearRxFIFO(SPI_T *spi);
439void SPI_ClearTxFIFO(SPI_T *spi);
440void SPI_DisableAutoSS(SPI_T *spi);
441void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
442uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
443void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
444uint32_t SPI_GetBusClock(SPI_T *spi);
445void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
446void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
447
448 /* end of group NUC472_442_SPI_EXPORTED_FUNCTIONS */
450 /* end of group NUC472_442_SPI_Driver */
452 /* end of group NUC472_442_Device_Driver */
454
455#ifdef __cplusplus
456}
457#endif
458
459#endif //__SPI_H__
460
461/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
462
SPI_CTL_DWIDTH_Pos
#define SPI_CTL_DWIDTH_Pos
Definition: NUC472_442.h:23082
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:319
SPI_SetFIFOThreshold
void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Set Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:195
SPI_SET_DATA_WIDTH
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
Set the data width of a SPI transaction.
Definition: spi.h:288
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:264
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:127
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:111
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:138
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:61
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:101
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:46
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:207
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:91
SPI_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:22774
SPI_T
Definition: NUC472_442.h:22695