| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

adc.h
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1/**************************************************************************/
12#ifndef __ADC_H__
13#define __ADC_H__
14
15#ifdef __cplusplus
16extern "C"
17{
18#endif
19
20
33#define ADC_CH_0_MASK (1UL << 0)
34#define ADC_CH_1_MASK (1UL << 1)
35#define ADC_CH_2_MASK (1UL << 2)
36#define ADC_CH_3_MASK (1UL << 3)
37#define ADC_CH_4_MASK (1UL << 4)
38#define ADC_CH_5_MASK (1UL << 5)
39#define ADC_CH_6_MASK (1UL << 6)
40#define ADC_CH_7_MASK (1UL << 7)
41#define ADC_CH_8_MASK (1UL << 8)
42#define ADC_CH_9_MASK (1UL << 9)
43#define ADC_CH_10_MASK (1UL << 10)
44#define ADC_CH_11_MASK (1UL << 11)
45#define ADC_CH_BG_MASK (1UL << 16)
46#define ADC_CH_TS_MASK (1UL << 17)
47#define ADC_CMP_LESS_THAN (0UL)
48#define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMP0_CMPCOND_Msk)
49#define ADC_TRIGGER_BY_EXT_PIN (0UL)
50#define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
51#define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos)
52#define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CTL_HWTRGCOND_Pos)
53#define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CTL_HWTRGCOND_Pos)
54#define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CTL_HWTRGCOND_Pos)
55#define ADC_ADF_INT (ADC_STATUS0_ADIF_Msk)
56#define ADC_CMP0_INT (ADC_STATUS0_ADCMPF0_Msk)
57#define ADC_CMP1_INT (ADC_STATUS0_ADCMPF1_Msk)
58#define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CTL_DIFFEN_Pos)
59#define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CTL_DIFFEN_Pos)
60#define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CTL_OPMODE_Pos)
61#define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CTL_OPMODE_Pos)
62#define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CTL_OPMODE_Pos)
63#define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CTL_DMOF_Pos)
64#define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CTL_DMOF_Pos) /* end of group NUC472_442_ADC_EXPORTED_CONSTANTS */
67
68
80#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ( ADC->DAT[u32ChNum] & ADC_DAT0_RESULT_Msk)
81
92#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->STATUS0 & (u32Mask))
93
104#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->STATUS0 = (ADC->STATUS0 & ~(ADC_STATUS0_ADIF_Msk | \
105 ADC_STATUS0_ADCMPF0_Msk | \
106 ADC_STATUS0_ADCMPF1_Msk)) | (u32Mask))
107
116#define ADC_IS_BUSY(adc) (ADC->STATUS0 & ADC_STATUS0_BUSY_Msk ? 1 : 0)
117
127#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_OV_Pos + u32ChNum)) ? 1 : 0)
128
138#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_VALID_Pos + u32ChNum)) ? 1 : 0)
139
146#define ADC_POWER_DOWN(adc) (ADC->CTL &= ~ADC_CTL_ADCEN_Msk)
147
154#define ADC_POWER_ON(adc) (ADC->CTL |= ADC_CTL_ADCEN_Msk)
155
171#define ADC_ENABLE_CMP0(adc, \
172 u32ChNum, \
173 u32Condition, \
174 u32Data, \
175 u32MatchCount) (ADC->CMP[0] = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
176 (u32Condition) | \
177 ((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
178 (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
179 ADC_CMP0_ADCMPEN_Msk)
180
186#define ADC_DISABLE_CMP0(adc) (ADC->CMP[0] = 0)
187
203#define ADC_ENABLE_CMP1(adc, \
204 u32ChNum, \
205 u32Condition, \
206 u32Data, \
207 u32MatchCount) (ADC->CMP[1] = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
208 (u32Condition) | \
209 ((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
210 ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
211 ADC_CMP1_ADCMPEN_Msk)
212
218#define ADC_DISABLE_CMP1(adc) (ADC->CMP[1] = 0)
219
227#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN_Msk) | (u32Mask))
228
235#define ADC_START_CONV(adc) (ADC->CTL |= ADC_CTL_SWTRG_Msk)
236
243#define ADC_STOP_CONV(adc) (ADC->CTL &= ~ADC_CTL_SWTRG_Msk)
244
254#define ADC_SET_DMOF(adc, u32Format) (ADC->CTL = (ADC->CTL & ~ADC_CTL_DMOF_Msk) | u32Format)
255
262#define ADC_ENABLE_PDMA(adc) (ADC->CTL |= ADC_CTL_PDMAEN_Msk)
263
270#define ADC_DISABLE_PDMA(adc) (ADC->CTL &= ~ADC_CTL_PDMAEN_Msk)
271
278#define ADC_GET_PDMA_DATA(adc) ( ADC->CURDAT & ADC_CURDAT_CURDAT_Msk)
279
280void ADC_Open(ADC_T *adc,
281 uint32_t u32InputMode,
282 uint32_t u32OpMode,
283 uint32_t u32ChMask);
284void ADC_Close(ADC_T *adc);
285void ADC_EnableHWTrigger(ADC_T *adc,
286 uint32_t u32Source,
287 uint32_t u32Param);
288void ADC_DisableHWTrigger(ADC_T *adc);
289void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
290void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
291
292
293 /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */
295 /* end of group NUC472_442_ADC_Driver */
297 /* end of group NUC472_442_Device_Driver */
299
300#ifdef __cplusplus
301}
302#endif
303
304#endif //__ADC_H__
305
306/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
ADC_EnableHWTrigger
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:96
ADC_Close
void ADC_Close(ADC_T *adc)
Disable ADC module.
Definition: adc.c:72
ADC_Open
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
Definition: adc.c:55
ADC_DisableInt
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:160
ADC_DisableHWTrigger
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
Definition: adc.c:120
ADC_EnableInt
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:137
ADC_T
Definition: NUC472_442.h:370