![]() |
NUC472_NUC442_BSP V3.03.004
The Board Support Package for NUC472/NUC442
|
Macros | |
#define | SPI_SET_SLAVE_TIMEOUT_PERIOD(spi, u32TimeoutPeriod) |
Set time out period for slave. More... | |
#define | SPI_ENABLE_TIMEOUT_FIFO_CLEAR(spi) |
Enable time out clear function for FIFO mode. More... | |
#define | SPI_DISABLE_TIMEOUT_FIFO_CLEAR(spi) |
Disable time out clear function for FIFO mode. More... | |
#define | SPI_SET_TX_UNDERRUN_DATA_LOW(spi) |
Set data out signal to low (0) if transmit under-run occurs. More... | |
#define | SPI_SET_TX_UNDERRUN_DATA_HIGH(spi) |
Set data out signal to high (1) if transmit under-run occurs. More... | |
#define | SPI_GET_STATUS(spi) |
Get the status flags. More... | |
#define | SPI_CLR_UNIT_TRANS_INT_FLAG(spi) |
Clear the unit transfer interrupt flag. More... | |
#define | SPI_DISABLE_3WIRE_MODE(spi) |
Disable slave 3-wire mode. More... | |
#define | SPI_ENABLE_3WIRE_MODE(spi) |
Enable slave 3-wire mode. More... | |
#define | SPI_GET_RX_FIFO_COUNT(spi) |
Get the count of available data in RX FIFO. More... | |
#define | SPI_GET_RX_FIFO_EMPTY_FLAG(spi) |
Get the Rx FIFO empty flag. More... | |
#define | SPI_GET_TX_FIFO_EMPTY_FLAG(spi) |
Get the Tx FIFO empty flag. More... | |
#define | SPI_GET_TX_FIFO_FULL_FLAG(spi) |
Get the Tx FIFO full flag. More... | |
#define | SPI_READ_RX(spi) |
Get the datum read from R0 FIFO. More... | |
#define | SPI_WRITE_TX(spi, u32TxData) |
Write datum to TX register. More... | |
#define | SPI_SET_SS0_HIGH(spi) |
Set SPIn_SS0 pin to high state. More... | |
#define | SPI_SET_SS0_LOW(spi) |
Set SPIn_SS0 pin to low state. More... | |
#define | SPI_SET_SS1_HIGH(spi) |
Set SPIn_SS1 pin to high state. More... | |
#define | SPI_SET_SS1_LOW(spi) |
Set SPIn_SS1 pin to low state. More... | |
#define | SPI_ENABLE_BYTE_REORDER(spi) |
Enable byte reorder function. More... | |
#define | SPI_DISABLE_BYTE_REORDER(spi) |
Disable byte reorder function. More... | |
#define | SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) |
Set the length of suspend interval. More... | |
#define | SPI_SET_LSB_FIRST(spi) |
Set the SPI transfer sequence with LSB first. More... | |
#define | SPI_SET_MSB_FIRST(spi) |
Set the SPI transfer sequence with MSB first. More... | |
#define | SPI_IS_BUSY(spi) |
Get the SPI busy state. More... | |
#define | SPI_TRIGGER(spi) |
Set the SPIEN bit to trigger SPI transfer. More... | |
#define | SPI_ENABLE(spi) |
Set the SPIEN bit to trigger SPI transfer. More... | |
#define | SPI_DISABLE(spi) |
Disable SPI function. More... | |
#define | SPI_DISABLE_DUAL_MODE(spi) |
Disable SPI Dual IO function. More... | |
#define | SPI_ENABLE_DUAL_INPUT_MODE(spi) |
Enable Dual IO function and set SPI Dual IO direction to input. More... | |
#define | SPI_ENABLE_DUAL_OUTPUT_MODE(spi) |
Enable Dual IO function and set SPI Dual IO direction to output. More... | |
#define | SPI_DISABLE_QUAD_MODE(spi) |
Disable SPI Dual IO function. More... | |
#define | SPI_ENABLE_QUAD_INPUT_MODE(spi) |
Set SPI Quad IO direction to input. More... | |
#define | SPI_ENABLE_QUAD_OUTPUT_MODE(spi) |
Set SPI Quad IO direction to output. More... | |
#define | SPI_TRIGGER_RX_PDMA(spi) |
Trigger RX PDMA transfer. More... | |
#define | SPI_TRIGGER_TX_PDMA(spi) |
Trigger TX PDMA transfer. More... | |
#define | SPI_TRIGGER_TXRX_PDMA(spi) |
Trigger TX/RX PDMA transfer at the same time. More... | |
#define | SPI_DISABLE_RX_PDMA(spi) |
Disable RX PDMA transfer. More... | |
#define | SPI_DISABLE_TX_PDMA(spi) |
Trigger TX PDMA transfer. More... | |
#define | SPI_ENABLE_2BIT_MODE(spi) |
Enable 2-bit transfer mode. More... | |
#define | SPI_DISABLE_2BIT_MODE(spi) |
Disable 2-bit transfer mode. More... | |
Functions | |
static __INLINE void | SPI_SET_DATA_WIDTH (SPI_T *spi, uint32_t u32Width) |
Set the data width of a SPI transaction. More... | |
uint32_t | SPI_Open (SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) |
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB first and the automatic slave select function is disabled. In Slave mode, the u32BusClock must be NULL and the SPI clock divider setting will be 0. More... | |
void | SPI_Close (SPI_T *spi) |
Reset SPI module and disable SPI peripheral clock. More... | |
void | SPI_ClearRxFIFO (SPI_T *spi) |
Clear Rx FIFO buffer. More... | |
void | SPI_ClearTxFIFO (SPI_T *spi) |
Clear Tx FIFO buffer. More... | |
void | SPI_DisableAutoSS (SPI_T *spi) |
Disable the automatic slave select function. More... | |
void | SPI_EnableAutoSS (SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) |
Enable the automatic slave select function. Only available in Master mode. More... | |
uint32_t | SPI_SetBusClock (SPI_T *spi, uint32_t u32BusClock) |
Set the SPI bus clock. Only available in Master mode. More... | |
void | SPI_SetFIFOThreshold (SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) |
Set Tx FIFO threshold and Rx FIFO threshold configurations. More... | |
uint32_t | SPI_GetBusClock (SPI_T *spi) |
Get the actual frequency of SPI bus clock. Only available in Master mode. More... | |
void | SPI_EnableInt (SPI_T *spi, uint32_t u32Mask) |
Enable FIFO related interrupts specified by u32Mask parameter. More... | |
void | SPI_DisableInt (SPI_T *spi, uint32_t u32Mask) |
Disable FIFO related interrupts specified by u32Mask parameter. More... | |
#define SPI_CLR_UNIT_TRANS_INT_FLAG | ( | spi | ) |
#define SPI_DISABLE | ( | spi | ) |
#define SPI_DISABLE_2BIT_MODE | ( | spi | ) |
Disable 2-bit transfer mode.
[in] | spi | is the base address of SPI module. |
#define SPI_DISABLE_3WIRE_MODE | ( | spi | ) |
Disable slave 3-wire mode.
[in] | spi | is the base address of SPI module. |
#define SPI_DISABLE_BYTE_REORDER | ( | spi | ) |
Disable byte reorder function.
[in] | spi | is the base address of SPI module. |
#define SPI_DISABLE_DUAL_MODE | ( | spi | ) |
#define SPI_DISABLE_QUAD_MODE | ( | spi | ) |
#define SPI_DISABLE_RX_PDMA | ( | spi | ) |
#define SPI_DISABLE_TIMEOUT_FIFO_CLEAR | ( | spi | ) |
#define SPI_DISABLE_TX_PDMA | ( | spi | ) |
#define SPI_ENABLE | ( | spi | ) |
#define SPI_ENABLE_2BIT_MODE | ( | spi | ) |
Enable 2-bit transfer mode.
[in] | spi | is the base address of SPI module. |
#define SPI_ENABLE_3WIRE_MODE | ( | spi | ) |
Enable slave 3-wire mode.
[in] | spi | is the base address of SPI module. |
#define SPI_ENABLE_BYTE_REORDER | ( | spi | ) |
Enable byte reorder function.
[in] | spi | is the base address of SPI module. |
#define SPI_ENABLE_DUAL_INPUT_MODE | ( | spi | ) |
#define SPI_ENABLE_DUAL_OUTPUT_MODE | ( | spi | ) |
#define SPI_ENABLE_QUAD_INPUT_MODE | ( | spi | ) |
#define SPI_ENABLE_QUAD_OUTPUT_MODE | ( | spi | ) |
#define SPI_ENABLE_TIMEOUT_FIFO_CLEAR | ( | spi | ) |
#define SPI_GET_RX_FIFO_COUNT | ( | spi | ) |
#define SPI_GET_RX_FIFO_EMPTY_FLAG | ( | spi | ) |
#define SPI_GET_STATUS | ( | spi | ) |
#define SPI_GET_TX_FIFO_EMPTY_FLAG | ( | spi | ) |
#define SPI_GET_TX_FIFO_FULL_FLAG | ( | spi | ) |
#define SPI_IS_BUSY | ( | spi | ) |
#define SPI_READ_RX | ( | spi | ) |
#define SPI_SET_LSB_FIRST | ( | spi | ) |
Set the SPI transfer sequence with LSB first.
[in] | spi | is the base address of SPI module. |
#define SPI_SET_MSB_FIRST | ( | spi | ) |
Set the SPI transfer sequence with MSB first.
[in] | spi | is the base address of SPI module. |
#define SPI_SET_SLAVE_TIMEOUT_PERIOD | ( | spi, | |
u32TimeoutPeriod | |||
) |
Set time out period for slave.
[in] | spi | is the base address of SPI module. |
[in] | u32TimeoutPeriod | is the period of time out. |
#define SPI_SET_SS0_HIGH | ( | spi | ) |
#define SPI_SET_SS0_LOW | ( | spi | ) |
#define SPI_SET_SS1_HIGH | ( | spi | ) |
#define SPI_SET_SS1_LOW | ( | spi | ) |
#define SPI_SET_SUSPEND_CYCLE | ( | spi, | |
u32SuspCycle | |||
) |
Set the length of suspend interval.
[in] | spi | is the base address of SPI module. |
[in] | u32SuspCycle | decides the length of suspend interval. |
#define SPI_SET_TX_UNDERRUN_DATA_HIGH | ( | spi | ) |
#define SPI_SET_TX_UNDERRUN_DATA_LOW | ( | spi | ) |
#define SPI_TRIGGER | ( | spi | ) |
#define SPI_TRIGGER_RX_PDMA | ( | spi | ) |
#define SPI_TRIGGER_TX_PDMA | ( | spi | ) |
#define SPI_TRIGGER_TXRX_PDMA | ( | spi | ) |
#define SPI_WRITE_TX | ( | spi, | |
u32TxData | |||
) |
void SPI_ClearRxFIFO | ( | SPI_T * | spi | ) |
void SPI_ClearTxFIFO | ( | SPI_T * | spi | ) |
void SPI_Close | ( | SPI_T * | spi | ) |
void SPI_DisableAutoSS | ( | SPI_T * | spi | ) |
void SPI_DisableInt | ( | SPI_T * | spi, |
uint32_t | u32Mask | ||
) |
Disable FIFO related interrupts specified by u32Mask parameter.
[in] | spi | is the base address of SPI module. |
[in] | u32Mask | is the combination of all related interrupt enable bits. Each bit corresponds to a interrupt bit. This parameter decides which interrupts will be enabled. Valid values are: |
void SPI_EnableAutoSS | ( | SPI_T * | spi, |
uint32_t | u32SSPinMask, | ||
uint32_t | u32ActiveLevel | ||
) |
Enable the automatic slave select function. Only available in Master mode.
[in] | spi | is the base address of SPI module. |
[in] | u32SSPinMask | specifies slave select pins. Valid values are: |
[in] | u32ActiveLevel | specifies the active level of slave select signal. Valid values are: |
void SPI_EnableInt | ( | SPI_T * | spi, |
uint32_t | u32Mask | ||
) |
Enable FIFO related interrupts specified by u32Mask parameter.
[in] | spi | is the base address of SPI module. |
[in] | u32Mask | is the combination of all related interrupt enable bits. Each bit corresponds to a interrupt bit. This parameter decides which interrupts will be enabled. Valid values are: |
uint32_t SPI_GetBusClock | ( | SPI_T * | spi | ) |
uint32_t SPI_Open | ( | SPI_T * | spi, |
uint32_t | u32MasterSlave, | ||
uint32_t | u32SPIMode, | ||
uint32_t | u32DataWidth, | ||
uint32_t | u32BusClock | ||
) |
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB first and the automatic slave select function is disabled. In Slave mode, the u32BusClock must be NULL and the SPI clock divider setting will be 0.
[in] | spi | is the base address of SPI module. |
[in] | u32MasterSlave | decides the SPI module is operating in master mode or in slave mode. Valid values are: |
[in] | u32SPIMode | decides the transfer timing. Valid values are: |
[in] | u32DataWidth | decides the data width of a SPI transaction. |
[in] | u32BusClock | is the expected frequency of SPI bus clock in Hz. |
Definition at line 46 of file spi.c.
|
static |
Set the data width of a SPI transaction.
[in] | spi | is the base address of SPI module. |
[in] | u32Width | data width |
uint32_t SPI_SetBusClock | ( | SPI_T * | spi, |
uint32_t | u32BusClock | ||
) |
Set the SPI bus clock. Only available in Master mode.
[in] | spi | is the base address of SPI module. |
[in] | u32BusClock | is the expected frequency of SPI bus clock. |
Definition at line 138 of file spi.c.
void SPI_SetFIFOThreshold | ( | SPI_T * | spi, |
uint32_t | u32TxThreshold, | ||
uint32_t | u32RxThreshold | ||
) |