| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

spi.c
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1/****************************************************************************/
12#include "NUC472_442.h"
13
46uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
47{
48 if(u32DataWidth == 32)
49 u32DataWidth = 0;
50
51 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode);
52
53 return ( SPI_SetBusClock(spi, u32BusClock) );
54}
55
61 void SPI_Close(SPI_T *spi)
62{
63 /* Reset SPI */
64 if((uint32_t)spi == SPI0_BASE)
65 {
66 SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
67 SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
68 }
69 else if((uint32_t)spi == SPI1_BASE)
70 {
71 SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
72 SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
73 }
74 else if((uint32_t)spi == SPI2_BASE)
75 {
76 SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
77 SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
78 }
79 else
80 {
81 SYS->IPRST1 |= SYS_IPRST1_SPI3RST_Msk;
82 SYS->IPRST1 &= ~SYS_IPRST1_SPI3RST_Msk;
83 }
84}
85
91 void SPI_ClearRxFIFO(SPI_T *spi)
92{
93 spi->FIFOCTL |= SPI_FIFOCTL_RXRST_Msk;
94}
95
101 void SPI_ClearTxFIFO(SPI_T *spi)
102{
103 spi->FIFOCTL |= SPI_FIFOCTL_TXRST_Msk;
104}
105
111 void SPI_DisableAutoSS(SPI_T *spi)
112{
113 spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
114}
115
127 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
128{
129 spi->SSCTL = (spi->SSCTL & ~(SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
130}
131
138uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
139{
140 uint32_t u32ClkSrc, u32Div = 0;
141
142 if(spi == SPI0)
143 {
144 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK)
145 u32ClkSrc = CLK_GetPCLKFreq();
146 else
147 u32ClkSrc = CLK_GetPLLClockFreq();
148 }
149 else if(spi == SPI1)
150 {
151 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK)
152 u32ClkSrc = CLK_GetPCLKFreq();
153 else
154 u32ClkSrc = CLK_GetPLLClockFreq();
155 }
156 else if(spi == SPI2)
157 {
158 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK)
159 u32ClkSrc = CLK_GetPCLKFreq();
160 else
161 u32ClkSrc = CLK_GetPLLClockFreq();
162 }
163 else
164 {
165 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK)
166 u32ClkSrc = CLK_GetPCLKFreq();
167 else
168 u32ClkSrc = CLK_GetPLLClockFreq();
169 }
170
171 if(u32BusClock > u32ClkSrc)
172 u32BusClock = u32ClkSrc;
173
174 if(u32BusClock != 0 )
175 {
176 u32Div = (u32ClkSrc / u32BusClock) - 1;
177 if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
178 u32Div = SPI_CLKDIV_DIVIDER_Msk;
179 }
180 else
181 return 0;
182
183 spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
184
185 return ( u32ClkSrc / (u32Div+1) );
186}
187
195 void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
196{
197 spi->FIFOCTL = ((spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
198 (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
199 (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
200}
201
207uint32_t SPI_GetBusClock(SPI_T *spi)
208{
209 uint32_t u32Div;
210 uint32_t u32ClkSrc;
211
212 if(spi == SPI0)
213 {
214 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK)
215 u32ClkSrc = CLK_GetPCLKFreq();
216 else
217 u32ClkSrc = CLK_GetPLLClockFreq();
218 }
219 else if(spi == SPI1)
220 {
221 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK)
222 u32ClkSrc = CLK_GetPCLKFreq();
223 else
224 u32ClkSrc = CLK_GetPLLClockFreq();
225 }
226 else if(spi == SPI2)
227 {
228 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK)
229 u32ClkSrc = CLK_GetPCLKFreq();
230 else
231 u32ClkSrc = CLK_GetPLLClockFreq();
232 }
233 else
234 {
235 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK)
236 u32ClkSrc = CLK_GetPCLKFreq();
237 else
238 u32ClkSrc = CLK_GetPLLClockFreq();
239 }
240
241 u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk;
242 return (u32ClkSrc / (u32Div + 1));
243}
244
264 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
265{
266 if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK)
267 spi->CTL |= SPI_CTL_UNITIEN_Msk;
268
269 if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK)
270 spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
271
272 if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK)
273 spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
274
275 if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK)
276 spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
277
278 if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK)
279 spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
280
281 if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK)
282 spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk;
283
284 if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
285 spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
286
287 if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
288 spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
289
290 if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
291 spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
292
293 if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK)
294 spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
295
296 if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK)
297 spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
298}
299
319 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
320{
321 if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK)
322 spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
323
324 if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK)
325 spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
326
327 if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK)
328 spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
329
330 if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK)
331 spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
332
333 if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK)
334 spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
335
336 if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK)
337 spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
338
339 if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
340 spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
341
342 if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
343 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
344
345 if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
346 spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
347
348 if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK)
349 spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
350
351 if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK)
352 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
353}
354 /* end of group NUC472_442_SPI_EXPORTED_FUNCTIONS */
356 /* end of group NUC472_442_SPI_Driver */
358 /* end of group NUC472_442_Device_Driver */
360
361/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
NUC472_442.h
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's d...
SPI_SSCTL_SSACTPOL_Msk
#define SPI_SSCTL_SSACTPOL_Msk
Definition: NUC472_442.h:23116
SPI_FIFOCTL_RXOVIEN_Msk
#define SPI_FIFOCTL_RXOVIEN_Msk
Definition: NUC472_442.h:23170
SPI_SSCTL_SS_Msk
#define SPI_SSCTL_SS_Msk
Definition: NUC472_442.h:23113
SPI_CTL_UNITIEN_Msk
#define SPI_CTL_UNITIEN_Msk
Definition: NUC472_442.h:23092
SPI_FIFOCTL_RXTH_Pos
#define SPI_FIFOCTL_RXTH_Pos
Definition: NUC472_442.h:23178
SPI_FIFOCTL_TXTH_Msk
#define SPI_FIFOCTL_TXTH_Msk
Definition: NUC472_442.h:23182
SPI_CTL_DWIDTH_Pos
#define SPI_CTL_DWIDTH_Pos
Definition: NUC472_442.h:23082
SPI_SSCTL_SLVTOIEN_Msk
#define SPI_SSCTL_SLVTOIEN_Msk
Definition: NUC472_442.h:23125
SYS_IPRST1_SPI2RST_Msk
#define SYS_IPRST1_SPI2RST_Msk
Definition: NUC472_442.h:24277
SPI_FIFOCTL_RXRST_Msk
#define SPI_FIFOCTL_RXRST_Msk
Definition: NUC472_442.h:23155
CLK_CLKSEL1_SPI0SEL_Msk
#define CLK_CLKSEL1_SPI0SEL_Msk
Definition: NUC472_442.h:3785
SPI_FIFOCTL_TXRST_Msk
#define SPI_FIFOCTL_TXRST_Msk
Definition: NUC472_442.h:23158
SPI_SSCTL_SSACTIEN_Msk
#define SPI_SSCTL_SSACTIEN_Msk
Definition: NUC472_442.h:23137
SYS_IPRST1_SPI1RST_Msk
#define SYS_IPRST1_SPI1RST_Msk
Definition: NUC472_442.h:24274
SYS_IPRST1_SPI0RST_Msk
#define SYS_IPRST1_SPI0RST_Msk
Definition: NUC472_442.h:24271
SPI_FIFOCTL_TXUFIEN_Msk
#define SPI_FIFOCTL_TXUFIEN_Msk
Definition: NUC472_442.h:23176
CLK_CLKSEL1_SPI2SEL_Msk
#define CLK_CLKSEL1_SPI2SEL_Msk
Definition: NUC472_442.h:3791
SPI_CLKDIV_DIVIDER_Msk
#define SPI_CLKDIV_DIVIDER_Msk
Definition: NUC472_442.h:23110
SPI_FIFOCTL_TXTH_Pos
#define SPI_FIFOCTL_TXTH_Pos
Definition: NUC472_442.h:23181
SPI_SSCTL_SLVBEIEN_Msk
#define SPI_SSCTL_SLVBEIEN_Msk
Definition: NUC472_442.h:23131
CLK_CLKSEL1_SPI3SEL_Msk
#define CLK_CLKSEL1_SPI3SEL_Msk
Definition: NUC472_442.h:3794
SPI_SSCTL_SSINAIEN_Msk
#define SPI_SSCTL_SSINAIEN_Msk
Definition: NUC472_442.h:23140
SPI_FIFOCTL_RXTOIEN_Msk
#define SPI_FIFOCTL_RXTOIEN_Msk
Definition: NUC472_442.h:23167
SPI_FIFOCTL_RXTHIEN_Msk
#define SPI_FIFOCTL_RXTHIEN_Msk
Definition: NUC472_442.h:23161
SPI_FIFOCTL_RXTH_Msk
#define SPI_FIFOCTL_RXTH_Msk
Definition: NUC472_442.h:23179
CLK_CLKSEL1_SPI1SEL_Msk
#define CLK_CLKSEL1_SPI1SEL_Msk
Definition: NUC472_442.h:3788
SYS_IPRST1_SPI3RST_Msk
#define SYS_IPRST1_SPI3RST_Msk
Definition: NUC472_442.h:24280
SPI_SSCTL_SLVURIEN_Msk
#define SPI_SSCTL_SLVURIEN_Msk
Definition: NUC472_442.h:23134
SPI_FIFOCTL_TXTHIEN_Msk
#define SPI_FIFOCTL_TXTHIEN_Msk
Definition: NUC472_442.h:23164
SPI_SSCTL_AUTOSS_Msk
#define SPI_SSCTL_AUTOSS_Msk
Definition: NUC472_442.h:23119
CLK_CLKSEL1_SPI1SEL_PCLK
#define CLK_CLKSEL1_SPI1SEL_PCLK
Definition: clk.h:142
CLK_CLKSEL1_SPI2SEL_PCLK
#define CLK_CLKSEL1_SPI2SEL_PCLK
Definition: clk.h:145
CLK_CLKSEL1_SPI0SEL_PCLK
#define CLK_CLKSEL1_SPI0SEL_PCLK
Definition: clk.h:139
CLK_CLKSEL1_SPI3SEL_PCLK
#define CLK_CLKSEL1_SPI3SEL_PCLK
Definition: clk.h:148
CLK_GetPCLKFreq
uint32_t CLK_GetPCLKFreq(void)
This function get PCLK frequency. The frequency unit is Hz.
Definition: clk.c:104
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:166
CLK
#define CLK
Definition: NUC472_442.h:28798
SPI1
#define SPI1
Definition: NUC472_442.h:28850
SYS
#define SYS
Definition: NUC472_442.h:28797
SPI0
#define SPI0
Definition: NUC472_442.h:28849
SPI2
#define SPI2
Definition: NUC472_442.h:28851
SPI1_BASE
#define SPI1_BASE
Definition: NUC472_442.h:28774
SPI2_BASE
#define SPI2_BASE
Definition: NUC472_442.h:28748
SPI0_BASE
#define SPI0_BASE
Definition: NUC472_442.h:28747
SPI_SSINAIEN_MASK
#define SPI_SSINAIEN_MASK
Definition: spi.h:47
SPI_SLVTOIEN_MASK
#define SPI_SLVTOIEN_MASK
Definition: spi.h:51
SPI_FIFO_TXUFIEN_MASK
#define SPI_FIFO_TXUFIEN_MASK
Definition: spi.h:55
SPI_UNITIEN_MASK
#define SPI_UNITIEN_MASK
Definition: spi.h:46
SPI_FIFO_RXOVIEN_MASK
#define SPI_FIFO_RXOVIEN_MASK
Definition: spi.h:54
SPI_SLVBEIEN_MASK
#define SPI_SLVBEIEN_MASK
Definition: spi.h:50
SPI_FIFO_RXTOIEN_MASK
#define SPI_FIFO_RXTOIEN_MASK
Definition: spi.h:56
SPI_FIFO_RXTHIEN_MASK
#define SPI_FIFO_RXTHIEN_MASK
Definition: spi.h:53
SPI_SSACTIEN_MASK
#define SPI_SSACTIEN_MASK
Definition: spi.h:48
SPI_SLVURIEN_MASK
#define SPI_SLVURIEN_MASK
Definition: spi.h:49
SPI_FIFO_TXTHIEN_MASK
#define SPI_FIFO_TXTHIEN_MASK
Definition: spi.h:52
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:319
SPI_SetFIFOThreshold
void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Set Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:195
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:264
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:127
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:111
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:138
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:61
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:101
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:46
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:207
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:91
SPI_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:22774
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: NUC472_442.h:22789
SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: NUC472_442.h:22919
SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: NUC472_442.h:22848
SPI_T
Definition: NUC472_442.h:22695