| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

eadc.h
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1/**************************************************************************/
12#ifndef __EADC_H__
13#define __EADC_H__
14
15#ifdef __cplusplus
16extern "C"
17{
18#endif
19
20
33/*---------------------------------------------------------------------------------------------------------*/
34/* EADC SAMPLE module number Definitions */
35/*---------------------------------------------------------------------------------------------------------*/
36#define EADC0_SAMPLE_MODULE0 0
37#define EADC0_SAMPLE_MODULE1 1
38#define EADC0_SAMPLE_MODULE2 2
39#define EADC0_SAMPLE_MODULE3 3
40#define EADC0_SAMPLE_MODULE4 4
41#define EADC0_SAMPLE_MODULE5 5
42#define EADC0_SAMPLE_MODULE6 6
43#define EADC0_SAMPLE_MODULE7 7
44#define EADC1_SAMPLE_MODULE0 8
45#define EADC1_SAMPLE_MODULE1 9
46#define EADC1_SAMPLE_MODULE2 10
47#define EADC1_SAMPLE_MODULE3 11
48#define EADC1_SAMPLE_MODULE4 12
49#define EADC1_SAMPLE_MODULE5 13
50#define EADC1_SAMPLE_MODULE6 14
51#define EADC1_SAMPLE_MODULE7 15
53/*---------------------------------------------------------------------------------------------------------*/
54/* EADC Compare SAMPLE module number Definitions */
55/*---------------------------------------------------------------------------------------------------------*/
56#define CMP_EADC0_SAMPLE_MODULE0 0
57#define CMP_EADC0_SAMPLE_MODULE1 1
58#define CMP_EADC0_SAMPLE_MODULE2 2
59#define CMP_EADC0_SAMPLE_MODULE3 3
60#define CMP_EADC1_SAMPLE_MODULE0 4
61#define CMP_EADC1_SAMPLE_MODULE1 5
62#define CMP_EADC1_SAMPLE_MODULE2 6
63#define CMP_EADC1_SAMPLE_MODULE3 7
65/*---------------------------------------------------------------------------------------------------------*/
66/* EADC_ADnSPCTLx Constant Definitions */
67/*---------------------------------------------------------------------------------------------------------*/
68#define EADC_SCTL_CHSEL(x) ((x) << EADC_AD0SPCTL0_CHSEL_Pos)
69#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_AD0SPCTL0_TRGDLYDIV_Pos)
70#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_AD0SPCTL0_TRGDLYCNT_Pos)
72#define EADC_SOFTWARE_TRIGGER (0UL << EADC_AD0SPCTL0_TRGSEL_Pos)
73#define EADC_STADC_TRIGGER (1UL << EADC_AD0SPCTL0_TRGSEL_Pos)
74#define EADC_ADINT0_TRIGGER (2UL << EADC_AD0SPCTL0_TRGSEL_Pos)
75#define EADC_ADINT1_TRIGGER (3UL << EADC_AD0SPCTL0_TRGSEL_Pos)
76#define EADC_TIMER0_TRIGGER (4UL << EADC_AD0SPCTL0_TRGSEL_Pos)
77#define EADC_TIMER1_TRIGGER (5UL << EADC_AD0SPCTL0_TRGSEL_Pos)
78#define EADC_TIMER2_TRIGGER (6UL << EADC_AD0SPCTL0_TRGSEL_Pos)
79#define EADC_TIMER3_TRIGGER (7UL << EADC_AD0SPCTL0_TRGSEL_Pos)
80#define EADC_EPWM0CH0_TRIGGER (8UL << EADC_AD0SPCTL0_TRGSEL_Pos)
81#define EADC_EPWM0CH2_TRIGGER (9UL << EADC_AD0SPCTL0_TRGSEL_Pos)
82#define EADC_EPWM0CH4_TRIGGER (0xAUL << EADC_AD0SPCTL0_TRGSEL_Pos)
83#define EADC_EPWM1CH0_TRIGGER (0xBUL << EADC_AD0SPCTL0_TRGSEL_Pos)
84#define EADC_EPWM1CH2_TRIGGER (0xCUL << EADC_AD0SPCTL0_TRGSEL_Pos)
85#define EADC_EPWM1CH4_TRIGGER (0xDUL << EADC_AD0SPCTL0_TRGSEL_Pos)
86#define EADC_PWM0CH0_TRIGGER (0xEUL << EADC_AD0SPCTL0_TRGSEL_Pos)
87#define EADC_PWM0CH1_TRIGGER (0xFUL << EADC_AD0SPCTL0_TRGSEL_Pos)
89#define EADC_SPCTL_TRGDLYDIV_DIVIDER_1 (0 << EADC_AD0SPCTL0_TRGDLYDIV_Pos)
90#define EADC_SPCTL_TRGDLYDIV_DIVIDER_2 (0x1UL << EADC_AD0SPCTL0_TRGDLYDIV_Pos)
91#define EADC_SPCTL_TRGDLYDIV_DIVIDER_4 (0x2UL << EADC_AD0SPCTL0_TRGDLYDIV_Pos)
92#define EADC_SPCTL_TRGDLYDIV_DIVIDER_16 (0x3UL << EADC_AD0SPCTL0_TRGDLYDIV_Pos)
95/*---------------------------------------------------------------------------------------------------------*/
96/* EADC_CMP Constant Definitions */
97/*---------------------------------------------------------------------------------------------------------*/
98#define EADC_CMP_CMPCOND_LESS_THAN (0UL << EADC_CMP0_CMPCOND_Pos)
99#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL << EADC_CMP0_CMPCOND_Pos)
100#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP0_ADCMPIE_Msk)
101#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP0_ADCMPIE_Msk)
103/*---------------------------------------------------------------------------------------------------------*/
104/* EADC PWM Trigger Condition Definitions */
105/*---------------------------------------------------------------------------------------------------------*/
106#define EADC0_TRIGGEREN0 0
107#define EADC0_TRIGGEREN1 1
108#define EADC0_TRIGGEREN2 2
109#define EADC0_TRIGGEREN3 3
110#define EADC1_TRIGGEREN0 4
111#define EADC1_TRIGGEREN1 5
112#define EADC1_TRIGGEREN2 6
113#define EADC1_TRIGGEREN3 7
115/*---------------------------------------------------------------------------------------------------------*/
116/* EADC Channel selection Definitions */
117/*---------------------------------------------------------------------------------------------------------*/
118#define EADC0_CH0 0
119#define EADC0_CH1 1
120#define EADC0_CH2 2
121#define EADC0_CH3 3
122#define EADC0_CH4 4
123#define EADC0_CH5 5
124#define EADC0_CH6 6
125#define EADC0_CH7 7
126#define EADC0_VBG 8
127#define EADC0_VTEMP 9
128#define EADC0_AVSS 10
129#define EADC0_OP0 11
130#define EADC1_CH0 0
131#define EADC1_CH1 1
132#define EADC1_CH2 2
133#define EADC1_CH3 3
134#define EADC1_CH4 4
135#define EADC1_CH5 5
136#define EADC1_CH6 6
137#define EADC1_CH7 7
138#define EADC1_OP1 8 /* end of group NUC472_442_EADC_EXPORTED_CONSTANTS */
141
145/*---------------------------------------------------------------------------------------------------------*/
146/* EADC Macro Definitions */
147/*---------------------------------------------------------------------------------------------------------*/
148
155#define EADC_POWER_DOWN(eadc) (EADC->CTL &= ~EADC_CTL_ADCEN_Msk)
156
163#define EADC_POWER_ON(eadc) (EADC->CTL |= EADC_CTL_ADCEN_Msk)
164
172#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
173
190#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->DBMEN |= (1 << u32ModuleNum))
191
208#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->DBMEN &= ~(1 << u32ModuleNum))
209
220#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
221
231#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
232
243#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
244
255#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
256
267#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
268
278#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
279
304#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) (*(__IO uint32_t *)(&((eadc)->AD0DAT0) + (u32ModuleNum)) & EADC_AD0DAT0_RESULT_Msk)
305
314#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) (((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) & (u32ModuleMask))
315
324#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) (((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) & (u32ModuleMask))
325
342#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) (*(__IO uint32_t *)(&((eadc)->AD0DDAT0) + (u32ModuleNum)) & EADC_AD0DDAT0_RESULT_Msk)
343
354#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS1 & (u32Mask))
355
364#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) (((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) & u32ModuleMask)
365
376#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS1 = (u32Mask))
377
386#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS1 & EADC_STATUS1_AOV_Msk) >> EADC_STATUS1_AOV_Pos)
387
396#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS1 & EADC_STATUS1_AVALID_Msk) >> EADC_STATUS1_AVALID_Pos)
397
406#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS1 & EADC_STATUS1_STOVF_Msk) >> EADC_STATUS1_STOVF_Pos)
407
416#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS1 & EADC_STATUS1_ADOVIF_Msk) >> EADC_STATUS1_ADOVIF_Pos)
417
427#define EADC_IS_BUSY(eadc, converter) (((((eadc)->STATUS1 >> (EADC_STATUS1_BUSY0_Pos + (8 * converter)))) & EADC_STATUS1_BUSY0_Msk) )
428
452#define EADC_ENABLE_CMP0(eadc,\
453 u32ModuleNum,\
454 u32Condition,\
455 u16CMPData,\
456 u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP0_CMPSPL_Pos)|\
457 (u32Condition) |\
458 ((u16CMPData) << EADC_CMP0_CMPDAT_Pos)| \
459 (((u32MatchCount) - 1) << EADC_CMP0_CMPMCNT_Pos)|\
460 EADC_CMP0_ADCMPEN_Msk))
461
485#define EADC_ENABLE_CMP1(eadc,\
486 u32ModuleNum,\
487 u32Condition,\
488 u16CMPData,\
489 u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP1_CMPSPL_Pos)|\
490 (u32Condition) |\
491 ((u16CMPData) << EADC_CMP1_CMPDAT_Pos)| \
492 (((u32MatchCount) - 1) << EADC_CMP1_CMPMCNT_Pos)|\
493 EADC_CMP1_ADCMPEN_Msk))
494
505#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP0_ADCMPIE_Msk)
506
515#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP0_ADCMPIE_Msk)
516
524#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
525
533#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
534
545#define EADC_ENABLE_SIMULTANEOUS(eadc,u32ModuleMask) ((eadc)->SIMUSEL |= (u32ModuleMask))
546
557#define EADC_DISABLE_SIMULTANEOUS(eadc,u32ModuleMask) ((eadc)->SIMUSEL &= ~(u32ModuleMask))
558
575#define EADC_EnablePWMTriggerCondition(eadc,u32ADTriggerModuleNum,u32TriggerMask) (*(__IO uint32_t *)(&(eadc)->AD0TRGEN0 + (u32ADTriggerModuleNum)) |= (u32TriggerMask))
576
593#define EADC_DisablePWMTriggerCondition(eadc,u32ADTriggerModuleNum,u32TriggerMask) (*(__IO uint32_t *)(&(eadc)->AD0TRGEN0 + (u32ADTriggerModuleNum)) |= (u32TriggerMask))
594
595/*---------------------------------------------------------------------------------------------------------*/
596/* Define EADC functions prototype */
597/*---------------------------------------------------------------------------------------------------------*/
598void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
599void EADC_Close(EADC_T *eadc);
600void EADC_ConfigSampleModule(EADC_T *eadc, \
601 uint32_t u32ModuleNum, \
602 uint32_t u32TriggerSource, \
603 uint32_t u32Channel);
604void EADC_SetTriggerDelayTime(EADC_T *eadc, \
605 uint32_t u32ModuleNum, \
606 uint32_t u32TriggerDelayTime, \
607 uint32_t u32DelayClockDivider);
608void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
609 /* end of group NUC472_442_EADC_EXPORTED_FUNCTIONS */
611 /* end of group NUC472_442_EADC_Driver */
613 /* end of group NUC472_442_Device_Driver */
615
616
617#ifdef __cplusplus
618}
619#endif
620
621#endif //__EADC_H__
622
623/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
EADC_Close
void EADC_Close(EADC_T *eadc)
Disable EADC_module.
Definition: eadc.c:47
EADC_SetExtendSampleTime
void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
Set EADC extend sample time.
Definition: eadc.c:192
EADC_SetTriggerDelayTime
void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider)
Set trigger delay time.
Definition: eadc.c:157
EADC_ConfigSampleModule
void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel)
Configure the sample control logic module.
Definition: eadc.c:114
EADC_Open
void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
This function make EADC_module be ready to convert.
Definition: eadc.c:36
EADC_T
Definition: NUC472_442.h:7417