| NUC472_NUC442_BSP V3.04.000 The Board Support Package for NUC472/NUC442

pwm.c
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1/**************************************************************************/
12#include "NUC472_442.h"
13
21int32_t g_PWM_i32ErrCode = 0;
37uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
38 uint32_t u32ChannelNum,
39 uint32_t u32Frequency,
40 uint32_t u32DutyCycle)
41{
42 uint32_t i;
43 uint32_t u32PWM_CLock = __HIRC;
44 uint8_t u8Divider = 1, u8Prescale = 0xFF;
45 uint16_t u16CNR = 0xFFFF;
46 uint32_t u32Delay = SystemCoreClock; /* 1 second */
47
48 if (pwm == PWM0)
49 {
50 if (u32ChannelNum < 2)
51 {
52 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
53 u32PWM_CLock = __HXT;
54 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
55 u32PWM_CLock = __LXT;
56 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
57 u32PWM_CLock = SystemCoreClock;
58 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
59 u32PWM_CLock = __HIRC;
60 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
61 u32PWM_CLock = __LIRC;
62 }
63 else if (u32ChannelNum < 4)
64 {
65 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
66 u32PWM_CLock = __HXT;
67 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
68 u32PWM_CLock = __LXT;
69 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
70 u32PWM_CLock = SystemCoreClock;
71 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
72 u32PWM_CLock = __HIRC;
73 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
74 u32PWM_CLock = __LIRC;
75 }
76 else if (u32ChannelNum < 6)
77 {
78 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
79 u32PWM_CLock = __HXT;
80 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
81 u32PWM_CLock = __LXT;
82 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
83 u32PWM_CLock = SystemCoreClock;
84 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
85 u32PWM_CLock = __HIRC;
86 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
87 u32PWM_CLock = __LIRC;
88 }
89 }
90 else if (pwm == PWM1)
91 {
92 if (u32ChannelNum < 2)
93 {
94 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
95 u32PWM_CLock = __HXT;
96 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
97 u32PWM_CLock = __LXT;
98 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
99 u32PWM_CLock = SystemCoreClock;
100 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
101 u32PWM_CLock = __HIRC;
102 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
103 u32PWM_CLock = __LIRC;
104 }
105 else if (u32ChannelNum < 4)
106 {
107 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
108 u32PWM_CLock = __HXT;
109 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
110 u32PWM_CLock = __LXT;
111 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
112 u32PWM_CLock = SystemCoreClock;
113 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
114 u32PWM_CLock = __HIRC;
115 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
116 u32PWM_CLock = __LIRC;
117 }
118 else if (u32ChannelNum < 6)
119 {
120 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
121 u32PWM_CLock = __HXT;
122 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
123 u32PWM_CLock = __LXT;
124 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
125 u32PWM_CLock = SystemCoreClock;
126 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
127 u32PWM_CLock = __HIRC;
128 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
129 u32PWM_CLock = __LIRC;
130 }
131 }
132
133 for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16
134 {
135 i = (u32PWM_CLock / u32Frequency) / u8Divider;
136 // If target value is larger than CNR * prescale, need to use a larger divider
137 if(i > (0x10000 * 0x100))
138 continue;
139
140 // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
141 u8Prescale = (i + 0xFFFF)/ 0x10000;
142
143 // u8Prescale must at least be 2, otherwise the output stop
144 if(u8Prescale < 3)
145 u8Prescale = 2;
146
147 i /= u8Prescale;
148
149 if(i <= 0x10000)
150 {
151 if(i == 1)
152 u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
153 else
154 u16CNR = i;
155 break;
156 }
157
158 }
159 // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
160 i = u32PWM_CLock / (u8Prescale * u8Divider * u16CNR);
161
162 u8Prescale -= 1;
163 u16CNR -= 1;
164 // convert to real register value
165 if(u8Divider == 1)
166 u8Divider = 4;
167 else if (u8Divider == 2)
168 u8Divider = 0;
169 else if (u8Divider == 4)
170 u8Divider = 1;
171 else if (u8Divider == 8)
172 u8Divider = 2;
173 else // 16
174 u8Divider = 3;
175
176 // every two channels share a prescaler
177 while((pwm->SBS[u32ChannelNum] & 1) == 1)
178 {
179 u32Delay--;
180 if(u32Delay == 0){
181 g_PWM_i32ErrCode = PWM_TIMEOUT_ERR;
182 break;
183 }
184 }
185 pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
186 pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
187 pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
188 if(u32DutyCycle == 0)
189 pwm->CMPDAT[u32ChannelNum] = 0;
190 else
191 pwm->CMPDAT[u32ChannelNum] = u32DutyCycle * (u16CNR + 1) / 100 - 1;
192 pwm->PERIOD[u32ChannelNum] = u16CNR;
193
194 return(i);
195}
196
207uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
208 uint32_t u32ChannelNum,
209 uint32_t u32UnitTimeNsec,
210 uint32_t u32CaptureEdge)
211{
212 uint32_t i;
213 uint32_t u32PWM_CLock = __HIRC;
214 uint8_t u8Divider = 1, u8Prescale = 0xFF;
215 uint16_t u16CNR = 0xFFFF;
216 uint32_t u32Delay = SystemCoreClock; /* 1 second */
217
218 if (pwm == PWM0)
219 {
220 if (u32ChannelNum < 2)
221 {
222 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
223 u32PWM_CLock = __HXT;
224 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
225 u32PWM_CLock = __LXT;
226 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
227 u32PWM_CLock = SystemCoreClock;
228 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
229 u32PWM_CLock = __HIRC;
230 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
231 u32PWM_CLock = __LIRC;
232 }
233 else if (u32ChannelNum < 4)
234 {
235 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
236 u32PWM_CLock = __HXT;
237 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
238 u32PWM_CLock = __LXT;
239 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
240 u32PWM_CLock = SystemCoreClock;
241 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
242 u32PWM_CLock = __HIRC;
243 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
244 u32PWM_CLock = __LIRC;
245 }
246 else if (u32ChannelNum < 6)
247 {
248 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
249 u32PWM_CLock = __HXT;
250 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
251 u32PWM_CLock = __LXT;
252 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
253 u32PWM_CLock = SystemCoreClock;
254 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
255 u32PWM_CLock = __HIRC;
256 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
257 u32PWM_CLock = __LIRC;
258 }
259 }
260 else if (pwm == PWM1)
261 {
262 if (u32ChannelNum < 2)
263 {
264 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
265 u32PWM_CLock = __HXT;
266 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
267 u32PWM_CLock = __LXT;
268 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
269 u32PWM_CLock = SystemCoreClock;
270 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
271 u32PWM_CLock = __HIRC;
272 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
273 u32PWM_CLock = __LIRC;
274 }
275 else if (u32ChannelNum < 4)
276 {
277 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
278 u32PWM_CLock = __HXT;
279 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
280 u32PWM_CLock = __LXT;
281 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
282 u32PWM_CLock = SystemCoreClock;
283 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
284 u32PWM_CLock = __HIRC;
285 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
286 u32PWM_CLock = __LIRC;
287 }
288 else if (u32ChannelNum < 6)
289 {
290 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
291 u32PWM_CLock = __HXT;
292 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
293 u32PWM_CLock = __LXT;
294 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
295 u32PWM_CLock = SystemCoreClock;
296 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
297 u32PWM_CLock = __HIRC;
298 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
299 u32PWM_CLock = __LIRC;
300 }
301 }
302
303 for(; u8Divider < 17; u8Divider <<= 1) // clk divider could only be 1, 2, 4, 8, 16
304 {
305 i = ((u32PWM_CLock / u8Divider) * u32UnitTimeNsec) / 1000000000;
306
307 // If target value is larger than 0xFF, need to use a larger divider
308 if(i > (0xFF))
309 continue;
310
311 u8Prescale = i;
312
313 // u8Prescale must at least be 2, otherwise the output stop
314 if(u8Prescale < 3)
315 u8Prescale = 2;
316
317 break;
318 }
319
320 // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
321 i = (u8Prescale * u8Divider) * 1000000000/ u32PWM_CLock;
322
323 u8Prescale -= 1;
324 u16CNR -= 1;
325 // convert to real register value
326 if(u8Divider == 1)
327 u8Divider = 4;
328 else if (u8Divider == 2)
329 u8Divider = 0;
330 else if (u8Divider == 4)
331 u8Divider = 1;
332 else if (u8Divider == 8)
333 u8Divider = 2;
334 else // 16
335 u8Divider = 3;
336
337 // every two channels share a prescaler
338 while((pwm->SBS[u32ChannelNum] & 1) == 1)
339 {
340 u32Delay--;
341 if(u32Delay == 0){
342 g_PWM_i32ErrCode = PWM_TIMEOUT_ERR;
343 break;
344 }
345 }
346 pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
347 pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
348 pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
349 pwm->PERIOD[u32ChannelNum] = u16CNR;
350
351 return(i);
352}
353
361 void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
362{
363 pwm->CNTEN |= u32ChannelMask;
364}
365
373 void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
374{
375 uint32_t i;
376 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
377 {
378 if(u32ChannelMask & (1 << i))
379 {
380 *(__IO uint32_t *) (&pwm->CNTEN + 1 * i) = 0;
381 }
382 }
383
384}
385
393 void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
394{
395 pwm->CNTEN &= ~u32ChannelMask;
396}
397
409 void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
410{
411 pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
412 PWM_TRIGGER_ADC_CENTER_POINT |
413 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
414 PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum))) | (u32Condition << (1 * u32ChannelNum));
415}
416
423 void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
424{
425 pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
426 PWM_TRIGGER_ADC_CENTER_POINT |
427 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
428 PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum)));
429}
430
442 void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
443{
444 pwm->TRGADCSTS |= (u32Condition << (1 * u32ChannelNum));
445}
446
457uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
458{
459 uint32_t u32Ret;
460
461 u32Ret = pwm->TRGADCSTS >> u32ChannelNum;
462
463 return (u32Ret & (PWM_TRIGGER_ADC_PERIOD_POINT |
464 PWM_TRIGGER_ADC_CENTER_POINT |
465 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
466 PWM_TRIGGER_ADC_FALLING_EDGE_POINT));
467}
468
487 void PWM_EnableFaultBrake (PWM_T *pwm,
488 uint32_t u32ChannelMask,
489 uint32_t u32LevelMask,
490 uint32_t u32BrakeSource)
491{
492 if ((u32BrakeSource == PWM_BRK0_BKP0)||(u32BrakeSource == PWM_BRK0_CPO0)||(u32BrakeSource == PWM_BRK0_CPO1)||(u32BrakeSource == PWM_BRK0_CPO2))
493 pwm->BRKCTL |= (u32BrakeSource | PWM_BRKCTL_BRK0EN_Msk);
494 else if (u32BrakeSource == PWM_BRK1_LVDBK)
495 pwm->BRKCTL |= PWM_BRKCTL_LVDBKEN_Msk;
496 else
497 pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BK1SEL_Msk) | u32BrakeSource | PWM_BRKCTL_BRK1EN_Msk;
498
499 pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BKOD_Msk) | (u32LevelMask << PWM_BRKCTL_BKOD_Pos);
500
501}
502
511 void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
512{
513 if (u32BrakeSource == 0)
514 pwm->INTSTS = (PWM_INTSTS_BRKLK0_Msk | PWM_INTSTS_BRKIF0_Msk);
515 else
516 pwm->INTSTS = PWM_INTSTS_BRKIF1_Msk;
517}
518
526 void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
527{
528 pwm->CAPCTL |= u32ChannelMask;
529 pwm->CAPINEN |= u32ChannelMask;
530 pwm->CTL |= (u32ChannelMask << PWM_CTL_CNTMODE_Pos);
531}
532
540 void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
541{
542 pwm->CAPCTL &= ~u32ChannelMask;
543 pwm->CAPINEN &= ~u32ChannelMask;
544}
545
553 void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
554{
555 pwm->POEN |= u32ChannelMask;
556}
557
565 void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
566{
567 pwm->POEN &= ~u32ChannelMask;
568}
569
578 void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
579{
580 // every two channels shares the same setting
581 u32ChannelNum >>= 1;
582 // set duration
583 pwm->DTCTL = (pwm->DTCTL & ~(PWM_DTCTL_DTCNT01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
584 // enable dead zone
585 pwm->DTCTL |= (PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
586}
587
594 void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
595{
596 // every two channels shares the same setting
597 u32ChannelNum >>= 1;
598 // enable dead zone
599 pwm->DTCTL &= ~(PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
600}
601
612 void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
613{
614 // enable capture interrupt
615 pwm->INTEN |= (u32Edge << u32ChannelNum);
616}
617
628 void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
629{
630 // disable capture interrupt
631 pwm->INTEN &= ~(u32Edge << u32ChannelNum);
632}
633
644 void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
645{
646 // disable capture interrupt flag
647 pwm->INTSTS = (u32Edge << u32ChannelNum);
648}
649
660uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
661{
662 return ((pwm->INTSTS >> u32ChannelNum) & PWM_RISING_FALLING_LATCH_INT_FLAG);
663}
664
674 void PWM_EnableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
675{
676 // set duty interrupt type
677 pwm->INTCTL = (pwm->INTCTL & ~(PWM_DUTY_INT_MATCH_CMR_UP << u32ChannelNum)) | (u32IntDutyType << u32ChannelNum);
678 // enable duty interrupt
679 pwm->INTEN |= ((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
680}
681
688 void PWM_DisableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum)
689{
690 pwm->INTEN &= ~((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
691}
692
699 void PWM_ClearDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
700{
701 // write 1 clear
702 pwm->INTSTS = (1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum;
703}
704
713uint32_t PWM_GetDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
714{
715 return(pwm->INTSTS & ((1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum) ? 1 : 0);
716}
717
724 void PWM_EnableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
725{
726 pwm->INTEN |= PWM_INTEN_BRKIEN_Msk;
727}
728
735 void PWM_DisableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
736{
737 pwm->INTEN &= ~PWM_INTEN_BRKIEN_Msk;
738}
739
748 void PWM_ClearFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
749{
750 pwm->INTSTS = u32BrakeSource;
751}
752
763uint32_t PWM_GetFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
764{
765 return (pwm->INTSTS & u32BrakeSource ? 1 : 0);
766}
767
778 void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
779{
780 // set period interrupt type
781 pwm->INTCTL = (pwm->INTCTL & ~(PWM_PERIOD_INT_MATCH_CNR << u32ChannelNum)) | (u32IntPeriodType << u32ChannelNum);
782 // enable period interrupt
783 pwm->INTEN |= ((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
784}
785
792 void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
793{
794 pwm->INTEN &= ~((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
795}
796
803 void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
804{
805 // write 1 clear
806 pwm->INTSTS = ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum);
807}
808
817uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
818{
819 return(pwm->INTSTS & ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum) ? 1 : 0);
820}
821
822
823 /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
825 /* end of group NUC472_442_PWM_Driver */
827 /* end of group NUC472_442_Device_Driver */
829
830/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
NUC472_442.h
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's d...
PWM_BRKCTL_BKOD_Pos
#define PWM_BRKCTL_BKOD_Pos
Definition: NUC472_442.h:19948
CLK_CLKSEL2_PWM1CH45SEL_Msk
#define CLK_CLKSEL2_PWM1CH45SEL_Msk
Definition: NUC472_442.h:3833
PWM_INTSTS_PIF_Pos
#define PWM_INTSTS_PIF_Pos
Definition: NUC472_442.h:19972
PWM_INTSTS_BRKLK0_Msk
#define PWM_INTSTS_BRKLK0_Msk
Definition: NUC472_442.h:19985
PWM_CLKDIV_CLKDIV0_Msk
#define PWM_CLKDIV_CLKDIV0_Msk
Definition: NUC472_442.h:19760
PWM_CTL_CNTMODE_Pos
#define PWM_CTL_CNTMODE_Pos
Definition: NUC472_442.h:19792
PWM_DTCTL_DTCNT01_Msk
#define PWM_DTCTL_DTCNT01_Msk
Definition: NUC472_442.h:19865
PWM_BRKCTL_BRK0EN_Msk
#define PWM_BRKCTL_BRK0EN_Msk
Definition: NUC472_442.h:19910
CLK_CLKSEL2_PWM1CH45SEL_Pos
#define CLK_CLKSEL2_PWM1CH45SEL_Pos
Definition: NUC472_442.h:3832
PWM_INTSTS_BRKIF0_Msk
#define PWM_INTSTS_BRKIF0_Msk
Definition: NUC472_442.h:19976
PWM_BRKCTL_BRK1EN_Msk
#define PWM_BRKCTL_BRK1EN_Msk
Definition: NUC472_442.h:19922
CLK_CLKSEL2_PWM0CH23SEL_Msk
#define CLK_CLKSEL2_PWM0CH23SEL_Msk
Definition: NUC472_442.h:3821
CLK_CLKSEL2_PWM0CH45SEL_Pos
#define CLK_CLKSEL2_PWM0CH45SEL_Pos
Definition: NUC472_442.h:3823
PWM_INTSTS_DIF_Pos
#define PWM_INTSTS_DIF_Pos
Definition: NUC472_442.h:19981
CLK_CLKSEL2_PWM0CH23SEL_Pos
#define CLK_CLKSEL2_PWM0CH23SEL_Pos
Definition: NUC472_442.h:3820
PWM_DTCTL_DTEN01_Msk
#define PWM_DTCTL_DTEN01_Msk
Definition: NUC472_442.h:19877
CLK_CLKSEL2_PWM1CH23SEL_Pos
#define CLK_CLKSEL2_PWM1CH23SEL_Pos
Definition: NUC472_442.h:3829
PWM_INTSTS_BRKIF1_Msk
#define PWM_INTSTS_BRKIF1_Msk
Definition: NUC472_442.h:19979
PWM_INTEN_PIEN_Pos
#define PWM_INTEN_PIEN_Pos
Definition: NUC472_442.h:19957
CLK_CLKSEL2_PWM1CH01SEL_Pos
#define CLK_CLKSEL2_PWM1CH01SEL_Pos
Definition: NUC472_442.h:3826
CLK_CLKSEL2_PWM1CH01SEL_Msk
#define CLK_CLKSEL2_PWM1CH01SEL_Msk
Definition: NUC472_442.h:3827
PWM_INTEN_DIEN_Pos
#define PWM_INTEN_DIEN_Pos
Definition: NUC472_442.h:19963
CLK_CLKSEL2_PWM1CH23SEL_Msk
#define CLK_CLKSEL2_PWM1CH23SEL_Msk
Definition: NUC472_442.h:3830
PWM_BRKCTL_LVDBKEN_Msk
#define PWM_BRKCTL_LVDBKEN_Msk
Definition: NUC472_442.h:19946
CLK_CLKSEL2_PWM0CH01SEL_Msk
#define CLK_CLKSEL2_PWM0CH01SEL_Msk
Definition: NUC472_442.h:3818
CLK_CLKSEL2_PWM0CH45SEL_Msk
#define CLK_CLKSEL2_PWM0CH45SEL_Msk
Definition: NUC472_442.h:3824
PWM_INTEN_BRKIEN_Msk
#define PWM_INTEN_BRKIEN_Msk
Definition: NUC472_442.h:19961
PWM_CLKPSC_CLKPSC01_Msk
#define PWM_CLKPSC_CLKPSC01_Msk
Definition: NUC472_442.h:19751
CLK
#define CLK
Definition: NUC472_442.h:28798
PWM0
#define PWM0
Definition: NUC472_442.h:28841
PWM1
#define PWM1
Definition: NUC472_442.h:28842
g_PWM_i32ErrCode
int32_t g_PWM_i32ErrCode
Definition: pwm.c:21
PWM_PERIOD_INT_MATCH_CNR
#define PWM_PERIOD_INT_MATCH_CNR
Definition: pwm.h:65
PWM_TRIGGER_ADC_FALLING_EDGE_POINT
#define PWM_TRIGGER_ADC_FALLING_EDGE_POINT
Definition: pwm.h:53
PWM_BRK0_CPO1
#define PWM_BRK0_CPO1
Definition: pwm.h:58
PWM_DUTY_INT_MATCH_CMR_UP
#define PWM_DUTY_INT_MATCH_CMR_UP
Definition: pwm.h:67
PWM_TIMEOUT_ERR
#define PWM_TIMEOUT_ERR
Definition: pwm.h:78
PWM_TRIGGER_ADC_RISING_EDGE_POINT
#define PWM_TRIGGER_ADC_RISING_EDGE_POINT
Definition: pwm.h:52
PWM_RISING_FALLING_LATCH_INT_FLAG
#define PWM_RISING_FALLING_LATCH_INT_FLAG
Definition: pwm.h:73
PWM_BRK0_CPO2
#define PWM_BRK0_CPO2
Definition: pwm.h:59
PWM_TRIGGER_ADC_PERIOD_POINT
#define PWM_TRIGGER_ADC_PERIOD_POINT
Definition: pwm.h:55
PWM_CHANNEL_NUM
#define PWM_CHANNEL_NUM
Definition: pwm.h:32
PWM_BRK0_BKP0
#define PWM_BRK0_BKP0
Definition: pwm.h:56
PWM_BRK1_LVDBK
#define PWM_BRK1_LVDBK
Definition: pwm.h:60
PWM_BRK0_CPO0
#define PWM_BRK0_CPO0
Definition: pwm.h:57
PWM_TRIGGER_ADC_CENTER_POINT
#define PWM_TRIGGER_ADC_CENTER_POINT
Definition: pwm.h:54
PWM_ForceStop
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
This function stop PWM generation immediately by clear channel enable bit.
Definition: pwm.c:393
PWM_Stop
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
This function stop PWM module.
Definition: pwm.c:373
PWM_EnableCapture
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
This function enables PWM capture of selected channels.
Definition: pwm.c:526
PWM_EnableDeadZone
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
This function enable Dead zone of selected channel.
Definition: pwm.c:578
PWM_ClearCaptureIntFlag
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
This function clear capture interrupt flag of selected channel.
Definition: pwm.c:644
PWM_ClearADCTriggerFlag
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
This function clear selected channel trigger ADC flag.
Definition: pwm.c:442
PWM_DisableADCTrigger
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
This function disable selected channel to trigger ADC.
Definition: pwm.c:423
PWM_ConfigCaptureChannel
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
This function config PWM capture and get the nearest unit time.
Definition: pwm.c:207
PWM_DisablePeriodInt
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
This function disable period interrupt of selected channel.
Definition: pwm.c:792
PWM_EnableDutyInt
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
This function enable duty interrupt of selected channel.
Definition: pwm.c:674
PWM_GetFaultBrakeIntFlag
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
This function get fault brake interrupt of selected source.
Definition: pwm.c:763
PWM_DisableCaptureInt
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
This function disable capture interrupt of selected channel.
Definition: pwm.c:628
PWM_DisableFaultBrakeInt
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
This function disable fault brake interrupt.
Definition: pwm.c:735
PWM_ConfigOutputChannel
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode.
Definition: pwm.c:37
PWM_GetADCTriggerFlag
uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
This function get selected channel trigger ADC flag.
Definition: pwm.c:457
PWM_DisableCapture
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
This function disables PWM capture of selected channels.
Definition: pwm.c:540
PWM_DisableDutyInt
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
This function disable duty interrupt of selected channel.
Definition: pwm.c:688
PWM_ClearDutyIntFlag
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
This function clears duty interrupt flag of selected channel.
Definition: pwm.c:699
PWM_EnablePeriodInt
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
This function enable period interrupt of selected channel.
Definition: pwm.c:778
PWM_EnableFaultBrake
void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
This function enable fault brake of selected channels.
Definition: pwm.c:487
PWM_GetDutyIntFlag
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
This function get duty interrupt flag of selected channel.
Definition: pwm.c:713
PWM_DisableDeadZone
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
This function disable Dead zone of selected channel.
Definition: pwm.c:594
PWM_DisableOutput
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
This function disables PWM output generation of selected channels.
Definition: pwm.c:565
PWM_ClearFaultBrakeIntFlag
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
This function clear fault brake interrupt of selected source.
Definition: pwm.c:748
PWM_Start
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
This function start PWM module.
Definition: pwm.c:361
PWM_ClearPeriodIntFlag
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
This function clear period interrupt of selected channel.
Definition: pwm.c:803
PWM_EnableOutput
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
This function enables PWM output generation of selected channels.
Definition: pwm.c:553
PWM_EnableFaultBrakeInt
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
This function enable fault brake interrupt.
Definition: pwm.c:724
PWM_GetCaptureIntFlag
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
This function get capture interrupt flag of selected channel.
Definition: pwm.c:660
PWM_GetPeriodIntFlag
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
This function get period interrupt of selected channel.
Definition: pwm.c:817
PWM_ClearFaultBrakeFlag
void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource)
This function clear fault brake flag.
Definition: pwm.c:511
PWM_EnableCaptureInt
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
This function enable capture interrupt of selected channel.
Definition: pwm.c:612
PWM_EnableADCTrigger
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
This function enable selected channel to trigger ADC.
Definition: pwm.c:409
PWM_T::CMPDAT
__IO uint32_t CMPDAT[6]
Definition: NUC472_442.h:19208
PWM_T::CTL
__IO uint32_t CTL
Definition: NUC472_442.h:19141
PWM_T::PERIOD
__IO uint32_t PERIOD[6]
Definition: NUC472_442.h:19183
PWM_T::INTEN
__IO uint32_t INTEN
Definition: NUC472_442.h:19460
PWM_T::BRKCTL
__IO uint32_t BRKCTL
Definition: NUC472_442.h:19411
PWM_T::POEN
__IO uint32_t POEN
Definition: NUC472_442.h:19517
PWM_T::SBS
__I uint32_t SBS[6]
Definition: NUC472_442.h:19741
PWM_T::TRGADCSTS
__IO uint32_t TRGADCSTS
Definition: NUC472_442.h:19352
PWM_T::INTCTL
__IO uint32_t INTCTL
Definition: NUC472_442.h:19431
PWM_T::CNTEN
__IO uint32_t CNTEN
Definition: NUC472_442.h:19155
PWM_T::CAPINEN
__IO uint32_t CAPINEN
Definition: NUC472_442.h:19559
PWM_T::CLKDIV
__IO uint32_t CLKDIV
Definition: NUC472_442.h:19096
PWM_T::CLKPSC
__IO uint32_t CLKPSC
Definition: NUC472_442.h:19068
PWM_T::INTSTS
__IO uint32_t INTSTS
Definition: NUC472_442.h:19503
PWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: NUC472_442.h:19543
PWM_T::DTCTL
__IO uint32_t DTCTL
Definition: NUC472_442.h:19291
PWM_T::TRGADCTL
__IO uint32_t TRGADCTL
Definition: NUC472_442.h:19322
PWM_T
Definition: NUC472_442.h:19042
__HIRC
#define __HIRC
Definition: system_NUC472_442.h:27
__HXT
#define __HXT
Definition: system_NUC472_442.h:25
__LIRC
#define __LIRC
Definition: system_NUC472_442.h:28
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_NUC472_442.c:17
__LXT
#define __LXT
Definition: system_NUC472_442.h:26