| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

spi.c
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1 /****************************************************************************/
13 #include "Nano1X2Series.h"
14
47 uint32_t SPI_Open(SPI_T *spi,
48 uint32_t u32MasterSlave,
49 uint32_t u32SPIMode,
50 uint32_t u32DataWidth,
51 uint32_t u32BusClock)
52 {
53 if(u32DataWidth == 32)
54 u32DataWidth = 0;
55
56 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode);
57
58 return ( SPI_SetBusClock(spi, u32BusClock) );
59 }
60
66 void SPI_Close(SPI_T *spi)
67 {
68 /* Reset SPI */
69 if((uint32_t)spi == SPI0_BASE)
70 {
71 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI0_RST_Msk;
72 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk;
73 }
74 else
75 {
76 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI1_RST_Msk;
77 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk;
78 }
79 }
80
86 void SPI_ClearRxFIFO(SPI_T *spi)
87 {
88 spi->FFCTL |= SPI_FFCTL_RX_CLR_Msk;
89 }
90
96 void SPI_ClearTxFIFO(SPI_T *spi)
97 {
98 spi->FFCTL |= SPI_FFCTL_TX_CLR_Msk;
99 }
100
106 void SPI_DisableAutoSS(SPI_T *spi)
107 {
108 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
109 }
110
122 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
123 {
124 spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
125 }
126
133 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
134 {
135 uint32_t u32ClkSrc, u32Div = 0;
136
137 if(spi == SPI0)
138 {
139 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
140 u32ClkSrc = CLK_GetHCLKFreq();
141 else
142 u32ClkSrc = CLK_GetPLLClockFreq();
143 }
144 else
145 {
146 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
147 u32ClkSrc = CLK_GetHCLKFreq();
148 else
149 u32ClkSrc = CLK_GetPLLClockFreq();
150 }
151
152 if(u32BusClock > u32ClkSrc)
153 u32BusClock = u32ClkSrc;
154
155 if(u32BusClock != 0 )
156 {
157 u32Div = (u32ClkSrc / u32BusClock) - 1;
158 if(u32Div > SPI_CLKDIV_DIVIDER1_Msk)
159 u32Div = SPI_CLKDIV_DIVIDER1_Msk;
160 }
161 else
162 return 0;
163
164 spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div;
165
166 return ( u32ClkSrc / (u32Div+1) );
167 }
168
176 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
177 {
178 spi->FFCTL = (spi->FFCTL & ~(SPI_FFCTL_TX_THRESHOLD_Msk | SPI_FFCTL_RX_THRESHOLD_Msk) |
179 (u32TxThreshold << SPI_FFCTL_TX_THRESHOLD_Pos) |
180 (u32RxThreshold << SPI_FFCTL_RX_THRESHOLD_Pos));
181
182 spi->CTL |= SPI_CTL_FIFOM_Msk;
183 }
184
190 void SPI_DisableFIFO(SPI_T *spi)
191 {
192 spi->CTL &= ~SPI_CTL_FIFOM_Msk;
193 }
194
200 uint32_t SPI_GetBusClock(SPI_T *spi)
201 {
202 uint32_t u32Div;
203 uint32_t u32ClkSrc;
204
205 if(spi == SPI0)
206 {
207 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
208 u32ClkSrc = CLK_GetHCLKFreq();
209 else
210 u32ClkSrc = CLK_GetPLLClockFreq();
211 }
212 else
213 {
214 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
215 u32ClkSrc = CLK_GetHCLKFreq();
216 else
217 u32ClkSrc = CLK_GetPLLClockFreq();
218 }
219
220 u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER1_Msk;
221 return (u32ClkSrc / (u32Div + 1));
222 }
223
238 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
239 {
240 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
241 spi->CTL |= SPI_CTL_INTEN_Msk;
242
243 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
244 spi->SSR |= SPI_SSR_SSTA_INTEN_Msk;
245
246 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
247 spi->FFCTL |= SPI_FFCTL_TX_INTEN_Msk;
248
249 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
250 spi->FFCTL |= SPI_FFCTL_RX_INTEN_Msk;
251
252 if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
253 spi->FFCTL |= SPI_FFCTL_RXOVR_INTEN_Msk;
254
255 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
256 spi->FFCTL |= SPI_FFCTL_TIMEOUT_EN_Msk;
257 }
258
273 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
274 {
275 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
276 spi->CTL &= ~SPI_CTL_INTEN_Msk;
277
278 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
279 spi->SSR &= ~SPI_SSR_SSTA_INTEN_Msk;
280
281 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
282 spi->FFCTL &= ~SPI_FFCTL_TX_INTEN_Msk;
283
284 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
285 spi->FFCTL &= ~SPI_FFCTL_RX_INTEN_Msk;
286
287 if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
288 spi->FFCTL &= ~SPI_FFCTL_RXOVR_INTEN_Msk;
289
290 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
291 spi->FFCTL &= ~SPI_FFCTL_TIMEOUT_EN_Msk;
292 }
293
299 void SPI_EnableWakeup(SPI_T *spi)
300 {
301 spi->CTL |= SPI_CTL_WKEUP_EN_Msk;
302 }
303
309 void SPI_DisableWakeup(SPI_T *spi)
310 {
311 spi->CTL &= ~SPI_CTL_WKEUP_EN_Msk;
312 }
313 /* end of group NANO1X2_SPI_EXPORTED_FUNCTIONS */
315 /* end of group NANO1X2_SPI_Driver */
317 /* end of group NANO1X2_Device_Driver */
319
320 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
SPI_FIFO_RXOVR_INTEN_MASK
#define SPI_FIFO_RXOVR_INTEN_MASK
Definition: spi.h:54
SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_TIMEOUT_INTEN_MASK
Definition: spi.h:55
SPI_FFCTL_RX_CLR_Msk
#define SPI_FFCTL_RX_CLR_Msk
Definition: Nano1X2Series.h:8994
SPI_SSR_SS_LVL_Msk
#define SPI_SSR_SS_LVL_Msk
Definition: Nano1X2Series.h:8949
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:133
SPI_T::SSR
__IO uint32_t SSR
Definition: Nano1X2Series.h:8685
CLK
#define CLK
Pointer to CLK register structure.
Definition: Nano1X2Series.h:10651
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:86
CLK_CLKSEL2_SPI1_S_Msk
#define CLK_CLKSEL2_SPI1_S_Msk
Definition: Nano1X2Series.h:1613
SPI0_BASE
#define SPI0_BASE
SPI0 register base address.
Definition: Nano1X2Series.h:10588
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:228
SPI_IE_MASK
#define SPI_IE_MASK
Definition: spi.h:50
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:106
CLK_CLKSEL2_SPI0_S_HCLK
#define CLK_CLKSEL2_SPI0_S_HCLK
Definition: clk.h:171
SPI_FFCTL_RX_INTEN_Msk
#define SPI_FFCTL_RX_INTEN_Msk
Definition: Nano1X2Series.h:9000
SPI_T
Definition: Nano1X2Series.h:8460
CLK_CLKSEL2_SPI0_S_Msk
#define CLK_CLKSEL2_SPI0_S_Msk
Definition: Nano1X2Series.h:1610
SPI_CTL_TX_BIT_LEN_Pos
#define SPI_CTL_TX_BIT_LEN_Pos
Definition: Nano1X2Series.h:8861
SPI_FFCTL_TX_THRESHOLD_Msk
#define SPI_FFCTL_TX_THRESHOLD_Msk
Definition: Nano1X2Series.h:9015
SYS_IPRST_CTL2_SPI1_RST_Msk
#define SYS_IPRST_CTL2_SPI1_RST_Msk
Definition: Nano1X2Series.h:3675
SPI_CLKDIV_DIVIDER1_Msk
#define SPI_CLKDIV_DIVIDER1_Msk
Definition: Nano1X2Series.h:8940
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:200
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:66
SPI_SSR_SSTA_INTEN_Msk
#define SPI_SSR_SSTA_INTEN_Msk
Definition: Nano1X2Series.h:8964
SYS_IPRST_CTL2_SPI0_RST_Msk
#define SYS_IPRST_CTL2_SPI0_RST_Msk
Definition: Nano1X2Series.h:3672
SPI_SSR_AUTOSS_Msk
#define SPI_SSR_AUTOSS_Msk
Definition: Nano1X2Series.h:8952
SPI_FFCTL_TIMEOUT_EN_Msk
#define SPI_FFCTL_TIMEOUT_EN_Msk
Definition: Nano1X2Series.h:9009
Nano1X2Series.h
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:122
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:8551
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:238
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:96
SPI0
#define SPI0
Pointer to SPI0 register structure.
Definition: Nano1X2Series.h:10639
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:190
SPI_FFCTL_RXOVR_INTEN_Msk
#define SPI_FFCTL_RXOVR_INTEN_Msk
Definition: Nano1X2Series.h:9006
SPI_EnableWakeup
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
Definition: spi.c:299
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:192
SPI_FFCTL_TX_CLR_Msk
#define SPI_FFCTL_TX_CLR_Msk
Definition: Nano1X2Series.h:8997
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:176
SPI_SSR_SSR_Msk
#define SPI_SSR_SSR_Msk
Definition: Nano1X2Series.h:8946
SPI_FFCTL_RX_THRESHOLD_Pos
#define SPI_FFCTL_RX_THRESHOLD_Pos
Definition: Nano1X2Series.h:9011
SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
Definition: spi.h:52
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:273
SPI_FFCTL_TX_INTEN_Msk
#define SPI_FFCTL_TX_INTEN_Msk
Definition: Nano1X2Series.h:9003
SPI_SSTA_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
Definition: spi.h:51
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:47
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano1X2Series.h:8625
SPI_T::FFCTL
__IO uint32_t FFCTL
Definition: Nano1X2Series.h:8842
SPI_CTL_WKEUP_EN_Msk
#define SPI_CTL_WKEUP_EN_Msk
Definition: Nano1X2Series.h:8898
SPI_FFCTL_TX_THRESHOLD_Pos
#define SPI_FFCTL_TX_THRESHOLD_Pos
Definition: Nano1X2Series.h:9014
CLK_CLKSEL2_SPI1_S_HCLK
#define CLK_CLKSEL2_SPI1_S_HCLK
Definition: clk.h:168
SPI_CTL_INTEN_Msk
#define SPI_CTL_INTEN_Msk
Definition: Nano1X2Series.h:8874
SPI_FFCTL_RX_THRESHOLD_Msk
#define SPI_FFCTL_RX_THRESHOLD_Msk
Definition: Nano1X2Series.h:9012
SYS
#define SYS
Pointer to SYS register structure.
Definition: Nano1X2Series.h:10650
SPI_DisableWakeup
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
Definition: spi.c:309
SPI_FIFO_RX_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
Definition: spi.h:53
SPI_CTL_FIFOM_Msk
#define SPI_CTL_FIFOM_Msk
Definition: Nano1X2Series.h:8883