| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Data Fields
SPI_T Struct Reference

`#include <Nano1X2Series.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | STATUS
__IO uint32_t | CLKDIV
__IO uint32_t | SSR
__I uint32_t | RX0
__I uint32_t | RX1
uint32_t | RESERVE0 [2]
__O uint32_t | TX0
__O uint32_t | TX1
uint32_t | RESERVE1 [3]
__IO uint32_t | VARCLK
__IO uint32_t | DMA
__IO uint32_t | FFCTL
uint32_t | RESERVE2 [4]

## Detailed Description

    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
    Memory Mapped Structure for SPI Controller

Definition at line 8460 of file Nano1X2Series.h.

## Field Documentation

## ◆ CLKDIV

__IO uint32_t SPI_T::CLKDIV

# CLKDIV

## Offset: 0x08 SPI Clock Divider Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | DIVIDER1 | Clock Divider 1
|  | The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
|  | The desired frequency is obtained according to the following equation: fsclk = feclk / (DIVIDER1 + 1)
|  | Where feclk is the SPI peripheral clock source.
|  | It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18).
[23:16] | DIVIDER2 | Clock Divider 2
|  | The value is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
|  | The desired frequency is obtained according to the following equation: fsclk = feclk / (DIVIDER2 + 1)

Definition at line 8625 of file Nano1X2Series.h.

## ◆ CTL

__IO uint32_t SPI_T::CTL

# CTL

## Offset: 0x00 SPI Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | GO_BUSY | SPI Transfer Control Bit And Busy Status
|  | 0 = Writing this bit "0" will stop data transfer if SPI is transferring.
|  | 1 = In Master mode, writing "1" to this bit will start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master.
|  | If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1'.
|  | As the transfer is finished, this bit will be cleared automatically.
|  | Software can read this bit to check if the SPI is in busy status.
|  | In FIFO mode, this bit will be controlled by hardware.
|  | Software should not modify this bit.
|  | In slave mode, this bit always returns 1 when software reads this register.
|  | In master mode, this bit reflects the busy or idle status of SPI.
|  | Note1: When FIFO mode is disabled, all configurations should be set before writing "1" to the GO_BUSY bit in the SPI_CTL register.
|  | Note2: When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
[1] | RX_NEG | Receive At Negative Edge
|  | 0 = The received data is latched on the rising edge of SPI_SCLK.
|  | 1 = The received data is latched on the falling edge of SPI_SCLK.
[2] | TX_NEG | Transmit At Negative Edge
|  | 0 = The transmitted data output is changed on the rising edge of SPI_SCLK.
|  | 1 = The transmitted data output is changed on the falling edge of SPI_SCLK.
[7:3] | TX_BIT_LEN | Transmit Bit Length
|  | This field specifies how many bits can be transmitted / received in one transaction.
|  | The minimum bit length is 8 bits and can be up to 32 bits.
|  | 00000 = 32 bits are transmitted in one transaction.
|  | 01000 = 8 bits are transmitted in one transaction.
|  | 01001 = 9 bits are transmitted in one transaction.
|  | 01010 = 10 bits are transmitted in one transaction.
|  | --—
|  | 11111 = 31 bits are transmitted in one transaction.
[10] | LSB | Send LSB First
|  | 0 = The MSB, which bit of transmit/receive register depends on the setting of TX_BITLEN, is transmitted/received first.
|  | 1 = The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the SPI_RX register (SPI_RX0/1).
[11] | CLKP | Clock Polarity
|  | 0 = The default level of SCLK is low.
|  | 1 = The default level of SCLK is high.
[15:12] | SP_CYCLE | Suspend Interval (Master Only)
|  | These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
|  | The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = "0".
|  | If CLKP = "1", the interval is from the rising clock edge to the falling clock edge.
|  | The default value is 0x3. The desired suspend interval is obtained according to the following equation:
|  | (SP_CYCLE[3:0) + 0.5) * period of SPICLK
|  | Ex:
|  | SP_CYCLE = 0x0 .... 0.5 SPICLK clock cycle.
|  | SP_CYCLE = 0x1 .... 1.5 SPICLK clock cycle.
|  | ......
|  | SP_CYCLE = 0xE .... 14.5 SPICLK clock cycle.
|  | SP_CYCLE = 0xF .... 15.5 SPICLK clock cycle.
|  | If the Variable Clock function is enabled, the minimum period of suspend interval (the transmit data in FIFO buffer is not empty) between the successive transaction is (6.5 + SP_CYCLE) * SPICLK clock cycle
[17] | INTEN | Interrupt Enable Control
|  | 0 = SPI Interrupt Disabled.
|  | 1 = SPI Interrupt Enabled.
[18] | SLAVE | Slave Mode
|  | 0 = SPI controller set as Master mode.
|  | 1 = SPI controller set as Slave mode.
[19] | REORDER | Byte Reorder Function Enable Control
|  | 0 = Disable byte reorder function.
|  | 1 = Enable byte reorder function and insert a byte suspend interval among each byte.
|  | The setting of TX_BIT_LEN must be configured as 00b ( 32 bits/ word).
|  | The suspend interval is defined in SP_CYCLE.
|  | Note: Byte Suspend is only used in SPI Byte Reorder mode.
[21] | FIFOM | FIFO Mode Enable Control
|  | 0 = FIFO mode Disabled (in Normal mode).
|  | 1 = FIFO mode Enabled.
[22] | TWOB | 2-Bit Transfer Mode Active
|  | 0 = 2-bit transfer mode Disabled.
|  | 1 = 2-bit transfer mode Enabled.
[23] | VARCLK_EN | Variable Clock Enable Control
|  | 0 = The serial clock output frequency is fixed and only decided by the value of DIVIDER1.
|  | 1 = The serial clock output frequency is variable.
|  | The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1, and DIVIDER2.
[28] | DUAL_IO_DIR | Dual IO Mode Direction
|  | 0 = Date read in the Dual I/O Mode function.
|  | 1 = Data write in the Dual I/O Mode function.
[29] | DUAL_IO_EN | Dual IO Mode Enable Control
|  | 0 = Dual I/O Mode function Disabled.
|  | 1 = Dual I/O Mode function Enabled.
[31] | WKEUP_EN | Wake-Up Enable Control
|  | 0 = Wake-up function Disabled.
|  | 1 = Wake-up function Enabled.
|  | Note: When the system enters Power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port.
|  | After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.

Definition at line 8551 of file Nano1X2Series.h.

## ◆ DMA

__IO uint32_t SPI_T::DMA

# DMA

## Offset: 0x38 SPI DMA Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TX_DMA_EN | Transmit PDMA Enable Control
|  | 0 = Transmit PDMA function Disabled.
|  | 1 = Transmit PDMA function Enabled.
|  | Note1: Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.
|  | Note2: If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.
|  | Hardware will clear this bit to 0 automatically after PDMA transfer done.
[1] | RX_DMA_EN | Receiving PDMA Enable Control
|  | 0 = Receiver PDMA function Disabled.
|  | 1 = Receiver PDMA function Enabled.
|  | Note: Hardware will clear this bit to 0 automatically after PDMA transfer done.
|  | In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock
[2] | PDMA_RST | PDMA Reset
|  | It is used to reset the SPI PDMA function into default state.
|  | 0 = After reset PDMA function or in normal operation.
|  | 1 = Reset PDMA function.
|  | Note: it is auto cleared to "0" after the reset function has done.

Definition at line 8804 of file Nano1X2Series.h.

## ◆ FFCTL

__IO uint32_t SPI_T::FFCTL

# FFCTL

## Offset: 0x3C SPI FIFO Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | RX_CLR | Receiving FIFO Counter Clear
|  | 0 = No clear the received FIFO.
|  | 1 = Clear the received FIFO.
|  | Note: This bit is used to clear the receiver counter in FIFO Mode.
|  | This bit can be written "1" to clear the receiver counter and this bit will be cleared to "0" automatically after clearing receiving counter.
|  | After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to "1".
[1] | TX_CLR | Transmitting FIFO Counter Clear
|  | 0 = No clear the transmitted FIFO.
|  | 1 = Clear the transmitted FIFO.
|  | Note: This bit is used to clear the transmit counter in FIFO Mode.
|  | This bit can be written "1" to clear the transmitting counter and this bit will be cleared to "0" automatically after clearing transmitting counter.
|  | After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to "1".
[2] | RXINT_EN | RX Threshold Interrupt Enable Control
|  | 0 = Rx threshold interrupt Disabled.
|  | 1 = RX threshold interrupt Enable.
[3] | TXINT_EN | TX Threshold Interrupt Enable Control
|  | 0 = TX threshold interrupt Disabled.
|  | 1 = TX threshold interrupt Enable.
[4] | RXOVINT_EN | RX FIFO Over Run Interrupt Enable Control
|  | 0 = RX FIFO over run interrupt Disabled.
|  | 1 = RX FIFO over run interrupt Enable.
[7] | TIMEOUT_EN | RX Read Time Out Function Enable Control
|  | 0 = RX read Timeout function Disabled.
|  | 1 = RX read Timeout function Enable.
[26:24] | RX_THRESHOLD | Received FIFO Threshold
|  | If RX valid data counts large than RXTHRESHOLD, RXINT_STS (SPI_STATUS[8]) will set to 1,.
[30:28] | TX_THRESHOLD | Transmit FIFO Threshold
|  | If TX valid data counts small or equal than TXTHRESHOLD, TXINT_STS (SPI_STATUS[10]) will set to 1.

Definition at line 8842 of file Nano1X2Series.h.

## ◆ RESERVE0

uint32_t SPI_T::RESERVE0[2]

Definition at line 8722 of file Nano1X2Series.h.

## ◆ RESERVE1

uint32_t SPI_T::RESERVE1[3]

Definition at line 8764 of file Nano1X2Series.h.

## ◆ RESERVE2

uint32_t SPI_T::RESERVE2[4]

Definition at line 8843 of file Nano1X2Series.h.

## ◆ RX0

__I uint32_t SPI_T::RX0

# RX0

## Offset: 0x10 SPI Receive Data FIFO Register 0

Bits | Field | Descriptions
--- | --- | ---
[31:0] | RDATA | Receive Data FIFO Bits(Read Only)
|  | The received data can be read on it.
|  | If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not.
|  | Note1: The SPI_RX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
|  | The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode.
|  | SPI_RX0 shall be read first in TWOB mode.
|  | In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data.
|  | Note2: These registers are read only.

Definition at line 8703 of file Nano1X2Series.h.

## ◆ RX1

__I uint32_t SPI_T::RX1

# RX1

## Offset: 0x14 SPI Receive Data FIFO Register 1

Bits | Field | Descriptions
--- | --- | ---
[31:0] | RDATA | Receive Data FIFO Bits(Read Only)
|  | The received data can be read on it.
|  | If the FIFO bit is set as 1, the user also checks the RX_EMPTY, SPI_STATUS[0], to check if there is any more received data or not.
|  | Note1: The SPI_RX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
|  | The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode.
|  | SPI_RX0 shall be read first in TWOB mode.
|  | In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data.
|  | Note2: These registers are read only.

Definition at line 8721 of file Nano1X2Series.h.

## ◆ SSR

__IO uint32_t SPI_T::SSR

# SSR

## Offset: 0x0C SPI Slave Select Register

Bits | Field | Descriptions
--- | --- | ---
[1:0] | SSR | Slave Select Active Register (Master Only)
|  | If AUTOSS bit (SPI_SSR[3]) is cleared, writing "1" to SSR[0] bit sets the SPISS[0] line to an active state and writing "0" sets the line back to inactive state.(the same as SSR[1] for SPISS[1])
|  | AUTOSS = 0.
|  | 00 = Both SPISS[1] and SPISS[0] are inactive.
|  | 01 = SPISS[1] is inactive, SPISS[0] is active.
|  | 10 = SPISS[1] is active, SPISS[0] is inactive.
|  | 11 = Both SPISS[1] and SPISS[0] are active.
|  | If AUTOSS bit is set, writing "1" to any bit location of this field will select appropriate SPISS[1:0] line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time.
|  | (The active level of SPISS[1:0] is specified in SS_LVL).
|  | AUTOSS =1.
|  | 00 = Both SPISS[1] and SPISS[0] are inactive.
|  | 01 = SPISS[1] is inactive, SPISS[0] is active on the duration of transaction.
|  | 10 = SPISS[1] is active on the duration of transaction, SPISS[0] is inactive.
|  | 11 = Both SPISS[1] and SPISS[0] are active on the duration of transaction.
|  | Note1: This interface can only drive one device/slave at a given time.
|  | Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
|  | Note2: SPISS[0] is also defined as device/slave select input in Slave mode.
|  | And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software.
[2] | SS_LVL | Slave Select Active Level
|  | It defines the active level of device/slave select signal (SPISS[1:0]).
|  | 0 = The SPI_SS slave select signal is active Low.
|  | 1 = The SPI_SS slave select signal is active High.
[3] | AUTOSS | Automatic Slave Selection (Master Only)
|  | 0 = If this bit is set as "0", slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register.
|  | 1 = If this bit is set as "1", SPISS[1:0] signals are generated automatically.
|  | It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done.
[4] | SS_LTRIG | Slave Select Level Trigger
|  | 0 = The input slave select signal is edge-trigger.
|  | 1 = The slave select signal will be level-trigger.
|  | It depends on SS_LVL to decide the signal is active low or active high.
[5] | NOSLVSEL | No Slave Selected In Slave Mode
|  | This is used to ignore the slave select signal in Slave mode.
|  | The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.
|  | 0 = The controller is 4-wire bi-direction interface.
|  | 1 = The controller is 3-wire bi-direction interface in Slave mode.
|  | When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input.
|  | Note: In no slave select signal mode, the SS_LTRIG (SPI_SSR[4]) shall be set as "1".
[8] | SLV_ABORT | Abort In Slave Mode With No Slave Selected
|  | 0 = No force the slave abort.
|  | 1 = Force the current transfer done in no slave select mode.
|  | Note: It is auto cleared to "0" by hardware when the abort event is active.
[9] | SSTA_INTEN | Slave Start Interrupt Enable Control
|  | 0 = Transfer start interrupt Disabled in no slave select mode.
|  | 1 = Transaction start interrupt Enabled in no slave select mode.
|  | It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write 1 clear).
[16] | SS_INT_OPT | Slave Select Interrupt Option
|  | It is used to enable the interrupt when the transfer has done in slave mode.
|  | 0 = No any interrupt, even there is slave select inactive event.
|  | 1 = There is interrupt event when the slave select becomes inactive from active condition.
|  | It is used to inform the user to know that the transaction has finished and the slave select into the inactive state.

Definition at line 8685 of file Nano1X2Series.h.

## ◆ STATUS

__IO uint32_t SPI_T::STATUS

# STATUS

## Offset: 0x04 SPI Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | RX_EMPTY | Received FIFO_EMPTY Status
|  | 0 = Received data FIFO is not empty in the FIFO mode.
|  | 1 = Received data FIFO is empty in the FIFO mode.
[1] | RX_FULL | Received FIFO_FULL Status
|  | 0 = Received data FIFO is not full in FIFO mode.
|  | 1 = Received data FIFO is full in the FIFO mode.
[2] | TX_EMPTY | Transmitted FIFO_EMPTY Status
|  | 0 = Transmitted data FIFO is not empty in the FIFO mode.
|  | 1 =Transmitted data FIFO is empty in the FIFO mode.
[3] | TX_FULL | Transmitted FIFO_FULL Status
|  | 0 = Transmitted data FIFO is not full in the FIFO mode.
|  | 1 = Transmitted data FIFO is full in the FIFO mode.
[4] | LTRIG_FLAG | Level Trigger Accomplish Flag (INTERNAL ONLY)
|  | In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.
|  | 0 = The transferred bit length of one transaction does not meet the specified requirement.
|  | 1 = The transferred bit length meets the specified requirement which defined in TX_BIT_LEN.
|  | Note: This bit is READ only.
|  | As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period.
|  | In FIFO mode, this bit is unmeaning.
[6] | SLV_START_INTSTS | Slave Start Interrupt Status
|  | It is used to dedicate that the transfer has started in Slave mode with no slave select.
|  | 0 = Slave started transfer no active.
|  | 1 = Transfer has started in Slave mode with no slave select.
|  | It is auto clear by transfer done or writing one clear.
[7] | INTSTS | Interrupt Status
|  | 0 = Transfer is not finished yet.
|  | 1 = Transfer is done. The interrupt is requested when the INTEN(SPI_CTL[17]) bit is enabled.
|  | Note: This bit is read only, but can be cleared by writing "1" to this bit.
[8] | RXINT_STS | RX FIFO Threshold Interrupt Status (Read Only)
|  | 0 = RX valid data counts small or equal than RXTHRESHOLD (SPI_FFCTL[27:24]).
|  | 1 = RX valid data counts bigger than RXTHRESHOLD.
|  | Note: If RXINT_EN(SPI_FFCTL[2]) = 1 and RX_INTSTS = 1, SPI will generate interrupt.
[9] | RX_OVER_RUN | RX FIFO Over Run Status
|  | 0 = No FIFO is over run.
|  | 1 = Receive FIFO over run.
|  | Note1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will dropped.
|  | Note2: This bit will be cleared by writing 1 to it.
[10] | TXINT_STS | TX FIFO Threshold Interrupt Status (Read Only)
|  | 0 = TX valid data counts bigger than TXTHRESHOLD (SPI_FFCTL[31:28].
|  | 1 = TX valid data counts small or equal than TXTHRESHOLD.
[12] | TIME_OUT_STS | TIMEOUT Interrupt Flag
|  | 0 = There is not timeout event on the received buffer.
|  | 1 = Time out event active in RX FIFO is not empty.
|  | Note: This bit will be cleared by writing 1 to it.
[19:16] | RX_FIFO_CNT | Data counts in RX FIFO (Read Only)
[23:20] | TX_FIFO_CNT | Data counts in TX FIFO (Read Only)

Definition at line 8607 of file Nano1X2Series.h.

## ◆ TX0

__O uint32_t SPI_T::TX0

# TX0

## Offset: 0x20 SPI Transmit Data FIFO Register 0

Bits | Field | Descriptions
--- | --- | ---
[31:0] | TDATA | Transmit Data FIFO Bits(Write Only)
|  | The Data Transmit Registers hold the data to be transmitted in the next transfer.
|  | The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
|  | For example, if TX_BIT_LEN is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer.
|  | If TX_BIT_LEN is set to 0x0, the SPI controller will perform a 32-bit transfer.
|  | Note1: The SPI_TX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
|  | The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode.
|  | SPI_TX0 shall be written first in TWOB mode.
|  | In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_RX0 is the second channel's transmitted data.
|  | Note2: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.

Definition at line 8743 of file Nano1X2Series.h.

## ◆ TX1

__O uint32_t SPI_T::TX1

# TX1

## Offset: 0x24 SPI Transmit Data FIFO Register 1

Bits | Field | Descriptions
--- | --- | ---
[31:0] | TDATA | Transmit Data FIFO Bits(Write Only)
|  | The Data Transmit Registers hold the data to be transmitted in the next transfer.
|  | The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
|  | For example, if TX_BIT_LEN is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer.
|  | If TX_BIT_LEN is set to 0x0, the SPI controller will perform a 32-bit transfer.
|  | Note1: The SPI_TX1 is used only in TWOB bit (SPI_CTL[22]) is set 1.
|  | The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode.
|  | SPI_TX0 shall be written first in TWOB mode.
|  | In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_RX0 is the second channel's transmitted data.
|  | Note2: When the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.

Definition at line 8763 of file Nano1X2Series.h.

## ◆ VARCLK

__IO uint32_t SPI_T::VARCLK

# VARCLK

## Offset: 0x34 SPI Variable Clock Pattern Flag Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | VARCLK | Variable Clock Pattern Flag
|  | The value in this field is the frequency patterns of the SPICLK.
|  | Note: It is used for CLKP = 0 only.

Definition at line 8778 of file Nano1X2Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Nano1X2Series/Include/Nano1X2Series.h