| NANO102/112 BSP V3.04.000 The Board Support Package for Nano102/112 Series

timer.c
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1/**************************************************************************/
12#include "Nano1X2Series.h"
13
42uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
43{
44 uint32_t u32Clk = TIMER_GetModuleClock(timer);
45 uint32_t u32Cmpr = 0, u32Prescale = 0;
46
47 // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
48 if(u32Freq > (u32Clk / 2))
49 {
50 u32Cmpr = 2;
51 }
52 else
53 {
54 if(u32Clk > 0xFFFFFF) // For Nano1x2, only needs to consider 32MHz at most
55 {
56 u32Prescale = 1;
57 u32Clk >>= 1;
58 }
59 u32Cmpr = u32Clk / u32Freq;
60 }
61 timer->CMPR = u32Cmpr;
62 timer->PRECNT = u32Prescale;
63 timer->CTL = u32Mode;
64
65
66 return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
67}
68
74 void TIMER_Close(TIMER_T *timer)
75{
76 timer->CTL = 0;
77 timer->IER = 0;
78}
79
88 void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
89{
90 uint32_t u32Clk = TIMER_GetModuleClock(timer);
91 uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
92 long long u64Cmpr;
93
94 // Clear current timer configuration
95 timer->CTL = 0;
96
97 if(u32Clk == 10000) // min delay is 100us if timer clock source is LIRC 10k
98 {
99 u32Usec = ((u32Usec + 99) / 100) * 100;
100 }
101 else // 10 usec every step
102 {
103 u32Usec = ((u32Usec + 9) / 10) * 10;
104 }
105
106 if(u32Clk > 0xFFFFFF) // For Nano1x2, only needs to consider 32MHz at most
107 {
108 u32Prescale = 1;
109 u32Clk >>= 1;
110 }
111
112 // u32Usec * u32Clk might overflow if using uint32_t
113 u64Cmpr = (long long)u32Usec * (long long)u32Clk / (long long)1000000;
114
115 timer->CMPR = (uint32_t)u64Cmpr;
116 timer->PRECNT = u32Prescale;
117 timer->CTL = TIMER_CTL_TMR_EN_Msk; // one shot mode
118
119 // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
120 // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
121 for(; delay > 0; delay--)
122 {
123 __NOP();
124 }
125
126 delay = (SystemCoreClock / 1000000) * u32Usec * 10;
127
128 while ((timer->CTL & TIMER_CTL_TMR_ACT_Msk) && (delay-- > 0));
129}
130
146 void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
147{
148
149 timer->CTL = (timer->CTL & ~(TIMER_CTL_TCAP_MODE_Msk |
150 TIMER_CTL_TCAP_CNT_MODE_Msk |
151 TIMER_CTL_TCAP_EDGE_Msk)) |
152 u32CapMode | u32Edge | TIMER_CTL_TCAP_EN_Msk;
153}
154
160 void TIMER_DisableCapture(TIMER_T *timer)
161{
162 timer->CTL &= ~TIMER_CTL_TCAP_EN_Msk;
163
164}
165
175 void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
176{
177 timer->CTL = (timer->CTL & ~TIMER_CTL_EVENT_EDGE_Msk) | u32Edge;
178 timer->CTL |= TIMER_CTL_EVENT_EN_Msk;
179}
180
186 void TIMER_DisableEventCounter(TIMER_T *timer)
187{
188 timer->CTL &= ~TIMER_CTL_EVENT_EN_Msk;
189}
190
197uint32_t TIMER_GetModuleClock(TIMER_T *timer)
198{
199 uint32_t u32Src, u32Div;
200 const uint32_t au32Clk[] = {__HXT, __LXT, __LIRC, 0}; // we don't know actual clock if external pin is clock source, set to 0 here
201
202 if(timer == TIMER0)
203 {
204 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0_S_Msk) >> CLK_CLKSEL1_TMR0_S_Pos;
205 u32Div = (CLK->CLKDIV1 & CLK_CLKDIV1_TMR0_N_Msk) >> CLK_CLKDIV1_TMR0_N_Pos;
206 }
207 else if(timer == TIMER1)
208 {
209 u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1_S_Msk) >> CLK_CLKSEL1_TMR1_S_Pos;
210 u32Div = (CLK->CLKDIV1 & CLK_CLKDIV1_TMR1_N_Msk) >> CLK_CLKDIV1_TMR1_N_Pos;
211 }
212 else if(timer == TIMER2)
213 {
214 u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR2_S_Msk) >> CLK_CLKSEL2_TMR2_S_Pos;
215 u32Div = (CLK->CLKDIV1 & CLK_CLKDIV1_TMR2_N_Msk) >> CLK_CLKDIV1_TMR2_N_Pos;
216 }
217 else // Timer 3
218 {
219 u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR3_S_Msk) >> CLK_CLKSEL2_TMR3_S_Pos;
220 u32Div = (CLK->CLKDIV1 & CLK_CLKDIV1_TMR3_N_Msk) >> CLK_CLKDIV1_TMR3_N_Pos;
221 }
222 u32Div++;
223 if(u32Src < 4)
224 return au32Clk[u32Src] / u32Div;
225 else if(u32Src == 4)
226 {
227 if((CLK->PWRCTL & CLK_PWRCTL_HIRC_FSEL_Msk) == CLK_PWRCTL_HIRC_FSEL_Msk)
228 return __HIRC16M / u32Div;
229 else
230 return __HIRC12M / u32Div;
231 }
232 else
233 return CLK_GetHCLKFreq() / u32Div;
234}
235
241 void TIMER_ResetCounter(TIMER_T *timer)
242{
243 // A write with any value to TIMER DR register will trigger timer counter reset
244 timer->DR = 0;
245}
246
264 void TIMER_EnableFreqCounter(TIMER_T *timer,
265 uint32_t u32DropCount,
266 uint32_t u32Timeout,
267 uint32_t u32EnableInt)
268{
269 uint32_t mode = TIMER_CTL_INTR_TRG_EN_Msk;
270 TIMER_T *t; // store the timer base to configure compare value
271
272 if(u32DropCount != 0 || u32Timeout >= 2)
273 mode |= TIMER_CTL_INTR_TRG_MODE_Msk;
274 if(u32Timeout < 2)
275 u32Timeout = 0xFFFFFF;
276
277 timer->ECTL = u32DropCount << TIMER_ECTL_EVNT_DROP_CNT_Pos;
278 t = (timer == TIMER0) ? TIMER1 : TIMER3;
279
280 t->CMPR = u32Timeout;
281 t->IER = u32EnableInt ? TIMER_IER_TCAP_IE_Msk : 0;
282 timer->CTL = mode | TIMER_CTL_TMR_EN_Msk;
283
284 return;
285}
291 void TIMER_DisableFreqCounter(TIMER_T *timer)
292{
293 timer->CTL &= ~(TIMER_CTL_INTR_TRG_EN_Msk | TIMER_CTL_INTR_TRG_MODE_Msk);
294}
295
304 void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
305{
306 timer->CTL = (timer->CTL & ~TIMER_CTL_CAP_TRG_EN_Msk) | u32Src;
307}
308
317 void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
318{
319 timer->CTL = (timer->CTL & ~(TIMER_CTL_PDMA_TEEN_Msk | TIMER_CTL_ADC_TEEN_Msk)) | u32Mask;
320}
321 /* end of group NANO1X2_TIMER_EXPORTED_FUNCTIONS */
323 /* end of group NANO1X2_TIMER_Driver */
325 /* end of group NANO1X2_Device_Driver */
327
328/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
Nano1X2Series.h
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
TIMER_CTL_TCAP_MODE_Msk
#define TIMER_CTL_TCAP_MODE_Msk
Definition: Nano1X2Series.h:9398
TIMER_CTL_TCAP_CNT_MODE_Msk
#define TIMER_CTL_TCAP_CNT_MODE_Msk
Definition: Nano1X2Series.h:9404
TIMER_CTL_INTR_TRG_EN_Msk
#define TIMER_CTL_INTR_TRG_EN_Msk
Definition: Nano1X2Series.h:9410
TIMER_CTL_EVENT_EN_Msk
#define TIMER_CTL_EVENT_EN_Msk
Definition: Nano1X2Series.h:9386
TIMER_CTL_TMR_EN_Msk
#define TIMER_CTL_TMR_EN_Msk
Definition: Nano1X2Series.h:9353
TIMER_ECTL_EVNT_DROP_CNT_Pos
#define TIMER_ECTL_EVNT_DROP_CNT_Pos
Definition: Nano1X2Series.h:9466
TIMER_IER_TCAP_IE_Msk
#define TIMER_IER_TCAP_IE_Msk
Definition: Nano1X2Series.h:9425
TIMER_CTL_PDMA_TEEN_Msk
#define TIMER_CTL_PDMA_TEEN_Msk
Definition: Nano1X2Series.h:9380
TIMER_CTL_INTR_TRG_MODE_Msk
#define TIMER_CTL_INTR_TRG_MODE_Msk
Definition: Nano1X2Series.h:9413
TIMER_CTL_TMR_ACT_Msk
#define TIMER_CTL_TMR_ACT_Msk
Definition: Nano1X2Series.h:9371
TIMER_CTL_ADC_TEEN_Msk
#define TIMER_CTL_ADC_TEEN_Msk
Definition: Nano1X2Series.h:9374
TIMER_CTL_TCAP_EN_Msk
#define TIMER_CTL_TCAP_EN_Msk
Definition: Nano1X2Series.h:9395
TIMER_CTL_TCAP_EDGE_Msk
#define TIMER_CTL_TCAP_EDGE_Msk
Definition: Nano1X2Series.h:9401
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:192
CLK_CLKDIV1_TMR1_N_Msk
#define CLK_CLKDIV1_TMR1_N_Msk
Definition: Nano1X2Series.h:1634
CLK_CLKDIV1_TMR0_N_Pos
#define CLK_CLKDIV1_TMR0_N_Pos
Definition: Nano1X2Series.h:1630
CLK_CLKSEL2_TMR2_S_Pos
#define CLK_CLKSEL2_TMR2_S_Pos
Definition: Nano1X2Series.h:1600
CLK_CLKSEL2_TMR3_S_Pos
#define CLK_CLKSEL2_TMR3_S_Pos
Definition: Nano1X2Series.h:1603
CLK_CLKSEL2_TMR2_S_Msk
#define CLK_CLKSEL2_TMR2_S_Msk
Definition: Nano1X2Series.h:1601
CLK_CLKDIV1_TMR3_N_Pos
#define CLK_CLKDIV1_TMR3_N_Pos
Definition: Nano1X2Series.h:1639
CLK_CLKSEL2_TMR3_S_Msk
#define CLK_CLKSEL2_TMR3_S_Msk
Definition: Nano1X2Series.h:1604
CLK_CLKDIV1_TMR2_N_Pos
#define CLK_CLKDIV1_TMR2_N_Pos
Definition: Nano1X2Series.h:1636
CLK_CLKSEL1_TMR1_S_Msk
#define CLK_CLKSEL1_TMR1_S_Msk
Definition: Nano1X2Series.h:1586
CLK_CLKDIV1_TMR1_N_Pos
#define CLK_CLKDIV1_TMR1_N_Pos
Definition: Nano1X2Series.h:1633
CLK_CLKDIV1_TMR2_N_Msk
#define CLK_CLKDIV1_TMR2_N_Msk
Definition: Nano1X2Series.h:1637
CLK_CLKSEL1_TMR0_S_Pos
#define CLK_CLKSEL1_TMR0_S_Pos
Definition: Nano1X2Series.h:1582
CLK_CLKDIV1_TMR0_N_Msk
#define CLK_CLKDIV1_TMR0_N_Msk
Definition: Nano1X2Series.h:1631
CLK_PWRCTL_HIRC_FSEL_Msk
#define CLK_PWRCTL_HIRC_FSEL_Msk
Definition: Nano1X2Series.h:1469
CLK_CLKSEL1_TMR0_S_Msk
#define CLK_CLKSEL1_TMR0_S_Msk
Definition: Nano1X2Series.h:1583
CLK_CLKDIV1_TMR3_N_Msk
#define CLK_CLKDIV1_TMR3_N_Msk
Definition: Nano1X2Series.h:1640
CLK_CLKSEL1_TMR1_S_Pos
#define CLK_CLKSEL1_TMR1_S_Pos
Definition: Nano1X2Series.h:1585
CLK
#define CLK
Pointer to CLK register structure.
Definition: Nano1X2Series.h:10651
TIMER1
#define TIMER1
Pointer to TIMER1 register structure.
Definition: Nano1X2Series.h:10634
TIMER3
#define TIMER3
Pointer to TIMER3 register structure.
Definition: Nano1X2Series.h:10636
TIMER2
#define TIMER2
Pointer to TIMER2 register structure.
Definition: Nano1X2Series.h:10635
TIMER0
#define TIMER0
Pointer to TIMER0 register structure.
Definition: Nano1X2Series.h:10633
TIMER_SetTriggerSource
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
This function is used to select the interrupt source used to trigger other modules.
Definition: timer.c:304
TIMER_Delay
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
This API is used to create a delay loop for u32usec micro seconds.
Definition: timer.c:88
TIMER_DisableCapture
void TIMER_DisableCapture(TIMER_T *timer)
This API is used to disable the Timer capture function.
Definition: timer.c:160
TIMER_Open
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
This API is used to configure timer to operate in specified mode and frequency. If timer cannot work ...
Definition: timer.c:42
TIMER_DisableEventCounter
void TIMER_DisableEventCounter(TIMER_T *timer)
This API is used to disable the Timer event counter function.
Definition: timer.c:186
TIMER_ResetCounter
void TIMER_ResetCounter(TIMER_T *timer)
This function is used to reset the Timer counter value.
Definition: timer.c:241
TIMER_GetModuleClock
uint32_t TIMER_GetModuleClock(TIMER_T *timer)
This API is used to get the clock frequency of Timer.
Definition: timer.c:197
TIMER_DisableFreqCounter
void TIMER_DisableFreqCounter(TIMER_T *timer)
This function is used to disable the Timer frequency counter function.
Definition: timer.c:291
TIMER_EnableEventCounter
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
This function is used to enable the Timer counter function with specify detection edge.
Definition: timer.c:175
TIMER_EnableCapture
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
This API is used to enable timer capture function with specified mode and capture edge.
Definition: timer.c:146
TIMER_Close
void TIMER_Close(TIMER_T *timer)
This API stops Timer counting and disable the Timer interrupt function.
Definition: timer.c:74
TIMER_SetTriggerTarget
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
This function is used to set modules trigger by timer interrupt.
Definition: timer.c:317
TIMER_EnableFreqCounter
void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt)
This function is used to enable the Timer frequency counter function.
Definition: timer.c:264
TIMER_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:9226
TIMER_T::PRECNT
__IO uint32_t PRECNT
Definition: Nano1X2Series.h:9191
TIMER_T::DR
__IO uint32_t DR
Definition: Nano1X2Series.h:9287
TIMER_T::CMPR
__IO uint32_t CMPR
Definition: Nano1X2Series.h:9208
TIMER_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:9178
TIMER_T::ECTL
__IO uint32_t ECTL
Definition: Nano1X2Series.h:9343
TIMER_T
Definition: Nano1X2Series.h:9028
__HXT
#define __HXT
Definition: system_Nano1X2Series.h:26
__LIRC
#define __LIRC
Definition: system_Nano1X2Series.h:30
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_Nano1X2Series.c:20
__HIRC16M
#define __HIRC16M
Definition: system_Nano1X2Series.h:29
__LXT
#define __LXT
Definition: system_Nano1X2Series.h:27
__HIRC12M
#define __HIRC12M
Definition: system_Nano1X2Series.h:28