| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Data Fields
FMC_T Struct Reference

`#include <Nano1X2Series.h>`

## Data Fields
__IO uint32_t | ISPCON
__IO uint32_t | ISPADR
__IO uint32_t | ISPDAT
__IO uint32_t | ISPCMD
__IO uint32_t | ISPTRG
__I uint32_t | DFBADR
uint32_t | RESERVE0 [10]
__I uint32_t | ISPSTA

## Detailed Description

    @addtogroup FMC Flash Memory Controller(FMC)
    Memory Mapped Structure for FMC Controller

Definition at line 2468 of file Nano1X2Series.h.

## Field Documentation

## ◆ DFBADR

__I uint32_t FMC_T::DFBADR

# DFBADR

## Offset: 0x14 Data Flash Base Address Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | DFBADR | Data Flash Base Address
|  | This register indicates data flash start address. It is a read only register.
|  | The data flash start address is defined by user.
|  | Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.

Definition at line 2581 of file Nano1X2Series.h.

## ◆ ISPADR

__IO uint32_t FMC_T::ISPADR

# ISPADR

## Offset: 0x04 ISP Address Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | ISPADR | ISP Address
|  | This chip supports word program only.
|  | ISPADR[1:0] must be kept 00b for ISP operation, and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.

Definition at line 2519 of file Nano1X2Series.h.

## ◆ ISPCMD

__IO uint32_t FMC_T::ISPCMD

# ISPCMD

## Offset: 0x0C ISP Command Register

Bits | Field | Descriptions
--- | --- | ---
[3:0] | FCTRL | ISP Command
|  | The ISP command table is shown as follows
|  | Read (FOEN = 0, FCEN = 0, FCRTL = 0000)
|  | Program (FOEN = 1, FCEN = 0, FCRTL = 0001)
|  | Page Erase (FOEN = 1, FCEN = 0, FCRTL = 0010)
|  | Read CID (FOEN = 0, FCEN = 0, FCRTL = 1011)
|  | Read DID (FOEN = 0, FCEN = 0, FCRTL = 1100)
[4] | FCEN | ISP Command
|  | The ISP command table is shown as above.
[5] | FOEN | ISP Command
|  | The ISP command table is shown as above.

Definition at line 2553 of file Nano1X2Series.h.

## ◆ ISPCON

__IO uint32_t FMC_T::ISPCON

# ISPCON

## Offset: 0x00 ISP Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | ISPEN | ISP Enable Control (Write Protect)
|  | ISP function enable bit. Set this bit to enable ISP function.
|  | 0 = ISP function Disabled.
|  | 1 = ISP function Enabled.
[1] | BS | Boot Select (Write Protect)
|  | Set/clear this bit to select next booting from LDROM/APROM, respectively.
|  | This bit also functions as chip booting status flag, which can be used to check where chip booted from.
|  | This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset.
|  | 0 = Boot from APROM.
|  | 1 = Boot from LDROM.
[3] | APUEN | APROM Update Enable Control (Write Protect)
|  | 0 = APROM cannot be updated.
|  | 1 = APROM can be updated.
[4] | CFGUEN | Enable Config-Bits Update By ISP (Write Protect)
|  | 0 = ISP update User Configuration Disabled.
|  | 1 = ISP update User Configuration Enabled.
[5] | LDUEN | LDROM Update Enable Control (Write Protect)
|  | 0 = LDROM cannot be updated.
|  | 1 = LDROM can be updated.
[6] | ISPFF | ISP Fail Flag (Write Protect)
|  | This bit is set by hardware when a triggered ISP meets any of the following conditions:
|  | (1) APROM writes to itself if APUEN is set to 0 or CBS[0]=1.
|  | (2) LDROM writes to itself if LDUEN is set to 0 or CBS[0]=1.
|  | (3) User Configuration is erased/programmed when CFGUEN is 0.
|  | (4) Destination address is illegal, such as over an available range.
|  | Note: Write 1 to clear this bit to 0.

Definition at line 2506 of file Nano1X2Series.h.

## ◆ ISPDAT

__IO uint32_t FMC_T::ISPDAT

# ISPDAT

## Offset: 0x08 ISP Data Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | ISPDAT | ISP Data
|  | Write data to this register before ISP program operation
|  | Read data from this register after ISP read operation

Definition at line 2532 of file Nano1X2Series.h.

## ◆ ISPSTA

__I uint32_t FMC_T::ISPSTA

# ISPSTA

## Offset: 0x40 ISP Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | ISPBUSY | ISP Busy (Read Only)
|  | 0 = ISP operation is finished.
|  | 1 = ISP operation is busy.
[2:1] | CBS | Config Boot Selection Status (Read Only)
|  | This filed is a mirror of CBS in CONFIG0.
[5] | PGFF | Auto Flash Program Verified Fail Flag
|  | This chip will perform flash verification automatically at the end of ISP PROGRAM operation, and set 1 to this bit when flash data is not matched with programming.
|  | This bit is clear to 0 by "ERASE" command.
[6] | ISPFF | ISP Fail Flag
|  | (1) APROM writes to itself if APUEN is set to 0 or CBS[0]=1.
|  | (2) LDROM writes to itself if LDUEN is set to 0 or CBS[0]=1.
|  | (3) User Configuration is erased/programmed when CFGUEN is 0.
|  | (4) Destination address is illegal, such as over an available range.
|  | Note: Write 1 to clear this bit to 0.

Definition at line 2607 of file Nano1X2Series.h.

## ◆ ISPTRG

__IO uint32_t FMC_T::ISPTRG

# ISPTRG

## Offset: 0x10 ISP Trigger Register

Bits | Field | Descriptions
--- | --- | ---
[0] | ISPGO | ISP Start Trigger
|  | Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
|  | 0 = ISP operation is finished.
|  | 1 = ISP is progressing.

Definition at line 2567 of file Nano1X2Series.h.

## ◆ RESERVE0

uint32_t FMC_T::RESERVE0[10]

Definition at line 2582 of file Nano1X2Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Nano1X2Series/Include/Nano1X2Series.h