| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Data Fields
WWDT_T Struct Reference

`#include <Nano1X2Series.h>`

## Data Fields
__O uint32_t | RLD
__IO uint32_t | CR
__IO uint32_t | IER
__IO uint32_t | STS
__I uint32_t | VAL

## Detailed Description

    @addtogroup WWDT Window Watchdog Timer(WWDT)
    Memory Mapped Structure for WWDT Controller

Definition at line 10441 of file Nano1X2Series.h.

## Field Documentation

## ◆ CR

__IO uint32_t WWDT_T::CR

# CR

## Offset: 0x04 Window Watchdog Timer Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | WWDTEN | Window Watchdog Enable
|  | Set this bit to enable Window Watchdog timer.
|  | 0 = Window Watchdog timer function Disabled.
|  | 1 = Window Watchdog timer function Enabled.
[11:8] | PERIODSEL | WWDT Pre-Scale Period Select
|  | These three bits select the pre-scale for the WWDT counter period.
[21:16] | WINCMP | WWDT Window Compare Register
|  | Set this register to adjust the valid reload window.
|  | Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP.
|  | If SW writes WWDTRLD when WWDT counter value larger than WWCMP, WWDT will generate RESET signal.
[31] | DBGEN | WWDT Debug Enable
|  | 0 = WWDT stopped count if system is in Debug mode.
|  | 1 = WWDT still counted even system is in Debug mode.

Definition at line 10480 of file Nano1X2Series.h.

## ◆ IER

__IO uint32_t WWDT_T::IER

# IER

## Offset: 0x08 Window Watchdog Timer Interrupt Enable Register

Bits | Field | Descriptions
--- | --- | ---
[0] | WWDTIE | WWDT Interrupt Enable
|  | Setting this bit will enable the Watchdog timer interrupt function.
|  | 0 = Watchdog timer interrupt function Disabled.
|  | 1 = Watchdog timer interrupt function Enabled.

Definition at line 10494 of file Nano1X2Series.h.

## ◆ RLD

__O uint32_t WWDT_T::RLD

# RLD

## Offset: 0x00 Window Watchdog Timer Reload Counter Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | RLD | Window Watchdog Timer Reload Counter Register
|  | Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
|  | Note: SW only can write WWDTRLD when WWDT counter value between 0 and WINCMP.
|  | If SW writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal.

Definition at line 10457 of file Nano1X2Series.h.

## ◆ STS

__IO uint32_t WWDT_T::STS

# STS

## Offset: 0x0C Window Watchdog Timer Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | IF | WWDT Compare Match Interrupt Flag
|  | When WWCMP match the WWDT counter, then this bit is set to 1.
|  | This bit will be cleared by software write 1 to this bit.
[1] | RF | WWDT Reset Flag
|  | When WWDT counter down count to 0 or write WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1.
|  | Software can write 1 to clear this bit to 0.

Definition at line 10510 of file Nano1X2Series.h.

## ◆ VAL

__I uint32_t WWDT_T::VAL

# WWDTVAL

## Offset: 0x10 Window Watchdog Timer Counter Value Register

Bits | Field | Descriptions
--- | --- | ---
[5:0] | VAL | WWDT Counter Value
|  | This register reflects the counter value of window watchdog. This register is read only

Definition at line 10522 of file Nano1X2Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Nano1X2Series/Include/Nano1X2Series.h