| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Nano1X2Series.h
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1 /**************************************************************************/
49 #ifndef __NANO1X2SERIES_H__
50 #define __NANO1X2SERIES_H__
51
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55
66 /******************************************************************************/
67 /* Processor and Core Peripherals */
68 /******************************************************************************/
77 typedef enum IRQn
78 {
79 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
80
81 NonMaskableInt_IRQn = -14,
82 HardFault_IRQn = -13,
83 SVCall_IRQn = -5,
84 PendSV_IRQn = -2,
85 SysTick_IRQn = -1,
87 /****** NANO102/112 specific Interrupt Numbers ***********************************************/
88 BOD_IRQn = 0,
89 WDT_IRQn = 1,
90 EINT0_IRQn = 2,
91 EINT1_IRQn = 3,
92 GPABC_IRQn = 4,
93 GPDEF_IRQn = 5,
94 PWM0_IRQn = 6,
95 TMR0_IRQn = 8,
96 TMR1_IRQn = 9,
97 TMR2_IRQn = 10,
98 TMR3_IRQn = 11,
99 UART0_IRQn = 12,
100 UART1_IRQn = 13,
101 SPI0_IRQn = 14,
102 SPI1_IRQn = 15,
103 HIRC_IRQn = 17,
104 I2C0_IRQn = 18,
105 I2C1_IRQn = 19,
106 SC0_IRQn = 21,
107 SC1_IRQn = 22,
108 LCD_IRQn = 25,
109 PDMA_IRQn = 26,
110 PDWU_IRQn = 28,
111 ADC_IRQn = 29,
112 ACMP_IRQn = 30,
113 RTC_IRQn = 31
114 } IRQn_Type;
115
116
117 /*
118 * ==========================================================================
119 * ----------- Processor and Core Peripheral Section ------------------------
120 * ==========================================================================
121 */
122
123 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
124 #define __CM0_REV 0x0201
125 #define __NVIC_PRIO_BITS 2
126 #define __Vendor_SysTickConfig 0
127 #define __MPU_PRESENT 0
128 #define __FPU_PRESENT 0
130 /* end of group NANO1X2_CMSIS */
131
132
133 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
134 #include "system_Nano1X2Series.h" /* NANO102/112 Series System include file */
135 #include <stdint.h>
136
137 /******************************************************************************/
138 /* Device Specific Peripheral registers structures */
139 /******************************************************************************/
145 #if defined ( __CC_ARM )
146 #pragma anon_unions
147 #endif
148
149
150 /*---------------------- Analog Comparator Controller -------------------------*/
156 typedef struct
157 {
158
159
206 __IO uint32_t CR[2];
207
208
231 __IO uint32_t SR;
232
249 __IO uint32_t RVCR;
250
287 __IO uint32_t MODCR0;
288
289 } ACMP_T;
290
296 #define ACMP_CR_ACMPEN_Pos (0)
297 #define ACMP_CR_ACMPEN_Msk (0x1ul << ACMP_CR_ACMPEN_Pos)
299 #define ACMP_CR_ACMPIE_Pos (1)
300 #define ACMP_CR_ACMPIE_Msk (0x1ul << ACMP_CR_ACMPIE_Pos)
302 #define ACMP_CR_ACMP_HYSEN_Pos (2)
303 #define ACMP_CR_ACMP_HYSEN_Msk (0x1ul << ACMP_CR_ACMP_HYSEN_Pos)
305 #define ACMP_CR_CN_Pos (4)
306 #define ACMP_CR_CN_Msk (0x3ul << ACMP_CR_CN_Pos)
308 #define ACMP_CR_ACMP0_EX_Pos (16)
309 #define ACMP_CR_ACMP0_EX_Msk (0x1ul << ACMP_CR_ACMP0_EX_Pos)
311 #define ACMP_CR_ACMP0_INV_Pos (17)
312 #define ACMP_CR_ACMP0_INV_Msk (0x1UL<<ACMP_CR_ACMP0_INV_Pos)
314 #define ACMP_CR_ACOMP0_PN_AutoEx_Pos (19)
315 #define ACMP_CR_ACOMP0_PN_AutoEx_Msk (0x1ul << ACMP_CR_ACOMP0_PN_AutoEx_Pos)
317 #define ACMP_CR_ACMP0_FILTER_Pos (20)
318 #define ACMP_CR_ACMP0_FILTER_Msk (0x1ul << ACMP_CR_ACMP0_FILTER_Pos)
320 #define ACMP_CR_CPO0_SEL_Pos (21)
321 #define ACMP_CR_CPO0_SEL_Msk (0x1ul << ACMP_CR_CPO0_SEL_Pos)
323 #define ACMP_CR_CPP0SEL_Pos (29)
324 #define ACMP_CR_CPP0SEL_Msk (0x3ul << ACMP_CR_CPP0SEL_Pos)
326 #define ACMP_CR_ACMP_WKEUP_EN_Pos (31)
327 #define ACMP_CR_ACMP_WKEUP_EN_Msk (0x1ul << ACMP_CR_ACMP0_WKEUP_EN_Pos)
329 #define ACMP_SR_ACMPF0_Pos (0)
330 #define ACMP_SR_ACMPF0_Msk (0x1ul << ACMP_SR_ACMPF0_Pos)
332 #define ACMP_SR_ACMPF1_Pos (1)
333 #define ACMP_SR_ACMPF1_Msk (0x1ul << ACMP_SR_ACMPF1_Pos)
335 #define ACMP_SR_CO0_Pos (2)
336 #define ACMP_SR_CO0_Msk (0x1ul << ACMP_SR_CO0_Pos)
338 #define ACMP_SR_CO1_Pos (3)
339 #define ACMP_SR_CO1_Msk (0x1ul << ACMP_SR_CO1_Pos)
341 #define ACMP_RVCR_CRVS_Pos (0)
342 #define ACMP_RVCR_CRVS_Msk (0xful << ACMP_RVCR_CRVS_Pos)
344 #define ACMP_RVCR_CRV_EN_Pos (4)
345 #define ACMP_RVCR_CRV_EN_Msk (0x1ul << ACMP_RVCR_CRV_EN_Pos)
347 #define ACMP_RVCR_CRVSRC_SEL_Pos (5)
348 #define ACMP_RVCR_CRVSRC_SEL_Msk (0x1ul << ACMP_RVCR_CRVSRC_SEL_Pos)
350 #define ACMP_MODCR0_MOD_SEL_Pos (0)
351 #define ACMP_MODCR0_MOD_SEL_Msk (0x3ul << ACMP_MODCR0_MOD_SEL_Pos)
353 #define ACMP_MODCR0_TMR_SEL_Pos (2)
354 #define ACMP_MODCR0_TMR_SEL_Msk (0x1ul << ACMP_MODCR0_TMR_SEL_Pos)
356 #define ACMP_MODCR0_TMR_TRI_LV_Pos (3)
357 #define ACMP_MODCR0_TMR_TRI_LV_Msk (0x1ul << ACMP_MODCR0_TMR_TRI_LV_Pos)
359 #define ACMP_MODCR0_CH_DIS_PIN_SEL_Pos (4)
360 #define ACMP_MODCR0_CH_DIS_PIN_SEL_Msk (0x7ul << ACMP_MODCR0_CH_DIS_PIN_SEL_Pos)
362 #define ACMP_MODCR0_CH_DIS_FUN_SEL_Pos (7)
363 #define ACMP_MODCR0_CH_DIS_FUN_SEL_Msk (0x1ul << ACMP_MODCR0_CH_DIS_FUN_SEL_Pos)
365 #define ACMP_MODCR0_START_Pos (8)
366 #define ACMP_MODCR0_START_Msk (0x1ul << ACMP_MODCR0_START_Pos) /* ACMP_CONST */
369 /* end of ACMP register group */
370
371
372 /*---------------------- Analog to Digital Converter -------------------------*/
378 typedef struct
379 {
380
381
397 __I uint32_t RESULT[18];
398
399
482 __IO uint32_t CR;
483
529 __IO uint32_t CHEN;
530
560 __IO uint32_t CMPR0;
561
591 __IO uint32_t CMPR1;
592
634 __IO uint32_t SR;
635 uint32_t RESERVE1[1];
636
648 __I uint32_t PDMA;
649
671 __IO uint32_t PWRCTL;
672
695 __IO uint32_t CALCTL;
696
709 __IO uint32_t CALWORD;
710
746 __IO uint32_t SMPLCNT0;
747
758 __IO uint32_t SMPLCNT1;
759
760 } ADC_T;
761
767 #define ADC_RESULT_RSLT_Pos (0)
768 #define ADC_RESULT_RSLT_Msk (0xffful << ADC_RESULT_RSLT_Pos)
770 #define ADC_RESULT_VALID_Pos (16)
771 #define ADC_RESULT_VALID_Msk (0x1ul << ADC_RESULT_VALID_Pos)
773 #define ADC_RESULT_OVERRUN_Pos (17)
774 #define ADC_RESULT_OVERRUN_Msk (0x1ul << ADC_RESULT_OVERRUN_Pos)
776 #define ADC_CR_ADEN_Pos (0)
777 #define ADC_CR_ADEN_Msk (0x1ul << ADC_CR_ADEN_Pos)
779 #define ADC_CR_ADIE_Pos (1)
780 #define ADC_CR_ADIE_Msk (0x1ul << ADC_CR_ADIE_Pos)
782 #define ADC_CR_ADMD_Pos (2)
783 #define ADC_CR_ADMD_Msk (0x3ul << ADC_CR_ADMD_Pos)
785 #define ADC_CR_TRGS_Pos (4)
786 #define ADC_CR_TRGS_Msk (0x3ul << ADC_CR_TRGS_Pos)
788 #define ADC_CR_TRGCOND_Pos (6)
789 #define ADC_CR_TRGCOND_Msk (0x3ul << ADC_CR_TRGCOND_Pos)
791 #define ADC_CR_TRGE_Pos (8)
792 #define ADC_CR_TRGE_Msk (0x1ul << ADC_CR_TRGE_Pos)
794 #define ADC_CR_PTEN_Pos (9)
795 #define ADC_CR_PTEN_Msk (0x1ul << ADC_CR_PTEN_Pos)
797 #define ADC_CR_DIFF_Pos (10)
798 #define ADC_CR_DIFF_Msk (0x1ul << ADC_CR_DIFF_Pos)
800 #define ADC_CR_ADST_Pos (11)
801 #define ADC_CR_ADST_Msk (0x1ul << ADC_CR_ADST_Pos)
803 #define ADC_CR_TMSEL_Pos (12)
804 #define ADC_CR_TMSEL_Msk (0x3ul << ADC_CR_TMSEL_Pos)
806 #define ADC_CR_TMTRGMOD_Pos (15)
807 #define ADC_CR_TMTRGMOD_Msk (0x1ul << ADC_CR_TMTRGMOD_Pos)
809 #define ADC_CR_REFSEL_Pos (16)
810 #define ADC_CR_REFSEL_Msk (0x3ul << ADC_CR_REFSEL_Pos)
812 #define ADC_CR_RESSEL_Pos (18)
813 #define ADC_CR_RESSEL_Msk (0x3ul << ADC_CR_RESSEL_Pos)
815 #define ADC_CR_TMPDMACNT_Pos (24)
816 #define ADC_CR_TMPDMACNT_Msk (0xfful << ADC_CR_TMPDMACNT_Pos)
818 #define ADC_CHEN_CHEN0_Pos (0)
819 #define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
821 #define ADC_CMPR_CMPEN_Pos (0)
822 #define ADC_CMPR_CMPEN_Msk (0x1ul << ADC_CMPR_CMPEN_Pos)
824 #define ADC_CMPR_CMPIE_Pos (1)
825 #define ADC_CMPR_CMPIE_Msk (0x1ul << ADC_CMPR_CMPIE_Pos)
827 #define ADC_CMPR_CMPCOND_Pos (2)
828 #define ADC_CMPR_CMPCOND_Msk (0x1ul << ADC_CMPR_CMPCOND_Pos)
830 #define ADC_CMPR_CMPCH_Pos (3)
831 #define ADC_CMPR_CMPCH_Msk (0x1ful << ADC_CMPR_CMPCH_Pos)
833 #define ADC_CMPR_CMPMATCNT_Pos (8)
834 #define ADC_CMPR_CMPMATCNT_Msk (0xful << ADC_CMPR_CMPMATCNT_Pos)
836 #define ADC_CMPR_CMPD_Pos (16)
837 #define ADC_CMPR_CMPD_Msk (0xffful << ADC_CMPR_CMPD_Pos)
839 #define ADC_SR_ADF_Pos (0)
840 #define ADC_SR_ADF_Msk (0x1ul << ADC_SR_ADF_Pos)
842 #define ADC_SR_CMPF0_Pos (1)
843 #define ADC_SR_CMPF0_Msk (0x1ul << ADC_SR_CMPF0_Pos)
845 #define ADC_SR_CMPF1_Pos (2)
846 #define ADC_SR_CMPF1_Msk (0x1ul << ADC_SR_CMPF1_Pos)
848 #define ADC_SR_BUSY_Pos (3)
849 #define ADC_SR_BUSY_Msk (0x1ul << ADC_SR_BUSY_Pos)
851 #define ADC_SR_CHANNEL_Pos (4)
852 #define ADC_SR_CHANNEL_Msk (0x1ful << ADC_SR_CHANNEL_Pos)
854 #define ADC_SR_INITRDY_Pos (16)
855 #define ADC_SR_INITRDY_Msk (0x1ul << ADC_SR_INITRDY_Pos)
857 #define ADC_PDMA_AD_PDMA_Pos (0)
858 #define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos)
860 #define ADC_PWRCTL_PWUPRDY_Pos (0)
861 #define ADC_PWRCTL_PWUPRDY_Msk (0x1ul << ADC_PWRCTL_PWUPRDY_Pos)
863 #define ADC_PWRCTL_PWDCALEN_Pos (1)
864 #define ADC_PWRCTL_PWDCALEN_Msk (0x1ul << ADC_PWRCTL_PWDCALEN_Pos)
866 #define ADC_PWRCTL_PWDMOD_Pos (2)
867 #define ADC_PWRCTL_PWDMOD_Msk (0x3ul << ADC_PWRCTL_PWDMOD_Pos)
869 #define ADC_CALCTL_CALEN_Pos (0)
870 #define ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos)
872 #define ADC_CALCTL_CALSTART_Pos (1)
873 #define ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos)
875 #define ADC_CALCTL_CALDONE_Pos (2)
876 #define ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos)
878 #define ADC_CALCTL_CALSEL_Pos (3)
879 #define ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos)
881 #define ADC_CALWORD_CALWORD_Pos (0)
882 #define ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos)
884 #define ADC_SMPLCNT0_CH0SAMPCNT_Pos (0)
885 #define ADC_SMPLCNT0_CH0SAMPCNT_Msk (0xful << ADC_SMPLCNT0_CH0SAMPCNT_Pos)
887 #define ADC_SMPLCNT1_CH8SAMPCNT_Pos (0)
888 #define ADC_SMPLCNT1_CH8SAMPCNT_Msk (0xful << ADC_SMPLCNT1_CH8SAMPCNT_Pos)
890 #define ADC_SMPLCNT1_INTCHSAMPCNT_Pos (16)
891 #define ADC_SMPLCNT1_INTCHSAMPCNT_Msk (0xful << ADC_SMPLCNT1_INTCHSAMPCNT_Pos) /* ADC_CONST */
894 /* end of ADC register group */
895
896
897 /*---------------------- System Clock Controller -------------------------*/
903 typedef struct
904 {
905
906
983 __IO uint32_t PWRCTL;
984
1008 __IO uint32_t AHBCLK;
1009
1084 __IO uint32_t APBCLK;
1085
1113 __I uint32_t CLKSTATUS;
1114
1134 __IO uint32_t CLKSEL0;
1135
1184 __IO uint32_t CLKSEL1;
1185
1229 __IO uint32_t CLKSEL2;
1230
1247 __IO uint32_t CLKDIV0;
1248
1267 __IO uint32_t CLKDIV1;
1268
1300 __IO uint32_t PLLCTL;
1301
1320 __IO uint32_t FRQDIV0;
1321 uint32_t RESERVE0[1];
1322
1323
1336 __IO uint32_t WK_INTSTS;
1337
1354 __IO uint32_t APB_DIV;
1355
1374 __IO uint32_t FRQDIV1;
1375
1403 __IO uint32_t SP_DET;
1404
1429 __I uint32_t SP_STS;
1430
1431 } CLK_T;
1432
1438 #define CLK_PWRCTL_HXT_EN_Pos (0)
1439 #define CLK_PWRCTL_HXT_EN_Msk (0x1ul << CLK_PWRCTL_HXT_EN_Pos)
1441 #define CLK_PWRCTL_LXT_EN_Pos (1)
1442 #define CLK_PWRCTL_LXT_EN_Msk (0x1ul << CLK_PWRCTL_LXT_EN_Pos)
1444 #define CLK_PWRCTL_HIRC_EN_Pos (2)
1445 #define CLK_PWRCTL_HIRC_EN_Msk (0x1ul << CLK_PWRCTL_HIRC_EN_Pos)
1447 #define CLK_PWRCTL_LIRC_EN_Pos (3)
1448 #define CLK_PWRCTL_LIRC_EN_Msk (0x1ul << CLK_PWRCTL_LIRC_EN_Pos)
1450 #define CLK_PWRCTL_WK_DLY_Pos (4)
1451 #define CLK_PWRCTL_WK_DLY_Msk (0x1ul << CLK_PWRCTL_WK_DLY_Pos)
1453 #define CLK_PWRCTL_PD_WK_IE_Pos (5)
1454 #define CLK_PWRCTL_PD_WK_IE_Msk (0x1ul << CLK_PWRCTL_PD_WK_IE_Pos)
1456 #define CLK_PWRCTL_PD_EN_Pos (6)
1457 #define CLK_PWRCTL_PD_EN_Msk (0x1ul << CLK_PWRCTL_PD_EN_Pos)
1459 #define CLK_PWRCTL_HXT_SELXT_Pos (8)
1460 #define CLK_PWRCTL_HXT_SELXT_Msk (0x1ul << CLK_PWRCTL_HXT_SELXT_Pos)
1462 #define CLK_PWRCTL_HXT_CUR_SEL_Pos (9)
1463 #define CLK_PWRCTL_HXT_CUR_SEL_Msk (0x1ul << CLK_PWRCTL_HXT_CUR_SEL_Pos)
1465 #define CLK_PWRCTL_HXT_GAIN_Pos (10)
1466 #define CLK_PWRCTL_HXT_GAIN_Msk (0x3ul << CLK_PWRCTL_HXT_GAIN_Pos)
1468 #define CLK_PWRCTL_HIRC_FSEL_Pos (12)
1469 #define CLK_PWRCTL_HIRC_FSEL_Msk (0x1ul << CLK_PWRCTL_HIRC_FSEL_Pos)
1471 #define CLK_PWRCTL_HIRC_F_STOP_Pos (13)
1472 #define CLK_PWRCTL_HIRC_F_STOP_Msk (0x1ul << CLK_PWRCTL_HIRC_F_STOP_Pos)
1474 #define CLK_AHBCLK_GPIO_EN_Pos (0)
1475 #define CLK_AHBCLK_GPIO_EN_Msk (0x1ul << CLK_AHBCLK_GPIO_EN_Pos)
1477 #define CLK_AHBCLK_DMA_EN_Pos (1)
1478 #define CLK_AHBCLK_DMA_EN_Msk (0x1ul << CLK_AHBCLK_DMA_EN_Pos)
1480 #define CLK_AHBCLK_ISP_EN_Pos (2)
1481 #define CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos)
1483 #define CLK_AHBCLK_SRAM_EN_Pos (4)
1484 #define CLK_AHBCLK_SRAM_EN_Msk (0x1ul << CLK_AHBCLK_SRAM_EN_Pos)
1486 #define CLK_AHBCLK_TICK_EN_Pos (5)
1487 #define CLK_AHBCLK_TICK_EN_Msk (0x1ul << CLK_AHBCLK_TICK_EN_Pos)
1489 #define CLK_APBCLK_WDT_EN_Pos (0)
1490 #define CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos)
1492 #define CLK_APBCLK_RTC_EN_Pos (1)
1493 #define CLK_APBCLK_RTC_EN_Msk (0x1ul << CLK_APBCLK_RTC_EN_Pos)
1495 #define CLK_APBCLK_TMR0_EN_Pos (2)
1496 #define CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos)
1498 #define CLK_APBCLK_TMR1_EN_Pos (3)
1499 #define CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos)
1501 #define CLK_APBCLK_TMR2_EN_Pos (4)
1502 #define CLK_APBCLK_TMR2_EN_Msk (0x1ul << CLK_APBCLK_TMR2_EN_Pos)
1504 #define CLK_APBCLK_TMR3_EN_Pos (5)
1505 #define CLK_APBCLK_TMR3_EN_Msk (0x1ul << CLK_APBCLK_TMR3_EN_Pos)
1507 #define CLK_APBCLK_FDIV0_EN_Pos (6)
1508 #define CLK_APBCLK_FDIV0_EN_Msk (0x1ul << CLK_APBCLK_FDIV0_EN_Pos)
1510 #define CLK_APBCLK_FDIV1_EN_Pos (7)
1511 #define CLK_APBCLK_FDIV1_EN_Msk (0x1ul << CLK_APBCLK_FDIV1_EN_Pos)
1513 #define CLK_APBCLK_I2C0_EN_Pos (8)
1514 #define CLK_APBCLK_I2C0_EN_Msk (0x1ul << CLK_APBCLK_I2C0_EN_Pos)
1516 #define CLK_APBCLK_I2C1_EN_Pos (9)
1517 #define CLK_APBCLK_I2C1_EN_Msk (0x1ul << CLK_APBCLK_I2C1_EN_Pos)
1519 #define CLK_APBCLK_ACMP_EN_Pos (11)
1520 #define CLK_APBCLK_ACMP_EN_Msk (0x1ul << CLK_APBCLK_ACMP_EN_Pos)
1522 #define CLK_APBCLK_SPI0_EN_Pos (12)
1523 #define CLK_APBCLK_SPI0_EN_Msk (0x1ul << CLK_APBCLK_SPI0_EN_Pos)
1525 #define CLK_APBCLK_SPI1_EN_Pos (13)
1526 #define CLK_APBCLK_SPI1_EN_Msk (0x1ul << CLK_APBCLK_SPI1_EN_Pos)
1528 #define CLK_APBCLK_UART0_EN_Pos (16)
1529 #define CLK_APBCLK_UART0_EN_Msk (0x1ul << CLK_APBCLK_UART0_EN_Pos)
1531 #define CLK_APBCLK_UART1_EN_Pos (17)
1532 #define CLK_APBCLK_UART1_EN_Msk (0x1ul << CLK_APBCLK_UART1_EN_Pos)
1534 #define CLK_APBCLK_PWM0_CH01_EN_Pos (20)
1535 #define CLK_APBCLK_PWM0_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH01_EN_Pos)
1537 #define CLK_APBCLK_PWM0_CH23_EN_Pos (21)
1538 #define CLK_APBCLK_PWM0_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH23_EN_Pos)
1540 #define CLK_APBCLK_LCD_EN_Pos (26)
1541 #define CLK_APBCLK_LCD_EN_Msk (0x1ul << CLK_APBCLK_LCD_EN_Pos)
1543 #define CLK_APBCLK_ADC_EN_Pos (28)
1544 #define CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos)
1546 #define CLK_APBCLK_SC0_EN_Pos (30)
1547 #define CLK_APBCLK_SC0_EN_Msk (0x1ul << CLK_APBCLK_SC0_EN_Pos)
1549 #define CLK_APBCLK_SC1_EN_Pos (31)
1550 #define CLK_APBCLK_SC1_EN_Msk (0x1ul << CLK_APBCLK_SC1_EN_Pos)
1552 #define CLK_CLKSTATUS_HXT_STB_Pos (0)
1553 #define CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos)
1555 #define CLK_CLKSTATUS_LXT_STB_Pos (1)
1556 #define CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos)
1558 #define CLK_CLKSTATUS_PLL_STB_Pos (2)
1559 #define CLK_CLKSTATUS_PLL_STB_Msk (0x1ul << CLK_CLKSTATUS_PLL_STB_Pos)
1561 #define CLK_CLKSTATUS_LIRC_STB_Pos (3)
1562 #define CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos)
1564 #define CLK_CLKSTATUS_HIRC_STB_Pos (4)
1565 #define CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos)
1567 #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7)
1568 #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos)
1570 #define CLK_CLKSEL0_HCLK_S_Pos (0)
1571 #define CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos)
1573 #define CLK_CLKSEL1_UART_S_Pos (0)
1574 #define CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos)
1576 #define CLK_CLKSEL1_PWM0_CH01_S_Pos (4)
1577 #define CLK_CLKSEL1_PWM0_CH01_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH01_S_Pos)
1579 #define CLK_CLKSEL1_PWM0_CH23_S_Pos (6)
1580 #define CLK_CLKSEL1_PWM0_CH23_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH23_S_Pos)
1582 #define CLK_CLKSEL1_TMR0_S_Pos (8)
1583 #define CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos)
1585 #define CLK_CLKSEL1_TMR1_S_Pos (12)
1586 #define CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos)
1588 #define CLK_CLKSEL1_LCD_S_Pos (18)
1589 #define CLK_CLKSEL1_LCD_S_Msk (0x1ul << CLK_CLKSEL1_LCD_S_Pos)
1591 #define CLK_CLKSEL1_ADC_S_Pos (19)
1592 #define CLK_CLKSEL1_ADC_S_Msk (0x7ul << CLK_CLKSEL1_ADC_S_Pos)
1594 #define CLK_CLKSEL2_FRQDIV1_S_Pos (0)
1595 #define CLK_CLKSEL2_FRQDIV1_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV1_S_Pos)
1597 #define CLK_CLKSEL2_FRQDIV0_S_Pos (2)
1598 #define CLK_CLKSEL2_FRQDIV0_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV0_S_Pos)
1600 #define CLK_CLKSEL2_TMR2_S_Pos (8)
1601 #define CLK_CLKSEL2_TMR2_S_Msk (0x7ul << CLK_CLKSEL2_TMR2_S_Pos)
1603 #define CLK_CLKSEL2_TMR3_S_Pos (12)
1604 #define CLK_CLKSEL2_TMR3_S_Msk (0x7ul << CLK_CLKSEL2_TMR3_S_Pos)
1606 #define CLK_CLKSEL2_SC_S_Pos (18)
1607 #define CLK_CLKSEL2_SC_S_Msk (0x3ul << CLK_CLKSEL2_SC_S_Pos)
1609 #define CLK_CLKSEL2_SPI0_S_Pos (20)
1610 #define CLK_CLKSEL2_SPI0_S_Msk (0x1ul << CLK_CLKSEL2_SPI0_S_Pos)
1612 #define CLK_CLKSEL2_SPI1_S_Pos (21)
1613 #define CLK_CLKSEL2_SPI1_S_Msk (0x1ul << CLK_CLKSEL2_SPI1_S_Pos)
1615 #define CLK_CLKDIV0_HCLK_N_Pos (0)
1616 #define CLK_CLKDIV0_HCLK_N_Msk (0xful << CLK_CLKDIV0_HCLK_N_Pos)
1618 #define CLK_CLKDIV0_UART_N_Pos (8)
1619 #define CLK_CLKDIV0_UART_N_Msk (0xful << CLK_CLKDIV0_UART_N_Pos)
1621 #define CLK_CLKDIV0_ADC_N_Pos (16)
1622 #define CLK_CLKDIV0_ADC_N_Msk (0xfful << CLK_CLKDIV0_ADC_N_Pos)
1624 #define CLK_CLKDIV0_SC0_N_Pos (28)
1625 #define CLK_CLKDIV0_SC0_N_Msk (0xful << CLK_CLKDIV0_SC0_N_Pos)
1627 #define CLK_CLKDIV1_SC1_N_Pos (0)
1628 #define CLK_CLKDIV1_SC1_N_Msk (0xful << CLK_CLKDIV1_SC1_N_Pos)
1630 #define CLK_CLKDIV1_TMR0_N_Pos (8)
1631 #define CLK_CLKDIV1_TMR0_N_Msk (0xful << CLK_CLKDIV1_TMR0_N_Pos)
1633 #define CLK_CLKDIV1_TMR1_N_Pos (12)
1634 #define CLK_CLKDIV1_TMR1_N_Msk (0xful << CLK_CLKDIV1_TMR1_N_Pos)
1636 #define CLK_CLKDIV1_TMR2_N_Pos (16)
1637 #define CLK_CLKDIV1_TMR2_N_Msk (0xful << CLK_CLKDIV1_TMR2_N_Pos)
1639 #define CLK_CLKDIV1_TMR3_N_Pos (20)
1640 #define CLK_CLKDIV1_TMR3_N_Msk (0xful << CLK_CLKDIV1_TMR3_N_Pos)
1642 #define CLK_PLLCTL_PLL_MLP_Pos (0)
1643 #define CLK_PLLCTL_PLL_MLP_Msk (0x3ful << CLK_PLLCTL_PLL_MLP_Pos)
1645 #define CLK_PLLCTL_PLL_SRC_N_Pos (8)
1646 #define CLK_PLLCTL_PLL_SRC_N_Msk (0xful << CLK_PLLCTL_PLL_SRC_N_Pos)
1648 #define CLK_PLLCTL_PD_Pos (16)
1649 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
1651 #define CLK_PLLCTL_PLL_SRC_Pos (17)
1652 #define CLK_PLLCTL_PLL_SRC_Msk (0x1ul << CLK_PLLCTL_PLL_SRC_Pos)
1654 #define CLK_FRQDIV0_FSEL_Pos (0)
1655 #define CLK_FRQDIV0_FSEL_Msk (0xful << CLK_FRQDIV0_FSEL_Pos)
1657 #define CLK_FRQDIV0_FDIV_EN_Pos (4)
1658 #define CLK_FRQDIV0_FDIV_EN_Msk (0x1ul << CLK_FRQDIV0_FDIV_EN_Pos)
1660 #define CLK_FRQDIV0_DIV1_Pos (5)
1661 #define CLK_FRQDIV0_DIV1_Msk (0x1ul << CLK_FRQDIV0_DIV1_Pos)
1663 #define CLK_WK_INTSTS_PD_WK_IS_Pos (0)
1664 #define CLK_WK_INTSTS_PD_WK_IS_Msk (0x1ul << CLK_WK_INTSTS_PD_WK_IS_Pos)
1666 #define CLK_APB_DIV_APBDIV_Pos (0)
1667 #define CLK_APB_DIV_APBDIV_Msk (0x7ul << CLK_APB_DIV_APBDIV_Pos)
1669 #define CLK_FRQDIV1_FSEL_Pos (0)
1670 #define CLK_FRQDIV1_FSEL_Msk (0xful << CLK_FRQDIV1_FSEL_Pos)
1672 #define CLK_FRQDIV1_FDIV_EN_Pos (4)
1673 #define CLK_FRQDIV1_FDIV_EN_Msk (0x1ul << CLK_FRQDIV1_FDIV_EN_Pos)
1675 #define CLK_FRQDIV1_DIV1_Pos (5)
1676 #define CLK_FRQDIV1_DIV1_Msk (0x1ul << CLK_FRQDIV1_DIV1_Pos)
1678 #define CLK_SP_DET_HCLK_DET_Pos (0)
1679 #define CLK_SP_DET_HCLK_DET_Msk (0x1ul << CLK_SP_DET_HCLK_DET_Pos)
1681 #define CLK_SP_DET_HCLK_STOP_IE_Pos (1)
1682 #define CLK_SP_DET_HCLK_STOP_IE_Msk (0x1ul << CLK_SP_DET_HCLK_STOP_IE_Pos)
1684 #define CLK_SP_DET_HXT_DET_Pos (2)
1685 #define CLK_SP_DET_HXT_DET_Msk (0x1ul << CLK_SP_DET_HXT_DET_Pos)
1687 #define CLK_SP_DET_HXT_STOP_IE_Pos (3)
1688 #define CLK_SP_DET_HXT_STOP_IE_Msk (0x1ul << CLK_SP_DET_HXT_STOP_IE_Pos)
1690 #define CLK_SP_DET_HIRC_DET_Pos (4)
1691 #define CLK_SP_DET_HIRC_DET_Msk (0x1ul << CLK_SP_DET_HIRC_DET_Pos)
1693 #define CLK_SP_DET_HIRC_STOP_IE_Pos (5)
1694 #define CLK_SP_DET_HIRC_STOP_IE_Msk (0x1ul << CLK_SP_DET_HIRC_STOP_IE_Pos)
1696 #define CLK_SP_STS_HCLK_SP_IS_Pos (0)
1697 #define CLK_SP_STS_HCLK_SP_IS_Msk (0x1ul << CLK_SP_STS_HCLK_SP_IS_Pos)
1699 #define CLK_SP_STS_HXT_SP_IS_Pos (2)
1700 #define CLK_SP_STS_HXT_SP_IS_Msk (0x1ul << CLK_SP_STS_HXT_SP_IS_Pos)
1702 #define CLK_SP_STS_HIRC_SP_IS_Pos (4)
1703 #define CLK_SP_STS_HIRC_SP_IS_Msk (0x1ul << CLK_SP_STS_HIRC_SP_IS_Pos)
1705 #define CLK_SP_STS_HCLK_SEL_Pos (8)
1706 #define CLK_SP_STS_HCLK_SEL_Msk (0x7ul << CLK_SP_STS_HCLK_SEL_Pos) /* CLK_CONST */
1709 /* end of CLK register group */
1710
1711
1712 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
1719 typedef struct
1720 {
1721
1722
1776 __IO uint32_t CTL;
1777
1789 __IO uint32_t DMASAR;
1790 uint32_t RESERVE0[1];
1791
1792
1803 __IO uint32_t DMABCR;
1804 uint32_t RESERVE1[1];
1805
1806
1817 __I uint32_t DMACSAR;
1818 uint32_t RESERVE2[1];
1819
1820
1832 __I uint32_t DMACBCR;
1833
1848 __IO uint32_t DMAIER;
1849
1871 __IO uint32_t DMAISR;
1872 uint32_t RESERVE3[22];
1873
1874
1888 __IO uint32_t WDATA;
1889
1900 __IO uint32_t SEED;
1901
1912 __I uint32_t CHECKSUM;
1913
1914 } DMA_CRC_T;
1915
1916
1917 typedef struct
1918 {
1919
1920
1944 __IO uint32_t GCRCSR;
1945
1994 __IO uint32_t DSSR0;
1995
2034 __IO uint32_t DSSR1;
2035
2055 __I uint32_t GCRISR;
2056
2057 } DMA_GCR_T;
2058
2059
2060 typedef struct
2061 {
2114 __IO uint32_t CSR;
2115
2127 __IO uint32_t SAR;
2128
2140 __IO uint32_t DAR;
2141
2153 __IO uint32_t BCR;
2154 uint32_t RESERVE0[1];
2155
2156
2167 __I uint32_t CSAR;
2168
2179 __I uint32_t CDAR;
2180
2192 __I uint32_t CBCR;
2193
2214 __IO uint32_t IER;
2215
2247 __IO uint32_t ISR;
2248
2262 __IO uint32_t TCR;
2263
2264 } PDMA_T;
2265
2271 #define DMA_CRC_CTL_CRCCEN_Pos (0)
2272 #define DMA_CRC_CTL_CRCCEN_Msk (0x1ul << DMA_CRC_CTL_CRCCEN_Pos)
2274 #define DMA_CRC_CTL_CRC_RST_Pos (1)
2275 #define DMA_CRC_CTL_CRC_RST_Msk (0x1ul << DMA_CRC_CTL_CRC_RST_Pos)
2277 #define DMA_CRC_CTL_TRIG_EN_Pos (23)
2278 #define DMA_CRC_CTL_TRIG_EN_Msk (0x1ul << DMA_CRC_CTL_TRIG_EN_Pos)
2280 #define DMA_CRC_CTL_WDATA_RVS_Pos (24)
2281 #define DMA_CRC_CTL_WDATA_RVS_Msk (0x1ul << DMA_CRC_CTL_WDATA_RVS_Pos)
2283 #define DMA_CRC_CTL_CHECKSUM_RVS_Pos (25)
2284 #define DMA_CRC_CTL_CHECKSUM_RVS_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_RVS_Pos)
2286 #define DMA_CRC_CTL_WDATA_COM_Pos (26)
2287 #define DMA_CRC_CTL_WDATA_COM_Msk (0x1ul << DMA_CRC_CTL_WDATA_COM_Pos)
2289 #define DMA_CRC_CTL_CHECKSUM_COM_Pos (27)
2290 #define DMA_CRC_CTL_CHECKSUM_COM_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_COM_Pos)
2292 #define DMA_CRC_CTL_CPU_WDLEN_Pos (28)
2293 #define DMA_CRC_CTL_CPU_WDLEN_Msk (0x3ul << DMA_CRC_CTL_CPU_WDLEN_Pos)
2295 #define DMA_CRC_CTL_CRC_MODE_Pos (30)
2296 #define DMA_CRC_CTL_CRC_MODE_Msk (0x3ul << DMA_CRC_CTL_CRC_MODE_Pos)
2298 #define DMA_CRC_DMASAR_CRC_DMASAR_Pos (0)
2299 #define DMA_CRC_DMASAR_CRC_DMASAR_Msk (0xfffffffful << DMA_CRC_DMASAR_CRC_DMASAR_Pos)
2301 #define DMA_CRC_DMABCR_CRC_DMABCR_Pos (0)
2302 #define DMA_CRC_DMABCR_CRC_DMABCR_Msk (0xfffful << DMA_CRC_DMABCR_CRC_DMABCR_Pos)
2304 #define DMA_CRC_DMACSAR_CRC_DMACSAR_Pos (0)
2305 #define DMA_CRC_DMACSAR_CRC_DMACSAR_Msk (0xfffffffful << DMA_CRC_DMACSAR_CRC_DMACSAR_Pos)
2307 #define DMA_CRC_DMACBCR_CRC_DMACBCR_Pos (0)
2308 #define DMA_CRC_DMACBCR_CRC_DMACBCR_Msk (0xfffful << DMA_CRC_DMACBCR_CRC_DMACBCR_Pos)
2310 #define DMA_CRC_DMAIER_TABORT_IE_Pos (0)
2311 #define DMA_CRC_DMAIER_TABORT_IE_Msk (0x1ul << DMA_CRC_DMAIER_TABORT_IE_Pos)
2313 #define DMA_CRC_DMAIER_BLKD_IE_Pos (1)
2314 #define DMA_CRC_DMAIER_BLKD_IE_Msk (0x1ul << DMA_CRC_DMAIER_BLKD_IE_Pos)
2316 #define DMA_CRC_DMAISR_TABORT_IF_Pos (0)
2317 #define DMA_CRC_DMAISR_TABORT_IF_Msk (0x1ul << DMA_CRC_DMAISR_TABORT_IF_Pos)
2319 #define DMA_CRC_DMAISR_BLKD_IF_Pos (1)
2320 #define DMA_CRC_DMAISR_BLKD_IF_Msk (0x1ul << DMA_CRC_DMAISR_BLKD_IF_Pos)
2322 #define DMA_CRC_WDATA_CRC_WDATA_Pos (0)
2323 #define DMA_CRC_WDATA_CRC_WDATA_Msk (0xfffffffful << DMA_CRC_WDATA_CRC_WDATA_Pos)
2325 #define DMA_CRC_SEED_CRC_SEED_Pos (0)
2326 #define DMA_CRC_SEED_CRC_SEED_Msk (0xfffffffful << DMA_CRC_SEED_CRC_SEED_Pos)
2328 #define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos (0)
2329 #define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos) /* DMA_CRC_CONST */
2332
2333
2339 #define DMA_GCR_GCRCSR_CLK1_EN_Pos (9)
2340 #define DMA_GCR_GCRCSR_CLK1_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK1_EN_Pos)
2342 #define DMA_GCR_GCRCSR_CLK2_EN_Pos (10)
2343 #define DMA_GCR_GCRCSR_CLK2_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK2_EN_Pos)
2345 #define DMA_GCR_GCRCSR_CLK3_EN_Pos (11)
2346 #define DMA_GCR_GCRCSR_CLK3_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK3_EN_Pos)
2348 #define DMA_GCR_GCRCSR_CLK4_EN_Pos (12)
2349 #define DMA_GCR_GCRCSR_CLK4_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK4_EN_Pos)
2351 #define DMA_GCR_GCRCSR_CRC_CLK_EN_Pos (24)
2352 #define DMA_GCR_GCRCSR_CRC_CLK_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CRC_CLK_EN_Pos)
2354 #define DMA_GCR_DSSR0_CH1_SEL_Pos (8)
2355 #define DMA_GCR_DSSR0_CH1_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH1_SEL_Pos)
2357 #define DMA_GCR_DSSR0_CH2_SEL_Pos (16)
2358 #define DMA_GCR_DSSR0_CH2_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH2_SEL_Pos)
2360 #define DMA_GCR_DSSR0_CH3_SEL_Pos (24)
2361 #define DMA_GCR_DSSR0_CH3_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH3_SEL_Pos)
2363 #define DMA_GCR_DSSR1_CH4_SEL_Pos (0)
2364 #define DMA_GCR_DSSR1_CH4_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH4_SEL_Pos)
2366 #define DMA_GCR_GCRISR_INTR1_Pos (1)
2367 #define DMA_GCR_GCRISR_INTR1_Msk (0x1ul << DMA_GCR_GCRISR_INTR1_Pos)
2369 #define DMA_GCR_GCRISR_INTR2_Pos (2)
2370 #define DMA_GCR_GCRISR_INTR2_Msk (0x1ul << DMA_GCR_GCRISR_INTR2_Pos)
2372 #define DMA_GCR_GCRISR_INTR3_Pos (3)
2373 #define DMA_GCR_GCRISR_INTR3_Msk (0x1ul << DMA_GCR_GCRISR_INTR3_Pos)
2375 #define DMA_GCR_GCRISR_INTR4_Pos (4)
2376 #define DMA_GCR_GCRISR_INTR4_Msk (0x1ul << DMA_GCR_GCRISR_INTR4_Pos)
2378 #define DMA_GCR_GCRISR_INTRCRC_Pos (16)
2379 #define DMA_GCR_GCRISR_INTRCRC_Msk (0x1ul << DMA_GCR_GCRISR_INTRCRC_Pos) /* DMA_GCR_CONST */
2382
2388 #define PDMA_CSR_PDMACEN_Pos (0)
2389 #define PDMA_CSR_PDMACEN_Msk (0x1ul << PDMA_CSR_PDMACEN_Pos)
2391 #define PDMA_CSR_SW_RST_Pos (1)
2392 #define PDMA_CSR_SW_RST_Msk (0x1ul << PDMA_CSR_SW_RST_Pos)
2394 #define PDMA_CSR_MODE_SEL_Pos (2)
2395 #define PDMA_CSR_MODE_SEL_Msk (0x3ul << PDMA_CSR_MODE_SEL_Pos)
2397 #define PDMA_CSR_SAD_SEL_Pos (4)
2398 #define PDMA_CSR_SAD_SEL_Msk (0x3ul << PDMA_CSR_SAD_SEL_Pos)
2400 #define PDMA_CSR_DAD_SEL_Pos (6)
2401 #define PDMA_CSR_DAD_SEL_Msk (0x3ul << PDMA_CSR_DAD_SEL_Pos)
2403 #define PDMA_CSR_TO_EN_Pos (12)
2404 #define PDMA_CSR_TO_EN_Msk (0x1ul << PDMA_CSR_TO_EN_Pos)
2406 #define PDMA_CSR_APB_TWS_Pos (19)
2407 #define PDMA_CSR_APB_TWS_Msk (0x3ul << PDMA_CSR_APB_TWS_Pos)
2409 #define PDMA_CSR_TRIG_EN_Pos (23)
2410 #define PDMA_CSR_TRIG_EN_Msk (0x1ul << PDMA_CSR_TRIG_EN_Pos)
2412 #define PDMA_SAR_PDMA_SAR_Pos (0)
2413 #define PDMA_SAR_PDMA_SAR_Msk (0xfffffffful << PDMA_SAR_PDMA_SAR_Pos)
2415 #define PDMA_DAR_PDMA_DAR_Pos (0)
2416 #define PDMA_DAR_PDMA_DAR_Msk (0xfffffffful << PDMA_DAR_PDMA_DAR_Pos)
2418 #define PDMA_BCR_PDMA_BCR_Pos (0)
2419 #define PDMA_BCR_PDMA_BCR_Msk (0xfffful << PDMA_BCR_PDMA_BCR_Pos)
2421 #define PDMA_CSAR_PDMA_CSAR_Pos (0)
2422 #define PDMA_CSAR_PDMA_CSAR_Msk (0xfffffffful << PDMA_CSAR_PDMA_CSAR_Pos)
2424 #define PDMA_CDAR_PDMA_CDAR_Pos (0)
2425 #define PDMA_CDAR_PDMA_CDAR_Msk (0xfffffffful << PDMA_CDAR_PDMA_CDAR_Pos)
2427 #define PDMA_CBCR_PDMA_CBCR_Pos (0)
2428 #define PDMA_CBCR_PDMA_CBCR_Msk (0xfffffful << PDMA_CBCR_PDMA_CBCR_Pos)
2430 #define PDMA_IER_TABORT_IE_Pos (0)
2431 #define PDMA_IER_TABORT_IE_Msk (0x1ul << PDMA_IER_TABORT_IE_Pos)
2433 #define PDMA_IER_TD_IE_Pos (1)
2434 #define PDMA_IER_TD_IE_Msk (0x1ul << PDMA_IER_TD_IE_Pos)
2436 #define PDMA_IER_WRA_BCR_IE_Pos (2)
2437 #define PDMA_IER_WRA_BCR_IE_Msk (0xful << PDMA_IER_WRA_BCR_IE_Pos)
2439 #define PDMA_IER_TO_IE_Pos (6)
2440 #define PDMA_IER_TO_IE_Msk (0x1ul << PDMA_IER_TO_IE_Pos)
2442 #define PDMA_ISR_TABORT_IS_Pos (0)
2443 #define PDMA_ISR_TABORT_IS_Msk (0x1ul << PDMA_ISR_TABORT_IS_Pos)
2445 #define PDMA_ISR_TD_IS_Pos (1)
2446 #define PDMA_ISR_TD_IS_Msk (0x1ul << PDMA_ISR_TD_IS_Pos)
2448 #define PDMA_ISR_WRA_BCR_IS_Pos (2)
2449 #define PDMA_ISR_WRA_BCR_IS_Msk (0xful << PDMA_ISR_WRA_BCR_IS_Pos)
2451 #define PDMA_ISR_TO_IS_Pos (6)
2452 #define PDMA_ISR_TO_IS_Msk (0x1ul << PDMA_ISR_TO_IS_Pos)
2454 #define PDMA_TCR_PDMA_TCR_Pos (0)
2455 #define PDMA_TCR_PDMA_TCR_Msk (0xfffful << PDMA_TCR_PDMA_TCR_Pos) /* PDMA_CONST */
2458 /* end of DMA_GCR register group */
2460
2461
2462 /*---------------------- Flash Memory Controller -------------------------*/
2468 typedef struct
2469 {
2470
2471
2506 __IO uint32_t ISPCON;
2507
2519 __IO uint32_t ISPADR;
2520
2532 __IO uint32_t ISPDAT;
2533
2553 __IO uint32_t ISPCMD;
2554
2567 __IO uint32_t ISPTRG;
2568
2581 __I uint32_t DFBADR;
2582 uint32_t RESERVE0[10];
2583
2584
2607 __I uint32_t ISPSTA;
2608
2609 } FMC_T;
2610
2616 #define FMC_ISPCON_ISPEN_Pos (0)
2617 #define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos)
2619 #define FMC_ISPCON_BS_Pos (1)
2620 #define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos)
2622 #define FMC_ISPCON_APUEN_Pos (3)
2623 #define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos)
2625 #define FMC_ISPCON_CFGUEN_Pos (4)
2626 #define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos)
2628 #define FMC_ISPCON_LDUEN_Pos (5)
2629 #define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos)
2631 #define FMC_ISPCON_ISPFF_Pos (6)
2632 #define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos)
2634 #define FMC_ISPADR_ISPADR_Pos (0)
2635 #define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos)
2637 #define FMC_ISPDAT_ISPDAT_Pos (0)
2638 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
2640 #define FMC_ISPCMD_FCTRL_Pos (0)
2641 #define FMC_ISPCMD_FCTRL_Msk (0xful << FMC_ISPCMD_FCTRL_Pos)
2643 #define FMC_ISPCMD_FCEN_Pos (4)
2644 #define FMC_ISPCMD_FCEN_Msk (0x1ul << FMC_ISPCMD_FCEN_Pos)
2646 #define FMC_ISPCMD_FOEN_Pos (5)
2647 #define FMC_ISPCMD_FOEN_Msk (0x1ul << FMC_ISPCMD_FOEN_Pos)
2649 #define FMC_ISPTRG_ISPGO_Pos (0)
2650 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
2652 #define FMC_DFBADR_DFBADR_Pos (0)
2653 #define FMC_DFBADR_DFBADR_Msk (0xfffffffful << FMC_DFBADR_DFBADR_Pos)
2655 #define FMC_ISPSTA_ISPBUSY_Pos (0)
2656 #define FMC_ISPSTA_ISPBUSY_Msk (0x1ul << FMC_ISPSTA_ISPBUSY_Pos)
2658 #define FMC_ISPSTA_CBS_Pos (1)
2659 #define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos)
2661 #define FMC_ISPSTA_PGFF_Pos (5)
2662 #define FMC_ISPSTA_PGFF_Msk (0x1ul << FMC_ISPSTA_PGFF_Pos)
2664 #define FMC_ISPSTA_ISPFF_Pos (6)
2665 #define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos) /* FMC_CONST */
2668 /* end of FMC register group */
2669
2670
2671 /*---------------------- System Global Control Registers -------------------------*/
2677 typedef struct
2678 {
2679
2680
2692 __I uint32_t PDID;
2693
2726 __IO uint32_t RST_SRC;
2727
2758 __IO uint32_t IPRST_CTL1;
2759
2819 __IO uint32_t IPRST_CTL2;
2820
2821 uint32_t RESERVE0[4];
2833 __IO uint32_t TEMPCTL;
2834 uint32_t RESERVE1[3];
2835
2836
2891 __IO uint32_t PA_L_MFP;
2892
2941 __IO uint32_t PA_H_MFP;
2942
2996 __IO uint32_t PB_L_MFP;
2997
3050 __IO uint32_t PB_H_MFP;
3051
3101 __IO uint32_t PC_L_MFP;
3102
3145 __IO uint32_t PC_H_MFP;
3146
3181 __IO uint32_t PD_L_MFP;
3182
3227 __IO uint32_t PD_H_MFP;
3228
3261 __IO uint32_t PE_L_MFP;
3262
3279 __IO uint32_t PE_H_MFP;
3280
3322 __IO uint32_t PF_L_MFP;
3323 uint32_t RESERVE2[1];
3324
3325
3338 __IO uint32_t PORCTL;
3339
3406 __IO uint32_t BODCTL;
3407
3453 __IO uint32_t BODSTS;
3454
3488 __IO uint32_t Int_VREFCTL;
3489
3509 __IO uint32_t LDO_CTL;
3510 uint32_t RESERVE3[3];
3511
3512
3549 __IO uint32_t IRCTRIMCTL;
3550
3569 __IO uint32_t IRCTRIMIEN;
3570
3596 __IO uint32_t IRCTRIMINT;
3597 uint32_t RESERVE4[29];
3598
3599
3611 __IO uint32_t RegLockAddr;
3612
3613 } SYS_T;
3614
3620 #define SYS_PDID_PDID_Pos (0)
3621 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
3623 #define SYS_RST_SRC_RSTS_POR_Pos (0)
3624 #define SYS_RST_SRC_RSTS_POR_Msk (0x1ul << SYS_RST_SRC_RSTS_POR_Pos)
3626 #define SYS_RST_SRC_RSTS_PAD_Pos (1)
3627 #define SYS_RST_SRC_RSTS_PAD_Msk (0x1ul << SYS_RST_SRC_RSTS_PAD_Pos)
3629 #define SYS_RST_SRC_RSTS_WDT_Pos (2)
3630 #define SYS_RST_SRC_RSTS_WDT_Msk (0x1ul << SYS_RST_SRC_RSTS_WDT_Pos)
3632 #define SYS_RST_SRC_RSTS_BOD_Pos (4)
3633 #define SYS_RST_SRC_RSTS_BOD_Msk (0x1ul << SYS_RST_SRC_RSTS_BOD_Pos)
3635 #define SYS_RST_SRC_RSTS_SYS_Pos (5)
3636 #define SYS_RST_SRC_RSTS_SYS_Msk (0x1ul << SYS_RST_SRC_RSTS_SYS_Pos)
3638 #define SYS_RST_SRC_RSTS_CPU_Pos (7)
3639 #define SYS_RST_SRC_RSTS_CPU_Msk (0x1ul << SYS_RST_SRC_RSTS_CPU_Pos)
3641 #define SYS_IPRST_CTL1_CHIP_RST_Pos (0)
3642 #define SYS_IPRST_CTL1_CHIP_RST_Msk (0x1ul << SYS_IPRST_CTL1_CHIP_RST_Pos)
3644 #define SYS_IPRST_CTL1_CPU_RST_Pos (1)
3645 #define SYS_IPRST_CTL1_CPU_RST_Msk (0x1ul << SYS_IPRST_CTL1_CPU_RST_Pos)
3647 #define SYS_IPRST_CTL1_DMA_RST_Pos (2)
3648 #define SYS_IPRST_CTL1_DMA_RST_Msk (0x1ul << SYS_IPRST_CTL1_DMA_RST_Pos)
3650 #define SYS_IPRST_CTL2_GPIO_RST_Pos (1)
3651 #define SYS_IPRST_CTL2_GPIO_RST_Msk (0x1ul << SYS_IPRST_CTL2_GPIO_RST_Pos)
3653 #define SYS_IPRST_CTL2_TMR0_RST_Pos (2)
3654 #define SYS_IPRST_CTL2_TMR0_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR0_RST_Pos)
3656 #define SYS_IPRST_CTL2_TMR1_RST_Pos (3)
3657 #define SYS_IPRST_CTL2_TMR1_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR1_RST_Pos)
3659 #define SYS_IPRST_CTL2_TMR2_RST_Pos (4)
3660 #define SYS_IPRST_CTL2_TMR2_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR2_RST_Pos)
3662 #define SYS_IPRST_CTL2_TMR3_RST_Pos (5)
3663 #define SYS_IPRST_CTL2_TMR3_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR3_RST_Pos)
3665 #define SYS_IPRST_CTL2_I2C0_RST_Pos (8)
3666 #define SYS_IPRST_CTL2_I2C0_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C0_RST_Pos)
3668 #define SYS_IPRST_CTL2_I2C1_RST_Pos (9)
3669 #define SYS_IPRST_CTL2_I2C1_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C1_RST_Pos)
3671 #define SYS_IPRST_CTL2_SPI0_RST_Pos (12)
3672 #define SYS_IPRST_CTL2_SPI0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI0_RST_Pos)
3674 #define SYS_IPRST_CTL2_SPI1_RST_Pos (13)
3675 #define SYS_IPRST_CTL2_SPI1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI1_RST_Pos)
3677 #define SYS_IPRST_CTL2_UART0_RST_Pos (16)
3678 #define SYS_IPRST_CTL2_UART0_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART0_RST_Pos)
3680 #define SYS_IPRST_CTL2_UART1_RST_Pos (17)
3681 #define SYS_IPRST_CTL2_UART1_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART1_RST_Pos)
3683 #define SYS_IPRST_CTL2_PWM0_RST_Pos (20)
3684 #define SYS_IPRST_CTL2_PWM0_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM0_RST_Pos)
3686 #define SYS_IPRST_CTL2_ACMP01_RST_Pos (22)
3687 #define SYS_IPRST_CTL2_ACMP01_RST_Msk (0x1ul << SYS_IPRST_CTL2_ACMP01_RST_Pos)
3689 #define SYS_IPRST_CTL2_LCD_RST_Pos (26)
3690 #define SYS_IPRST_CTL2_LCD_RST_Msk (0x1ul << SYS_IPRST_CTL2_LCD_RST_Pos)
3692 #define SYS_IPRST_CTL2_ADC_RST_Pos (28)
3693 #define SYS_IPRST_CTL2_ADC_RST_Msk (0x1ul << SYS_IPRST_CTL2_ADC_RST_Pos)
3695 #define SYS_IPRST_CTL2_SC0_RST_Pos (30)
3696 #define SYS_IPRST_CTL2_SC0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC0_RST_Pos)
3698 #define SYS_IPRST_CTL2_SC1_RST_Pos (31)
3699 #define SYS_IPRST_CTL2_SC1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC1_RST_Pos)
3701 #define SYS_TEMPCTL_VTEMP_EN_Pos (0)
3702 #define SYS_TEMPCTL_VTEMP_EN_Msk (0x1ul << SYS_TEMPCTL_VTEMP_EN_Pos)
3704 #define SYS_PA_L_MFP_PA0_MFP_Pos (0)
3705 #define SYS_PA_L_MFP_PA0_MFP_Msk (0xful << SYS_PA_L_MFP_PA0_MFP_Pos)
3707 #define SYS_PA_L_MFP_PA1_MFP_Pos (4)
3708 #define SYS_PA_L_MFP_PA1_MFP_Msk (0xful << SYS_PA_L_MFP_PA1_MFP_Pos)
3710 #define SYS_PA_L_MFP_PA2_MFP_Pos (8)
3711 #define SYS_PA_L_MFP_PA2_MFP_Msk (0xful << SYS_PA_L_MFP_PA2_MFP_Pos)
3713 #define SYS_PA_L_MFP_PA3_MFP_Pos (12)
3714 #define SYS_PA_L_MFP_PA3_MFP_Msk (0xful << SYS_PA_L_MFP_PA3_MFP_Pos)
3716 #define SYS_PA_L_MFP_PA4_MFP_Pos (16)
3717 #define SYS_PA_L_MFP_PA4_MFP_Msk (0xful << SYS_PA_L_MFP_PA4_MFP_Pos)
3719 #define SYS_PA_L_MFP_PA5_MFP_Pos (20)
3720 #define SYS_PA_L_MFP_PA5_MFP_Msk (0xful << SYS_PA_L_MFP_PA5_MFP_Pos)
3722 #define SYS_PA_L_MFP_PA6_MFP_Pos (24)
3723 #define SYS_PA_L_MFP_PA6_MFP_Msk (0xful << SYS_PA_L_MFP_PA6_MFP_Pos)
3725 #define SYS_PA_L_MFP_PA7_MFP_Pos (28)
3726 #define SYS_PA_L_MFP_PA7_MFP_Msk (0xful << SYS_PA_L_MFP_PA7_MFP_Pos)
3728 #define SYS_PA_H_MFP_PA8_MFP_Pos (0)
3729 #define SYS_PA_H_MFP_PA8_MFP_Msk (0xful << SYS_PA_H_MFP_PA8_MFP_Pos)
3731 #define SYS_PA_H_MFP_PA9_MFP_Pos (4)
3732 #define SYS_PA_H_MFP_PA9_MFP_Msk (0xful << SYS_PA_H_MFP_PA9_MFP_Pos)
3734 #define SYS_PA_H_MFP_PA10_MFP_Pos (8)
3735 #define SYS_PA_H_MFP_PA10_MFP_Msk (0xful << SYS_PA_H_MFP_PA10_MFP_Pos)
3737 #define SYS_PA_H_MFP_PA11_MFP_Pos (12)
3738 #define SYS_PA_H_MFP_PA11_MFP_Msk (0xful << SYS_PA_H_MFP_PA11_MFP_Pos)
3740 #define SYS_PA_H_MFP_PA12_MFP_Pos (16)
3741 #define SYS_PA_H_MFP_PA12_MFP_Msk (0xful << SYS_PA_H_MFP_PA12_MFP_Pos)
3743 #define SYS_PA_H_MFP_PA13_MFP_Pos (20)
3744 #define SYS_PA_H_MFP_PA13_MFP_Msk (0xful << SYS_PA_H_MFP_PA13_MFP_Pos)
3746 #define SYS_PA_H_MFP_PA14_MFP_Pos (24)
3747 #define SYS_PA_H_MFP_PA14_MFP_Msk (0xful << SYS_PA_H_MFP_PA14_MFP_Pos)
3749 #define SYS_PA_H_MFP_PA15_MFP_Pos (28)
3750 #define SYS_PA_H_MFP_PA15_MFP_Msk (0xful << SYS_PA_H_MFP_PA15_MFP_Pos)
3752 #define SYS_PB_L_MFP_PB0_MFP_Pos (0)
3753 #define SYS_PB_L_MFP_PB0_MFP_Msk (0xful << SYS_PB_L_MFP_PB0_MFP_Pos)
3755 #define SYS_PB_L_MFP_PB1_MFP_Pos (4)
3756 #define SYS_PB_L_MFP_PB1_MFP_Msk (0xful << SYS_PB_L_MFP_PB1_MFP_Pos)
3758 #define SYS_PB_L_MFP_PB2_MFP_Pos (8)
3759 #define SYS_PB_L_MFP_PB2_MFP_Msk (0xful << SYS_PB_L_MFP_PB2_MFP_Pos)
3761 #define SYS_PB_L_MFP_PB3_MFP_Pos (12)
3762 #define SYS_PB_L_MFP_PB3_MFP_Msk (0xful << SYS_PB_L_MFP_PB3_MFP_Pos)
3764 #define SYS_PB_L_MFP_PB4_MFP_Pos (16)
3765 #define SYS_PB_L_MFP_PB4_MFP_Msk (0xful << SYS_PB_L_MFP_PB4_MFP_Pos)
3767 #define SYS_PB_L_MFP_PB5_MFP_Pos (20)
3768 #define SYS_PB_L_MFP_PB5_MFP_Msk (0xful << SYS_PB_L_MFP_PB5_MFP_Pos)
3770 #define SYS_PB_L_MFP_PB6_MFP_Pos (24)
3771 #define SYS_PB_L_MFP_PB6_MFP_Msk (0xful << SYS_PB_L_MFP_PB6_MFP_Pos)
3773 #define SYS_PB_L_MFP_PB7_MFP_Pos (28)
3774 #define SYS_PB_L_MFP_PB7_MFP_Msk (0xful << SYS_PB_L_MFP_PB7_MFP_Pos)
3776 #define SYS_PB_H_MFP_PB8_MFP_Pos (0)
3777 #define SYS_PB_H_MFP_PB8_MFP_Msk (0xful << SYS_PB_H_MFP_PB8_MFP_Pos)
3779 #define SYS_PB_H_MFP_PB9_MFP_Pos (4)
3780 #define SYS_PB_H_MFP_PB9_MFP_Msk (0xful << SYS_PB_H_MFP_PB9_MFP_Pos)
3782 #define SYS_PB_H_MFP_PB10_MFP_Pos (8)
3783 #define SYS_PB_H_MFP_PB10_MFP_Msk (0xful << SYS_PB_H_MFP_PB10_MFP_Pos)
3785 #define SYS_PB_H_MFP_PB11_MFP_Pos (12)
3786 #define SYS_PB_H_MFP_PB11_MFP_Msk (0xful << SYS_PB_H_MFP_PB11_MFP_Pos)
3788 #define SYS_PB_H_MFP_PB12_MFP_Pos (16)
3789 #define SYS_PB_H_MFP_PB12_MFP_Msk (0xful << SYS_PB_H_MFP_PB12_MFP_Pos)
3791 #define SYS_PB_H_MFP_PB13_MFP_Pos (20)
3792 #define SYS_PB_H_MFP_PB13_MFP_Msk (0xful << SYS_PB_H_MFP_PB13_MFP_Pos)
3794 #define SYS_PB_H_MFP_PB14_MFP_Pos (24)
3795 #define SYS_PB_H_MFP_PB14_MFP_Msk (0xful << SYS_PB_H_MFP_PB14_MFP_Pos)
3797 #define SYS_PB_H_MFP_PB15_MFP_Pos (28)
3798 #define SYS_PB_H_MFP_PB15_MFP_Msk (0xful << SYS_PB_H_MFP_PB15_MFP_Pos)
3800 #define SYS_PC_L_MFP_PC0_MFP_Pos (0)
3801 #define SYS_PC_L_MFP_PC0_MFP_Msk (0xful << SYS_PC_L_MFP_PC0_MFP_Pos)
3803 #define SYS_PC_L_MFP_PC1_MFP_Pos (4)
3804 #define SYS_PC_L_MFP_PC1_MFP_Msk (0xful << SYS_PC_L_MFP_PC1_MFP_Pos)
3806 #define SYS_PC_L_MFP_PC2_MFP_Pos (8)
3807 #define SYS_PC_L_MFP_PC2_MFP_Msk (0xful << SYS_PC_L_MFP_PC2_MFP_Pos)
3809 #define SYS_PC_L_MFP_PC3_MFP_Pos (12)
3810 #define SYS_PC_L_MFP_PC3_MFP_Msk (0xful << SYS_PC_L_MFP_PC3_MFP_Pos)
3812 #define SYS_PC_L_MFP_PC4_MFP_Pos (16)
3813 #define SYS_PC_L_MFP_PC4_MFP_Msk (0xful << SYS_PC_L_MFP_PC4_MFP_Pos)
3815 #define SYS_PC_L_MFP_PC5_MFP_Pos (20)
3816 #define SYS_PC_L_MFP_PC5_MFP_Msk (0xful << SYS_PC_L_MFP_PC5_MFP_Pos)
3818 #define SYS_PC_L_MFP_PC6_MFP_Pos (24)
3819 #define SYS_PC_L_MFP_PC6_MFP_Msk (0xful << SYS_PC_L_MFP_PC6_MFP_Pos)
3821 #define SYS_PC_L_MFP_PC7_MFP_Pos (28)
3822 #define SYS_PC_L_MFP_PC7_MFP_Msk (0xful << SYS_PC_L_MFP_PC7_MFP_Pos)
3824 #define SYS_PC_H_MFP_PC8_MFP_Pos (0)
3825 #define SYS_PC_H_MFP_PC8_MFP_Msk (0xful << SYS_PC_H_MFP_PC8_MFP_Pos)
3827 #define SYS_PC_H_MFP_PC9_MFP_Pos (4)
3828 #define SYS_PC_H_MFP_PC9_MFP_Msk (0xful << SYS_PC_H_MFP_PC9_MFP_Pos)
3830 #define SYS_PC_H_MFP_PC10_MFP_Pos (8)
3831 #define SYS_PC_H_MFP_PC10_MFP_Msk (0xful << SYS_PC_H_MFP_PC10_MFP_Pos)
3833 #define SYS_PC_H_MFP_PC11_MFP_Pos (12)
3834 #define SYS_PC_H_MFP_PC11_MFP_Msk (0xful << SYS_PC_H_MFP_PC11_MFP_Pos)
3836 #define SYS_PC_H_MFP_PC12_MFP_Pos (16)
3837 #define SYS_PC_H_MFP_PC12_MFP_Msk (0xful << SYS_PC_H_MFP_PC12_MFP_Pos)
3839 #define SYS_PC_H_MFP_PC13_MFP_Pos (20)
3840 #define SYS_PC_H_MFP_PC13_MFP_Msk (0xful << SYS_PC_H_MFP_PC13_MFP_Pos)
3842 #define SYS_PC_H_MFP_PC14_MFP_Pos (24)
3843 #define SYS_PC_H_MFP_PC14_MFP_Msk (0xful << SYS_PC_H_MFP_PC14_MFP_Pos)
3845 #define SYS_PC_H_MFP_PC15_MFP_Pos (28)
3846 #define SYS_PC_H_MFP_PC15_MFP_Msk (0xful << SYS_PC_H_MFP_PC15_MFP_Pos)
3848 #define SYS_PD_L_MFP_PD0_MFP_Pos (0)
3849 #define SYS_PD_L_MFP_PD0_MFP_Msk (0xful << SYS_PD_L_MFP_PD0_MFP_Pos)
3851 #define SYS_PD_L_MFP_PD1_MFP_Pos (4)
3852 #define SYS_PD_L_MFP_PD1_MFP_Msk (0xful << SYS_PD_L_MFP_PD1_MFP_Pos)
3854 #define SYS_PD_L_MFP_PD2_MFP_Pos (8)
3855 #define SYS_PD_L_MFP_PD2_MFP_Msk (0xful << SYS_PD_L_MFP_PD2_MFP_Pos)
3857 #define SYS_PD_L_MFP_PD3_MFP_Pos (12)
3858 #define SYS_PD_L_MFP_PD3_MFP_Msk (0xful << SYS_PD_L_MFP_PD3_MFP_Pos)
3860 #define SYS_PD_L_MFP_PD4_MFP_Pos (16)
3861 #define SYS_PD_L_MFP_PD4_MFP_Msk (0xful << SYS_PD_L_MFP_PD4_MFP_Pos)
3863 #define SYS_PD_L_MFP_PD5_MFP_Pos (20)
3864 #define SYS_PD_L_MFP_PD5_MFP_Msk (0xful << SYS_PD_L_MFP_PD5_MFP_Pos)
3866 #define SYS_PD_L_MFP_PD6_MFP_Pos (24)
3867 #define SYS_PD_L_MFP_PD6_MFP_Msk (0xful << SYS_PD_L_MFP_PD6_MFP_Pos)
3869 #define SYS_PD_L_MFP_PD7_MFP_Pos (28)
3870 #define SYS_PD_L_MFP_PD7_MFP_Msk (0xful << SYS_PD_L_MFP_PD7_MFP_Pos)
3872 #define SYS_PD_H_MFP_PD8_MFP_Pos (0)
3873 #define SYS_PD_H_MFP_PD8_MFP_Msk (0xful << SYS_PD_H_MFP_PD8_MFP_Pos)
3875 #define SYS_PD_H_MFP_PD9_MFP_Pos (4)
3876 #define SYS_PD_H_MFP_PD9_MFP_Msk (0xful << SYS_PD_H_MFP_PD9_MFP_Pos)
3878 #define SYS_PD_H_MFP_PD10_MFP_Pos (8)
3879 #define SYS_PD_H_MFP_PD10_MFP_Msk (0xful << SYS_PD_H_MFP_PD10_MFP_Pos)
3881 #define SYS_PD_H_MFP_PD11_MFP_Pos (12)
3882 #define SYS_PD_H_MFP_PD11_MFP_Msk (0xful << SYS_PD_H_MFP_PD11_MFP_Pos)
3884 #define SYS_PD_H_MFP_PD12_MFP_Pos (16)
3885 #define SYS_PD_H_MFP_PD12_MFP_Msk (0xful << SYS_PD_H_MFP_PD12_MFP_Pos)
3887 #define SYS_PD_H_MFP_PD13_MFP_Pos (20)
3888 #define SYS_PD_H_MFP_PD13_MFP_Msk (0xful << SYS_PD_H_MFP_PD13_MFP_Pos)
3890 #define SYS_PD_H_MFP_PD14_MFP_Pos (24)
3891 #define SYS_PD_H_MFP_PD14_MFP_Msk (0xful << SYS_PD_H_MFP_PD14_MFP_Pos)
3893 #define SYS_PD_H_MFP_PD15_MFP_Pos (28)
3894 #define SYS_PD_H_MFP_PD15_MFP_Msk (0xful << SYS_PD_H_MFP_PD15_MFP_Pos)
3896 #define SYS_PE_L_MFP_PE0_MFP_Pos (0)
3897 #define SYS_PE_L_MFP_PE0_MFP_Msk (0xful << SYS_PE_L_MFP_PE0_MFP_Pos)
3899 #define SYS_PE_L_MFP_PE1_MFP_Pos (4)
3900 #define SYS_PE_L_MFP_PE1_MFP_Msk (0xful << SYS_PE_L_MFP_PE1_MFP_Pos)
3902 #define SYS_PE_L_MFP_PE2_MFP_Pos (8)
3903 #define SYS_PE_L_MFP_PE2_MFP_Msk (0xful << SYS_PE_L_MFP_PE2_MFP_Pos)
3905 #define SYS_PE_L_MFP_PE3_MFP_Pos (12)
3906 #define SYS_PE_L_MFP_PE3_MFP_Msk (0xful << SYS_PE_L_MFP_PE3_MFP_Pos)
3908 #define SYS_PE_L_MFP_PE4_MFP_Pos (16)
3909 #define SYS_PE_L_MFP_PE4_MFP_Msk (0xful << SYS_PE_L_MFP_PE4_MFP_Pos)
3911 #define SYS_PE_L_MFP_PE5_MFP_Pos (20)
3912 #define SYS_PE_L_MFP_PE5_MFP_Msk (0xful << SYS_PE_L_MFP_PE5_MFP_Pos)
3914 #define SYS_PE_L_MFP_PE6_MFP_Pos (24)
3915 #define SYS_PE_L_MFP_PE6_MFP_Msk (0xful << SYS_PE_L_MFP_PE6_MFP_Pos)
3917 #define SYS_PE_L_MFP_PE7_MFP_Pos (28)
3918 #define SYS_PE_L_MFP_PE7_MFP_Msk (0xful << SYS_PE_L_MFP_PE7_MFP_Pos)
3920 #define SYS_PE_H_MFP_PE8_MFP_Pos (0)
3921 #define SYS_PE_H_MFP_PE8_MFP_Msk (0xful << SYS_PE_H_MFP_PE8_MFP_Pos)
3923 #define SYS_PE_H_MFP_PE9_MFP_Pos (4)
3924 #define SYS_PE_H_MFP_PE9_MFP_Msk (0xful << SYS_PE_H_MFP_PE9_MFP_Pos)
3926 #define SYS_PF_L_MFP_PF0_MFP_Pos (0)
3927 #define SYS_PF_L_MFP_PF0_MFP_Msk (0xful << SYS_PF_L_MFP_PF0_MFP_Pos)
3929 #define SYS_PF_L_MFP_PF1_MFP_Pos (4)
3930 #define SYS_PF_L_MFP_PF1_MFP_Msk (0xful << SYS_PF_L_MFP_PF1_MFP_Pos)
3932 #define SYS_PF_L_MFP_PF2_MFP_Pos (8)
3933 #define SYS_PF_L_MFP_PF2_MFP_Msk (0xful << SYS_PF_L_MFP_PF2_MFP_Pos)
3935 #define SYS_PF_L_MFP_PF3_MFP_Pos (12)
3936 #define SYS_PF_L_MFP_PF3_MFP_Msk (0xful << SYS_PF_L_MFP_PF3_MFP_Pos)
3938 #define SYS_PF_L_MFP_PF4_MFP_Pos (16)
3939 #define SYS_PF_L_MFP_PF4_MFP_Msk (0xful << SYS_PF_L_MFP_PF4_MFP_Pos)
3941 #define SYS_PF_L_MFP_PF5_MFP_Pos (20)
3942 #define SYS_PF_L_MFP_PF5_MFP_Msk (0xful << SYS_PF_L_MFP_PF5_MFP_Pos)
3944 #define SYS_PORCTL_POR_DIS_CODE_Pos (0)
3945 #define SYS_PORCTL_POR_DIS_CODE_Msk (0xfffful << SYS_PORCTL_POR_DIS_CODE_Pos)
3947 #define SYS_BODCTL_BOD17_EN_Pos (0)
3948 #define SYS_BODCTL_BOD17_EN_Msk (0x1ul << SYS_BODCTL_BOD17_EN_Pos)
3950 #define SYS_BODCTL_BOD20_EN_Pos (1)
3951 #define SYS_BODCTL_BOD20_EN_Msk (0x1ul << SYS_BODCTL_BOD20_EN_Pos)
3953 #define SYS_BODCTL_BOD25_EN_Pos (2)
3954 #define SYS_BODCTL_BOD25_EN_Msk (0x1ul << SYS_BODCTL_BOD25_EN_Pos)
3956 #define SYS_BODCTL_BOD17_RST_EN_Pos (4)
3957 #define SYS_BODCTL_BOD17_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD17_RST_EN_Pos)
3959 #define SYS_BODCTL_BOD20_RST_EN_Pos (5)
3960 #define SYS_BODCTL_BOD20_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD20_RST_EN_Pos)
3962 #define SYS_BODCTL_BOD25_RST_EN_Pos (6)
3963 #define SYS_BODCTL_BOD25_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD25_RST_EN_Pos)
3965 #define SYS_BODCTL_BOD17_INT_EN_Pos (8)
3966 #define SYS_BODCTL_BOD17_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD17_INT_EN_Pos)
3968 #define SYS_BODCTL_BOD20_INT_EN_Pos (9)
3969 #define SYS_BODCTL_BOD20_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD20_INT_EN_Pos)
3971 #define SYS_BODCTL_BOD25_INT_EN_Pos (10)
3972 #define SYS_BODCTL_BOD25_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD25_INT_EN_Pos)
3974 #define SYS_BODCTL_BOD17_TRIM_Pos (12)
3975 #define SYS_BODCTL_BOD17_TRIM_Msk (0xful << SYS_BODCTL_BOD17_TRIM_Pos)
3977 #define SYS_BODCTL_BOD20_TRIM_Pos (16)
3978 #define SYS_BODCTL_BOD20_TRIM_Msk (0xful << SYS_BODCTL_BOD20_TRIM_Pos)
3980 #define SYS_BODCTL_BOD25_TRIM_Pos (20)
3981 #define SYS_BODCTL_BOD25_TRIM_Msk (0xful << SYS_BODCTL_BOD25_TRIM_Pos)
3983 #define SYS_BODSTS_BOD_INT_Pos (0)
3984 #define SYS_BODSTS_BOD_INT_Msk (0x1ul << SYS_BODSTS_BOD_INT_Pos)
3986 #define SYS_BODSTS_BOD17_drop_Pos (1)
3987 #define SYS_BODSTS_BOD17_drop_Msk (0x1ul << SYS_BODSTS_BOD17_drop_Pos)
3989 #define SYS_BODSTS_BOD20_drop_Pos (2)
3990 #define SYS_BODSTS_BOD20_drop_Msk (0x1ul << SYS_BODSTS_BOD20_drop_Pos)
3992 #define SYS_BODSTS_BOD25_drop_Pos (3)
3993 #define SYS_BODSTS_BOD25_drop_Msk (0x1ul << SYS_BODSTS_BOD25_drop_Pos)
3995 #define SYS_BODSTS_BOD17_rise_Pos (4)
3996 #define SYS_BODSTS_BOD17_rise_Msk (0x1ul << SYS_BODSTS_BOD17_rise_Pos)
3998 #define SYS_BODSTS_BOD20_rise_Pos (5)
3999 #define SYS_BODSTS_BOD20_rise_Msk (0x1ul << SYS_BODSTS_BOD20_rise_Pos)
4001 #define SYS_BODSTS_BOD25_rise_Pos (6)
4002 #define SYS_BODSTS_BOD25_rise_Msk (0x1ul << SYS_BODSTS_BOD25_rise_Pos)
4004 #define SYS_BODSTS_BOD17_Pos (8)
4005 #define SYS_BODSTS_BOD17_Msk (0x1ul << SYS_BODSTS_BOD17_Pos)
4007 #define SYS_BODSTS_BOD20_Pos (9)
4008 #define SYS_BODSTS_BOD20_Msk (0x1ul << SYS_BODSTS_BOD20_Pos)
4010 #define SYS_BODSTS_BOD25_Pos (10)
4011 #define SYS_BODSTS_BOD25_Msk (0x1ul << SYS_BODSTS_BOD25_Pos)
4013 #define SYS_VREFCTL_BGP_EN_Pos (0)
4014 #define SYS_VREFCTL_BGP_EN_Msk (0x1ul << SYS_VREFCTL_BGP_EN_Pos)
4016 #define SYS_VREFCTL_REG_EN_Pos (1)
4017 #define SYS_VREFCTL_REG_EN_Msk (0x1ul << SYS_VREFCTL_REG_EN_Pos)
4019 #define SYS_VREFCTL_SEL25_Pos (2)
4020 #define SYS_VREFCTL_SEL25_Msk (0x3ul << SYS_VREFCTL_SEL25_Pos)
4022 #define SYS_VREFCTL_EXT_MODE_Pos (4)
4023 #define SYS_VREFCTL_EXT_MODE_Msk (0x1ul << SYS_VREFCTL_EXT_MODE_Pos)
4025 #define SYS_VREFCTL_VREF_TRIM_Pos (8)
4026 #define SYS_VREFCTL_VREF_TRIM_Msk (0xful << SYS_VREFCTL_VREF_TRIM_Pos)
4028 #define SYS_CTL_LDO_PD_Pos (0)
4029 #define SYS_CTL_LDO_PD_Msk (0x1ul << SYS_CTL_LDO_PD_Pos)
4031 #define SYS_CTL_LDO_LEVEL_Pos (2)
4032 #define SYS_CTL_LDO_LEVEL_Msk (0x3ul << SYS_CTL_LDO_LEVEL_Pos)
4034 #define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0)
4035 #define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos)
4037 #define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4)
4038 #define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos)
4040 #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos (6)
4041 #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos)
4043 #define SYS_IRCTRIMCTL_ERR_STOP_Pos (8)
4044 #define SYS_IRCTRIMCTL_ERR_STOP_Msk (0x1ul << SYS_IRCTRIMCTL_ERR_STOP_Pos)
4046 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1)
4047 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos)
4049 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2)
4050 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos)
4052 #define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0)
4053 #define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos)
4055 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1)
4056 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos)
4058 #define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2)
4059 #define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos)
4061 #define SYS_RegLockAddr_RegUnLock_Pos (0)
4062 #define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) /* SYS_CONST */
4065 /* end of SYS register group */
4066
4067
4068 /*---------------------- General Purpose Input/Output Controller -------------------------*/
4074 typedef struct
4075 {
4076
4213 __IO uint32_t PMD;
4214
4228 __IO uint32_t OFFD;
4229
4243 __IO uint32_t DOUT;
4244
4262 __IO uint32_t DMASK;
4263
4275 __I uint32_t PIN;
4276
4294 __IO uint32_t DBEN;
4295
4315 __IO uint32_t IMD;
4316
4613 __IO uint32_t IER;
4614
4631 __IO uint32_t ISRC;
4632
4646 __IO uint32_t PUEN;
4647
4648 } GPIO_T;
4649
4650
4651 typedef struct
4652 {
4688 __IO uint32_t DBNCECON;
4689 } GP_DB_T;
4690
4691
4698 #define GP_PMD_PMD0_Pos (0)
4699 #define GP_PMD_PMD0_Msk (0x3ul << GP_PMD_PMD0_Pos)
4701 #define GP_PMD_PMD1_Pos (2)
4702 #define GP_PMD_PMD1_Msk (0x3ul << GP_PMD_PMD1_Pos)
4704 #define GP_PMD_PMD2_Pos (4)
4705 #define GP_PMD_PMD2_Msk (0x3ul << GP_PMD_PMD2_Pos)
4707 #define GP_PMD_PMD3_Pos (6)
4708 #define GP_PMD_PMD3_Msk (0x3ul << GP_PMD_PMD3_Pos)
4710 #define GP_PMD_PMD4_Pos (8)
4711 #define GP_PMD_PMD4_Msk (0x3ul << GP_PMD_PMD4_Pos)
4713 #define GP_PMD_PMD5_Pos (10)
4714 #define GP_PMD_PMD5_Msk (0x3ul << GP_PMD_PMD5_Pos)
4716 #define GP_PMD_PMD6_Pos (12)
4717 #define GP_PMD_PMD6_Msk (0x3ul << GP_PMD_PMD6_Pos)
4719 #define GP_PMD_PMD7_Pos (14)
4720 #define GP_PMD_PMD7_Msk (0x3ul << GP_PMD_PMD7_Pos)
4722 #define GP_PMD_PMD8_Pos (16)
4723 #define GP_PMD_PMD8_Msk (0x3ul << GP_PMD_PMD8_Pos)
4725 #define GP_PMD_PMD9_Pos (18)
4726 #define GP_PMD_PMD9_Msk (0x3ul << GP_PMD_PMD9_Pos)
4728 #define GP_PMD_PMD10_Pos (20)
4729 #define GP_PMD_PMD10_Msk (0x3ul << GP_PMD_PMD10_Pos)
4731 #define GP_PMD_PMD11_Pos (22)
4732 #define GP_PMD_PMD11_Msk (0x3ul << GP_PMD_PMD11_Pos)
4734 #define GP_PMD_PMD12_Pos (24)
4735 #define GP_PMD_PMD12_Msk (0x3ul << GP_PMD_PMD12_Pos)
4737 #define GP_PMD_PMD13_Pos (26)
4738 #define GP_PMD_PMD13_Msk (0x3ul << GP_PMD_PMD13_Pos)
4740 #define GP_PMD_PMD14_Pos (28)
4741 #define GP_PMD_PMD14_Msk (0x3ul << GP_PMD_PMD14_Pos)
4743 #define GP_PMD_PMD15_Pos (30)
4744 #define GP_PMD_PMD15_Msk (0x3ul << GP_PMD_PMD15_Pos)
4746 #define GP_OFFD_OFFD_Pos (16)
4747 #define GP_OFFD_OFFD_Msk (0xfffful << GP_OFFD_OFFD_Pos)
4749 #define GP_DOUT_DOUT_Pos (0)
4750 #define GP_DOUT_DOUT_Msk (0xfffful << GP_DOUT_DOUT_Pos)
4752 #define GP_DMASK_DMASK_Pos (0)
4753 #define GP_DMASK_DMASK_Msk (0xfffful << GP_DMASK_DMASK_Pos)
4755 #define GP_PIN_PIN_Pos (0)
4756 #define GP_PIN_PIN_Msk (0xfffful << GP_PIN_PIN_Pos)
4758 #define GP_DBEN_DBEN_Pos (0)
4759 #define GP_DBEN_DBEN_Msk (0xfffful << GP_DBEN_DBEN_Pos)
4761 #define GP_IMD_IMD_Pos (0)
4762 #define GP_IMD_IMD_Msk (0xfffful << GP_IMD_IMD_Pos)
4764 #define GP_IER_FIER0_Pos (0)
4765 #define GP_IER_FIER0_Msk (0x1ul << GP_IER_FIER0_Pos)
4767 #define GP_IER_FIER1_Pos (1)
4768 #define GP_IER_FIER1_Msk (0x1ul << GP_IER_FIER1_Pos)
4770 #define GP_IER_FIER2_Pos (2)
4771 #define GP_IER_FIER2_Msk (0x1ul << GP_IER_FIER2_Pos)
4773 #define GP_IER_FIER3_Pos (3)
4774 #define GP_IER_FIER3_Msk (0x1ul << GP_IER_FIER3_Pos)
4776 #define GP_IER_FIER4_Pos (4)
4777 #define GP_IER_FIER4_Msk (0x1ul << GP_IER_FIER4_Pos)
4779 #define GP_IER_FIER5_Pos (5)
4780 #define GP_IER_FIER5_Msk (0x1ul << GP_IER_FIER5_Pos)
4782 #define GP_IER_FIER6_Pos (6)
4783 #define GP_IER_FIER6_Msk (0x1ul << GP_IER_FIER6_Pos)
4785 #define GP_IER_FIER7_Pos (7)
4786 #define GP_IER_FIER7_Msk (0x1ul << GP_IER_FIER7_Pos)
4788 #define GP_IER_FIER8_Pos (8)
4789 #define GP_IER_FIER8_Msk (0x1ul << GP_IER_FIER8_Pos)
4791 #define GP_IER_FIER9_Pos (9)
4792 #define GP_IER_FIER9_Msk (0x1ul << GP_IER_FIER9_Pos)
4794 #define GP_IER_FIER10_Pos (10)
4795 #define GP_IER_FIER10_Msk (0x1ul << GP_IER_FIER10_Pos)
4797 #define GP_IER_FIER11_Pos (11)
4798 #define GP_IER_FIER11_Msk (0x1ul << GP_IER_FIER11_Pos)
4800 #define GP_IER_FIER12_Pos (12)
4801 #define GP_IER_FIER12_Msk (0x1ul << GP_IER_FIER12_Pos)
4803 #define GP_IER_FIER13_Pos (13)
4804 #define GP_IER_FIER13_Msk (0x1ul << GP_IER_FIER13_Pos)
4806 #define GP_IER_FIER14_Pos (14)
4807 #define GP_IER_FIER14_Msk (0x1ul << GP_IER_FIER14_Pos)
4809 #define GP_IER_FIER15_Pos (15)
4810 #define GP_IER_FIER15_Msk (0x1ul << GP_IER_FIER15_Pos)
4812 #define GP_IER_RIER0_Pos (16)
4813 #define GP_IER_RIER0_Msk (0x1ul << GP_IER_RIER0_Pos)
4815 #define GP_IER_RIER1_Pos (17)
4816 #define GP_IER_RIER1_Msk (0x1ul << GP_IER_RIER1_Pos)
4818 #define GP_IER_RIER2_Pos (18)
4819 #define GP_IER_RIER2_Msk (0x1ul << GP_IER_RIER2_Pos)
4821 #define GP_IER_RIER3_Pos (19)
4822 #define GP_IER_RIER3_Msk (0x1ul << GP_IER_RIER3_Pos)
4824 #define GP_IER_RIER4_Pos (20)
4825 #define GP_IER_RIER4_Msk (0x1ul << GP_IER_RIER4_Pos)
4827 #define GP_IER_RIER5_Pos (21)
4828 #define GP_IER_RIER5_Msk (0x1ul << GP_IER_RIER5_Pos)
4830 #define GP_IER_RIER6_Pos (22)
4831 #define GP_IER_RIER6_Msk (0x1ul << GP_IER_RIER6_Pos)
4833 #define GP_IER_RIER7_Pos (23)
4834 #define GP_IER_RIER7_Msk (0x1ul << GP_IER_RIER7_Pos)
4836 #define GP_IER_RIER8_Pos (24)
4837 #define GP_IER_RIER8_Msk (0x1ul << GP_IER_RIER8_Pos)
4839 #define GP_IER_RIER9_Pos (25)
4840 #define GP_IER_RIER9_Msk (0x1ul << GP_IER_RIER9_Pos)
4842 #define GP_IER_RIER10_Pos (26)
4843 #define GP_IER_RIER10_Msk (0x1ul << GP_IER_RIER10_Pos)
4845 #define GP_IER_RIER11_Pos (27)
4846 #define GP_IER_RIER11_Msk (0x1ul << GP_IER_RIER11_Pos)
4848 #define GP_IER_RIER12_Pos (28)
4849 #define GP_IER_RIER12_Msk (0x1ul << GP_IER_RIER12_Pos)
4851 #define GP_IER_RIER13_Pos (29)
4852 #define GP_IER_RIER13_Msk (0x1ul << GP_IER_RIER13_Pos)
4854 #define GP_IER_RIER14_Pos (30)
4855 #define GP_IER_RIER14_Msk (0x1ul << GP_IER_RIER14_Pos)
4857 #define GP_IER_RIER15_Pos (31)
4858 #define GP_IER_RIER15_Msk (0x1ul << GP_IER_RIER15_Pos)
4860 #define GP_ISRC_ISRC_Pos (0)
4861 #define GP_ISRC_ISRC_Msk (0xfffful << GP_ISRC_ISRC_Pos)
4863 #define GP_PUEN_PUEN_Pos (0)
4864 #define GP_PUEN_PUEN_Msk (0xfffful << GP_PUEN_PUEN_Pos) /* GPIO_CONST */
4866
4871 #define GP_DBNCECON_DBCLKSEL_Pos (0)
4872 #define GP_DBNCECON_DBCLKSEL_Msk (0xful << GP_DBNCECON_DBCLKSEL_Pos)
4874 #define GP_DBNCECON_DBCLKSRC_Pos (4)
4875 #define GP_DBNCECON_DBCLKSRC_Msk (0x1ul << GP_DBNCECON_DBCLKSRC_Pos)
4877 #define GP_DBNCECON_DBCLK_ON_Pos (5)
4878 #define GP_DBNCECON_DBCLK_ON_Msk (0x1ul << GP_DBNCECON_DBCLK_ON_Pos) /* GP_DB_CONST */
4881 /* end of GP register group */
4882
4883
4884 /*---------------------- Inter-IC Bus Controller -------------------------*/
4890 typedef struct
4891 {
4892
4893
4928 __IO uint32_t CON;
4929
4947 __IO uint32_t INTSTS;
4948
4960 __I uint32_t STATUS;
4961
4973 __IO uint32_t DIV;
4974
4992 __IO uint32_t TOUT;
4993
5004 __IO uint32_t DATA;
5005
5021 __IO uint32_t SADDR0;
5022
5038 __IO uint32_t SADDR1;
5039 uint32_t RESERVE0[2];
5040
5041
5053 __IO uint32_t SAMASK0;
5054
5066 __IO uint32_t SAMASK1;
5067 uint32_t RESERVE1[4];
5068
5069
5093 __IO uint32_t CON2;
5094
5126 __IO uint32_t STATUS2;
5127
5128 } I2C_T;
5129
5135 #define I2C_CON_IPEN_Pos (0)
5136 #define I2C_CON_IPEN_Msk (0x1ul << I2C_CON_IPEN_Pos)
5138 #define I2C_CON_ACK_Pos (1)
5139 #define I2C_CON_ACK_Msk (0x1ul << I2C_CON_ACK_Pos)
5141 #define I2C_CON_STOP_Pos (2)
5142 #define I2C_CON_STOP_Msk (0x1ul << I2C_CON_STOP_Pos)
5144 #define I2C_CON_START_Pos (3)
5145 #define I2C_CON_START_Msk (0x1ul << I2C_CON_START_Pos)
5147 #define I2C_CON_I2C_STS_Pos (4)
5148 #define I2C_CON_I2C_STS_Msk (0x1ul << I2C_CON_I2C_STS_Pos)
5150 #define I2C_CON_INTEN_Pos (7)
5151 #define I2C_CON_INTEN_Msk (0x1ul << I2C_CON_INTEN_Pos)
5153 #define I2C_INTSTS_INTSTS_Pos (0)
5154 #define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos)
5156 #define I2C_INTSTS_TIF_Pos (1)
5157 #define I2C_INTSTS_TIF_Msk (0x1ul << I2C_INTSTS_TIF_Pos)
5159 #define I2C_INTSTS_WAKEUP_ACK_DONE_Pos (7)
5160 #define I2C_INTSTS_WAKEUP_ACK_DONE_Msk (0x1ul << I2C_INTSTS_WAKEUP_ACK_DONE_Pos)
5162 #define I2C_STATUS_STATUS_Pos (0)
5163 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
5165 #define I2C_DIV_CLK_DIV_Pos (0)
5166 #define I2C_DIV_CLK_DIV_Msk (0xfful << I2C_DIV_CLK_DIV_Pos)
5168 #define I2C_TOUT_TOUTEN_Pos (0)
5169 #define I2C_TOUT_TOUTEN_Msk (0x1ul << I2C_TOUT_TOUTEN_Pos)
5171 #define I2C_TOUT_DIV4_Pos (1)
5172 #define I2C_TOUT_DIV4_Msk (0x1ul << I2C_TOUT_DIV4_Pos)
5174 #define I2C_DATA_DATA_Pos (0)
5175 #define I2C_DATA_DATA_Msk (0xfful << I2C_DATA_DATA_Pos)
5177 #define I2C_SADDR0_GCALL_Pos (0)
5178 #define I2C_SADDR0_GCALL_Msk (0x1ul << I2C_SADDR0_GCALL_Pos)
5180 #define I2C_SADDR0_SADDR_Pos (1)
5181 #define I2C_SADDR0_SADDR_Msk (0x7ful << I2C_SADDR0_SADDR_Pos)
5183 #define I2C_SADDR1_GCALL_Pos (0)
5184 #define I2C_SADDR1_GCALL_Msk (0x1ul << I2C_SADDR1_GCALL_Pos)
5186 #define I2C_SADDR1_SADDR_Pos (1)
5187 #define I2C_SADDR1_SADDR_Msk (0x7ful << I2C_SADDR1_SADDR_Pos)
5189 #define I2C_SAMASK0_SAMASK_Pos (1)
5190 #define I2C_SAMASK0_SAMASK_Msk (0x7ful << I2C_SAMASK0_SAMASK_Pos)
5192 #define I2C_SAMASK1_SAMASK_Pos (1)
5193 #define I2C_SAMASK1_SAMASK_Msk (0x7ful << I2C_SAMASK1_SAMASK_Pos)
5195 #define I2C_CON2_WKUPEN_Pos (0)
5196 #define I2C_CON2_WKUPEN_Msk (0x1ul << I2C_CON2_WKUPEN_Pos)
5198 #define I2C_CON2_OVER_INTEN_Pos (1)
5199 #define I2C_CON2_OVER_INTEN_Msk (0x1ul << I2C_CON2_OVER_INTEN_Pos)
5201 #define I2C_CON2_UNDER_INTEN_Pos (2)
5202 #define I2C_CON2_UNDER_INTEN_Msk (0x1ul << I2C_CON2_UNDER_INTEN_Pos)
5204 #define I2C_CON2_TWOFF_EN_Pos (4)
5205 #define I2C_CON2_TWOFF_EN_Msk (0x1ul << I2C_CON2_TWOFF_EN_Pos)
5207 #define I2C_CON2_NOSTRETCH_Pos (5)
5208 #define I2C_CON2_NOSTRETCH_Msk (0x1ul << I2C_CON2_NOSTRETCH_Pos)
5210 #define I2C_STATUS2_WKUPIF_Pos (0)
5211 #define I2C_STATUS2_WKUPIF_Msk (0x1ul << I2C_STATUS2_WKUPIF_Pos)
5213 #define I2C_STATUS2_OVERUN_Pos (1)
5214 #define I2C_STATUS2_OVERUN_Msk (0x1ul << I2C_STATUS2_OVERUN_Pos)
5216 #define I2C_STATUS2_UNDERUN_Pos (2)
5217 #define I2C_STATUS2_UNDERUN_Msk (0x1ul << I2C_STATUS2_UNDERUN_Pos)
5219 #define I2C_STATUS2_WR_STATUS_Pos (3)
5220 #define I2C_STATUS2_WR_STATUS_Msk (0x1ul << I2C_STATUS2_WR_STATUS_Pos)
5222 #define I2C_STATUS2_FULL_Pos (4)
5223 #define I2C_STATUS2_FULL_Msk (0x1ul << I2C_STATUS2_FULL_Pos)
5225 #define I2C_STATUS2_EMPTY_Pos (5)
5226 #define I2C_STATUS2_EMPTY_Msk (0x1ul << I2C_STATUS2_EMPTY_Pos)
5228 #define I2C_STATUS2_BUS_FREE_Pos (6)
5229 #define I2C_STATUS2_BUS_FREE_Msk (0x1ul << I2C_STATUS2_BUS_FREE_Pos) /* I2C_CONST */
5232 /* end of I2C register group */
5233
5234
5235 /*---------------------- LCD Controller -------------------------*/
5241 typedef struct
5242 {
5243
5244
5288 __IO uint32_t CTL;
5289
5343 __IO uint32_t DISPCTL;
5344
5361 __IO uint32_t MEM_0;
5362
5379 __IO uint32_t MEM_1;
5380
5397 __IO uint32_t MEM_2;
5398
5415 __IO uint32_t MEM_3;
5416
5433 __IO uint32_t MEM_4;
5434
5451 __IO uint32_t MEM_5;
5452
5469 __IO uint32_t MEM_6;
5470
5487 __IO uint32_t MEM_7;
5488
5505 __IO uint32_t MEM_8;
5506 uint32_t RESERVE0[1];
5507
5508
5530 __IO uint32_t FCR;
5531
5547 __IO uint32_t FCSTS;
5548
5549 } LCD_T;
5550
5556 #define LCD_CTL_EN_Pos (0)
5557 #define LCD_CTL_EN_Msk (0x1ul << LCD_CTL_EN_Pos)
5559 #define LCD_CTL_MUX_Pos (1)
5560 #define LCD_CTL_MUX_Msk (0x7ul << LCD_CTL_MUX_Pos)
5562 #define LCD_CTL_FREQ_Pos (4)
5563 #define LCD_CTL_FREQ_Msk (0x7ul << LCD_CTL_FREQ_Pos)
5565 #define LCD_CTL_BLINK_Pos (7)
5566 #define LCD_CTL_BLINK_Msk (0x1ul << LCD_CTL_BLINK_Pos)
5568 #define LCD_CTL_PDDISP_EN_Pos (8)
5569 #define LCD_CTL_PDDISP_EN_Msk (0x1ul << LCD_CTL_PDDISP_EN_Pos)
5571 #define LCD_CTL_PDINT_EN_Pos (9)
5572 #define LCD_CTL_PDINT_EN_Msk (0x1ul << LCD_CTL_PDINT_EN_Pos)
5574 #define LCD_DISPCTL_CPUMP_EN_Pos (0)
5575 #define LCD_DISPCTL_CPUMP_EN_Msk (0x1ul << LCD_DISPCTL_CPUMP_EN_Pos)
5577 #define LCD_DISPCTL_BIAS_SEL_Pos (1)
5578 #define LCD_DISPCTL_BIAS_SEL_Msk (0x3ul << LCD_DISPCTL_BIAS_SEL_Pos)
5580 #define LCD_DISPCTL_IBRL_EN_Pos (4)
5581 #define LCD_DISPCTL_IBRL_EN_Msk (0x1ul << LCD_DISPCTL_IBRL_EN_Pos)
5583 #define LCD_DISPCTL_BV_SEL_Pos (6)
5584 #define LCD_DISPCTL_BV_SEL_Msk (0x1ul << LCD_DISPCTL_BV_SEL_Pos)
5586 #define LCD_DISPCTL_CPUMP_VOL_SET_Pos (8)
5587 #define LCD_DISPCTL_CPUMP_VOL_SET_Msk (0x7ul << LCD_DISPCTL_CPUMP_VOL_SET_Pos)
5589 #define LCD_DISPCTL_CPUMP_FREQ_Pos (11)
5590 #define LCD_DISPCTL_CPUMP_FREQ_Msk (0x7ul << LCD_DISPCTL_CPUMP_FREQ_Pos)
5592 #define LCD_DISPCTL_Ext_C_Pos (16)
5593 #define LCD_DISPCTL_Ext_C_Msk (0x1ul << LCD_DISPCTL_Ext_C_Pos)
5595 #define LCD_DISPCTL_Res_Sel_Pos (17)
5596 #define LCD_DISPCTL_Res_Sel_Msk (0x3ul << LCD_DISPCTL_Res_Sel_Pos)
5598 #define LCD_MEM_0_SEG_0_4x_Pos (0)
5599 #define LCD_MEM_0_SEG_0_4x_Msk (0x3ful << LCD_MEM_0_SEG_0_4x_Pos)
5601 #define LCD_MEM_0_SEG_1_4x_Pos (8)
5602 #define LCD_MEM_0_SEG_1_4x_Msk (0x7ful << LCD_MEM_0_SEG_1_4x_Pos)
5604 #define LCD_MEM_0_SEG_2_4x_Pos (16)
5605 #define LCD_MEM_0_SEG_2_4x_Msk (0x3ful << LCD_MEM_0_SEG_2_4x_Pos)
5607 #define LCD_MEM_0_SEG_3_4x_Pos (24)
5608 #define LCD_MEM_0_SEG_3_4x_Msk (0x3ful << LCD_MEM_0_SEG_3_4x_Pos)
5610 #define LCD_MEM_1_SEG_0_4x_Pos (0)
5611 #define LCD_MEM_1_SEG_0_4x_Msk (0x3ful << LCD_MEM_1_SEG_0_4x_Pos)
5613 #define LCD_MEM_1_SEG_1_4x_Pos (8)
5614 #define LCD_MEM_1_SEG_1_4x_Msk (0x7ful << LCD_MEM_1_SEG_1_4x_Pos)
5616 #define LCD_MEM_1_SEG_2_4x_Pos (16)
5617 #define LCD_MEM_1_SEG_2_4x_Msk (0x3ful << LCD_MEM_1_SEG_2_4x_Pos)
5619 #define LCD_MEM_1_SEG_3_4x_Pos (24)
5620 #define LCD_MEM_1_SEG_3_4x_Msk (0x3ful << LCD_MEM_1_SEG_3_4x_Pos)
5622 #define LCD_MEM_2_SEG_0_4x_Pos (0)
5623 #define LCD_MEM_2_SEG_0_4x_Msk (0x3ful << LCD_MEM_2_SEG_0_4x_Pos)
5625 #define LCD_MEM_2_SEG_1_4x_Pos (8)
5626 #define LCD_MEM_2_SEG_1_4x_Msk (0x7ful << LCD_MEM_2_SEG_1_4x_Pos)
5628 #define LCD_MEM_2_SEG_2_4x_Pos (16)
5629 #define LCD_MEM_2_SEG_2_4x_Msk (0x3ful << LCD_MEM_2_SEG_2_4x_Pos)
5631 #define LCD_MEM_2_SEG_3_4x_Pos (24)
5632 #define LCD_MEM_2_SEG_3_4x_Msk (0x3ful << LCD_MEM_2_SEG_3_4x_Pos)
5634 #define LCD_MEM_3_SEG_0_4x_Pos (0)
5635 #define LCD_MEM_3_SEG_0_4x_Msk (0x3ful << LCD_MEM_3_SEG_0_4x_Pos)
5637 #define LCD_MEM_3_SEG_1_4x_Pos (8)
5638 #define LCD_MEM_3_SEG_1_4x_Msk (0x7ful << LCD_MEM_3_SEG_1_4x_Pos)
5640 #define LCD_MEM_3_SEG_2_4x_Pos (16)
5641 #define LCD_MEM_3_SEG_2_4x_Msk (0x3ful << LCD_MEM_3_SEG_2_4x_Pos)
5643 #define LCD_MEM_3_SEG_3_4x_Pos (24)
5644 #define LCD_MEM_3_SEG_3_4x_Msk (0x3ful << LCD_MEM_3_SEG_3_4x_Pos)
5646 #define LCD_MEM_4_SEG_0_4x_Pos (0)
5647 #define LCD_MEM_4_SEG_0_4x_Msk (0x3ful << LCD_MEM_4_SEG_0_4x_Pos)
5649 #define LCD_MEM_4_SEG_1_4x_Pos (8)
5650 #define LCD_MEM_4_SEG_1_4x_Msk (0x7ful << LCD_MEM_4_SEG_1_4x_Pos)
5652 #define LCD_MEM_4_SEG_2_4x_Pos (16)
5653 #define LCD_MEM_4_SEG_2_4x_Msk (0x3ful << LCD_MEM_4_SEG_2_4x_Pos)
5655 #define LCD_MEM_4_SEG_3_4x_Pos (24)
5656 #define LCD_MEM_4_SEG_3_4x_Msk (0x3ful << LCD_MEM_4_SEG_3_4x_Pos)
5658 #define LCD_MEM_5_SEG_0_4x_Pos (0)
5659 #define LCD_MEM_5_SEG_0_4x_Msk (0x3ful << LCD_MEM_5_SEG_0_4x_Pos)
5661 #define LCD_MEM_5_SEG_1_4x_Pos (8)
5662 #define LCD_MEM_5_SEG_1_4x_Msk (0x7ful << LCD_MEM_5_SEG_1_4x_Pos)
5664 #define LCD_MEM_5_SEG_2_4x_Pos (16)
5665 #define LCD_MEM_5_SEG_2_4x_Msk (0x3ful << LCD_MEM_5_SEG_2_4x_Pos)
5667 #define LCD_MEM_5_SEG_3_4x_Pos (24)
5668 #define LCD_MEM_5_SEG_3_4x_Msk (0x3ful << LCD_MEM_5_SEG_3_4x_Pos)
5670 #define LCD_MEM_6_SEG_0_4x_Pos (0)
5671 #define LCD_MEM_6_SEG_0_4x_Msk (0x3ful << LCD_MEM_6_SEG_0_4x_Pos)
5673 #define LCD_MEM_6_SEG_1_4x_Pos (8)
5674 #define LCD_MEM_6_SEG_1_4x_Msk (0x7ful << LCD_MEM_6_SEG_1_4x_Pos)
5676 #define LCD_MEM_6_SEG_2_4x_Pos (16)
5677 #define LCD_MEM_6_SEG_2_4x_Msk (0x3ful << LCD_MEM_6_SEG_2_4x_Pos)
5679 #define LCD_MEM_6_SEG_3_4x_Pos (24)
5680 #define LCD_MEM_6_SEG_3_4x_Msk (0x3ful << LCD_MEM_6_SEG_3_4x_Pos)
5682 #define LCD_MEM_7_SEG_0_4x_Pos (0)
5683 #define LCD_MEM_7_SEG_0_4x_Msk (0x3ful << LCD_MEM_7_SEG_0_4x_Pos)
5685 #define LCD_MEM_7_SEG_1_4x_Pos (8)
5686 #define LCD_MEM_7_SEG_1_4x_Msk (0x7ful << LCD_MEM_7_SEG_1_4x_Pos)
5688 #define LCD_MEM_7_SEG_2_4x_Pos (16)
5689 #define LCD_MEM_7_SEG_2_4x_Msk (0x3ful << LCD_MEM_7_SEG_2_4x_Pos)
5691 #define LCD_MEM_7_SEG_3_4x_Pos (24)
5692 #define LCD_MEM_7_SEG_3_4x_Msk (0x3ful << LCD_MEM_7_SEG_3_4x_Pos)
5694 #define LCD_MEM_8_SEG_0_4x_Pos (0)
5695 #define LCD_MEM_8_SEG_0_4x_Msk (0x3ful << LCD_MEM_8_SEG_0_4x_Pos)
5697 #define LCD_MEM_8_SEG_1_4x_Pos (8)
5698 #define LCD_MEM_8_SEG_1_4x_Msk (0x7ful << LCD_MEM_8_SEG_1_4x_Pos)
5700 #define LCD_MEM_8_SEG_2_4x_Pos (16)
5701 #define LCD_MEM_8_SEG_2_4x_Msk (0x3ful << LCD_MEM_8_SEG_2_4x_Pos)
5703 #define LCD_MEM_8_SEG_3_4x_Pos (24)
5704 #define LCD_MEM_8_SEG_3_4x_Msk (0x3ful << LCD_MEM_8_SEG_3_4x_Pos)
5706 #define LCD_FCR_FCEN_Pos (0)
5707 #define LCD_FCR_FCEN_Msk (0x1ul << LCD_FCR_FCEN_Pos)
5709 #define LCD_FCR_FCINTEN_Pos (1)
5710 #define LCD_FCR_FCINTEN_Msk (0x1ul << LCD_FCR_FCINTEN_Pos)
5712 #define LCD_FCR_PRESCL_Pos (2)
5713 #define LCD_FCR_PRESCL_Msk (0x3ul << LCD_FCR_PRESCL_Pos)
5715 #define LCD_FCR_FCV_Pos (4)
5716 #define LCD_FCR_FCV_Msk (0x3ful << LCD_FCR_FCV_Pos)
5718 #define LCD_FCSTS_FCSTS_Pos (0)
5719 #define LCD_FCSTS_FCSTS_Msk (0x1ul << LCD_FCSTS_FCSTS_Pos)
5721 #define LCD_FCSTS_PDSTS_Pos (1)
5722 #define LCD_FCSTS_PDSTS_Msk (0x1ul << LCD_FCSTS_PDSTS_Pos) /* LCD_CONST */
5725 /* end of LCD register group */
5726
5727
5728 /*---------------------- Pulse Width Modulation Controller -------------------------*/
5734 typedef struct
5735 {
5736
5737
5758 __IO uint32_t PRES;
5759
5784 __IO uint32_t CLKSEL;
5785
5848 __IO uint32_t CTL;
5849
5870 __IO uint32_t INTEN;
5871
5908 __IO uint32_t INTSTS;
5909
5930 __IO uint32_t OE;
5931 uint32_t RESERVE0[1];
5932
5933
5976 __IO uint32_t DUTY0;
5977
5995 __I uint32_t DATA0;
5996 uint32_t RESERVE1[1];
5997
5998
6041 __IO uint32_t DUTY1;
6042
6060 __I uint32_t DATA1;
6061 uint32_t RESERVE2[1];
6062
6063
6106 __IO uint32_t DUTY2;
6107
6125 __I uint32_t DATA2;
6126 uint32_t RESERVE3[1];
6127
6128
6171 __IO uint32_t DUTY3;
6172
6190 __I uint32_t DATA3;
6191 uint32_t RESERVE4[3];
6192
6193
6296 __IO uint32_t CAPCTL;
6297
6338 __IO uint32_t CAPINTEN;
6339
6400 __IO uint32_t CAPINTSTS;
6401
6414 __I uint32_t CRL0;
6415
6428 __I uint32_t CFL0;
6429
6442 __I uint32_t CRL1;
6443
6456 __I uint32_t CFL1;
6457
6470 __I uint32_t CRL2;
6471
6484 __I uint32_t CFL2;
6485
6498 __I uint32_t CRL3;
6499
6512 __I uint32_t CFL3;
6513
6532 __I uint32_t PDMACH0;
6533
6553 __I uint32_t PDMACH2;
6554
6579 __IO uint32_t ADTRGEN;
6580
6605 __IO uint32_t ADTRGSTS;
6606
6607 } PWM_T;
6608
6614 #define PWM_PRES_CP01_Pos (0)
6615 #define PWM_PRES_CP01_Msk (0xfful << PWM_PRES_CP01_Pos)
6617 #define PWM_PRES_CP23_Pos (8)
6618 #define PWM_PRES_CP23_Msk (0xfful << PWM_PRES_CP23_Pos)
6620 #define PWM_PRES_DZ01_Pos (16)
6621 #define PWM_PRES_DZ01_Msk (0xfful << PWM_PRES_DZ01_Pos)
6623 #define PWM_PRES_DZ23_Pos (24)
6624 #define PWM_PRES_DZ23_Msk (0xfful << PWM_PRES_DZ23_Pos)
6626 #define PWM_CLKSEL_CLKSEL0_Pos (0)
6627 #define PWM_CLKSEL_CLKSEL0_Msk (0x7ul << PWM_CLKSEL_CLKSEL0_Pos)
6629 #define PWM_CLKSEL_CLKSEL1_Pos (4)
6630 #define PWM_CLKSEL_CLKSEL1_Msk (0x7ul << PWM_CLKSEL_CLKSEL1_Pos)
6632 #define PWM_CLKSEL_CLKSEL2_Pos (8)
6633 #define PWM_CLKSEL_CLKSEL2_Msk (0x7ul << PWM_CLKSEL_CLKSEL2_Pos)
6635 #define PWM_CLKSEL_CLKSEL3_Pos (12)
6636 #define PWM_CLKSEL_CLKSEL3_Msk (0x7ul << PWM_CLKSEL_CLKSEL3_Pos)
6638 #define PWM_CTL_CH0EN_Pos (0)
6639 #define PWM_CTL_CH0EN_Msk (0x1ul << PWM_CTL_CH0EN_Pos)
6641 #define PWM_CTL_CH0INV_Pos (2)
6642 #define PWM_CTL_CH0INV_Msk (0x1ul << PWM_CTL_CH0INV_Pos)
6644 #define PWM_CTL_CH0MOD_Pos (3)
6645 #define PWM_CTL_CH0MOD_Msk (0x1ul << PWM_CTL_CH0MOD_Pos)
6647 #define PWM_CTL_DZEN01_Pos (4)
6648 #define PWM_CTL_DZEN01_Msk (0x1ul << PWM_CTL_DZEN01_Pos)
6650 #define PWM_CTL_DZEN23_Pos (5)
6651 #define PWM_CTL_DZEN23_Msk (0x1ul << PWM_CTL_DZEN23_Pos)
6653 #define PWM_CTL_CH1EN_Pos (8)
6654 #define PWM_CTL_CH1EN_Msk (0x1ul << PWM_CTL_CH1EN_Pos)
6656 #define PWM_CTL_CH1INV_Pos (10)
6657 #define PWM_CTL_CH1INV_Msk (0x1ul << PWM_CTL_CH1INV_Pos)
6659 #define PWM_CTL_CH1MOD_Pos (11)
6660 #define PWM_CTL_CH1MOD_Msk (0x1ul << PWM_CTL_CH1MOD_Pos)
6662 #define PWM_CTL_CH2EN_Pos (16)
6663 #define PWM_CTL_CH2EN_Msk (0x1ul << PWM_CTL_CH2EN_Pos)
6665 #define PWM_CTL_CH2INV_Pos (18)
6666 #define PWM_CTL_CH2INV_Msk (0x1ul << PWM_CTL_CH2INV_Pos)
6668 #define PWM_CTL_CH2MOD_Pos (19)
6669 #define PWM_CTL_CH2MOD_Msk (0x1ul << PWM_CTL_CH2MOD_Pos)
6671 #define PWM_CTL_CH3EN_Pos (24)
6672 #define PWM_CTL_CH3EN_Msk (0x1ul << PWM_CTL_CH3EN_Pos)
6674 #define PWM_CTL_CH3INV_Pos (26)
6675 #define PWM_CTL_CH3INV_Msk (0x1ul << PWM_CTL_CH3INV_Pos)
6677 #define PWM_CTL_CH3MOD_Pos (27)
6678 #define PWM_CTL_CH3MOD_Msk (0x1ul << PWM_CTL_CH3MOD_Pos)
6680 #define PWM_CTL_PWMTYPE01_Pos (30)
6681 #define PWM_CTL_PWMTYPE01_Msk (0x1ul << PWM_CTL_PWMTYPE01_Pos)
6683 #define PWM_CTL_PWMTYPE23_Pos (31)
6684 #define PWM_CTL_PWMTYPE23_Msk (0x1ul << PWM_CTL_PWMTYPE23_Pos)
6686 #define PWM_INTEN_TMIE0_Pos (0)
6687 #define PWM_INTEN_TMIE0_Msk (0x1ul << PWM_INTEN_TMIE0_Pos)
6689 #define PWM_INTEN_TMIE1_Pos (1)
6690 #define PWM_INTEN_TMIE1_Msk (0x1ul << PWM_INTEN_TMIE1_Pos)
6692 #define PWM_INTEN_TMIE2_Pos (2)
6693 #define PWM_INTEN_TMIE2_Msk (0x1ul << PWM_INTEN_TMIE2_Pos)
6695 #define PWM_INTEN_TMIE3_Pos (3)
6696 #define PWM_INTEN_TMIE3_Msk (0x1ul << PWM_INTEN_TMIE3_Pos)
6698 #define PWM_INTSTS_TMINT0_Pos (0)
6699 #define PWM_INTSTS_TMINT0_Msk (0x1ul << PWM_INTSTS_TMINT0_Pos)
6701 #define PWM_INTSTS_TMINT1_Pos (1)
6702 #define PWM_INTSTS_TMINT1_Msk (0x1ul << PWM_INTSTS_TMINT1_Pos)
6704 #define PWM_INTSTS_TMINT2_Pos (2)
6705 #define PWM_INTSTS_TMINT2_Msk (0x1ul << PWM_INTSTS_TMINT2_Pos)
6707 #define PWM_INTSTS_TMINT3_Pos (3)
6708 #define PWM_INTSTS_TMINT3_Msk (0x1ul << PWM_INTSTS_TMINT3_Pos)
6710 #define PWM_INTSTS_Duty0Syncflag_Pos (4)
6711 #define PWM_INTSTS_Duty0Syncflag_Msk (0x1ul << PWM_INTSTS_Duty0Syncflag_Pos)
6713 #define PWM_INTSTS_Duty1Syncflag_Pos (5)
6714 #define PWM_INTSTS_Duty1Syncflag_Msk (0x1ul << PWM_INTSTS_Duty1Syncflag_Pos)
6716 #define PWM_INTSTS_Duty2Syncflag_Pos (6)
6717 #define PWM_INTSTS_Duty2Syncflag_Msk (0x1ul << PWM_INTSTS_Duty2Syncflag_Pos)
6719 #define PWM_INTSTS_Duty3Syncflag_Pos (7)
6720 #define PWM_INTSTS_Duty3Syncflag_Msk (0x1ul << PWM_INTSTS_Duty3Syncflag_Pos)
6722 #define PWM_INTSTS_PresSyncFlag_Pos (8)
6723 #define PWM_INTSTS_PresSyncFlag_Msk (0x1ul << PWM_INTSTS_PresSyncFlag_Pos)
6725 #define PWM_OE_CH0_OE_Pos (0)
6726 #define PWM_OE_CH0_OE_Msk (0x1ul << PWM_OE_CH0_OE_Pos)
6728 #define PWM_OE_CH1_OE_Pos (1)
6729 #define PWM_OE_CH1_OE_Msk (0x1ul << PWM_OE_CH1_OE_Pos)
6731 #define PWM_OE_CH2_OE_Pos (2)
6732 #define PWM_OE_CH2_OE_Msk (0x1ul << PWM_OE_CH2_OE_Pos)
6734 #define PWM_OE_CH3_OE_Pos (3)
6735 #define PWM_OE_CH3_OE_Msk (0x1ul << PWM_OE_CH3_OE_Pos)
6737 #define PWM_DUTY0_CN_Pos (0)
6738 #define PWM_DUTY0_CN_Msk (0xfffful << PWM_DUTY0_CN_Pos)
6740 #define PWM_DUTY0_CM_Pos (16)
6741 #define PWM_DUTY0_CM_Msk (0xfffful << PWM_DUTY0_CM_Pos)
6743 #define PWM_DATA0_DATA_Pos (0)
6744 #define PWM_DATA0_DATA_Msk (0xfffful << PWM_DATA0_DATA_Pos)
6746 #define PWM_DATA0_DATA_H_Pos (16)
6747 #define PWM_DATA0_DATA_H_Msk (0x7ffful << PWM_DATA0_DATA_H_Pos)
6749 #define PWM_DATA0_sync_Pos (31)
6750 #define PWM_DATA0_sync_Msk (0x1ul << PWM_DATA0_sync_Pos)
6752 #define PWM_DUTY1_CN_Pos (0)
6753 #define PWM_DUTY1_CN_Msk (0xfffful << PWM_DUTY1_CN_Pos)
6755 #define PWM_DUTY1_CM_Pos (16)
6756 #define PWM_DUTY1_CM_Msk (0xfffful << PWM_DUTY1_CM_Pos)
6758 #define PWM_DATA1_DATA_Pos (0)
6759 #define PWM_DATA1_DATA_Msk (0xfffful << PWM_DATA1_DATA_Pos)
6761 #define PWM_DATA1_DATA_H_Pos (16)
6762 #define PWM_DATA1_DATA_H_Msk (0x7ffful << PWM_DATA1_DATA_H_Pos)
6764 #define PWM_DATA1_sync_Pos (31)
6765 #define PWM_DATA1_sync_Msk (0x1ul << PWM_DATA1_sync_Pos)
6767 #define PWM_DUTY2_CN_Pos (0)
6768 #define PWM_DUTY2_CN_Msk (0xfffful << PWM_DUTY2_CN_Pos)
6770 #define PWM_DUTY2_CM_Pos (16)
6771 #define PWM_DUTY2_CM_Msk (0xfffful << PWM_DUTY2_CM_Pos)
6773 #define PWM_DATA2_DATA_Pos (0)
6774 #define PWM_DATA2_DATA_Msk (0xfffful << PWM_DATA2_DATA_Pos)
6776 #define PWM_DATA2_DATA_H_Pos (16)
6777 #define PWM_DATA2_DATA_H_Msk (0x7ffful << PWM_DATA2_DATA_H_Pos)
6779 #define PWM_DATA2_sync_Pos (31)
6780 #define PWM_DATA2_sync_Msk (0x1ul << PWM_DATA2_sync_Pos)
6782 #define PWM_DUTY3_CN_Pos (0)
6783 #define PWM_DUTY3_CN_Msk (0xfffful << PWM_DUTY3_CN_Pos)
6785 #define PWM_DUTY3_CM_Pos (16)
6786 #define PWM_DUTY3_CM_Msk (0xfffful << PWM_DUTY3_CM_Pos)
6788 #define PWM_DATA3_DATA_Pos (0)
6789 #define PWM_DATA3_DATA_Msk (0xfffful << PWM_DATA3_DATA_Pos)
6791 #define PWM_DATA3_DATA_H_Pos (16)
6792 #define PWM_DATA3_DATA_H_Msk (0x7ffful << PWM_DATA3_DATA_H_Pos)
6794 #define PWM_DATA3_sync_Pos (31)
6795 #define PWM_DATA3_sync_Msk (0x1ul << PWM_DATA3_sync_Pos)
6797 #define PWM_CAPCTL_INV0_Pos (0)
6798 #define PWM_CAPCTL_INV0_Msk (0x1ul << PWM_CAPCTL_INV0_Pos)
6800 #define PWM_CAPCTL_CAPCH0EN_Pos (1)
6801 #define PWM_CAPCTL_CAPCH0EN_Msk (0x1ul << PWM_CAPCTL_CAPCH0EN_Pos)
6803 #define PWM_CAPCTL_CAPCH0PADEN_Pos (2)
6804 #define PWM_CAPCTL_CAPCH0PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH0PADEN_Pos)
6806 #define PWM_CAPCTL_CH0PDMAEN_Pos (3)
6807 #define PWM_CAPCTL_CH0PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH0PDMAEN_Pos)
6809 #define PWM_CAPCTL_PDMACAPMOD0_Pos (4)
6810 #define PWM_CAPCTL_PDMACAPMOD0_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD0_Pos)
6812 #define PWM_CAPCTL_CAPRELOADREN0_Pos (6)
6813 #define PWM_CAPCTL_CAPRELOADREN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN0_Pos)
6815 #define PWM_CAPCTL_CAPRELOADFEN0_Pos (7)
6816 #define PWM_CAPCTL_CAPRELOADFEN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN0_Pos)
6818 #define PWM_CAPCTL_INV1_Pos (8)
6819 #define PWM_CAPCTL_INV1_Msk (0x1ul << PWM_CAPCTL_INV1_Pos)
6821 #define PWM_CAPCTL_CAPCH1EN_Pos (9)
6822 #define PWM_CAPCTL_CAPCH1EN_Msk (0x1ul << PWM_CAPCTL_CAPCH1EN_Pos)
6824 #define PWM_CAPCTL_CAPCH1PADEN_Pos (10)
6825 #define PWM_CAPCTL_CAPCH1PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH1PADEN_Pos)
6827 #define PWM_CAPCTL_CH0RFORDER_Pos (12)
6828 #define PWM_CAPCTL_CH0RFORDER_Msk (0x1ul << PWM_CAPCTL_CH0RFORDER_Pos)
6830 #define PWM_CAPCTL_CH01CASK_Pos (13)
6831 #define PWM_CAPCTL_CH01CASK_Msk (0x1ul << PWM_CAPCTL_CH01CASK_Pos)
6833 #define PWM_CAPCTL_CAPRELOADREN1_Pos (14)
6834 #define PWM_CAPCTL_CAPRELOADREN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN1_Pos)
6836 #define PWM_CAPCTL_CAPRELOADFEN1_Pos (15)
6837 #define PWM_CAPCTL_CAPRELOADFEN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN1_Pos)
6839 #define PWM_CAPCTL_INV2_Pos (16)
6840 #define PWM_CAPCTL_INV2_Msk (0x1ul << PWM_CAPCTL_INV2_Pos)
6842 #define PWM_CAPCTL_CAPCH2EN_Pos (17)
6843 #define PWM_CAPCTL_CAPCH2EN_Msk (0x1ul << PWM_CAPCTL_CAPCH2EN_Pos)
6845 #define PWM_CAPCTL_CAPCH2PADEN_Pos (18)
6846 #define PWM_CAPCTL_CAPCH2PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH2PADEN_Pos)
6848 #define PWM_CAPCTL_CH2PDMAEN_Pos (19)
6849 #define PWM_CAPCTL_CH2PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH2PDMAEN_Pos)
6851 #define PWM_CAPCTL_PDMACAPMOD2_Pos (20)
6852 #define PWM_CAPCTL_PDMACAPMOD2_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD2_Pos)
6854 #define PWM_CAPCTL_CAPRELOADREN2_Pos (22)
6855 #define PWM_CAPCTL_CAPRELOADREN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN2_Pos)
6857 #define PWM_CAPCTL_CAPRELOADFEN2_Pos (23)
6858 #define PWM_CAPCTL_CAPRELOADFEN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN2_Pos)
6860 #define PWM_CAPCTL_INV3_Pos (24)
6861 #define PWM_CAPCTL_INV3_Msk (0x1ul << PWM_CAPCTL_INV3_Pos)
6863 #define PWM_CAPCTL_CAPCH3EN_Pos (25)
6864 #define PWM_CAPCTL_CAPCH3EN_Msk (0x1ul << PWM_CAPCTL_CAPCH3EN_Pos)
6866 #define PWM_CAPCTL_CAPCH3PADEN_Pos (26)
6867 #define PWM_CAPCTL_CAPCH3PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH3PADEN_Pos)
6869 #define PWM_CAPCTL_CH2RFORDER_Pos (28)
6870 #define PWM_CAPCTL_CH2RFORDER_Msk (0x1ul << PWM_CAPCTL_CH2RFORDER_Pos)
6872 #define PWM_CAPCTL_CH23CASK_Pos (29)
6873 #define PWM_CAPCTL_CH23CASK_Msk (0x1ul << PWM_CAPCTL_CH23CASK_Pos)
6875 #define PWM_CAPCTL_CAPRELOADREN3_Pos (30)
6876 #define PWM_CAPCTL_CAPRELOADREN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN3_Pos)
6878 #define PWM_CAPCTL_CAPRELOADFEN3_Pos (31)
6879 #define PWM_CAPCTL_CAPRELOADFEN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN3_Pos)
6881 #define PWM_CAPINTEN_CRL_IE0_Pos (0)
6882 #define PWM_CAPINTEN_CRL_IE0_Msk (0x1ul << PWM_CAPINTEN_CRL_IE0_Pos)
6884 #define PWM_CAPINTEN_CFL_IE0_Pos (1)
6885 #define PWM_CAPINTEN_CFL_IE0_Msk (0x1ul << PWM_CAPINTEN_CFL_IE0_Pos)
6887 #define PWM_CAPINTEN_CRL_IE1_Pos (8)
6888 #define PWM_CAPINTEN_CRL_IE1_Msk (0x1ul << PWM_CAPINTEN_CRL_IE1_Pos)
6890 #define PWM_CAPINTEN_CFL_IE1_Pos (9)
6891 #define PWM_CAPINTEN_CFL_IE1_Msk (0x1ul << PWM_CAPINTEN_CFL_IE1_Pos)
6893 #define PWM_CAPINTEN_CRL_IE2_Pos (16)
6894 #define PWM_CAPINTEN_CRL_IE2_Msk (0x1ul << PWM_CAPINTEN_CRL_IE2_Pos)
6896 #define PWM_CAPINTEN_CFL_IE2_Pos (17)
6897 #define PWM_CAPINTEN_CFL_IE2_Msk (0x1ul << PWM_CAPINTEN_CFL_IE2_Pos)
6899 #define PWM_CAPINTEN_CRL_IE3_Pos (24)
6900 #define PWM_CAPINTEN_CRL_IE3_Msk (0x1ul << PWM_CAPINTEN_CRL_IE3_Pos)
6902 #define PWM_CAPINTEN_CFL_IE3_Pos (25)
6903 #define PWM_CAPINTEN_CFL_IE3_Msk (0x1ul << PWM_CAPINTEN_CFL_IE3_Pos)
6905 #define PWM_CAPINTSTS_CAPIF0_Pos (0)
6906 #define PWM_CAPINTSTS_CAPIF0_Msk (0x1ul << PWM_CAPINTSTS_CAPIF0_Pos)
6908 #define PWM_CAPINTSTS_CRLI0_Pos (1)
6909 #define PWM_CAPINTSTS_CRLI0_Msk (0x1ul << PWM_CAPINTSTS_CRLI0_Pos)
6911 #define PWM_CAPINTSTS_CFLI0_Pos (2)
6912 #define PWM_CAPINTSTS_CFLI0_Msk (0x1ul << PWM_CAPINTSTS_CFLI0_Pos)
6914 #define PWM_CAPINTSTS_CAPOVR0_Pos (3)
6915 #define PWM_CAPINTSTS_CAPOVR0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR0_Pos)
6917 #define PWM_CAPINTSTS_CAPOVF0_Pos (4)
6918 #define PWM_CAPINTSTS_CAPOVF0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF0_Pos)
6920 #define PWM_CAPINTSTS_CAPIF1_Pos (8)
6921 #define PWM_CAPINTSTS_CAPIF1_Msk (0x1ul << PWM_CAPINTSTS_CAPIF1_Pos)
6923 #define PWM_CAPINTSTS_CRLI1_Pos (9)
6924 #define PWM_CAPINTSTS_CRLI1_Msk (0x1ul << PWM_CAPINTSTS_CRLI1_Pos)
6926 #define PWM_CAPINTSTS_CFLI1_Pos (10)
6927 #define PWM_CAPINTSTS_CFLI1_Msk (0x1ul << PWM_CAPINTSTS_CFLI1_Pos)
6929 #define PWM_CAPINTSTS_CAPOVR1_Pos (11)
6930 #define PWM_CAPINTSTS_CAPOVR1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR1_Pos)
6932 #define PWM_CAPINTSTS_CAPOVF1_Pos (12)
6933 #define PWM_CAPINTSTS_CAPOVF1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF1_Pos)
6935 #define PWM_CAPINTSTS_CAPIF2_Pos (16)
6936 #define PWM_CAPINTSTS_CAPIF2_Msk (0x1ul << PWM_CAPINTSTS_CAPIF2_Pos)
6938 #define PWM_CAPINTSTS_CRLI2_Pos (17)
6939 #define PWM_CAPINTSTS_CRLI2_Msk (0x1ul << PWM_CAPINTSTS_CRLI2_Pos)
6941 #define PWM_CAPINTSTS_CFLI2_Pos (18)
6942 #define PWM_CAPINTSTS_CFLI2_Msk (0x1ul << PWM_CAPINTSTS_CFLI2_Pos)
6944 #define PWM_CAPINTSTS_CAPOVR2_Pos (19)
6945 #define PWM_CAPINTSTS_CAPOVR2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR2_Pos)
6947 #define PWM_CAPINTSTS_CAPOVF2_Pos (20)
6948 #define PWM_CAPINTSTS_CAPOVF2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF2_Pos)
6950 #define PWM_CAPINTSTS_CAPIF3_Pos (24)
6951 #define PWM_CAPINTSTS_CAPIF3_Msk (0x1ul << PWM_CAPINTSTS_CAPIF3_Pos)
6953 #define PWM_CAPINTSTS_CRLI3_Pos (25)
6954 #define PWM_CAPINTSTS_CRLI3_Msk (0x1ul << PWM_CAPINTSTS_CRLI3_Pos)
6956 #define PWM_CAPINTSTS_CFLI3_Pos (26)
6957 #define PWM_CAPINTSTS_CFLI3_Msk (0x1ul << PWM_CAPINTSTS_CFLI3_Pos)
6959 #define PWM_CAPINTSTS_CAPOVR3_Pos (27)
6960 #define PWM_CAPINTSTS_CAPOVR3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR3_Pos)
6962 #define PWM_CAPINTSTS_CAPOVF3_Pos (28)
6963 #define PWM_CAPINTSTS_CAPOVF3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF3_Pos)
6965 #define PWM_CRL0_CRL_Pos (0)
6966 #define PWM_CRL0_CRL_Msk (0xfffful << PWM_CRL0_CRL_Pos)
6968 #define PWM_CRL0_CRL_H_Pos (16)
6969 #define PWM_CRL0_CRL_H_Msk (0xfffful << PWM_CRL0_CRL_H_Pos)
6971 #define PWM_CFL0_CFL_Pos (0)
6972 #define PWM_CFL0_CFL_Msk (0xfffful << PWM_CFL0_CFL_Pos)
6974 #define PWM_CFL0_CFL_H_Pos (16)
6975 #define PWM_CFL0_CFL_H_Msk (0xfffful << PWM_CFL0_CFL_H_Pos)
6977 #define PWM_CRL1_CRL_Pos (0)
6978 #define PWM_CRL1_CRL_Msk (0xfffful << PWM_CRL1_CRL_Pos)
6980 #define PWM_CRL1_CRL_H_Pos (16)
6981 #define PWM_CRL1_CRL_H_Msk (0xfffful << PWM_CRL1_CRL_H_Pos)
6983 #define PWM_CFL1_CFL_Pos (0)
6984 #define PWM_CFL1_CFL_Msk (0xfffful << PWM_CFL1_CFL_Pos)
6986 #define PWM_CFL1_CFL_H_Pos (16)
6987 #define PWM_CFL1_CFL_H_Msk (0xfffful << PWM_CFL1_CFL_H_Pos)
6989 #define PWM_CRL2_CRL_Pos (0)
6990 #define PWM_CRL2_CRL_Msk (0xfffful << PWM_CRL2_CRL_Pos)
6992 #define PWM_CRL2_CRL_H_Pos (16)
6993 #define PWM_CRL2_CRL_H_Msk (0xfffful << PWM_CRL2_CRL_H_Pos)
6995 #define PWM_CFL2_CFL_Pos (0)
6996 #define PWM_CFL2_CFL_Msk (0xfffful << PWM_CFL2_CFL_Pos)
6998 #define PWM_CFL2_CFL_H_Pos (16)
6999 #define PWM_CFL2_CFL_H_Msk (0xfffful << PWM_CFL2_CFL_H_Pos)
7001 #define PWM_CRL3_CRL_Pos (0)
7002 #define PWM_CRL3_CRL_Msk (0xfffful << PWM_CRL3_CRL_Pos)
7004 #define PWM_CRL3_CRL_H_Pos (16)
7005 #define PWM_CRL3_CRL_H_Msk (0xfffful << PWM_CRL3_CRL_H_Pos)
7007 #define PWM_CFL3_CFL_Pos (0)
7008 #define PWM_CFL3_CFL_Msk (0xfffful << PWM_CFL3_CFL_Pos)
7010 #define PWM_CFL3_CFL_H_Pos (16)
7011 #define PWM_CFL3_CFL_H_Msk (0xfffful << PWM_CFL3_CFL_H_Pos)
7013 #define PWM_PDMACH0_PDMACH01_Pos (0)
7014 #define PWM_PDMACH0_PDMACH01_Msk (0xfful << PWM_PDMACH0_PDMACH01_Pos)
7016 #define PWM_PDMACH0_PDMACH02_Pos (8)
7017 #define PWM_PDMACH0_PDMACH02_Msk (0xfful << PWM_PDMACH0_PDMACH02_Pos)
7019 #define PWM_PDMACH0_PDMACH03_Pos (16)
7020 #define PWM_PDMACH0_PDMACH03_Msk (0xfful << PWM_PDMACH0_PDMACH03_Pos)
7022 #define PWM_PDMACH0_PDMACH04_Pos (24)
7023 #define PWM_PDMACH0_PDMACH04_Msk (0xfful << PWM_PDMACH0_PDMACH04_Pos)
7025 #define PWM_PDMACH2_PDMACH21_Pos (0)
7026 #define PWM_PDMACH2_PDMACH21_Msk (0xfful << PWM_PDMACH2_PDMACH21_Pos)
7028 #define PWM_PDMACH2_PDMACH22_Pos (8)
7029 #define PWM_PDMACH2_PDMACH22_Msk (0xfful << PWM_PDMACH2_PDMACH22_Pos)
7031 #define PWM_PDMACH2_PDMACH23_Pos (16)
7032 #define PWM_PDMACH2_PDMACH23_Msk (0xfful << PWM_PDMACH2_PDMACH23_Pos)
7034 #define PWM_PDMACH2_PDMACH24_Pos (24)
7035 #define PWM_PDMACH2_PDMACH24_Msk (0xfful << PWM_PDMACH2_PDMACH24_Pos)
7037 #define PWM_ADTRGEN_TRGCH0EN_Pos (0)
7038 #define PWM_ADTRGEN_TRGCH0EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH0EN_Pos)
7040 #define PWM_ADTRGEN_TRGCH1EN_Pos (1)
7041 #define PWM_ADTRGEN_TRGCH1EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH1EN_Pos)
7043 #define PWM_ADTRGEN_TRGCH2EN_Pos (2)
7044 #define PWM_ADTRGEN_TRGCH2EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH2EN_Pos)
7046 #define PWM_ADTRGEN_TRGCH3EN_Pos (3)
7047 #define PWM_ADTRGEN_TRGCH3EN_Msk (0x1ul << PWM_ADTRGEN_TRGCH3EN_Pos)
7049 #define PWM_ADTRGSTS_ADTRG0Flag_Pos (0)
7050 #define PWM_ADTRGSTS_ADTRG0Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG0Flag_Pos)
7052 #define PWM_ADTRGSTS_ADTRG1Flag_Pos (1)
7053 #define PWM_ADTRGSTS_ADTRG1Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG1Flag_Pos)
7055 #define PWM_ADTRGSTS_ADTRG2Flag_Pos (2)
7056 #define PWM_ADTRGSTS_ADTRG2Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG2Flag_Pos)
7058 #define PWM_ADTRGSTS_ADTRG3Flag_Pos (3)
7059 #define PWM_ADTRGSTS_ADTRG3Flag_Msk (0x1ul << PWM_ADTRGSTS_ADTRG3Flag_Pos) /* PWM_CONST */
7062 /* end of PWM register group */
7063
7064
7065 /*---------------------- Real Time Clock Controller -------------------------*/
7071 typedef struct
7072 {
7073
7074
7091 __IO uint32_t INIR;
7092
7107 __O uint32_t AER;
7108
7120 __IO uint32_t FCR;
7121
7136 __IO uint32_t TLR;
7137
7152 __IO uint32_t CLR;
7153
7166 __IO uint32_t TSSR;
7167
7184 __IO uint32_t DWR;
7185
7200 __IO uint32_t TAR;
7201
7216 __IO uint32_t CAR;
7217
7229 __I uint32_t LIR;
7230
7248 __IO uint32_t RIER;
7249
7276 __IO uint32_t RIIR;
7277
7302 __IO uint32_t TTR;
7303 uint32_t RESERVE0[2];
7304
7305
7325 __IO uint32_t SPRCTL;
7326
7338 __IO uint32_t SPR[20];
7339
7340 } RTC_T;
7341
7347 #define RTC_INIR_ACTIVE_Pos (0)
7348 #define RTC_INIR_ACTIVE_Msk (0x1ul << RTC_INIR_ACTIVE_Pos)
7350 #define RTC_INIR_INIR_Pos (0)
7351 #define RTC_INIR_INIR_Msk (0xfffffffful << RTC_INIR_INIR_Pos)
7353 #define RTC_AER_AER_Pos (0)
7354 #define RTC_AER_AER_Msk (0xfffful << RTC_AER_AER_Pos)
7356 #define RTC_AER_ENF_Pos (16)
7357 #define RTC_AER_ENF_Msk (0x1ul << RTC_AER_ENF_Pos)
7359 #define RTC_FCR_FCR_Pos (0)
7360 #define RTC_FCR_FCR_Msk (0x3ffffful << RTC_FCR_FCR_Pos)
7362 #define RTC_TLR_1SEC_Pos (0)
7363 #define RTC_TLR_1SEC_Msk (0xful << RTC_TLR_1SEC_Pos)
7365 #define RTC_TLR_10SEC_Pos (4)
7366 #define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos)
7368 #define RTC_TLR_1MIN_Pos (8)
7369 #define RTC_TLR_1MIN_Msk (0xful << RTC_TLR_1MIN_Pos)
7371 #define RTC_TLR_10MIN_Pos (12)
7372 #define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos)
7374 #define RTC_TLR_1HR_Pos (16)
7375 #define RTC_TLR_1HR_Msk (0xful << RTC_TLR_1HR_Pos)
7377 #define RTC_TLR_10HR_Pos (20)
7378 #define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos)
7380 #define RTC_CLR_1DAY_Pos (0)
7381 #define RTC_CLR_1DAY_Msk (0xful << RTC_CLR_1DAY_Pos)
7383 #define RTC_CLR_10DAY_Pos (4)
7384 #define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos)
7386 #define RTC_CLR_1MON_Pos (8)
7387 #define RTC_CLR_1MON_Msk (0xful << RTC_CLR_1MON_Pos)
7389 #define RTC_CLR_10MON_Pos (12)
7390 #define RTC_CLR_10MON_Msk (0x1ul << RTC_CLR_10MON_Pos)
7392 #define RTC_CLR_1YEAR_Pos (16)
7393 #define RTC_CLR_1YEAR_Msk (0xful << RTC_CLR_1YEAR_Pos)
7395 #define RTC_CLR_10YEAR_Pos (20)
7396 #define RTC_CLR_10YEAR_Msk (0xful << RTC_CLR_10YEAR_Pos)
7398 #define RTC_TSSR_24H_12H_Pos (0)
7399 #define RTC_TSSR_24H_12H_Msk (0x1ul << RTC_TSSR_24H_12H_Pos)
7401 #define RTC_DWR_DWR_Pos (0)
7402 #define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos)
7404 #define RTC_TAR_1SEC_Pos (0)
7405 #define RTC_TAR_1SEC_Msk (0xful << RTC_TAR_1SEC_Pos)
7407 #define RTC_TAR_10SEC_Pos (4)
7408 #define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos)
7410 #define RTC_TAR_1MIN_Pos (8)
7411 #define RTC_TAR_1MIN_Msk (0xful << RTC_TAR_1MIN_Pos)
7413 #define RTC_TAR_10MIN_Pos (12)
7414 #define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos)
7416 #define RTC_TAR_1HR_Pos (16)
7417 #define RTC_TAR_1HR_Msk (0xful << RTC_TAR_1HR_Pos)
7419 #define RTC_TAR_10HR_Pos (20)
7420 #define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos)
7422 #define RTC_CAR_1DAY_Pos (0)
7423 #define RTC_CAR_1DAY_Msk (0xful << RTC_CAR_1DAY_Pos)
7425 #define RTC_CAR_10DAY_Pos (4)
7426 #define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos)
7428 #define RTC_CAR_1MON_Pos (8)
7429 #define RTC_CAR_1MON_Msk (0xful << RTC_CAR_1MON_Pos)
7431 #define RTC_CAR_10MON_Pos (12)
7432 #define RTC_CAR_10MON_Msk (0x1ul << RTC_CAR_10MON_Pos)
7434 #define RTC_CAR_1YEAR_Pos (16)
7435 #define RTC_CAR_1YEAR_Msk (0xful << RTC_CAR_1YEAR_Pos)
7437 #define RTC_CAR_10YEAR_Pos (20)
7438 #define RTC_CAR_10YEAR_Msk (0xful << RTC_CAR_10YEAR_Pos)
7440 #define RTC_LIR_LIR_Pos (0)
7441 #define RTC_LIR_LIR_Msk (0x1ul << RTC_LIR_LIR_Pos)
7443 #define RTC_RIER_AIER_Pos (0)
7444 #define RTC_RIER_AIER_Msk (0x1ul << RTC_RIER_AIER_Pos)
7446 #define RTC_RIER_TIER_Pos (1)
7447 #define RTC_RIER_TIER_Msk (0x1ul << RTC_RIER_TIER_Pos)
7449 #define RTC_RIER_SNOOPIER_Pos (2)
7450 #define RTC_RIER_SNOOPIER_Msk (0x1ul << RTC_RIER_SNOOPIER_Pos)
7452 #define RTC_RIIR_AIF_Pos (0)
7453 #define RTC_RIIR_AIF_Msk (0x1ul << RTC_RIIR_AIF_Pos)
7455 #define RTC_RIIR_TIF_Pos (1)
7456 #define RTC_RIIR_TIF_Msk (0x1ul << RTC_RIIR_TIF_Pos)
7458 #define RTC_RIIR_SNOOPIF_Pos (2)
7459 #define RTC_RIIR_SNOOPIF_Msk (0x1ul << RTC_RIIR_SNOOPIF_Pos)
7461 #define RTC_TTR_TTR_Pos (0)
7462 #define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos)
7464 #define RTC_TTR_TWKE_Pos (3)
7465 #define RTC_TTR_TWKE_Msk (0x1ul << RTC_TTR_TWKE_Pos)
7467 #define RTC_SPRCTL_SNOOPEN_Pos (0)
7468 #define RTC_SPRCTL_SNOOPEN_Msk (0x1ul << RTC_SPRCTL_SNOOPEN_Pos)
7470 #define RTC_SPRCTL_SNOOPEDGE_Pos (1)
7471 #define RTC_SPRCTL_SNOOPEDGE_Msk (0x1ul << RTC_SPRCTL_SNOOPEDGE_Pos)
7473 #define RTC_SPR0_SPARE_Pos (0)
7474 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos)
7476 #define RTC_SPR1_SPARE_Pos (0)
7477 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos)
7479 #define RTC_SPR2_SPARE_Pos (0)
7480 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos)
7482 #define RTC_SPR3_SPARE_Pos (0)
7483 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos)
7485 #define RTC_SPR4_SPARE_Pos (0)
7486 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos)
7488 #define RTC_SPR5_SPARE_Pos (0)
7489 #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos)
7491 #define RTC_SPR6_SPARE_Pos (0)
7492 #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos)
7494 #define RTC_SPR7_SPARE_Pos (0)
7495 #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos)
7497 #define RTC_SPR8_SPARE_Pos (0)
7498 #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos)
7500 #define RTC_SPR9_SPARE_Pos (0)
7501 #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos)
7503 #define RTC_SPR10_SPARE_Pos (0)
7504 #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos)
7506 #define RTC_SPR11_SPARE_Pos (0)
7507 #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos)
7509 #define RTC_SPR12_SPARE_Pos (0)
7510 #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos)
7512 #define RTC_SPR13_SPARE_Pos (0)
7513 #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos)
7515 #define RTC_SPR14_SPARE_Pos (0)
7516 #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos)
7518 #define RTC_SPR15_SPARE_Pos (0)
7519 #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos)
7521 #define RTC_SPR16_SPARE_Pos (0)
7522 #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos)
7524 #define RTC_SPR17_SPARE_Pos (0)
7525 #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos)
7527 #define RTC_SPR18_SPARE_Pos (0)
7528 #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos)
7530 #define RTC_SPR19_SPARE_Pos (0)
7531 #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /* RTC_CONST */
7534 /* end of RTC register group */
7535
7536
7537 /*---------------------- Smart Card Host Interface Controller -------------------------*/
7543 typedef struct
7544 {
7545
7546
7547 union
7548 {
7559 __I uint32_t RBR;
7570 __O uint32_t THR;
7571 };
7572
7658 __IO uint32_t CTL;
7659
7748 __IO uint32_t ALTCTL;
7749
7761 __IO uint32_t EGTR;
7762
7776 __IO uint32_t RFTMR;
7777
7796 __IO uint32_t ETUCR;
7797
7852 __IO uint32_t IER;
7853
7904 __IO uint32_t ISR;
7905
7979 __IO uint32_t TRSR;
7980
8055 __IO uint32_t PINCSR;
8056
8069 __IO uint32_t TMR0;
8070
8083 __IO uint32_t TMR1;
8084
8097 __IO uint32_t TMR2;
8098
8127 __IO uint32_t UACTL;
8128
8139 __I uint32_t TDRA;
8140
8153 __I uint32_t TDRB;
8154
8155 } SC_T;
8156
8162 #define SC_DAT_DAT_Pos (0)
8163 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
8165 #define SC_CTL_SC_CEN_Pos (0)
8166 #define SC_CTL_SC_CEN_Msk (0x1ul << SC_CTL_SC_CEN_Pos)
8168 #define SC_CTL_DIS_RX_Pos (1)
8169 #define SC_CTL_DIS_RX_Msk (0x1ul << SC_CTL_DIS_RX_Pos)
8171 #define SC_CTL_DIS_TX_Pos (2)
8172 #define SC_CTL_DIS_TX_Msk (0x1ul << SC_CTL_DIS_TX_Pos)
8174 #define SC_CTL_AUTO_CON_EN_Pos (3)
8175 #define SC_CTL_AUTO_CON_EN_Msk (0x1ul << SC_CTL_AUTO_CON_EN_Pos)
8177 #define SC_CTL_CON_SEL_Pos (4)
8178 #define SC_CTL_CON_SEL_Msk (0x3ul << SC_CTL_CON_SEL_Pos)
8180 #define SC_CTL_RX_FTRI_LEV_Pos (6)
8181 #define SC_CTL_RX_FTRI_LEV_Msk (0x3ul << SC_CTL_RX_FTRI_LEV_Pos)
8183 #define SC_CTL_BGT_Pos (8)
8184 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
8186 #define SC_CTL_TMR_SEL_Pos (13)
8187 #define SC_CTL_TMR_SEL_Msk (0x3ul << SC_CTL_TMR_SEL_Pos)
8189 #define SC_CTL_SLEN_Pos (15)
8190 #define SC_CTL_SLEN_Msk (0x1ul << SC_CTL_SLEN_Pos)
8192 #define SC_CTL_RX_ERETRY_Pos (16)
8193 #define SC_CTL_RX_ERETRY_Msk (0x7ul << SC_CTL_RX_ERETRY_Pos)
8195 #define SC_CTL_RX_ERETRY_EN_Pos (19)
8196 #define SC_CTL_RX_ERETRY_EN_Msk (0x1ul << SC_CTL_RX_ERETRY_EN_Pos)
8198 #define SC_CTL_TX_ERETRY_Pos (20)
8199 #define SC_CTL_TX_ERETRY_Msk (0x7ul << SC_CTL_TX_ERETRY_Pos)
8201 #define SC_CTL_TX_ERETRY_EN_Pos (23)
8202 #define SC_CTL_TX_ERETRY_EN_Msk (0x1ul << SC_CTL_TX_ERETRY_EN_Pos)
8204 #define SC_CTL_CD_DEB_SEL_Pos (24)
8205 #define SC_CTL_CD_DEB_SEL_Msk (0x3ul << SC_CTL_CD_DEB_SEL_Pos)
8207 #define SC_ALTCTL_TX_RST_Pos (0)
8208 #define SC_ALTCTL_TX_RST_Msk (0x1ul << SC_ALTCTL_TX_RST_Pos)
8210 #define SC_ALTCTL_RX_RST_Pos (1)
8211 #define SC_ALTCTL_RX_RST_Msk (0x1ul << SC_ALTCTL_RX_RST_Pos)
8213 #define SC_ALTCTL_DACT_EN_Pos (2)
8214 #define SC_ALTCTL_DACT_EN_Msk (0x1ul << SC_ALTCTL_DACT_EN_Pos)
8216 #define SC_ALTCTL_ACT_EN_Pos (3)
8217 #define SC_ALTCTL_ACT_EN_Msk (0x1ul << SC_ALTCTL_ACT_EN_Pos)
8219 #define SC_ALTCTL_WARST_EN_Pos (4)
8220 #define SC_ALTCTL_WARST_EN_Msk (0x1ul << SC_ALTCTL_WARST_EN_Pos)
8222 #define SC_ALTCTL_TMR0_SEN_Pos (5)
8223 #define SC_ALTCTL_TMR0_SEN_Msk (0x1ul << SC_ALTCTL_TMR0_SEN_Pos)
8225 #define SC_ALTCTL_TMR1_SEN_Pos (6)
8226 #define SC_ALTCTL_TMR1_SEN_Msk (0x1ul << SC_ALTCTL_TMR1_SEN_Pos)
8228 #define SC_ALTCTL_TMR2_SEN_Pos (7)
8229 #define SC_ALTCTL_TMR2_SEN_Msk (0x1ul << SC_ALTCTL_TMR2_SEN_Pos)
8231 #define SC_ALTCTL_INIT_SEL_Pos (8)
8232 #define SC_ALTCTL_INIT_SEL_Msk (0x3ul << SC_ALTCTL_INIT_SEL_Pos)
8234 #define SC_ALTCTL_RX_BGT_EN_Pos (12)
8235 #define SC_ALTCTL_RX_BGT_EN_Msk (0x1ul << SC_ALTCTL_RX_BGT_EN_Pos)
8237 #define SC_ALTCTL_TMR0_ATV_Pos (13)
8238 #define SC_ALTCTL_TMR0_ATV_Msk (0x1ul << SC_ALTCTL_TMR0_ATV_Pos)
8240 #define SC_ALTCTL_TMR1_ATV_Pos (14)
8241 #define SC_ALTCTL_TMR1_ATV_Msk (0x1ul << SC_ALTCTL_TMR1_ATV_Pos)
8243 #define SC_ALTCTL_TMR2_ATV_Pos (15)
8244 #define SC_ALTCTL_TMR2_ATV_Msk (0x1ul << SC_ALTCTL_TMR2_ATV_Pos)
8246 #define SC_EGTR_EGT_Pos (0)
8247 #define SC_EGTR_EGT_Msk (0xfful << SC_EGTR_EGT_Pos)
8249 #define SC_RFTMR_RFTM_Pos (0)
8250 #define SC_RFTMR_RFTM_Msk (0x1fful << SC_RFTMR_RFTM_Pos)
8252 #define SC_ETUCR_ETU_RDIV_Pos (0)
8253 #define SC_ETUCR_ETU_RDIV_Msk (0xffful << SC_ETUCR_ETU_RDIV_Pos)
8255 #define SC_ETUCR_COMPEN_EN_Pos (15)
8256 #define SC_ETUCR_COMPEN_EN_Msk (0x1ul << SC_ETUCR_COMPEN_EN_Pos)
8258 #define SC_IER_RDA_IE_Pos (0)
8259 #define SC_IER_RDA_IE_Msk (0x1ul << SC_IER_RDA_IE_Pos)
8261 #define SC_IER_TBE_IE_Pos (1)
8262 #define SC_IER_TBE_IE_Msk (0x1ul << SC_IER_TBE_IE_Pos)
8264 #define SC_IER_TERR_IE_Pos (2)
8265 #define SC_IER_TERR_IE_Msk (0x1ul << SC_IER_TERR_IE_Pos)
8267 #define SC_IER_TMR0_IE_Pos (3)
8268 #define SC_IER_TMR0_IE_Msk (0x1ul << SC_IER_TMR0_IE_Pos)
8270 #define SC_IER_TMR1_IE_Pos (4)
8271 #define SC_IER_TMR1_IE_Msk (0x1ul << SC_IER_TMR1_IE_Pos)
8273 #define SC_IER_TMR2_IE_Pos (5)
8274 #define SC_IER_TMR2_IE_Msk (0x1ul << SC_IER_TMR2_IE_Pos)
8276 #define SC_IER_BGT_IE_Pos (6)
8277 #define SC_IER_BGT_IE_Msk (0x1ul << SC_IER_BGT_IE_Pos)
8279 #define SC_IER_CD_IE_Pos (7)
8280 #define SC_IER_CD_IE_Msk (0x1ul << SC_IER_CD_IE_Pos)
8282 #define SC_IER_INIT_IE_Pos (8)
8283 #define SC_IER_INIT_IE_Msk (0x1ul << SC_IER_INIT_IE_Pos)
8285 #define SC_IER_RTMR_IE_Pos (9)
8286 #define SC_IER_RTMR_IE_Msk (0x1ul << SC_IER_RTMR_IE_Pos)
8288 #define SC_IER_ACON_ERR_IE_Pos (10)
8289 #define SC_IER_ACON_ERR_IE_Msk (0x1ul << SC_IER_ACON_ERR_IE_Pos)
8291 #define SC_ISR_RDA_IS_Pos (0)
8292 #define SC_ISR_RDA_IS_Msk (0x1ul << SC_ISR_RDA_IS_Pos)
8294 #define SC_ISR_TBE_IS_Pos (1)
8295 #define SC_ISR_TBE_IS_Msk (0x1ul << SC_ISR_TBE_IS_Pos)
8297 #define SC_ISR_TERR_IS_Pos (2)
8298 #define SC_ISR_TERR_IS_Msk (0x1ul << SC_ISR_TERR_IS_Pos)
8300 #define SC_ISR_TMR0_IS_Pos (3)
8301 #define SC_ISR_TMR0_IS_Msk (0x1ul << SC_ISR_TMR0_IS_Pos)
8303 #define SC_ISR_TMR1_IS_Pos (4)
8304 #define SC_ISR_TMR1_IS_Msk (0x1ul << SC_ISR_TMR1_IS_Pos)
8306 #define SC_ISR_TMR2_IS_Pos (5)
8307 #define SC_ISR_TMR2_IS_Msk (0x1ul << SC_ISR_TMR2_IS_Pos)
8309 #define SC_ISR_BGT_IS_Pos (6)
8310 #define SC_ISR_BGT_IS_Msk (0x1ul << SC_ISR_BGT_IS_Pos)
8312 #define SC_ISR_CD_IS_Pos (7)
8313 #define SC_ISR_CD_IS_Msk (0x1ul << SC_ISR_CD_IS_Pos)
8315 #define SC_ISR_INIT_IS_Pos (8)
8316 #define SC_ISR_INIT_IS_Msk (0x1ul << SC_ISR_INIT_IS_Pos)
8318 #define SC_ISR_RTMR_IS_Pos (9)
8319 #define SC_ISR_RTMR_IS_Msk (0x1ul << SC_ISR_RTMR_IS_Pos)
8321 #define SC_ISR_ACON_ERR_IS_Pos (10)
8322 #define SC_ISR_ACON_ERR_IS_Msk (0x1ul << SC_ISR_ACON_ERR_IS_Pos)
8324 #define SC_TRSR_RX_OVER_F_Pos (0)
8325 #define SC_TRSR_RX_OVER_F_Msk (0x1ul << SC_TRSR_RX_OVER_F_Pos)
8327 #define SC_TRSR_RX_EMPTY_F_Pos (1)
8328 #define SC_TRSR_RX_EMPTY_F_Msk (0x1ul << SC_TRSR_RX_EMPTY_F_Pos)
8330 #define SC_TRSR_RX_FULL_F_Pos (2)
8331 #define SC_TRSR_RX_FULL_F_Msk (0x1ul << SC_TRSR_RX_FULL_F_Pos)
8333 #define SC_TRSR_RX_EPA_F_Pos (4)
8334 #define SC_TRSR_RX_EPA_F_Msk (0x1ul << SC_TRSR_RX_EPA_F_Pos)
8336 #define SC_TRSR_RX_EFR_F_Pos (5)
8337 #define SC_TRSR_RX_EFR_F_Msk (0x1ul << SC_TRSR_RX_EFR_F_Pos)
8339 #define SC_TRSR_RX_EBR_F_Pos (6)
8340 #define SC_TRSR_RX_EBR_F_Msk (0x1ul << SC_TRSR_RX_EBR_F_Pos)
8342 #define SC_TRSR_TX_OVER_F_Pos (8)
8343 #define SC_TRSR_TX_OVER_F_Msk (0x1ul << SC_TRSR_TX_OVER_F_Pos)
8345 #define SC_TRSR_TX_EMPTY_F_Pos (9)
8346 #define SC_TRSR_TX_EMPTY_F_Msk (0x1ul << SC_TRSR_TX_EMPTY_F_Pos)
8348 #define SC_TRSR_TX_FULL_F_Pos (10)
8349 #define SC_TRSR_TX_FULL_F_Msk (0x1ul << SC_TRSR_TX_FULL_F_Pos)
8351 #define SC_TRSR_RX_POINT_F_Pos (16)
8352 #define SC_TRSR_RX_POINT_F_Msk (0x7ul << SC_TRSR_RX_POINT_F_Pos)
8354 #define SC_TRSR_RX_REERR_Pos (21)
8355 #define SC_TRSR_RX_REERR_Msk (0x1ul << SC_TRSR_RX_REERR_Pos)
8357 #define SC_TRSR_RX_OVER_ERETRY_Pos (22)
8358 #define SC_TRSR_RX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_RX_OVER_ERETRY_Pos)
8360 #define SC_TRSR_RX_ATV_Pos (23)
8361 #define SC_TRSR_RX_ATV_Msk (0x1ul << SC_TRSR_RX_ATV_Pos)
8363 #define SC_TRSR_TX_POINT_F_Pos (24)
8364 #define SC_TRSR_TX_POINT_F_Msk (0x7ul << SC_TRSR_TX_POINT_F_Pos)
8366 #define SC_TRSR_TX_REERR_Pos (29)
8367 #define SC_TRSR_TX_REERR_Msk (0x1ul << SC_TRSR_TX_REERR_Pos)
8369 #define SC_TRSR_TX_OVER_ERETRY_Pos (30)
8370 #define SC_TRSR_TX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_TX_OVER_ERETRY_Pos)
8372 #define SC_TRSR_TX_ATV_Pos (31)
8373 #define SC_TRSR_TX_ATV_Msk (0x1ul << SC_TRSR_TX_ATV_Pos)
8375 #define SC_PINCSR_POW_EN_Pos (0)
8376 #define SC_PINCSR_POW_EN_Msk (0x1ul << SC_PINCSR_POW_EN_Pos)
8378 #define SC_PINCSR_SC_RST_Pos (1)
8379 #define SC_PINCSR_SC_RST_Msk (0x1ul << SC_PINCSR_SC_RST_Pos)
8381 #define SC_PINCSR_CD_REM_F_Pos (2)
8382 #define SC_PINCSR_CD_REM_F_Msk (0x1ul << SC_PINCSR_CD_REM_F_Pos)
8384 #define SC_PINCSR_CD_INS_F_Pos (3)
8385 #define SC_PINCSR_CD_INS_F_Msk (0x1ul << SC_PINCSR_CD_INS_F_Pos)
8387 #define SC_PINCSR_CD_PIN_ST_Pos (4)
8388 #define SC_PINCSR_CD_PIN_ST_Msk (0x1ul << SC_PINCSR_CD_PIN_ST_Pos)
8390 #define SC_PINCSR_CLK_KEEP_Pos (6)
8391 #define SC_PINCSR_CLK_KEEP_Msk (0x1ul << SC_PINCSR_CLK_KEEP_Pos)
8393 #define SC_PINCSR_ADAC_CD_EN_Pos (7)
8394 #define SC_PINCSR_ADAC_CD_EN_Msk (0x1ul << SC_PINCSR_ADAC_CD_EN_Pos)
8396 #define SC_PINCSR_SC_OEN_ST_Pos (8)
8397 #define SC_PINCSR_SC_OEN_ST_Msk (0x1ul << SC_PINCSR_SC_OEN_ST_Pos)
8399 #define SC_PINCSR_SC_DATA_O_Pos (9)
8400 #define SC_PINCSR_SC_DATA_O_Msk (0x1ul << SC_PINCSR_SC_DATA_O_Pos)
8402 #define SC_PINCSR_CD_LEV_Pos (10)
8403 #define SC_PINCSR_CD_LEV_Msk (0x1ul << SC_PINCSR_CD_LEV_Pos)
8405 #define SC_PINCSR_POW_INV_Pos (11)
8406 #define SC_PINCSR_POW_INV_Msk (0x1ul << SC_PINCSR_POW_INV_Pos)
8408 #define SC_PINCSR_SC_DATA_I_ST_Pos (16)
8409 #define SC_PINCSR_SC_DATA_I_ST_Msk (0x1ul << SC_PINCSR_SC_DATA_I_ST_Pos)
8411 #define SC_TMR0_CNT_Pos (0)
8412 #define SC_TMR0_CNT_Msk (0xfffffful << SC_TMR0_CNT_Pos)
8414 #define SC_TMR0_MODE_Pos (24)
8415 #define SC_TMR0_MODE_Msk (0xful << SC_TMR0_MODE_Pos)
8417 #define SC_TMR1_CNT_Pos (0)
8418 #define SC_TMR1_CNT_Msk (0xfful << SC_TMR1_CNT_Pos)
8420 #define SC_TMR1_MODE_Pos (24)
8421 #define SC_TMR1_MODE_Msk (0xful << SC_TMR1_MODE_Pos)
8423 #define SC_TMR2_CNT_Pos (0)
8424 #define SC_TMR2_CNT_Msk (0xfful << SC_TMR2_CNT_Pos)
8426 #define SC_TMR2_MODE_Pos (24)
8427 #define SC_TMR2_MODE_Msk (0xful << SC_TMR2_MODE_Pos)
8429 #define SC_UACTL_UA_MODE_EN_Pos (0)
8430 #define SC_UACTL_UA_MODE_EN_Msk (0x1ul << SC_UACTL_UA_MODE_EN_Pos)
8432 #define SC_UACTL_DATA_LEN_Pos (4)
8433 #define SC_UACTL_DATA_LEN_Msk (0x3ul << SC_UACTL_DATA_LEN_Pos)
8435 #define SC_UACTL_PBDIS_Pos (6)
8436 #define SC_UACTL_PBDIS_Msk (0x1ul << SC_UACTL_PBDIS_Pos)
8438 #define SC_UACTL_OPE_Pos (7)
8439 #define SC_UACTL_OPE_Msk (0x1ul << SC_UACTL_OPE_Pos)
8441 #define SC_TDRA_TDR0_Pos (0)
8442 #define SC_TDRA_TDR0_Msk (0xfffffful << SC_TDRA_TDR0_Pos)
8444 #define SC_TDRB_TDR1_Pos (0)
8445 #define SC_TDRB_TDR1_Msk (0xfful << SC_TDRB_TDR1_Pos)
8447 #define SC_TDRB_TDR2_Pos (8)
8448 #define SC_TDRB_TDR2_Msk (0xfful << SC_TDRB_TDR2_Pos) /* SC_CONST */
8451 /* end of SC register group */
8452
8453
8454 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
8460 typedef struct
8461 {
8462
8463
8551 __IO uint32_t CTL;
8552
8607 __IO uint32_t STATUS;
8608
8625 __IO uint32_t CLKDIV;
8626
8685 __IO uint32_t SSR;
8686
8703 __I uint32_t RX0;
8704
8721 __I uint32_t RX1;
8722 uint32_t RESERVE0[2];
8723
8724
8743 __O uint32_t TX0;
8744
8763 __O uint32_t TX1;
8764 uint32_t RESERVE1[3];
8765
8766
8778 __IO uint32_t VARCLK;
8779
8804 __IO uint32_t DMA;
8805
8842 __IO uint32_t FFCTL;
8843 uint32_t RESERVE2[4];
8844
8845 } SPI_T;
8846
8852 #define SPI_CTL_GO_BUSY_Pos (0)
8853 #define SPI_CTL_GO_BUSY_Msk (0x1ul << SPI_CTL_GO_BUSY_Pos)
8855 #define SPI_CTL_RX_NEG_Pos (1)
8856 #define SPI_CTL_RX_NEG_Msk (0x1ul << SPI_CTL_RX_NEG_Pos)
8858 #define SPI_CTL_TX_NEG_Pos (2)
8859 #define SPI_CTL_TX_NEG_Msk (0x1ul << SPI_CTL_TX_NEG_Pos)
8861 #define SPI_CTL_TX_BIT_LEN_Pos (3)
8862 #define SPI_CTL_TX_BIT_LEN_Msk (0x1ful << SPI_CTL_TX_BIT_LEN_Pos)
8864 #define SPI_CTL_LSB_Pos (10)
8865 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
8867 #define SPI_CTL_CLKP_Pos (11)
8868 #define SPI_CTL_CLKP_Msk (0x1ul << SPI_CTL_CLKP_Pos)
8870 #define SPI_CTL_SP_CYCLE_Pos (12)
8871 #define SPI_CTL_SP_CYCLE_Msk (0xful << SPI_CTL_SP_CYCLE_Pos)
8873 #define SPI_CTL_INTEN_Pos (17)
8874 #define SPI_CTL_INTEN_Msk (0x1ul << SPI_CTL_INTEN_Pos)
8876 #define SPI_CTL_SLAVE_Pos (18)
8877 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
8879 #define SPI_CTL_REORDER_Pos (19)
8880 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
8882 #define SPI_CTL_FIFOM_Pos (21)
8883 #define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos)
8885 #define SPI_CTL_TWOB_Pos (22)
8886 #define SPI_CTL_TWOB_Msk (0x1ul << SPI_CTL_TWOB_Pos)
8888 #define SPI_CTL_VARCLK_EN_Pos (23)
8889 #define SPI_CTL_VARCLK_EN_Msk (0x1ul << SPI_CTL_VARCLK_EN_Pos)
8891 #define SPI_CTL_DUAL_IO_DIR_Pos (28)
8892 #define SPI_CTL_DUAL_IO_DIR_Msk (0x1ul << SPI_CTL_DUAL_IO_DIR_Pos)
8894 #define SPI_CTL_DUAL_IO_EN_Pos (29)
8895 #define SPI_CTL_DUAL_IO_EN_Msk (0x1ul << SPI_CTL_DUAL_IO_EN_Pos)
8897 #define SPI_CTL_WKEUP_EN_Pos (31)
8898 #define SPI_CTL_WKEUP_EN_Msk (0x1ul << SPI_CTL_WKEUP_EN_Pos)
8900 #define SPI_STATUS_RX_EMPTY_Pos (0)
8901 #define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos)
8903 #define SPI_STATUS_RX_FULL_Pos (1)
8904 #define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos)
8906 #define SPI_STATUS_TX_EMPTY_Pos (2)
8907 #define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos)
8909 #define SPI_STATUS_TX_FULL_Pos (3)
8910 #define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos)
8912 #define SPI_STATUS_LTRIG_FLAG_Pos (4)
8913 #define SPI_STATUS_LTRIG_FLAG_Msk (0x1ul << SPI_STATUS_LTRIG_FLAG_Pos)
8915 #define SPI_STATUS_SLV_START_INTSTS_Pos (6)
8916 #define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos)
8918 #define SPI_STATUS_INTSTS_Pos (7)
8919 #define SPI_STATUS_INTSTS_Msk (0x1ul << SPI_STATUS_INTSTS_Pos)
8921 #define SPI_STATUS_RXINT_STS_Pos (8)
8922 #define SPI_STATUS_RXINT_STS_Msk (0x1ul << SPI_STATUS_RXINT_STS_Pos)
8924 #define SPI_STATUS_RX_OVER_RUN_Pos (9)
8925 #define SPI_STATUS_RX_OVER_RUN_Msk (0x1ul << SPI_STATUS_RX_OVER_RUN_Pos)
8927 #define SPI_STATUS_TXINT_STS_Pos (10)
8928 #define SPI_STATUS_TXINT_STS_Msk (0x1ul << SPI_STATUS_TXINT_STS_Pos)
8930 #define SPI_STATUS_TIME_OUT_STS_Pos (12)
8931 #define SPI_STATUS_TIME_OUT_STS_Msk (0x1ul << SPI_STATUS_TIME_OUT_STS_Pos)
8933 #define SPI_STATUS_RX_FIFO_CNT_Pos (16)
8934 #define SPI_STATUS_RX_FIFO_CNT_Msk (0xful << SPI_STATUS_RX_FIFO_CNT_Pos)
8936 #define SPI_STATUS_TX_FIFO_CNT_Pos (20)
8937 #define SPI_STATUS_TX_FIFO_CNT_Msk (0xful << SPI_STATUS_TX_FIFO_CNT_Pos)
8939 #define SPI_CLKDIV_DIVIDER1_Pos (0)
8940 #define SPI_CLKDIV_DIVIDER1_Msk (0xfful << SPI_CLKDIV_DIVIDER1_Pos)
8942 #define SPI_CLKDIV_DIVIDER2_Pos (16)
8943 #define SPI_CLKDIV_DIVIDER2_Msk (0xfful << SPI_CLKDIV_DIVIDER2_Pos)
8945 #define SPI_SSR_SSR_Pos (0)
8946 #define SPI_SSR_SSR_Msk (0x3ul << SPI_SSR_SSR_Pos)
8948 #define SPI_SSR_SS_LVL_Pos (2)
8949 #define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos)
8951 #define SPI_SSR_AUTOSS_Pos (3)
8952 #define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos)
8954 #define SPI_SSR_SS_LTRIG_Pos (4)
8955 #define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos)
8957 #define SPI_SSR_NOSLVSEL_Pos (5)
8958 #define SPI_SSR_NOSLVSEL_Msk (0x1ul << SPI_SSR_NOSLVSEL_Pos)
8960 #define SPI_SSR_SLV_ABORT_Pos (8)
8961 #define SPI_SSR_SLV_ABORT_Msk (0x1ul << SPI_SSR_SLV_ABORT_Pos)
8963 #define SPI_SSR_SSTA_INTEN_Pos (9)
8964 #define SPI_SSR_SSTA_INTEN_Msk (0x1ul << SPI_SSR_SSTA_INTEN_Pos)
8966 #define SPI_SSR_SS_INT_OPT_Pos (16)
8967 #define SPI_SSR_SS_INT_OPT_Msk (0x1ul << SPI_SSR_SS_INT_OPT_Pos)
8969 #define SPI_RX0_RDATA_Pos (0)
8970 #define SPI_RX0_RDATA_Msk (0xfffffffful << SPI_RX0_RDATA_Pos)
8972 #define SPI_RX1_RDATA_Pos (0)
8973 #define SPI_RX1_RDATA_Msk (0xfffffffful << SPI_RX1_RDATA_Pos)
8975 #define SPI_TX0_TDATA_Pos (0)
8976 #define SPI_TX0_TDATA_Msk (0xfffffffful << SPI_TX0_TDATA_Pos)
8978 #define SPI_TX1_TDATA_Pos (0)
8979 #define SPI_TX1_TDATA_Msk (0xfffffffful << SPI_TX1_TDATA_Pos)
8981 #define SPI_VARCLK_VARCLK_Pos (0)
8982 #define SPI_VARCLK_VARCLK_Msk (0xfffffffful << SPI_VARCLK_VARCLK_Pos)
8984 #define SPI_DMA_TX_DMA_EN_Pos (0)
8985 #define SPI_DMA_TX_DMA_EN_Msk (0x1ul << SPI_DMA_TX_DMA_EN_Pos)
8987 #define SPI_DMA_RX_DMA_EN_Pos (1)
8988 #define SPI_DMA_RX_DMA_EN_Msk (0x1ul << SPI_DMA_RX_DMA_EN_Pos)
8990 #define SPI_DMA_PDMA_RST_Pos (2)
8991 #define SPI_DMA_PDMA_RST_Msk (0x1ul << SPI_DMA_PDMA_RST_Pos)
8993 #define SPI_FFCTL_RX_CLR_Pos (0)
8994 #define SPI_FFCTL_RX_CLR_Msk (0x1ul << SPI_FFCTL_RX_CLR_Pos)
8996 #define SPI_FFCTL_TX_CLR_Pos (1)
8997 #define SPI_FFCTL_TX_CLR_Msk (0x1ul << SPI_FFCTL_TX_CLR_Pos)
8999 #define SPI_FFCTL_RX_INTEN_Pos (2)
9000 #define SPI_FFCTL_RX_INTEN_Msk (0x1ul << SPI_FFCTL_RX_INTEN_Pos)
9002 #define SPI_FFCTL_TX_INTEN_Pos (3)
9003 #define SPI_FFCTL_TX_INTEN_Msk (0x1ul << SPI_FFCTL_TX_INTEN_Pos)
9005 #define SPI_FFCTL_RXOVR_INTEN_Pos (4)
9006 #define SPI_FFCTL_RXOVR_INTEN_Msk (0x1ul << SPI_FFCTL_RXOVR_INTEN_Pos)
9008 #define SPI_FFCTL_TIMEOUT_EN_Pos (7)
9009 #define SPI_FFCTL_TIMEOUT_EN_Msk (0x1ul << SPI_FFCTL_TIMEOUT_EN_Pos)
9011 #define SPI_FFCTL_RX_THRESHOLD_Pos (24)
9012 #define SPI_FFCTL_RX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_RX_THRESHOLD_Pos)
9014 #define SPI_FFCTL_TX_THRESHOLD_Pos (28)
9015 #define SPI_FFCTL_TX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_TX_THRESHOLD_Pos) /* SPI_CONST */
9018 /* end of SPI register group */
9019
9020
9021 /*---------------------- Timer Controller -------------------------*/
9027 typedef struct
9028 {
9029
9030
9178 __IO uint32_t CTL;
9179
9191 __IO uint32_t PRECNT;
9192
9208 __IO uint32_t CMPR;
9209
9226 __IO uint32_t IER;
9227
9263 __IO uint32_t ISR;
9264
9287 __IO uint32_t DR;
9288
9302 __I uint32_t TCAP;
9303 uint32_t RESERVE0[1];
9304
9305
9343 __IO uint32_t ECTL;
9344
9345 } TIMER_T;
9346
9352 #define TIMER_CTL_TMR_EN_Pos (0)
9353 #define TIMER_CTL_TMR_EN_Msk (0x1ul << TIMER_CTL_TMR_EN_Pos)
9355 #define TIMER_CTL_SW_RST_Pos (1)
9356 #define TIMER_CTL_SW_RST_Msk (0x1ul << TIMER_CTL_SW_RST_Pos)
9358 #define TIMER_CTL_WAKE_EN_Pos (2)
9359 #define TIMER_CTL_WAKE_EN_Msk (0x1ul << TIMER_CTL_WAKE_EN_Pos)
9361 #define TIMER_CTL_DBGACK_EN_Pos (3)
9362 #define TIMER_CTL_DBGACK_EN_Msk (0x1ul << TIMER_CTL_DBGACK_EN_Pos)
9364 #define TIMER_CTL_MODE_SEL_Pos (4)
9365 #define TIMER_CTL_MODE_SEL_Msk (0x3ul << TIMER_CTL_MODE_SEL_Pos)
9367 #define TIMER_CTL_ACMP_EN_TMR_Pos (6)
9368 #define TIMER_CTL_ACMP_EN_TMR_Msk (0x1ul << TIMER_CTL_ACMP_EN_TMR_Pos)
9370 #define TIMER_CTL_TMR_ACT_Pos (7)
9371 #define TIMER_CTL_TMR_ACT_Msk (0x1ul << TIMER_CTL_TMR_ACT_Pos)
9373 #define TIMER_CTL_ADC_TEEN_Pos (8)
9374 #define TIMER_CTL_ADC_TEEN_Msk (0x1ul << TIMER_CTL_ADC_TEEN_Pos)
9376 #define TIMER_CTL_DAC_TEEN_Pos (9)
9377 #define TIMER_CTL_DAC_TEEN_Msk (0x1ul << TIMER_CTL_DAC_TEEN_Pos)
9379 #define TIMER_CTL_PDMA_TEEN_Pos (10)
9380 #define TIMER_CTL_PDMA_TEEN_Msk (0x1ul << TIMER_CTL_PDMA_TEEN_Pos)
9382 #define TIMER_CTL_CAP_TRG_EN_Pos (11)
9383 #define TIMER_CTL_CAP_TRG_EN_Msk (0x1ul << TIMER_CTL_CAP_TRG_EN_Pos)
9385 #define TIMER_CTL_EVENT_EN_Pos (12)
9386 #define TIMER_CTL_EVENT_EN_Msk (0x1ul << TIMER_CTL_EVENT_EN_Pos)
9388 #define TIMER_CTL_EVENT_EDGE_Pos (13)
9389 #define TIMER_CTL_EVENT_EDGE_Msk (0x1ul << TIMER_CTL_EVENT_EDGE_Pos)
9391 #define TIMER_CTL_EVNT_DEB_EN_Pos (14)
9392 #define TIMER_CTL_EVNT_DEB_EN_Msk (0x1ul << TIMER_CTL_EVNT_DEB_EN_Pos)
9394 #define TIMER_CTL_TCAP_EN_Pos (16)
9395 #define TIMER_CTL_TCAP_EN_Msk (0x1ul << TIMER_CTL_TCAP_EN_Pos)
9397 #define TIMER_CTL_TCAP_MODE_Pos (17)
9398 #define TIMER_CTL_TCAP_MODE_Msk (0x1ul << TIMER_CTL_TCAP_MODE_Pos)
9400 #define TIMER_CTL_TCAP_EDGE_Pos (18)
9401 #define TIMER_CTL_TCAP_EDGE_Msk (0x3ul << TIMER_CTL_TCAP_EDGE_Pos)
9403 #define TIMER_CTL_TCAP_CNT_MODE_Pos (20)
9404 #define TIMER_CTL_TCAP_CNT_MODE_Msk (0x1ul << TIMER_CTL_TCAP_CNT_MODE_Pos)
9406 #define TIMER_CTL_TCAP_DEB_EN_Pos (22)
9407 #define TIMER_CTL_TCAP_DEB_EN_Msk (0x1ul << TIMER_CTL_TCAP_DEB_EN_Pos)
9409 #define TIMER_CTL_INTR_TRG_EN_Pos (24)
9410 #define TIMER_CTL_INTR_TRG_EN_Msk (0x1ul << TIMER_CTL_INTR_TRG_EN_Pos)
9412 #define TIMER_CTL_INTR_TRG_MODE_Pos (25)
9413 #define TIMER_CTL_INTR_TRG_MODE_Msk (0x1ul << TIMER_CTL_INTR_TRG_MODE_Pos)
9415 #define TIMER_PRECNT_PRESCALE_CNT_Pos (0)
9416 #define TIMER_PRECNT_PRESCALE_CNT_Msk (0xfful << TIMER_PRECNT_PRESCALE_CNT_Pos)
9418 #define TIMER_CMPR_TMR_CMP_Pos (0)
9419 #define TIMER_CMPR_TMR_CMP_Msk (0xfffffful << TIMER_CMPR_TMR_CMP_Pos)
9421 #define TIMER_IER_TMR_IE_Pos (0)
9422 #define TIMER_IER_TMR_IE_Msk (0x1ul << TIMER_IER_TMR_IE_Pos)
9424 #define TIMER_IER_TCAP_IE_Pos (1)
9425 #define TIMER_IER_TCAP_IE_Msk (0x1ul << TIMER_IER_TCAP_IE_Pos)
9427 #define TIMER_ISR_TMR_IS_Pos (0)
9428 #define TIMER_ISR_TMR_IS_Msk (0x1ul << TIMER_ISR_TMR_IS_Pos)
9430 #define TIMER_ISR_TCAP_IS_Pos (1)
9431 #define TIMER_ISR_TCAP_IS_Msk (0x1ul << TIMER_ISR_TCAP_IS_Pos)
9433 #define TIMER_ISR_TMR_WAKE_STS_Pos (4)
9434 #define TIMER_ISR_TMR_WAKE_STS_Msk (0x1ul << TIMER_ISR_TMR_WAKE_STS_Pos)
9436 #define TIMER_ISR_NCAP_DET_STS_Pos (5)
9437 #define TIMER_ISR_NCAP_DET_STS_Msk (0x1ul << TIMER_ISR_NCAP_DET_STS_Pos)
9439 #define TIMER_ISR_TCAP_IS_FEDGE_Pos (6)
9440 #define TIMER_ISR_TCAP_IS_FEDGE_Msk (0x1ul << TIMER_ISR_TCAP_IS_FEDGE_Pos)
9442 #define TIMER_DR_TDR_Pos (0)
9443 #define TIMER_DR_TDR_Msk (0xfffffful << TIMER_DR_TDR_Pos)
9445 #define TIMER_DR_RSTACT_Pos (31)
9446 #define TIMER_DR_RSTACT_Msk (0x1ul << TIMER_DR_RSTACT_Pos)
9448 #define TIMER_TCAP_CAP_Pos (0)
9449 #define TIMER_TCAP_CAP_Msk (0xfffffful << TIMER_TCAP_CAP_Pos)
9451 #define TIMER_ECTL_EVNT_GEN_EN_Pos (0)
9452 #define TIMER_ECTL_EVNT_GEN_EN_Msk (0x1ul << TIMER_ECTL_EVNT_GEN_EN_Pos)
9454 #define TIMER_ECTL_EVNT_GEN_POL_Pos (1)
9455 #define TIMER_ECTL_EVNT_GEN_POL_Msk (0x1ul << TIMER_ECTL_EVNT_GEN_POL_Pos)
9457 #define TIMER_ECTL_EVNT_CNT_SRC_Pos (8)
9458 #define TIMER_ECTL_EVNT_CNT_SRC_Msk (0x1ul << TIMER_ECTL_EVNT_CNT_SRC_Pos)
9460 #define TIMER_ECTL_EVNT_GEN_SRC_Pos (12)
9461 #define TIMER_ECTL_EVNT_GEN_SRC_Msk (0x1ul << TIMER_ECTL_EVNT_GEN_SRC_Pos)
9463 #define TIMER_ECTL_CAP_SRC_Pos (16)
9464 #define TIMER_ECTL_CAP_SRC_Msk (0x1ul << TIMER_ECTL_CAP_SRC_Pos)
9466 #define TIMER_ECTL_EVNT_DROP_CNT_Pos (24)
9467 #define TIMER_ECTL_EVNT_DROP_CNT_Msk (0xfful << TIMER_ECTL_EVNT_DROP_CNT_Pos) /* TMR_CONST */
9470 /* end of TMR register group */
9471
9472
9473 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
9479 typedef struct
9480 {
9481
9482
9483 union
9484 {
9485
9496 __I uint32_t RBR;
9497
9498
9509 __O uint32_t THR;
9510 };
9511
9581 __IO uint32_t CTL;
9582
9629 __IO uint32_t TLCTL;
9630
9666 __IO uint32_t IER;
9667
9732 __IO uint32_t ISR;
9733
9784 __IO uint32_t TRSR;
9785
9855 __IO uint32_t FSR;
9856
9888 __IO uint32_t MCSR;
9889
9909 __IO uint32_t TMCTL;
9910
9925 __IO uint32_t BAUD;
9926 uint32_t RESERVE0[2];
9927
9928
9947 __IO uint32_t IRCR;
9948
10000 __IO uint32_t ALT_CTL;
10001
10015 __IO uint32_t FUN_SEL;
10016
10031 __IO uint32_t BR_COMP;
10032
10033 } UART_T;
10034
10040 #define UART_DAT_DAT_Pos (0)
10041 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos)
10043 #define UART_CTL_RX_RST_Pos (0)
10044 #define UART_CTL_RX_RST_Msk (0x1ul << UART_CTL_RX_RST_Pos)
10046 #define UART_CTL_TX_RST_Pos (1)
10047 #define UART_CTL_TX_RST_Msk (0x1ul << UART_CTL_TX_RST_Pos)
10049 #define UART_CTL_RX_DIS_Pos (2)
10050 #define UART_CTL_RX_DIS_Msk (0x1ul << UART_CTL_RX_DIS_Pos)
10052 #define UART_CTL_TX_DIS_Pos (3)
10053 #define UART_CTL_TX_DIS_Msk (0x1ul << UART_CTL_TX_DIS_Pos)
10055 #define UART_CTL_AUTO_RTS_EN_Pos (4)
10056 #define UART_CTL_AUTO_RTS_EN_Msk (0x1ul << UART_CTL_AUTO_RTS_EN_Pos)
10058 #define UART_CTL_AUTO_CTS_EN_Pos (5)
10059 #define UART_CTL_AUTO_CTS_EN_Msk (0x1ul << UART_CTL_AUTO_CTS_EN_Pos)
10061 #define UART_CTL_DMA_RX_EN_Pos (6)
10062 #define UART_CTL_DMA_RX_EN_Msk (0x1ul << UART_CTL_DMA_RX_EN_Pos)
10064 #define UART_CTL_DMA_TX_EN_Pos (7)
10065 #define UART_CTL_DMA_TX_EN_Msk (0x1ul << UART_CTL_DMA_TX_EN_Pos)
10067 #define UART_CTL_WAKE_CTS_EN_Pos (8)
10068 #define UART_CTL_WAKE_CTS_EN_Msk (0x1ul << UART_CTL_WAKE_CTS_EN_Pos)
10070 #define UART_CTL_WAKE_DATA_EN_Pos (9)
10071 #define UART_CTL_WAKE_DATA_EN_Msk (0x1ul << UART_CTL_WAKE_DATA_EN_Pos)
10073 #define UART_CTL_ABAUD_EN_Pos (12)
10074 #define UART_CTL_ABAUD_EN_Msk (0x1ul << UART_CTL_ABAUD_EN_Pos)
10076 #define UART_CTL_WAKE_THRESH_EN_Pos (17)
10077 #define UART_CTL_WAKE_THRESH_EN_Msk (0x1ul << UART_CTL_WAKE_THRESH_EN_Pos)
10079 #define UART_CTL_WAKE_RS485_AAD_EN_Pos (18)
10080 #define UART_CTL_WAKE_RS485_AAD_EN_Msk (0x1ul << UART_CTL_WAKE_RS485_AAD_EN_Pos)
10082 #define UART_CTL_PWM_SEL_Pos (24)
10083 #define UART_CTL_PWM_SEL_Msk (0x7ul << UART_CTL_PWM_SEL_Pos)
10085 #define UART_TLCTL_DATA_LEN_Pos (0)
10086 #define UART_TLCTL_DATA_LEN_Msk (0x3ul << UART_TLCTL_DATA_LEN_Pos)
10088 #define UART_TLCTL_NSB_Pos (2)
10089 #define UART_TLCTL_NSB_Msk (0x1ul << UART_TLCTL_NSB_Pos)
10091 #define UART_TLCTL_PBE_Pos (3)
10092 #define UART_TLCTL_PBE_Msk (0x1ul << UART_TLCTL_PBE_Pos)
10094 #define UART_TLCTL_EPE_Pos (4)
10095 #define UART_TLCTL_EPE_Msk (0x1ul << UART_TLCTL_EPE_Pos)
10097 #define UART_TLCTL_SPE_Pos (5)
10098 #define UART_TLCTL_SPE_Msk (0x1ul << UART_TLCTL_SPE_Pos)
10100 #define UART_TLCTL_BCB_Pos (6)
10101 #define UART_TLCTL_BCB_Msk (0x1ul << UART_TLCTL_BCB_Pos)
10103 #define UART_TLCTL_RFITL_Pos (8)
10104 #define UART_TLCTL_RFITL_Msk (0x3ul << UART_TLCTL_RFITL_Pos)
10106 #define UART_TLCTL_RTS_TRI_LEV_Pos (12)
10107 #define UART_TLCTL_RTS_TRI_LEV_Msk (0x3ul << UART_TLCTL_RTS_TRI_LEV_Pos)
10109 #define UART_IER_RDA_IE_Pos (0)
10110 #define UART_IER_RDA_IE_Msk (0x1ul << UART_IER_RDA_IE_Pos)
10112 #define UART_IER_THRE_IE_Pos (1)
10113 #define UART_IER_THRE_IE_Msk (0x1ul << UART_IER_THRE_IE_Pos)
10115 #define UART_IER_RLS_IE_Pos (2)
10116 #define UART_IER_RLS_IE_Msk (0x1ul << UART_IER_RLS_IE_Pos)
10118 #define UART_IER_MODEM_IE_Pos (3)
10119 #define UART_IER_MODEM_IE_Msk (0x1ul << UART_IER_MODEM_IE_Pos)
10121 #define UART_IER_RTO_IE_Pos (4)
10122 #define UART_IER_RTO_IE_Msk (0x1ul << UART_IER_RTO_IE_Pos)
10124 #define UART_IER_BUF_ERR_IE_Pos (5)
10125 #define UART_IER_BUF_ERR_IE_Msk (0x1ul << UART_IER_BUF_ERR_IE_Pos)
10127 #define UART_IER_WAKE_IE_Pos (6)
10128 #define UART_IER_WAKE_IE_Msk (0x1ul << UART_IER_WAKE_IE_Pos)
10130 #define UART_IER_ABAUD_IE_Pos (7)
10131 #define UART_IER_ABAUD_IE_Msk (0x1ul << UART_IER_ABAUD_IE_Pos)
10133 #define UART_IER_LIN_IE_Pos (8)
10134 #define UART_IER_LIN_IE_Msk (0x1ul << UART_IER_LIN_IE_Pos)
10136 #define UART_ISR_RDA_IS_Pos (0)
10137 #define UART_ISR_RDA_IS_Msk (0x1ul << UART_ISR_RDA_IS_Pos)
10139 #define UART_ISR_THRE_IS_Pos (1)
10140 #define UART_ISR_THRE_IS_Msk (0x1ul << UART_ISR_THRE_IS_Pos)
10142 #define UART_ISR_RLS_IS_Pos (2)
10143 #define UART_ISR_RLS_IS_Msk (0x1ul << UART_ISR_RLS_IS_Pos)
10145 #define UART_ISR_MODEM_IS_Pos (3)
10146 #define UART_ISR_MODEM_IS_Msk (0x1ul << UART_ISR_MODEM_IS_Pos)
10148 #define UART_ISR_RTO_IS_Pos (4)
10149 #define UART_ISR_RTO_IS_Msk (0x1ul << UART_ISR_RTO_IS_Pos)
10151 #define UART_ISR_BUF_ERR_IS_Pos (5)
10152 #define UART_ISR_BUF_ERR_IS_Msk (0x1ul << UART_ISR_BUF_ERR_IS_Pos)
10154 #define UART_ISR_WAKE_IS_Pos (6)
10155 #define UART_ISR_WAKE_IS_Msk (0x1ul << UART_ISR_WAKE_IS_Pos)
10157 #define UART_ISR_ABAUD_IS_Pos (7)
10158 #define UART_ISR_ABAUD_IS_Msk (0x1ul << UART_ISR_ABAUD_IS_Pos)
10160 #define UART_ISR_LIN_IS_Pos (8)
10161 #define UART_ISR_LIN_IS_Msk (0x1ul << UART_ISR_LIN_IS_Pos)
10163 #define UART_TRSR_RS485_ADDET_F_Pos (0)
10164 #define UART_TRSR_RS485_ADDET_F_Msk (0x1ul << UART_TRSR_RS485_ADDET_F_Pos)
10166 #define UART_TRSR_ABAUD_F_Pos (1)
10167 #define UART_TRSR_ABAUD_F_Msk (0x1ul << UART_TRSR_ABAUD_F_Pos)
10169 #define UART_TRSR_ABAUD_TOUT_F_Pos (2)
10170 #define UART_TRSR_ABAUD_TOUT_F_Msk (0x1ul << UART_TRSR_ABAUD_TOUT_F_Pos)
10172 #define UART_TRSR_LIN_TX_F_Pos (3)
10173 #define UART_TRSR_LIN_TX_F_Msk (0x1ul << UART_TRSR_LIN_TX_F_Pos)
10175 #define UART_TRSR_LIN_RX_F_Pos (4)
10176 #define UART_TRSR_LIN_RX_F_Msk (0x1ul << UART_TRSR_LIN_RX_F_Pos)
10178 #define UART_TRSR_BIT_ERR_F_Pos (5)
10179 #define UART_TRSR_BIT_ERR_F_Msk (0x1ul << UART_TRSR_BIT_ERR_F_Pos)
10181 #define UART_TRSR_LIN_RX_SYNC_ERR_F_Pos (8)
10182 #define UART_TRSR_LIN_RX_SYNC_ERR_F_Msk (0x1ul << UART_TRSR_LIN_RX_SYNC_ERR_F_Pos)
10184 #define UART_FSR_RX_OVER_F_Pos (0)
10185 #define UART_FSR_RX_OVER_F_Msk (0x1ul << UART_FSR_RX_OVER_F_Pos)
10187 #define UART_FSR_RX_EMPTY_F_Pos (1)
10188 #define UART_FSR_RX_EMPTY_F_Msk (0x1ul << UART_FSR_RX_EMPTY_F_Pos)
10190 #define UART_FSR_RX_FULL_F_Pos (2)
10191 #define UART_FSR_RX_FULL_F_Msk (0x1ul << UART_FSR_RX_FULL_F_Pos)
10193 #define UART_FSR_PE_F_Pos (4)
10194 #define UART_FSR_PE_F_Msk (0x1ul << UART_FSR_PE_F_Pos)
10196 #define UART_FSR_FE_F_Pos (5)
10197 #define UART_FSR_FE_F_Msk (0x1ul << UART_FSR_FE_F_Pos)
10199 #define UART_FSR_BI_F_Pos (6)
10200 #define UART_FSR_BI_F_Msk (0x1ul << UART_FSR_BI_F_Pos)
10202 #define UART_FSR_TX_OVER_F_Pos (8)
10203 #define UART_FSR_TX_OVER_F_Msk (0x1ul << UART_FSR_TX_OVER_F_Pos)
10205 #define UART_FSR_TX_EMPTY_F_Pos (9)
10206 #define UART_FSR_TX_EMPTY_F_Msk (0x1ul << UART_FSR_TX_EMPTY_F_Pos)
10208 #define UART_FSR_TX_FULL_F_Pos (10)
10209 #define UART_FSR_TX_FULL_F_Msk (0x1ul << UART_FSR_TX_FULL_F_Pos)
10211 #define UART_FSR_TE_F_Pos (11)
10212 #define UART_FSR_TE_F_Msk (0x1ul << UART_FSR_TE_F_Pos)
10214 #define UART_FSR_RX_POINTER_F_Pos (16)
10215 #define UART_FSR_RX_POINTER_F_Msk (0x1ful << UART_FSR_RX_POINTER_F_Pos)
10217 #define UART_FSR_TX_POINTER_F_Pos (24)
10218 #define UART_FSR_TX_POINTER_F_Msk (0x1ful << UART_FSR_TX_POINTER_F_Pos)
10220 #define UART_MCSR_LEV_RTS_Pos (0)
10221 #define UART_MCSR_LEV_RTS_Msk (0x1ul << UART_MCSR_LEV_RTS_Pos)
10223 #define UART_MCSR_RTS_ST_Pos (1)
10224 #define UART_MCSR_RTS_ST_Msk (0x1ul << UART_MCSR_RTS_ST_Pos)
10226 #define UART_MCSR_LEV_CTS_Pos (16)
10227 #define UART_MCSR_LEV_CTS_Msk (0x1ul << UART_MCSR_LEV_CTS_Pos)
10229 #define UART_MCSR_CTS_ST_Pos (17)
10230 #define UART_MCSR_CTS_ST_Msk (0x1ul << UART_MCSR_CTS_ST_Pos)
10232 #define UART_MCSR_DCT_F_Pos (18)
10233 #define UART_MCSR_DCT_F_Msk (0x1ul << UART_MCSR_DCT_F_Pos)
10235 #define UART_TMCTL_TOIC_Pos (0)
10236 #define UART_TMCTL_TOIC_Msk (0x1fful << UART_TMCTL_TOIC_Pos)
10238 #define UART_TMCTL_DLY_Pos (16)
10239 #define UART_TMCTL_DLY_Msk (0xfful << UART_TMCTL_DLY_Pos)
10241 #define UART_BAUD_BRD_Pos (0)
10242 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
10244 #define UART_BAUD_DIV_16_EN_Pos (31)
10245 #define UART_BAUD_DIV_16_EN_Msk (0x1ul << UART_BAUD_DIV_16_EN_Pos)
10247 #define UART_IRCR_TX_SELECT_Pos (1)
10248 #define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos)
10250 #define UART_IRCR_INV_TX_Pos (5)
10251 #define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos)
10253 #define UART_IRCR_INV_RX_Pos (6)
10254 #define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos)
10256 #define UART_ALT_CTL_LIN_TX_BCNT_Pos (0)
10257 #define UART_ALT_CTL_LIN_TX_BCNT_Msk (0x7ul << UART_ALT_CTL_LIN_TX_BCNT_Pos)
10259 #define UART_ALT_CTL_LIN_HEAD_SEL_Pos (4)
10260 #define UART_ALT_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_ALT_CTL_LIN_HEAD_SEL_Pos)
10262 #define UART_ALT_CTL_LIN_RX_EN_Pos (6)
10263 #define UART_ALT_CTL_LIN_RX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_RX_EN_Pos)
10265 #define UART_ALT_CTL_LIN_TX_EN_Pos (7)
10266 #define UART_ALT_CTL_LIN_TX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_TX_EN_Pos)
10268 #define UART_ALT_CTL_Bit_ERR_EN_Pos (8)
10269 #define UART_ALT_CTL_Bit_ERR_EN_Msk (0x1ul << UART_ALT_CTL_Bit_ERR_EN_Pos)
10271 #define UART_ALT_CTL_RS485_NMM_Pos (16)
10272 #define UART_ALT_CTL_RS485_NMM_Msk (0x1ul << UART_ALT_CTL_RS485_NMM_Pos)
10274 #define UART_ALT_CTL_RS485_AAD_Pos (17)
10275 #define UART_ALT_CTL_RS485_AAD_Msk (0x1ul << UART_ALT_CTL_RS485_AAD_Pos)
10277 #define UART_ALT_CTL_RS485_AUD_Pos (18)
10278 #define UART_ALT_CTL_RS485_AUD_Msk (0x1ul << UART_ALT_CTL_RS485_AUD_Pos)
10280 #define UART_ALT_CTL_RS485_ADD_EN_Pos (19)
10281 #define UART_ALT_CTL_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CTL_RS485_ADD_EN_Pos)
10283 #define UART_ALT_CTL_ADDR_PID_MATCH_Pos (24)
10284 #define UART_ALT_CTL_ADDR_PID_MATCH_Msk (0xfful << UART_ALT_CTL_ADDR_PID_MATCH_Pos)
10286 #define UART_FUN_SEL_FUN_SEL_Pos (0)
10287 #define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos)
10289 #define UART_BR_COMP_BR_COMP_Pos (0)
10290 #define UART_BR_COMP_BR_COMP_Msk (0x1fful << UART_BR_COMP_BR_COMP_Pos)
10292 #define UART_BR_COMP_BR_COMP_DEC_Pos (31)
10293 #define UART_BR_COMP_BR_COMP_DEC_Msk (0x1ul << UART_BR_COMP_BR_COMP_DEC_Pos) /* UART_CONST */
10296 /* end of UART register group */
10297
10298
10299 /*---------------------- Watch Dog Timer Controller -------------------------*/
10305 typedef struct
10306 {
10307
10308
10348 __IO uint32_t CTL;
10349
10361 __IO uint32_t IER;
10362
10392 __IO uint32_t ISR;
10393
10394 } WDT_T;
10395
10401 #define WDT_CTL_WTR_Pos (0)
10402 #define WDT_CTL_WTR_Msk (0x1ul << WDT_CTL_WTR_Pos)
10404 #define WDT_CTL_WTRE_Pos (1)
10405 #define WDT_CTL_WTRE_Msk (0x1ul << WDT_CTL_WTRE_Pos)
10407 #define WDT_CTL_WTWKE_Pos (2)
10408 #define WDT_CTL_WTWKE_Msk (0x1ul << WDT_CTL_WTWKE_Pos)
10410 #define WDT_CTL_WTE_Pos (3)
10411 #define WDT_CTL_WTE_Msk (0x1ul << WDT_CTL_WTE_Pos)
10413 #define WDT_CTL_WTIS_Pos (4)
10414 #define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos)
10416 #define WDT_CTL_WTRDSEL_Pos (8)
10417 #define WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos)
10419 #define WDT_IER_IE_Pos (0)
10420 #define WDT_IER_IE_Msk (0x1ul << WDT_IER_IE_Pos)
10422 #define WDT_ISR_IS_Pos (0)
10423 #define WDT_ISR_IS_Msk (0x1ul << WDT_ISR_IS_Pos)
10425 #define WDT_ISR_RST_IS_Pos (1)
10426 #define WDT_ISR_RST_IS_Msk (0x1ul << WDT_ISR_RST_IS_Pos)
10428 #define WDT_ISR_WAKE_IS_Pos (2)
10429 #define WDT_ISR_WAKE_IS_Msk (0x1ul << WDT_ISR_WAKE_IS_Pos) /* WDT_CONST */
10432 /* end of WDT register group */
10433
10434
10435 /*---------------------- Window Watchdog Timer -------------------------*/
10441 typedef struct
10442 {
10443
10444
10457 __O uint32_t RLD;
10458
10480 __IO uint32_t CR;
10481
10494 __IO uint32_t IER;
10495
10510 __IO uint32_t STS;
10511
10522 __I uint32_t VAL;
10523
10524 } WWDT_T;
10525
10526
10532 #define WWDT_RLD_WWDTRLD_Pos (0)
10533 #define WWDT_RLD_WWDTRLD_Msk (0xfffffffful << WWDT_RLD_RLD_Pos)
10535 #define WWDT_CR_WWDTEN_Pos (0)
10536 #define WWDT_CR_WWDTEN_Msk (0x1ul << WWDT_CR_WWDTEN_Pos)
10538 #define WWDT_CR_PERIODSEL_Pos (8)
10539 #define WWDT_CR_PERIODSEL_Msk (0xful << WWDT_CR_PERIODSEL_Pos)
10541 #define WWDT_CR_WINCMP_Pos (16)
10542 #define WWDT_CR_WINCMP_Msk (0x3ful << WWDT_CR_WINCMP_Pos)
10544 #define WWDT_CR_DBGEN_Pos (31)
10545 #define WWDT_CR_DBGEN_Msk (0x1ul << WWDT_CR_DBGEN_Pos)
10547 #define WWDT_IER_WWDTIE_Pos (0)
10548 #define WWDT_IER_WWDTIE_Msk (0x1ul << WWDT_IER_WWDTIE_Pos)
10550 #define WWDT_STS_IF_Pos (0)
10551 #define WWDT_STS_IF_Msk (0x1ul << WWDT_STS_IF_Pos)
10553 #define WWDT_STS_RF_Pos (1)
10554 #define WWDT_STS_RF_Msk (0x1ul << WWDT_STS_RF_Pos)
10556 #define WWDT_VAL_WWDTVAL_Pos (0)
10557 #define WWDT_VAL_WWDTVAL_Msk (0x3ful << WWDT_VAL_WWDTVAL_Pos) /* WWDT_CONST */
10560 /* end of WWDT register group */
10561
10562
10563
10564
10565 #if defined ( __CC_ARM )
10566 #pragma no_anon_unions
10567 #endif
10568
10574 #define FLASH_BASE ((uint32_t)0x00000000)
10575 #define SRAM_BASE ((uint32_t)0x20000000)
10576 #define APB1PERIPH_BASE ((uint32_t)0x40000000)
10577 #define APB2PERIPH_BASE ((uint32_t)0x40100000)
10578 #define AHBPERIPH_BASE ((uint32_t)0x50000000)
10579
10580
10582 #define WDT_BASE (APB1PERIPH_BASE + 0x04000)
10583 #define WWDT_BASE (APB1PERIPH_BASE + 0x04100)
10584 #define RTC_BASE (APB1PERIPH_BASE + 0x08000)
10585 #define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
10586 #define TIMER1_BASE (APB1PERIPH_BASE + 0x10100)
10587 #define I2C0_BASE (APB1PERIPH_BASE + 0x20000)
10588 #define SPI0_BASE (APB1PERIPH_BASE + 0x30000)
10589 #define PWM0_BASE (APB1PERIPH_BASE + 0x40000)
10590 #define UART0_BASE (APB1PERIPH_BASE + 0x50000)
10591 #define LCD_BASE (APB1PERIPH_BASE + 0xB0000)
10592 #define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
10593
10594 #define TIMER2_BASE (APB2PERIPH_BASE + 0x10000)
10595 #define TIMER3_BASE (APB2PERIPH_BASE + 0x10100)
10596 #define I2C1_BASE (APB2PERIPH_BASE + 0x20000)
10597 #define SPI1_BASE (APB2PERIPH_BASE + 0x30000)
10598 #define UART1_BASE (APB2PERIPH_BASE + 0x50000)
10599 #define SC0_BASE (APB2PERIPH_BASE + 0x90000)
10600 #define SC1_BASE (APB2PERIPH_BASE + 0xB0000)
10601 #define ACMP_BASE (APB2PERIPH_BASE + 0xD0000)
10602
10603 #define SYS_BASE (AHBPERIPH_BASE + 0x00000)
10604 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
10605 #define INTID_BASE (AHBPERIPH_BASE + 0x00300)
10606 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
10607 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
10608 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
10609 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
10610 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
10611 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
10612 #define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180)
10613 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
10614 #define PDMA0_BASE (AHBPERIPH_BASE + 0x08000)
10615 #define PDMA1_BASE (AHBPERIPH_BASE + 0x08100)
10616 #define PDMA2_BASE (AHBPERIPH_BASE + 0x08200)
10617 #define PDMA3_BASE (AHBPERIPH_BASE + 0x08300)
10618 #define PDMA4_BASE (AHBPERIPH_BASE + 0x08400)
10619 #define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00)
10620 #define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00)
10621 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
10622
10623 /* end of group NANO1X2_PERIPHERAL_MEM_MAP */
10624
10625
10630 #define WDT ((WDT_T *) WDT_BASE)
10631 #define WWDT ((WWDT_T *) WWDT_BASE)
10632 #define RTC ((RTC_T *) RTC_BASE)
10633 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
10634 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
10635 #define TIMER2 ((TIMER_T *) TIMER2_BASE)
10636 #define TIMER3 ((TIMER_T *) TIMER3_BASE)
10637 #define I2C0 ((I2C_T *) I2C0_BASE)
10638 #define I2C1 ((I2C_T *) I2C1_BASE)
10639 #define SPI0 ((SPI_T *) SPI0_BASE)
10640 #define SPI1 ((SPI_T *) SPI1_BASE)
10641 #define PWM0 ((PWM_T *) PWM0_BASE)
10642 #define UART0 ((UART_T *) UART0_BASE)
10643 #define UART1 ((UART_T *) UART1_BASE)
10644 #define LCD ((LCD_T *) LCD_BASE)
10645 #define ADC ((ADC_T *) ADC_BASE)
10646 #define SC0 ((SC_T *) SC0_BASE)
10647 #define SC1 ((SC_T *) SC1_BASE)
10648 #define ACMP ((ACMP_T *) ACMP_BASE)
10649
10650 #define SYS ((SYS_T *) SYS_BASE)
10651 #define CLK ((CLK_T *) CLK_BASE)
10652 #define PA ((GPIO_T *) GPIOA_BASE)
10653 #define PB ((GPIO_T *) GPIOB_BASE)
10654 #define PC ((GPIO_T *) GPIOC_BASE)
10655 #define PD ((GPIO_T *) GPIOD_BASE)
10656 #define PE ((GPIO_T *) GPIOE_BASE)
10657 #define PF ((GPIO_T *) GPIOF_BASE)
10658 #define GPIO ((GP_DB_T *) GPIODBNCE_BASE)
10659 #define PDMA1 ((PDMA_T *) PDMA1_BASE)
10660 #define PDMA2 ((PDMA_T *) PDMA2_BASE)
10661 #define PDMA3 ((PDMA_T *) PDMA3_BASE)
10662 #define PDMA4 ((PDMA_T *) PDMA4_BASE)
10663 #define PDMACRC ((DMA_CRC_T *) PDMACRC_BASE)
10664 #define PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE)
10665 #define FMC ((FMC_T *) FMC_BASE)
10666
10667 /* end of group NANO1X2_PERIPHERAL_DECLARATION */
10668 /* end of group NANO1X2_Peripherals */
10670
10676 typedef volatile unsigned char vu8;
10677 typedef volatile unsigned short vu16;
10678 typedef volatile unsigned long vu32;
10679
10685 #define M8(addr) (*((vu8 *) (addr)))
10686
10693 #define M16(addr) (*((vu16 *) (addr)))
10694
10701 #define M32(addr) (*((vu32 *) (addr)))
10702
10710 #define outpw(port,value) *((volatile unsigned int *)(port)) = value
10711
10718 #define inpw(port) (*((volatile unsigned int *)(port)))
10719
10727 #define outps(port,value) *((volatile unsigned short *)(port)) = value
10728
10735 #define inps(port) (*((volatile unsigned short *)(port)))
10736
10743 #define outpb(port,value) *((volatile unsigned char *)(port)) = value
10744
10750 #define inpb(port) (*((volatile unsigned char *)(port)))
10751
10759 #define outp32(port,value) *((volatile unsigned int *)(port)) = value
10760
10767 #define inp32(port) (*((volatile unsigned int *)(port)))
10768
10776 #define outp16(port,value) *((volatile unsigned short *)(port)) = value
10777
10784 #define inp16(port) (*((volatile unsigned short *)(port)))
10785
10792 #define outp8(port,value) *((volatile unsigned char *)(port)) = value
10793
10799 #define inp8(port) (*((volatile unsigned char *)(port)))
10800 /* end of group NANO1X2_IO_ROUTINE */
10802
10803 /******************************************************************************/
10804 /* Legacy Constants */
10805 /******************************************************************************/
10811 #ifndef NULL
10812 #define NULL (0)
10813 #endif
10814
10815 #define TRUE (1)
10816 #define FALSE (0)
10817
10818 #define ENABLE (1)
10819 #define DISABLE (0)
10820
10821 /* Define one bit mask */
10822 #define BIT0 (0x00000001)
10823 #define BIT1 (0x00000002)
10824 #define BIT2 (0x00000004)
10825 #define BIT3 (0x00000008)
10826 #define BIT4 (0x00000010)
10827 #define BIT5 (0x00000020)
10828 #define BIT6 (0x00000040)
10829 #define BIT7 (0x00000080)
10830 #define BIT8 (0x00000100)
10831 #define BIT9 (0x00000200)
10832 #define BIT10 (0x00000400)
10833 #define BIT11 (0x00000800)
10834 #define BIT12 (0x00001000)
10835 #define BIT13 (0x00002000)
10836 #define BIT14 (0x00004000)
10837 #define BIT15 (0x00008000)
10838 #define BIT16 (0x00010000)
10839 #define BIT17 (0x00020000)
10840 #define BIT18 (0x00040000)
10841 #define BIT19 (0x00080000)
10842 #define BIT20 (0x00100000)
10843 #define BIT21 (0x00200000)
10844 #define BIT22 (0x00400000)
10845 #define BIT23 (0x00800000)
10846 #define BIT24 (0x01000000)
10847 #define BIT25 (0x02000000)
10848 #define BIT26 (0x04000000)
10849 #define BIT27 (0x08000000)
10850 #define BIT28 (0x10000000)
10851 #define BIT29 (0x20000000)
10852 #define BIT30 (0x40000000)
10853 #define BIT31 (0x80000000)
10854
10855 /* Byte Mask Definitions */
10856 #define BYTE0_Msk (0x000000FF)
10857 #define BYTE1_Msk (0x0000FF00)
10858 #define BYTE2_Msk (0x00FF0000)
10859 #define BYTE3_Msk (0xFF000000)
10860
10861 #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
10862 #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
10863 #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
10864 #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
10866 /* end of group NANO1X2_legacy_Constants */
10867 /* end of group NANO1X2_Definitions */
10869
10870 #ifdef __cplusplus
10871 }
10872 #endif
10873
10874
10875 /******************************************************************************/
10876 /* Peripheral header files */
10877 /******************************************************************************/
10878 #include "sys.h"
10879 #include "clk.h"
10880 #include "acmp.h"
10881 #include "adc.h"
10882 #include "fmc.h"
10883 #include "gpio.h"
10884 #include "i2c.h"
10885 #include "crc.h"
10886 #include "pdma.h"
10887 #include "pwm.h"
10888 #include "rtc.h"
10889 #include "sc.h"
10890 #include "scuart.h"
10891 #include "spi.h"
10892 #include "timer.h"
10893 #include "uart.h"
10894 #include "wdt.h"
10895 #include "wwdt.h"
10896
10897 #endif // __NANO1X2SERIES_H__
10898
10899 /*** (C) COPYRIGHT 2013-2016 Nuvoton Technology Corp. ***/
10900
WDT_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:10361
HIRC_IRQn
Definition: Nano1X2Series.h:103
PDMA_T::DAR
__IO uint32_t DAR
Definition: Nano1X2Series.h:2140
SYS_T::IRCTRIMCTL
__IO uint32_t IRCTRIMCTL
Definition: Nano1X2Series.h:3549
ADC_T::SMPLCNT1
__IO uint32_t SMPLCNT1
Definition: Nano1X2Series.h:758
RTC_T::TLR
__IO uint32_t TLR
Definition: Nano1X2Series.h:7136
RTC_T
Definition: Nano1X2Series.h:7071
DMA_CRC_T
Definition: Nano1X2Series.h:1719
rtc.h
Nano102/112 series RTC driver header file.
UART_T::ALT_CTL
__IO uint32_t ALT_CTL
Definition: Nano1X2Series.h:10000
uart.h
Nano102/112 Series UART control header file.
RTC_T::RIER
__IO uint32_t RIER
Definition: Nano1X2Series.h:7248
GPIO_T
Definition: Nano1X2Series.h:4074
PWM_T::CRL3
__I uint32_t CRL3
Definition: Nano1X2Series.h:6498
PDMA_T::CSR
__IO uint32_t CSR
Definition: Nano1X2Series.h:2114
GPDEF_IRQn
Definition: Nano1X2Series.h:93
UART_T::FUN_SEL
__IO uint32_t FUN_SEL
Definition: Nano1X2Series.h:10015
pwm.h
Nano102/112 series PWM driver header file.
LCD_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:5288
SC_T::ETUCR
__IO uint32_t ETUCR
Definition: Nano1X2Series.h:7796
EINT1_IRQn
Definition: Nano1X2Series.h:91
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: Nano1X2Series.h:1229
WWDT_T::STS
__IO uint32_t STS
Definition: Nano1X2Series.h:10510
SC_T
Definition: Nano1X2Series.h:7543
PWM_T::DUTY1
__IO uint32_t DUTY1
Definition: Nano1X2Series.h:6041
acmp.h
Nano102/112 series Analog Comparator(ACMP) driver header file.
SPI0_IRQn
Definition: Nano1X2Series.h:101
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: Nano1X2Series.h:2553
RTC_T::INIR
__IO uint32_t INIR
Definition: Nano1X2Series.h:7091
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Nano1X2Series.h:10678
RTC_T::CAR
__IO uint32_t CAR
Definition: Nano1X2Series.h:7216
wwdt.h
Nano102/112 series WWDT driver header file.
ADC_T::SMPLCNT0
__IO uint32_t SMPLCNT0
Definition: Nano1X2Series.h:746
NonMaskableInt_IRQn
Definition: Nano1X2Series.h:81
SPI_T::SSR
__IO uint32_t SSR
Definition: Nano1X2Series.h:8685
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: Nano1X2Series.h:2532
SysTick_IRQn
Definition: Nano1X2Series.h:85
RTC_T::RIIR
__IO uint32_t RIIR
Definition: Nano1X2Series.h:7276
GPIO_T::DMASK
__IO uint32_t DMASK
Definition: Nano1X2Series.h:4262
LCD_T::MEM_5
__IO uint32_t MEM_5
Definition: Nano1X2Series.h:5451
FMC_T::DFBADR
__I uint32_t DFBADR
Definition: Nano1X2Series.h:2581
UART1_IRQn
Definition: Nano1X2Series.h:100
PWM_T::CRL1
__I uint32_t CRL1
Definition: Nano1X2Series.h:6442
SC_T::TMR1
__IO uint32_t TMR1
Definition: Nano1X2Series.h:8083
SC_T::ALTCTL
__IO uint32_t ALTCTL
Definition: Nano1X2Series.h:7748
LCD_T::MEM_3
__IO uint32_t MEM_3
Definition: Nano1X2Series.h:5415
CLK_T::CLKDIV1
__IO uint32_t CLKDIV1
Definition: Nano1X2Series.h:1267
SYS_T::PD_H_MFP
__IO uint32_t PD_H_MFP
Definition: Nano1X2Series.h:3227
gpio.h
Nano102/112 series GPIO driver header file.
PendSV_IRQn
Definition: Nano1X2Series.h:84
SYS_T::IRCTRIMIEN
__IO uint32_t IRCTRIMIEN
Definition: Nano1X2Series.h:3569
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: Nano1X2Series.h:4294
I2C1_IRQn
Definition: Nano1X2Series.h:105
PWM_T::INTEN
__IO uint32_t INTEN
Definition: Nano1X2Series.h:5870
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: Nano1X2Series.h:1084
I2C_T
Definition: Nano1X2Series.h:4890
UART_T::FSR
__IO uint32_t FSR
Definition: Nano1X2Series.h:9855
PDMA_T::ISR
__IO uint32_t ISR
Definition: Nano1X2Series.h:2247
IRQn
IRQn
Definition: Nano1X2Series.h:77
CLK_T::SP_DET
__IO uint32_t SP_DET
Definition: Nano1X2Series.h:1403
UART_T::TRSR
__IO uint32_t TRSR
Definition: Nano1X2Series.h:9784
PWM_T::CAPINTSTS
__IO uint32_t CAPINTSTS
Definition: Nano1X2Series.h:6400
DMA_CRC_T::DMASAR
__IO uint32_t DMASAR
Definition: Nano1X2Series.h:1789
PWM_T::CRL2
__I uint32_t CRL2
Definition: Nano1X2Series.h:6470
UART_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:9666
SC_T::TRSR
__IO uint32_t TRSR
Definition: Nano1X2Series.h:7979
system_Nano1X2Series.h
Nano1X2 series system clock definition file.
DMA_CRC_T::DMAIER
__IO uint32_t DMAIER
Definition: Nano1X2Series.h:1848
PWM_T::CFL2
__I uint32_t CFL2
Definition: Nano1X2Series.h:6484
DMA_GCR_T::DSSR0
__IO uint32_t DSSR0
Definition: Nano1X2Series.h:1994
sys.h
Nano102/112 Series system control header file.
I2C0_IRQn
Definition: Nano1X2Series.h:104
ADC_T::CALWORD
__IO uint32_t CALWORD
Definition: Nano1X2Series.h:709
PWM_T::DUTY3
__IO uint32_t DUTY3
Definition: Nano1X2Series.h:6171
DMA_CRC_T::SEED
__IO uint32_t SEED
Definition: Nano1X2Series.h:1900
DMA_GCR_T
Definition: Nano1X2Series.h:1917
I2C_T::CON2
__IO uint32_t CON2
Definition: Nano1X2Series.h:5093
CLK_T
Definition: Nano1X2Series.h:903
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Nano1X2Series.h:8607
SPI_T::DMA
__IO uint32_t DMA
Definition: Nano1X2Series.h:8804
FMC_T::ISPADR
__IO uint32_t ISPADR
Definition: Nano1X2Series.h:2519
PWM_T::OE
__IO uint32_t OE
Definition: Nano1X2Series.h:5930
DMA_CRC_T::WDATA
__IO uint32_t WDATA
Definition: Nano1X2Series.h:1888
SYS_T::LDO_CTL
__IO uint32_t LDO_CTL
Definition: Nano1X2Series.h:3509
UART_T::RBR
__I uint32_t RBR
Definition: Nano1X2Series.h:9496
ACMP_T::MODCR0
__IO uint32_t MODCR0
Definition: Nano1X2Series.h:287
SPI1_IRQn
Definition: Nano1X2Series.h:102
PWM_T::PRES
__IO uint32_t PRES
Definition: Nano1X2Series.h:5758
GPIO_T::OFFD
__IO uint32_t OFFD
Definition: Nano1X2Series.h:4228
RTC_T::FCR
__IO uint32_t FCR
Definition: Nano1X2Series.h:7120
HardFault_IRQn
Definition: Nano1X2Series.h:82
PWM_T::DATA3
__I uint32_t DATA3
Definition: Nano1X2Series.h:6190
crc.h
Nano102/112 series CRC driver header file.
I2C_T::STATUS
__I uint32_t STATUS
Definition: Nano1X2Series.h:4960
UART_T::ISR
__IO uint32_t ISR
Definition: Nano1X2Series.h:9732
SYS_T::RST_SRC
__IO uint32_t RST_SRC
Definition: Nano1X2Series.h:2726
pdma.h
Nano102/112 series PDMA driver header file.
PDMA_T
Definition: Nano1X2Series.h:2060
SC_T::EGTR
__IO uint32_t EGTR
Definition: Nano1X2Series.h:7761
DMA_CRC_T::DMACSAR
__I uint32_t DMACSAR
Definition: Nano1X2Series.h:1817
sc.h
Nano102/112 series Smartcard (SC) driver header file.
SYS_T::PDID
__I uint32_t PDID
Definition: Nano1X2Series.h:2692
timer.h
Nano102/112 series TIMER driver header file.
UART_T::TMCTL
__IO uint32_t TMCTL
Definition: Nano1X2Series.h:9909
adc.h
Nano102/112 series ADC driver header file.
DMA_GCR_T::GCRCSR
__IO uint32_t GCRCSR
Definition: Nano1X2Series.h:1944
LCD_T::MEM_1
__IO uint32_t MEM_1
Definition: Nano1X2Series.h:5379
TIMER_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:9226
LCD_T::FCSTS
__IO uint32_t FCSTS
Definition: Nano1X2Series.h:5547
SPI_T
Definition: Nano1X2Series.h:8460
PWM_T::CFL1
__I uint32_t CFL1
Definition: Nano1X2Series.h:6456
PWM_T::DUTY2
__IO uint32_t DUTY2
Definition: Nano1X2Series.h:6106
LCD_T::MEM_2
__IO uint32_t MEM_2
Definition: Nano1X2Series.h:5397
DMA_CRC_T::CHECKSUM
__I uint32_t CHECKSUM
Definition: Nano1X2Series.h:1912
wdt.h
Nano102/112 series WDT driver header file.
RTC_IRQn
Definition: Nano1X2Series.h:113
SYS_T::BODSTS
__IO uint32_t BODSTS
Definition: Nano1X2Series.h:3453
WWDT_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:10494
PWM_T::CFL3
__I uint32_t CFL3
Definition: Nano1X2Series.h:6512
GPIO_T::ISRC
__IO uint32_t ISRC
Definition: Nano1X2Series.h:4631
spi.h
Nano102/112 series SPI driver header file.
ADC_T::CALCTL
__IO uint32_t CALCTL
Definition: Nano1X2Series.h:695
PDMA_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:2214
UART_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:9581
SPI_T::TX0
__O uint32_t TX0
Definition: Nano1X2Series.h:8743
TIMER_T::ISR
__IO uint32_t ISR
Definition: Nano1X2Series.h:9263
SYS_T
Definition: Nano1X2Series.h:2677
PWM_T::PDMACH0
__I uint32_t PDMACH0
Definition: Nano1X2Series.h:6532
TMR1_IRQn
Definition: Nano1X2Series.h:96
PWM_T::ADTRGSTS
__IO uint32_t ADTRGSTS
Definition: Nano1X2Series.h:6605
DMA_CRC_T::DMABCR
__IO uint32_t DMABCR
Definition: Nano1X2Series.h:1803
LCD_T::MEM_0
__IO uint32_t MEM_0
Definition: Nano1X2Series.h:5361
DMA_GCR_T::GCRISR
__I uint32_t GCRISR
Definition: Nano1X2Series.h:2055
LCD_T::MEM_4
__IO uint32_t MEM_4
Definition: Nano1X2Series.h:5433
RTC_T::AER
__O uint32_t AER
Definition: Nano1X2Series.h:7107
CLK_T::FRQDIV0
__IO uint32_t FRQDIV0
Definition: Nano1X2Series.h:1320
SC_T::ISR
__IO uint32_t ISR
Definition: Nano1X2Series.h:7904
PDWU_IRQn
Definition: Nano1X2Series.h:110
ADC_IRQn
Definition: Nano1X2Series.h:111
WDT_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:10348
RTC_T::CLR
__IO uint32_t CLR
Definition: Nano1X2Series.h:7152
RTC_T::TAR
__IO uint32_t TAR
Definition: Nano1X2Series.h:7200
scuart.h
CLK_T::CLKSTATUS
__I uint32_t CLKSTATUS
Definition: Nano1X2Series.h:1113
I2C_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano1X2Series.h:4947
WDT_T
Definition: Nano1X2Series.h:10305
ADC_T::CR
__IO uint32_t CR
Definition: Nano1X2Series.h:482
PWM_T::CFL0
__I uint32_t CFL0
Definition: Nano1X2Series.h:6428
LCD_T::DISPCTL
__IO uint32_t DISPCTL
Definition: Nano1X2Series.h:5343
WWDT_T
Definition: Nano1X2Series.h:10441
FMC_T::ISPCON
__IO uint32_t ISPCON
Definition: Nano1X2Series.h:2506
GPIO_T::IMD
__IO uint32_t IMD
Definition: Nano1X2Series.h:4315
PDMA_T::CBCR
__I uint32_t CBCR
Definition: Nano1X2Series.h:2192
RTC_T::DWR
__IO uint32_t DWR
Definition: Nano1X2Series.h:7184
LCD_T::MEM_8
__IO uint32_t MEM_8
Definition: Nano1X2Series.h:5505
PWM_T::CRL0
__I uint32_t CRL0
Definition: Nano1X2Series.h:6414
RTC_T::SPRCTL
__IO uint32_t SPRCTL
Definition: Nano1X2Series.h:7325
ACMP_T
Definition: Nano1X2Series.h:156
ADC_T::PWRCTL
__IO uint32_t PWRCTL
Definition: Nano1X2Series.h:671
fmc.h
Nano102/112 Series Flash Memory Controller Driver Header File.
TMR3_IRQn
Definition: Nano1X2Series.h:98
I2C_T::SAMASK1
__IO uint32_t SAMASK1
Definition: Nano1X2Series.h:5066
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:8551
DMA_CRC_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:1776
UART_T::BR_COMP
__IO uint32_t BR_COMP
Definition: Nano1X2Series.h:10031
DMA_CRC_T::DMACBCR
__I uint32_t DMACBCR
Definition: Nano1X2Series.h:1832
SYS_T::PE_L_MFP
__IO uint32_t PE_L_MFP
Definition: Nano1X2Series.h:3261
CLK_T::SP_STS
__I uint32_t SP_STS
Definition: Nano1X2Series.h:1429
TIMER_T::DR
__IO uint32_t DR
Definition: Nano1X2Series.h:9287
DMA_GCR_T::DSSR1
__IO uint32_t DSSR1
Definition: Nano1X2Series.h:2034
PDMA_T::CDAR
__I uint32_t CDAR
Definition: Nano1X2Series.h:2179
PDMA_IRQn
Definition: Nano1X2Series.h:109
UART_T::MCSR
__IO uint32_t MCSR
Definition: Nano1X2Series.h:9888
BOD_IRQn
Definition: Nano1X2Series.h:88
ACMP_T::SR
__IO uint32_t SR
Definition: Nano1X2Series.h:231
SPI_T::RX0
__I uint32_t RX0
Definition: Nano1X2Series.h:8703
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: Nano1X2Series.h:2567
I2C_T::STATUS2
__IO uint32_t STATUS2
Definition: Nano1X2Series.h:5126
SYS_T::PE_H_MFP
__IO uint32_t PE_H_MFP
Definition: Nano1X2Series.h:3279
I2C_T::SADDR0
__IO uint32_t SADDR0
Definition: Nano1X2Series.h:5021
clk.h
Nano102/112 series CLK driver header file.
GPIO_T::PMD
__IO uint32_t PMD
Definition: Nano1X2Series.h:4213
RTC_T::TSSR
__IO uint32_t TSSR
Definition: Nano1X2Series.h:7166
SC_T::TDRA
__I uint32_t TDRA
Definition: Nano1X2Series.h:8139
ADC_T::CMPR1
__IO uint32_t CMPR1
Definition: Nano1X2Series.h:591
SVCall_IRQn
Definition: Nano1X2Series.h:83
DMA_CRC_T::DMAISR
__IO uint32_t DMAISR
Definition: Nano1X2Series.h:1871
WWDT_T::CR
__IO uint32_t CR
Definition: Nano1X2Series.h:10480
SYS_T::PC_L_MFP
__IO uint32_t PC_L_MFP
Definition: Nano1X2Series.h:3101
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: Nano1X2Series.h:4243
UART_T::TLCTL
__IO uint32_t TLCTL
Definition: Nano1X2Series.h:9629
TIMER_T::ECTL
__IO uint32_t ECTL
Definition: Nano1X2Series.h:9343
CLK_T::APB_DIV
__IO uint32_t APB_DIV
Definition: Nano1X2Series.h:1354
PWM_T::DATA0
__I uint32_t DATA0
Definition: Nano1X2Series.h:5995
RTC_T::LIR
__I uint32_t LIR
Definition: Nano1X2Series.h:7229
RTC_T::TTR
__IO uint32_t TTR
Definition: Nano1X2Series.h:7302
SYS_T::IPRST_CTL2
__IO uint32_t IPRST_CTL2
Definition: Nano1X2Series.h:2819
WWDT_T::RLD
__O uint32_t RLD
Definition: Nano1X2Series.h:10457
I2C_T::DIV
__IO uint32_t DIV
Definition: Nano1X2Series.h:4973
SC_T::TMR0
__IO uint32_t TMR0
Definition: Nano1X2Series.h:8069
SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: Nano1X2Series.h:3406
SC_T::TDRB
__I uint32_t TDRB
Definition: Nano1X2Series.h:8153
TMR2_IRQn
Definition: Nano1X2Series.h:97
SYS_T::PF_L_MFP
__IO uint32_t PF_L_MFP
Definition: Nano1X2Series.h:3322
ADC_T
Definition: Nano1X2Series.h:378
SC_T::RBR
__I uint32_t RBR
Definition: Nano1X2Series.h:7559
WDT_IRQn
Definition: Nano1X2Series.h:89
GPABC_IRQn
Definition: Nano1X2Series.h:92
TMR0_IRQn
Definition: Nano1X2Series.h:95
SYS_T::PB_L_MFP
__IO uint32_t PB_L_MFP
Definition: Nano1X2Series.h:2996
SYS_T::PB_H_MFP
__IO uint32_t PB_H_MFP
Definition: Nano1X2Series.h:3050
SYS_T::IRCTRIMINT
__IO uint32_t IRCTRIMINT
Definition: Nano1X2Series.h:3596
ADC_T::SR
__IO uint32_t SR
Definition: Nano1X2Series.h:634
SC_T::TMR2
__IO uint32_t TMR2
Definition: Nano1X2Series.h:8097
SYS_T::PA_L_MFP
__IO uint32_t PA_L_MFP
Definition: Nano1X2Series.h:2891
PWM_T::ADTRGEN
__IO uint32_t ADTRGEN
Definition: Nano1X2Series.h:6579
SPI_T::RX1
__I uint32_t RX1
Definition: Nano1X2Series.h:8721
TIMER_T::TCAP
__I uint32_t TCAP
Definition: Nano1X2Series.h:9302
FMC_T
Definition: Nano1X2Series.h:2468
SYS_T::PD_L_MFP
__IO uint32_t PD_L_MFP
Definition: Nano1X2Series.h:3181
IRQn_Type
enum IRQn IRQn_Type
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: Nano1X2Series.h:1134
PDMA_T::CSAR
__I uint32_t CSAR
Definition: Nano1X2Series.h:2167
PDMA_T::BCR
__IO uint32_t BCR
Definition: Nano1X2Series.h:2153
TIMER_T::CMPR
__IO uint32_t CMPR
Definition: Nano1X2Series.h:9208
PDMA_T::TCR
__IO uint32_t TCR
Definition: Nano1X2Series.h:2262
PWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: Nano1X2Series.h:6296
SC_T::RFTMR
__IO uint32_t RFTMR
Definition: Nano1X2Series.h:7776
FMC_T::ISPSTA
__I uint32_t ISPSTA
Definition: Nano1X2Series.h:2607
SYS_T::PA_H_MFP
__IO uint32_t PA_H_MFP
Definition: Nano1X2Series.h:2941
PWM_T::PDMACH2
__I uint32_t PDMACH2
Definition: Nano1X2Series.h:6553
TIMER_T
Definition: Nano1X2Series.h:9027
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Nano1X2Series.h:10677
PWM_T::DATA2
__I uint32_t DATA2
Definition: Nano1X2Series.h:6125
SYS_T::IPRST_CTL1
__IO uint32_t IPRST_CTL1
Definition: Nano1X2Series.h:2758
SYS_T::PC_H_MFP
__IO uint32_t PC_H_MFP
Definition: Nano1X2Series.h:3145
I2C_T::DATA
__IO uint32_t DATA
Definition: Nano1X2Series.h:5004
I2C_T::TOUT
__IO uint32_t TOUT
Definition: Nano1X2Series.h:4992
CLK_T::FRQDIV1
__IO uint32_t FRQDIV1
Definition: Nano1X2Series.h:1374
TIMER_T::PRECNT
__IO uint32_t PRECNT
Definition: Nano1X2Series.h:9191
LCD_T::MEM_7
__IO uint32_t MEM_7
Definition: Nano1X2Series.h:5487
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: Nano1X2Series.h:1184
SYS_T::RegLockAddr
__IO uint32_t RegLockAddr
Definition: Nano1X2Series.h:3611
WWDT_T::VAL
__I uint32_t VAL
Definition: Nano1X2Series.h:10522
GPIO_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:4613
LCD_T::FCR
__IO uint32_t FCR
Definition: Nano1X2Series.h:5530
PWM_T::DATA1
__I uint32_t DATA1
Definition: Nano1X2Series.h:6060
PWM_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:5848
ACMP_T::RVCR
__IO uint32_t RVCR
Definition: Nano1X2Series.h:249
PWM_T::CLKSEL
__IO uint32_t CLKSEL
Definition: Nano1X2Series.h:5784
PDMA_T::SAR
__IO uint32_t SAR
Definition: Nano1X2Series.h:2127
SC_T::THR
__O uint32_t THR
Definition: Nano1X2Series.h:7570
GPIO_T::PUEN
__IO uint32_t PUEN
Definition: Nano1X2Series.h:4646
GP_DB_T::DBNCECON
__IO uint32_t DBNCECON
Definition: Nano1X2Series.h:4688
ACMP_IRQn
Definition: Nano1X2Series.h:112
UART0_IRQn
Definition: Nano1X2Series.h:99
SPI_T::VARCLK
__IO uint32_t VARCLK
Definition: Nano1X2Series.h:8778
PWM_T::DUTY0
__IO uint32_t DUTY0
Definition: Nano1X2Series.h:5976
UART_T
Definition: Nano1X2Series.h:9479
UART_T::IRCR
__IO uint32_t IRCR
Definition: Nano1X2Series.h:9947
LCD_T::MEM_6
__IO uint32_t MEM_6
Definition: Nano1X2Series.h:5469
ADC_T::PDMA
__I uint32_t PDMA
Definition: Nano1X2Series.h:648
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano1X2Series.h:8625
SC1_IRQn
Definition: Nano1X2Series.h:107
SC0_IRQn
Definition: Nano1X2Series.h:106
CLK_T::PLLCTL
__IO uint32_t PLLCTL
Definition: Nano1X2Series.h:1300
I2C_T::SAMASK0
__IO uint32_t SAMASK0
Definition: Nano1X2Series.h:5053
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: Nano1X2Series.h:1008
CLK_T::WK_INTSTS
__IO uint32_t WK_INTSTS
Definition: Nano1X2Series.h:1336
GP_DB_T
Definition: Nano1X2Series.h:4651
SC_T::PINCSR
__IO uint32_t PINCSR
Definition: Nano1X2Series.h:8055
SPI_T::FFCTL
__IO uint32_t FFCTL
Definition: Nano1X2Series.h:8842
CLK_T::PWRCTL
__IO uint32_t PWRCTL
Definition: Nano1X2Series.h:983
SC_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:7658
LCD_T
Definition: Nano1X2Series.h:5241
CLK_T::CLKDIV0
__IO uint32_t CLKDIV0
Definition: Nano1X2Series.h:1247
UART_T::THR
__O uint32_t THR
Definition: Nano1X2Series.h:9509
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Nano1X2Series.h:10676
TIMER_T::CTL
__IO uint32_t CTL
Definition: Nano1X2Series.h:9178
I2C_T::SADDR1
__IO uint32_t SADDR1
Definition: Nano1X2Series.h:5038
PWM_T::CAPINTEN
__IO uint32_t CAPINTEN
Definition: Nano1X2Series.h:6338
SYS_T::Int_VREFCTL
__IO uint32_t Int_VREFCTL
Definition: Nano1X2Series.h:3488
SC_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:7852
ADC_T::CMPR0
__IO uint32_t CMPR0
Definition: Nano1X2Series.h:560
PWM_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano1X2Series.h:5908
SPI_T::TX1
__O uint32_t TX1
Definition: Nano1X2Series.h:8763
ADC_T::CHEN
__IO uint32_t CHEN
Definition: Nano1X2Series.h:529
EINT0_IRQn
Definition: Nano1X2Series.h:90
WDT_T::ISR
__IO uint32_t ISR
Definition: Nano1X2Series.h:10392
PWM0_IRQn
Definition: Nano1X2Series.h:94
SYS_T::TEMPCTL
__IO uint32_t TEMPCTL
Definition: Nano1X2Series.h:2833
LCD_IRQn
Definition: Nano1X2Series.h:108
SYS_T::PORCTL
__IO uint32_t PORCTL
Definition: Nano1X2Series.h:3338
GPIO_T::PIN
__I uint32_t PIN
Definition: Nano1X2Series.h:4275
UART_T::BAUD
__IO uint32_t BAUD
Definition: Nano1X2Series.h:9925
I2C_T::CON
__IO uint32_t CON
Definition: Nano1X2Series.h:4928
i2c.h
Nano102/112 series I2C driver header file.
SC_T::UACTL
__IO uint32_t UACTL
Definition: Nano1X2Series.h:8127
PWM_T
Definition: Nano1X2Series.h:5734