32#define SPI_FLASH_PORT SPI0
35#define TEST_LENGTH 256
45volatile uint32_t PDMA_CH1_INT_Flag;
46volatile uint32_t PDMA_CH2_INT_Flag;
57 uint32_t status =
PDMAGCR->GCRISR;
64 PDMA_CH1_INT_Flag = 1;
73 PDMA_CH2_INT_Flag = 1;
102 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
105 SPI_FLASH_PORT->CLKDIV = (SPI_FLASH_PORT->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | (0x14 <<
SPI_CLKDIV_DIVIDER1_Pos);
138 PDMA_CH1->
BCR = TEST_LENGTH;
141 PDMA_CH1->
SAR = u32SrcAddr;
144 PDMA_CH1->
DAR = SPI0_TX;
184 PDMA_CH2->
BCR = TEST_LENGTH;
187 PDMA_CH2->
SAR = SPI0_RX;
190 PDMA_CH2->
DAR = u32DstAddr;
210 unsigned int au32SourceData;
211 unsigned int au32DestinationData;
217 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
220 au32SourceData = 0x90;
221 SPI_FLASH_PORT->TX0 = au32SourceData;
231 au32SourceData = 0x0;
232 SPI_FLASH_PORT->TX0 = au32SourceData;
242 au32SourceData = 0x0;
243 SPI_FLASH_PORT->TX0 = au32SourceData;
250 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
253 au32DestinationData = SPI_FLASH_PORT->RX0;
255 return (au32DestinationData & 0xffff);
266 unsigned int au32SourceData;
272 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
275 au32SourceData = 0x06;
276 SPI_FLASH_PORT->TX0 = au32SourceData;
283 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
286 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
289 au32SourceData = 0xc7;
290 SPI_FLASH_PORT->TX0 = au32SourceData;
297 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
308 unsigned int au32SourceData;
309 unsigned int au32DestinationData;
315 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
318 au32SourceData = 0x0500;
319 SPI_FLASH_PORT->TX0 = au32SourceData;
326 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
329 au32DestinationData = SPI_FLASH_PORT->RX0;
331 return (au32DestinationData & 0xFF);
342 unsigned int au32SourceData;
343 unsigned int au32DestinationData;
349 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
352 au32SourceData = 0x3500;
353 SPI_FLASH_PORT->TX0 = au32SourceData;
360 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
363 au32DestinationData = SPI_FLASH_PORT->RX0;
365 return (au32DestinationData & 0xFF);
376 unsigned int ReturnValue;
381 ReturnValue = ReturnValue & 1;
383 while(ReturnValue!=0);
398 unsigned int au32SourceData;
404 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
407 au32SourceData = 0x06;
408 SPI_FLASH_PORT->TX0 = au32SourceData;
415 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
418 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
421 au32SourceData = 0x02;
422 SPI_FLASH_PORT->TX0 = au32SourceData;
432 au32SourceData = StartAddress;
433 SPI_FLASH_PORT->TX0 = au32SourceData;
446 PDMA_CH1_INT_Flag = 0;
452 if (PDMA_CH1_INT_Flag)
454 PDMA_CH1_INT_Flag = 0;
460 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
475 unsigned int au32SourceData;
481 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
484 au32SourceData = 0x03;
485 SPI_FLASH_PORT->TX0 = au32SourceData;
495 au32SourceData = StartAddress;
496 SPI_FLASH_PORT->TX0 = au32SourceData;
509 PDMA_CH2_INT_Flag = 0;
515 if (PDMA_CH2_INT_Flag)
517 PDMA_CH2_INT_Flag = 0;
523 SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
#define PDMA_CSR_MODE_SEL_Msk
#define DMA_GCR_DSSR0_CH1_SEL_Pos
#define SPI_CTL_RX_NEG_Msk
#define SPI_DMA_TX_DMA_EN_Msk
#define SPI_CTL_GO_BUSY_Msk
#define PDMA_CSR_APB_TWS_Msk
#define PDMA_CSR_MODE_SEL_Pos
#define SPI_CTL_TX_BIT_LEN_Msk
#define PDMA_IER_TD_IE_Msk
#define SPI_CTL_TX_NEG_Msk
#define SPI_CTL_SLAVE_Msk
#define PDMA_CSR_SAD_SEL_Msk
#define PDMA_CSR_DAD_SEL_Msk
#define SPI_CTL_TX_BIT_LEN_Pos
#define SPI_DMA_RX_DMA_EN_Msk
#define DMA_GCR_DSSR0_CH2_SEL_Pos
#define PDMA_ISR_TD_IS_Msk
#define SPI_CLKDIV_DIVIDER1_Pos
#define PDMA_IER_TABORT_IE_Msk
NuEdu-Basic01 SPI Flash with PDMA driver header file for NuEdu-SDK-Nano130.
#define CLK_APBCLK_SPI0_EN_Msk
#define CLK_AHBCLK_DMA_EN_Msk
#define PDMA_GET_CH_INT_STS(u32Ch)
Get PDMA Channel Interrupt Status.
#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask)
Clear PDMA Channel Interrupt Flag.
#define CLK
Pointer to CLK register structure.
#define SYS
Pointer to SYS register structure.
#define PDMAGCR
Pointer to PDMA global control register structure.
#define PDMA1_BASE
PDMA1 register base address.
#define SPI0_BASE
SPI0 register base address.
#define SYS_PE_L_MFP_PE1_MFP_SPI0_SS0
#define SYS_PE_L_MFP_PE3_MFP_SPI0_MISO0
#define SYS_PE_L_MFP_PE4_MFP_SPI0_MOSI0
#define SYS_PE_L_MFP_PE2_MFP_SPI0_SCLK
unsigned int SpiFlash_w_PDMA_ReadStatusReg2(void)
Read back the Status Register 2 from SPI Flash device.
void SpiFlash_w_PDMA_WaitReady(void)
Waiting for the BUSY bit of SPI Flash that be cleared to 0.
unsigned int SpiFlash_w_PDMA_ReadMidDid(void)
Read back the Manufacturer ID and Device ID from SPI Flash device.
void SpiFlash_w_PDMA_ChipErase(void)
This function do the chip erasing to SPI Flash device.
void PDMA_IRQHandler(void)
PDMA interrupt handler. Check the PDMA interrupt flag and clear the corresponding event flag.
void SpiFlash_w_PDMA_PageProgram(unsigned int StartAddress, unsigned int ByteCount)
This function do the page programming to SPI Flash device.
void Open_SPI_Flash(void)
Open GPIO port for SPI interface and configure this SPI controller as Master, MSB first,...
void Init_PDMA_CH1_for_SPI0_TX(uint32_t u32SrcAddr)
This function initializes the PDMA channel 1 for SPI0 transmitting TX and the data that will be trans...
unsigned int SpiFlash_w_PDMA_ReadStatusReg1(void)
Read back the Status Register 1 from SPI Flash device.
void Init_PDMA_CH2_for_SPI0_RX(uint32_t u32DstAddr)
This function initializes the PDMA channel 2 for SPI0 receiving RX and the receiving data will be sto...
void SpiFlash_w_PDMA_ReadData(unsigned int StartAddress, unsigned int ByteCount)
This function do the data reading from SPI Flash device.