| NANO100_BSP V3.05.000 The Board Support Package for Nano100BN Series

pdma.h
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1/**************************************************************************/
12#ifndef __PDMA_H__
13#define __PDMA_H__
14
15#ifdef __cplusplus
16 extern "C"
17{
18#endif
19
20
33/*---------------------------------------------------------------------------------------------------------*/
34/* Data Width Constant Definitions */
35/*---------------------------------------------------------------------------------------------------------*/
36#define PDMA_WIDTH_8 0x00080000UL
37#define PDMA_WIDTH_16 0x00100000UL
38#define PDMA_WIDTH_32 0x00000000UL
40/*---------------------------------------------------------------------------------------------------------*/
41/* Address Attribute Constant Definitions */
42/*---------------------------------------------------------------------------------------------------------*/
43#define PDMA_SAR_INC 0x00000000UL
44#define PDMA_SAR_FIX 0x00000020UL
45#define PDMA_SAR_WRA 0x00000030UL
46#define PDMA_DAR_INC 0x00000000UL
47#define PDMA_DAR_FIX 0x00000080UL
48#define PDMA_DAR_WRA 0x000000C0UL
50/*---------------------------------------------------------------------------------------------------------*/
51/* Peripheral Transfer Mode Constant Definitions */
52/*---------------------------------------------------------------------------------------------------------*/
53#define PDMA_SPI0_TX 0x00000000UL
54#define PDMA_SPI1_TX 0x00000001UL
55#define PDMA_UART0_TX 0x00000002UL
56#define PDMA_UART1_TX 0x00000003UL
57#define PDMA_USB_TX 0x00000004UL
58#define PDMA_I2S_TX 0x00000005UL
59#define PDMA_DAC0_TX 0x00000006UL
60#define PDMA_DAC1_TX 0x00000007UL
61#define PDMA_SPI2_TX 0x00000008UL
62#define PDMA_TMR0 0x00000009UL
63#define PDMA_TMR1 0x0000000AUL
64#define PDMA_TMR2 0x0000000BUL
65#define PDMA_TMR3 0x0000000CUL
67#define PDMA_SPI0_RX 0x00000010UL
68#define PDMA_SPI1_RX 0x00000011UL
69#define PDMA_UART0_RX 0x00000012UL
70#define PDMA_UART1_RX 0x00000013UL
71#define PDMA_USB_RX 0x00000014UL
72#define PDMA_I2S_RX 0x00000015UL
73#define PDMA_ADC 0x00000016UL
74#define PDMA_SPI2_RX 0x00000018UL
75#define PDMA_PWM0_CH0 0x00000019UL
76#define PDMA_PWM0_CH2 0x0000001AUL
77#define PDMA_PWM1_CH0 0x0000001BUL
78#define PDMA_PWM1_CH2 0x0000001CUL
79#define PDMA_MEM 0x0000001FUL /* end of group NANO100_PDMA_EXPORTED_CONSTANTS */
84
99#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMAGCR->GCRISR))
100
111#define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))))
112
124#define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA1->ISR + (uint32_t)((u32Ch-1)*0x100))) = (u32Mask))
125
137#define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA1->CSR +(uint32_t)((u32Ch-1)*0x100)))&PDMA_CSR_TRIG_EN_Msk)? 1 : 0)
138
150#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->SAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
151
163#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->DAR + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr))
164
176#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) \
177 do{\
178 if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_32) \
179 *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 2); \
180 else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_8) \
181 *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = (u32Count); \
182 else if (((uint32_t)*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) & PDMA_CSR_APB_TWS_Msk) == PDMA_WIDTH_16) \
183 *((__IO uint32_t *)((uint32_t)&PDMA1->BCR + (uint32_t)((u32Ch-1)*0x100))) = ((u32Count) << 1); \
184}while(0)
185
196#define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->CSR + (uint32_t)((u32Ch-1)*0x100))) &= ~PDMA_CSR_PDMACEN_Msk)
197
198 void PDMA_Open(uint32_t u32Mask);
199 void PDMA_Close(void);
200 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
201 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
202 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
203 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
204 void PDMA_Trigger(uint32_t u32Ch);
205 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
206 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
207 /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
209 /* end of group NANO100_PDMA_Driver */
211 /* end of group NANO100_Device_Driver */
213
214#ifdef __cplusplus
215}
216#endif
217
218#endif //__PDMA_H__
219
220/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
PDMA_SetTransferAddr
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
Definition: pdma.c:105
PDMA_Trigger
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
Definition: pdma.c:193
PDMA_SetTimeOut
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
Definition: pdma.c:174
PDMA_EnableInt
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
Definition: pdma.c:211
PDMA_Open
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
Definition: pdma.c:38
PDMA_Close
void PDMA_Close(void)
PDMA Close.
Definition: pdma.c:52
PDMA_DisableInt
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
Definition: pdma.c:229
PDMA_SetTransferMode
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
Definition: pdma.c:133
PDMA_SetTransferCnt
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
Definition: pdma.c:68