| NANO100_BSP V3.05.000 The Board Support Package for Nano100BN Series

spi.h
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1/****************************************************************************/
12#ifndef __SPI_H__
13#define __SPI_H__
14
15#ifdef __cplusplus
16 extern "C"
17{
18#endif
19
20
34#define SPI_MODE_0 (SPI_CTL_TX_NEG_Msk)
35#define SPI_MODE_1 (SPI_CTL_RX_NEG_Msk)
36#define SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk)
37#define SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk)
39#define SPI_SLAVE (SPI_CTL_SLAVE_Msk)
40#define SPI_MASTER (0x0)
42#define SPI_SS0 (0x1)
43#define SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk)
44#define SPI_SS0_ACTIVE_LOW (0x0)
46#define SPI_SS1 (0x2)
47#define SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk)
48#define SPI_SS1_ACTIVE_LOW (0x0)
50#define SPI_IE_MASK (0x01)
51#define SPI_SSTA_INTEN_MASK (0x04)
52#define SPI_FIFO_TX_INTEN_MASK (0x08)
53#define SPI_FIFO_RX_INTEN_MASK (0x10)
54#define SPI_FIFO_RXOVR_INTEN_MASK (0x20)
55#define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) /* end of group NANO100_SPI_EXPORTED_CONSTANTS */
59
60
71#define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSR |= SPI_SSR_SLV_ABORT_Msk )
72
79#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk )
80
87#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_INTSTS_Msk )
88
95#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSR &= ~SPI_SSR_NOSLVSEL_Msk )
96
103#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSR |= SPI_SSR_NOSLVSEL_Msk )
104
111#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RX_FIFO_CNT_Msk) >> SPI_STATUS_RX_FIFO_CNT_Pos) & 0xf )
112
121#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0)
122
131#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0)
132
141#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0)
142
149#define SPI_READ_RX0(spi) ( (spi)->RX0 )
150
156#define SPI_READ_RX1(spi) ( (spi)->RX1 )
157
165#define SPI_WRITE_TX0(spi, u32TxData) ( (spi)->TX0 = u32TxData )
166
174#define SPI_WRITE_TX1(spi, u32TxData) ( (spi)->TX1 = u32TxData )
175
183#define SPI_SET_SS0_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)))
184
192#define SPI_SET_SS0_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS0)) | SPI_SS0)
193
201#define SPI_SET_SS1_HIGH(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)))
202
210#define SPI_SET_SS1_LOW(spi) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SS1)) | SPI_SS1)
211
221#define SPI_SET_SS_LEVEL(spi, ss0, ss1) ((spi)->SSR = ((spi)->SSR & ~(SPI_SSR_AUTOSS_Msk|SPI_SSR_SS_LVL_Msk|SPI_SSR_SSR_Msk)) | (((ss1)^1) << 1) | ((ss0)^1))
222
229#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
230
237#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
238
246#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CTL_SP_CYCLE_Pos) )
247
254#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
255
262#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
263
271 static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
272{
273 if(u32Width == 32)
274 u32Width = 0;
275
276 spi->CTL = (spi->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (u32Width << SPI_CTL_TX_BIT_LEN_Pos);
277}
278
287#define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_GO_BUSY_Msk) == SPI_CTL_GO_BUSY_Msk ? 1:0)
288
295#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_GO_BUSY_Msk )
296
303#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUAL_IO_EN_Msk )
304
311#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DUAL_IO_DIR_Msk) | SPI_CTL_DUAL_IO_EN_Msk )
312
319#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= (SPI_CTL_DUAL_IO_DIR_Msk | SPI_CTL_DUAL_IO_EN_Msk) )
320
327#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_RX_DMA_EN_Msk )
328
335#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->DMA |= SPI_DMA_TX_DMA_EN_Msk )
336
343#define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOB_Msk )
344
351#define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOB_Msk )
352
359#define SPI_GET_STATUS(spi) ( (spi)->STATUS )
360
361uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
362 void SPI_Close(SPI_T *spi);
363 void SPI_ClearRxFIFO(SPI_T *spi);
364 void SPI_ClearTxFIFO(SPI_T *spi);
365 void SPI_DisableAutoSS(SPI_T *spi);
366 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
367uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
368 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
369 void SPI_DisableFIFO(SPI_T *spi);
370uint32_t SPI_GetBusClock(SPI_T *spi);
371 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
372 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
373 void SPI_EnableWakeup(SPI_T *spi);
374 void SPI_DisableWakeup(SPI_T *spi); /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
376 /* end of group NANO100_SPI_Driver */
378 /* end of group NANO100_Device_Driver */
380
381#ifdef __cplusplus
382}
383#endif
384
385#endif //__SPI_H__
386
387/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
SPI_CTL_TX_BIT_LEN_Pos
#define SPI_CTL_TX_BIT_LEN_Pos
Definition: Nano100Series.h:9579
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:292
SPI_SET_DATA_WIDTH
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
Set the data width of a SPI transaction.
Definition: spi.h:271
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:202
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:257
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:127
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:188
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:111
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:138
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:66
SPI_EnableWakeup
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
Definition: spi.c:318
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:101
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:47
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:212
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:91
SPI_DisableWakeup
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
Definition: spi.c:328
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:9291
SPI_T
Definition: Nano100Series.h:9191