| NANO100_BSP V3.05.000 The Board Support Package for Nano100BN Series

Functions
CLK Exported Functions
NANO100 Device Driver » CLK Driver » CLK Exported Constants
Collaboration diagram for CLK Exported Functions:

## Functions
void | CLK_DisableCKO (void)
| This function disable frequency output function. More...
void | CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
| This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More...
void | CLK_PowerDown (void)
| This function let system enter to Power-down mode. More...
void | CLK_Idle (void)
| This function let system enter to Idle mode. More...
uint32_t | CLK_GetHXTFreq (void)
| This function get external high frequency crystal frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetLXTFreq (void)
| This function get external low frequency crystal frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetHCLKFreq (void)
| This function get HCLK frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetCPUFreq (void)
| This function get CPU frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetPLLClockFreq (void)
| This function get PLL frequency. The frequency unit is Hz. More...
uint32_t | CLK_SetCoreClock (uint32_t u32Hclk)
| This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 ~ 42 MHz. More...
void | CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
| This function set HCLK clock source and HCLK clock divider. More...
void | CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
| This function set selected module clock source and module clock divider. More...
void | CLK_EnableXtalRC (uint32_t u32ClkMask)
| This function enable clock source. More...
void | CLK_DisableXtalRC (uint32_t u32ClkMask)
| This function disable clock source. More...
void | CLK_EnableModuleClock (uint32_t u32ModuleIdx)
| This function enable module clock. More...
void | CLK_DisableModuleClock (uint32_t u32ModuleIdx)
| This function disable module clock. More...
uint32_t | CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
| This function set PLL frequency. More...
void | CLK_DisablePLL (void)
| This function disable PLL. More...
int32_t | CLK_SysTickDelay (uint32_t us)
| This function execute delay function. More...
void | CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
| Enable System Tick counter. More...
void | CLK_DisableSysTick (void)
| Disable System Tick counter. More...
uint32_t | CLK_WaitClockReady (uint32_t u32ClkMask)
| This function check selected clock source status. More...

## Detailed Description

## Function Documentation

## ◆ CLK_DisableCKO()

void CLK_DisableCKO | ( | void |  | ) |

This function disable frequency output function.

Parameters

  None |

Returns
  None

Definition at line 32 of file clk.c.

## ◆ CLK_DisableModuleClock()

void CLK_DisableModuleClock | ( | uint32_t | u32ModuleIdx | ) |

This function disable module clock.

Parameters

  [in] | u32ModuleIdx | is module index. Including : GPIO_MODULE DMA_MODULE ISP_MODULE EBI_MODULE SRAM_MODULE TICK_MODULE SC2_MODULE SC1_MODULE SC0_MODULE USBD_MODULE I2S_MODULE ADC_MODULE PWM1_CH23_MODULE PWM1_CH01_MODULE PWM0_CH23_MODULE PWM0_CH01_MODULE UART1_MODULE UART0_MODULE SPI2_MODULE SPI1_MODULE SPI0_MODULE I2C1_MODULE I2C0_MODULE FDIV_MODULE TMR3_MODULE TMR2_MODULE TMR1_MODULE TMR0_MODULE RTC_MODULE WDT_MODULE LCD_MODULE DAC_MODULE

Returns
  None

Definition at line 478 of file clk.c.

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## ◆ CLK_DisablePLL()

void CLK_DisablePLL | ( | void |  | ) |

This function disable PLL.

Parameters

  None |

Returns
  None

Definition at line 546 of file clk.c.

## ◆ CLK_DisableSysTick()

void CLK_DisableSysTick | ( | void |  | ) |

Disable System Tick counter.

Returns
  None

This function disable System Tick counter.

Definition at line 606 of file clk.c.

## ◆ CLK_DisableXtalRC()

void CLK_DisableXtalRC | ( | uint32_t | u32ClkMask | ) |

This function disable clock source.

Parameters

  [in] | u32ClkMask | is clock source mask. Including: CLK_PWRCTL_HXT_EN_Msk CLK_PWRCTL_LXT_EN_Msk CLK_PWRCTL_HIRC_EN_Msk CLK_PWRCTL_LIRC_EN_Msk

Returns
  None

Definition at line 394 of file clk.c.

## ◆ CLK_EnableCKO()

void CLK_EnableCKO | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv
| ) |  |

This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider.

Parameters

  [in] | u32ClkSrc | is frequency divider function clock source CLK_CLKSEL2_FRQDIV_S_HXT CLK_CLKSEL2_FRQDIV_S_LXT CLK_CLKSEL2_FRQDIV_S_HCLK CLK_CLKSEL2_FRQDIV_S_HIRC
  [in] | u32ClkDiv | is divider output frequency selection.

Returns
  None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. The formula is: CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 55 of file clk.c.

## ◆ CLK_EnableModuleClock()

void CLK_EnableModuleClock | ( | uint32_t | u32ModuleIdx | ) |

This function enable module clock.

Parameters

  [in] | u32ModuleIdx | is module index. Including : GPIO_MODULE DMA_MODULE ISP_MODULE EBI_MODULE SRAM_MODULE TICK_MODULE SC2_MODULE SC1_MODULE SC0_MODULE USBD_MODULE I2S_MODULE ADC_MODULE PWM1_CH23_MODULE PWM1_CH01_MODULE PWM0_CH23_MODULE PWM0_CH01_MODULE UART1_MODULE UART0_MODULE SPI2_MODULE SPI1_MODULE SPI0_MODULE I2C1_MODULE I2C0_MODULE FDIV_MODULE TMR3_MODULE TMR2_MODULE TMR1_MODULE TMR0_MODULE RTC_MODULE WDT_MODULE LCD_MODULE DAC_MODULE

Returns
  None

Definition at line 436 of file clk.c.

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## ◆ CLK_EnablePLL()

uint32_t CLK_EnablePLL | ( | uint32_t | u32PllClkSrc,
|  | uint32_t | u32PllFreq
| ) |  |

This function set PLL frequency.

Parameters

  [in] | u32PllClkSrc | is PLL clock source. Including : CLK_PLLCTL_PLL_SRC_HIRC CLK_PLLCTL_PLL_SRC_HXT
  [in] | u32PllFreq | is PLL frequency

Returns
  None

Definition at line 491 of file clk.c.

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## ◆ CLK_EnableSysTick()

void CLK_EnableSysTick | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32Count
| ) |  |

Enable System Tick counter.

Parameters

  [in] | u32ClkSrc | is System Tick clock source. Including: CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 CLK_CLKSEL0_STCLKSEL_HCLK
  [in] | u32Count | is System Tick reload value. It should be 0x1~0xFFFFFF.

Returns
  None

This function set System Tick clock source, reload value, enable System Tick counter and interrupt. The register write-protection function should be disabled before using this function.

Definition at line 587 of file clk.c.

## ◆ CLK_EnableXtalRC()

void CLK_EnableXtalRC | ( | uint32_t | u32ClkMask | ) |

This function enable clock source.

Parameters

  [in] | u32ClkMask | is clock source mask. Including: CLK_PWRCTL_HXT_EN_Msk CLK_PWRCTL_LXT_EN_Msk CLK_PWRCTL_HIRC_EN_Msk CLK_PWRCTL_LIRC_EN_Msk

Returns
  None

Definition at line 369 of file clk.c.

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## ◆ CLK_GetCPUFreq()

uint32_t CLK_GetCPUFreq | ( | void |  | ) |

This function get CPU frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  CPU frequency

Definition at line 131 of file clk.c.

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## ◆ CLK_GetHCLKFreq()

uint32_t CLK_GetHCLKFreq | ( | void |  | ) |

This function get HCLK frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  HCLK frequency

Definition at line 119 of file clk.c.

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## ◆ CLK_GetHXTFreq()

uint32_t CLK_GetHXTFreq | ( | void |  | ) |

This function get external high frequency crystal frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  None

Definition at line 94 of file clk.c.

## ◆ CLK_GetLXTFreq()

uint32_t CLK_GetLXTFreq | ( | void |  | ) |

This function get external low frequency crystal frequency. The frequency unit is Hz.

Returns
  LXT frequency

Definition at line 106 of file clk.c.

## ◆ CLK_GetPLLClockFreq()

uint32_t CLK_GetPLLClockFreq | ( | void |  | ) |

This function get PLL frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  PLL frequency

Definition at line 142 of file clk.c.

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## ◆ CLK_Idle()

void CLK_Idle | ( | void |  | ) |

This function let system enter to Idle mode.

Returns
  None

Definition at line 83 of file clk.c.

## ◆ CLK_PowerDown()

void CLK_PowerDown | ( | void |  | ) |

This function let system enter to Power-down mode.

Parameters

  None |

Returns
  None

Definition at line 72 of file clk.c.

## ◆ CLK_SetCoreClock()

uint32_t CLK_SetCoreClock | ( | uint32_t | u32Hclk | ) |

This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 ~ 42 MHz.

Parameters

  [in] | u32Hclk | is HCLK frequency

Returns
  None

Definition at line 177 of file clk.c.

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## ◆ CLK_SetHCLK()

void CLK_SetHCLK | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv
| ) |  |

This function set HCLK clock source and HCLK clock divider.

Parameters

  [in] | u32ClkSrc | is HCLK clock source. Including : CLK_CLKSEL0_HCLK_S_HXT CLK_CLKSEL0_HCLK_S_LXT CLK_CLKSEL0_HCLK_S_PLL CLK_CLKSEL0_HCLK_S_LIRC CLK_CLKSEL0_HCLK_S_HIRC
  [in] | u32ClkDiv | is HCLK clock divider. Including : CLK_HCLK_CLK_DIVIDER(x)

Returns
  None

Definition at line 223 of file clk.c.

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## ◆ CLK_SetModuleClock()

void CLK_SetModuleClock | ( | uint32_t | u32ModuleIdx,
|  | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv
| ) |  |

This function set selected module clock source and module clock divider.

Parameters

  [in] | u32ModuleIdx | is module index.
  [in] | u32ClkSrc | is module clock source.
  [in] | u32ClkDiv | is module clock divider.

Returns
  None

Valid parameter combinations listed in following table:

Module index | Clock source | Divider
--- | --- | ---
GPIO_MODULE | x | x
DMA_MODULE | x | x
ISP_MODULE | x | x
EBI_MODULE | x | x
SRAM_MODULE | x | x
TICK_MODULE | x | x
SC2_MODULE | CLK_CLKSEL2_SC_S_HXT | CLK_SC2_CLK_DIVIDER(x)
SC2_MODULE | CLK_CLKSEL2_SC_S_PLL | CLK_SC2_CLK_DIVIDER(x)
SC2_MODULE | CLK_CLKSEL2_SC_S_HIRC | CLK_SC2_CLK_DIVIDER(x)
SC1_MODULE | CLK_CLKSEL2_SC_S_HXT | CLK_SC1_CLK_DIVIDER(x)
SC1_MODULE | CLK_CLKSEL2_SC_S_PLL | CLK_SC1_CLK_DIVIDER(x)
SC1_MODULE | CLK_CLKSEL2_SC_S_HIRC | CLK_SC1_CLK_DIVIDER(x)
SC0_MODULE | CLK_CLKSEL2_SC_S_HXT | CLK_SC0_CLK_DIVIDER(x)
SC0_MODULE | CLK_CLKSEL2_SC_S_PLL | CLK_SC0_CLK_DIVIDER(x)
SC0_MODULE | CLK_CLKSEL2_SC_S_HIRC | CLK_SC0_CLK_DIVIDER(x)
I2S_MODULE | CLK_CLKSEL2_I2S_S_HXT | CLK_I2S_CLK_DIVIDER(x)
I2S_MODULE | CLK_CLKSEL2_I2S_S_PLL | CLK_I2S_CLK_DIVIDER(x)
I2S_MODULE | CLK_CLKSEL2_I2S_S_HIRC | CLK_I2S_CLK_DIVIDER(x)
ADC_MODULE | CLK_CLKSEL1_ADC_S_HXT | CLK_ADC_CLK_DIVIDER(x)
ADC_MODULE | CLK_CLKSEL1_ADC_S_LXT | CLK_ADC_CLK_DIVIDER(x)
ADC_MODULE | CLK_CLKSEL1_ADC_S_PLL | CLK_ADC_CLK_DIVIDER(x)
ADC_MODULE | CLK_CLKSEL1_ADC_S_HIRC | CLK_ADC_CLK_DIVIDER(x)
USBD_MODULE | x | CLK_USB_CLK_DIVIDER(x)
PWM1_CH23_MODULE | CLK_CLKSEL2_PWM1_CH23_S_HXT | x
PWM1_CH23_MODULE | CLK_CLKSEL2_PWM1_CH23_S_LXT | x
PWM1_CH23_MODULE | CLK_CLKSEL2_PWM1_CH23_S_HCLK | x
PWM1_CH23_MODULE | CLK_CLKSEL2_PWM1_CH23_S_HIRC | x
PWM1_CH01_MODULE | CLK_CLKSEL2_PWM1_CH01_S_HXT | x
PWM1_CH01_MODULE | CLK_CLKSEL2_PWM1_CH01_S_LXT | x
PWM1_CH01_MODULE | CLK_CLKSEL2_PWM1_CH01_S_HCLK | x
PWM1_CH01_MODULE | CLK_CLKSEL2_PWM1_CH01_S_HIRC | x
LCD_MODULE | CLK_CLKSEL1_LCD_S_LXT | x
PWM0_CH23_MODULE | CLK_CLKSEL1_PWM0_CH23_S_HXT | x
PWM0_CH23_MODULE | CLK_CLKSEL1_PWM0_CH23_S_LXT | x
PWM0_CH23_MODULE | CLK_CLKSEL1_PWM0_CH23_S_HCLK | x
PWM0_CH23_MODULE | CLK_CLKSEL1_PWM0_CH23_S_HIRC | x
PWM0_CH01_MODULE | CLK_CLKSEL1_PWM0_CH01_S_HXT | x
PWM0_CH01_MODULE | CLK_CLKSEL1_PWM0_CH01_S_LXT | x
PWM0_CH01_MODULE | CLK_CLKSEL1_PWM0_CH01_S_HCLK | x
PWM0_CH01_MODULE | CLK_CLKSEL1_PWM0_CH01_S_HIRC | x
UART1_MODULE | CLK_CLKSEL1_UART_S_HXT | CLK_UART_CLK_DIVIDER(x)
UART1_MODULE | CLK_CLKSEL1_UART_S_LXT | CLK_UART_CLK_DIVIDER(x)
UART1_MODULE | CLK_CLKSEL1_UART_S_PLL | CLK_UART_CLK_DIVIDER(x)
UART1_MODULE | CLK_CLKSEL1_UART_S_HIRC | CLK_UART_CLK_DIVIDER(x)
UART0_MODULE | CLK_CLKSEL1_UART_S_HXT | CLK_UART_CLK_DIVIDER(x)
UART0_MODULE | CLK_CLKSEL1_UART_S_LXT | CLK_UART_CLK_DIVIDER(x)
UART0_MODULE | CLK_CLKSEL1_UART_S_PLL | CLK_UART_CLK_DIVIDER(x)
UART0_MODULE | CLK_CLKSEL1_UART_S_HIRC | CLK_UART_CLK_DIVIDER(x)
SPI2_MODULE | CLK_CLKSEL2_SPI2_S_PLL | x
SPI2_MODULE | CLK_CLKSEL2_SPI2_S_HCLK | x
SPI1_MODULE | CLK_CLKSEL2_SPI1_S_PLL | x
SPI1_MODULE | CLK_CLKSEL2_SPI1_S_HCLK | x
SPI0_MODULE | CLK_CLKSEL2_SPI0_S_PLL | x
SPI0_MODULE | CLK_CLKSEL2_SPI0_S_HCLK | x
I2C1_MODULE | x | x
I2C0_MODULE | x | x
FDIV_MODULE | CLK_CLKSEL2_FRQDIV_S_HXT | x
FDIV_MODULE | CLK_CLKSEL2_FRQDIV_S_LXT | x
FDIV_MODULE | CLK_CLKSEL2_FRQDIV_S_HCLK | x
FDIV_MODULE | CLK_CLKSEL2_FRQDIV_S_HIRC | x
TMR3_MODULE | CLK_CLKSEL2_TMR3_S_HXT | x
TMR3_MODULE | CLK_CLKSEL2_TMR3_S_LXT | x
TMR3_MODULE | CLK_CLKSEL2_TMR3_S_LIRC | x
TMR3_MODULE | CLK_CLKSEL2_TMR3_S_EXT | x
TMR3_MODULE | CLK_CLKSEL2_TMR3_S_HIRC | x
TMR2_MODULE | CLK_CLKSEL2_TMR2_S_HXT | x
TMR2_MODULE | CLK_CLKSEL2_TMR2_S_LXT | x
TMR2_MODULE | CLK_CLKSEL2_TMR2_S_LIRC | x
TMR2_MODULE | CLK_CLKSEL2_TMR2_S_EXT | x
TMR2_MODULE | CLK_CLKSEL2_TMR2_S_HIRC | x
TMR1_MODULE | CLK_CLKSEL1_TMR1_S_HXT | x
TMR1_MODULE | CLK_CLKSEL1_TMR1_S_LXT | x
TMR1_MODULE | CLK_CLKSEL1_TMR1_S_LIRC | x
TMR1_MODULE | CLK_CLKSEL1_TMR1_S_EXT | x
TMR1_MODULE | CLK_CLKSEL1_TMR1_S_HIRC | x
TMR0_MODULE | CLK_CLKSEL1_TMR0_S_HXT | x
TMR0_MODULE | CLK_CLKSEL1_TMR0_S_LXT | x
TMR0_MODULE | CLK_CLKSEL1_TMR0_S_LIRC | x
TMR0_MODULE | CLK_CLKSEL1_TMR0_S_EXT | x
TMR0_MODULE | CLK_CLKSEL1_TMR0_S_HIRC | x
RTC_MODULE | x | x
WDT_MODULE | x | x

|

Definition at line 339 of file clk.c.

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## ◆ CLK_SysTickDelay()

int32_t CLK_SysTickDelay | ( | uint32_t | us | ) |

This function execute delay function.

Parameters

  us | Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...

Returns
  0 success -1 clock time out

Use the SysTick to generate the delay time and the UNIT is in us. The SysTick clock source is from HCLK, i.e the same as system core clock.

Definition at line 560 of file clk.c.

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## ◆ CLK_WaitClockReady()

uint32_t CLK_WaitClockReady | ( | uint32_t | u32ClkMask | ) |

This function check selected clock source status.

Parameters

  [in] | u32ClkMask | is selected clock source. Including CLK_CLKSTATUS_CLK_SW_FAIL_Msk CLK_CLKSTATUS_HIRC_STB_Msk CLK_CLKSTATUS_LIRC_STB_Msk CLK_CLKSTATUS_PLL_STB_Msk CLK_CLKSTATUS_LXT_STB_Msk CLK_CLKSTATUS_HXT_STB_Msk

Returns
  0 clock is not stable 1 clock is stable

To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)

Definition at line 625 of file clk.c.

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