48 uint32_t u32MasterSlave,
50 uint32_t u32DataWidth,
53 if(u32DataWidth == 32)
72 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk;
77 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk;
82 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI2_RST_Msk;
113 spi->
SSR &= ~SPI_SSR_AUTOSS_Msk;
140 uint32_t u32ClkSrc, u32Div = 0;
164 if(u32BusClock > u32ClkSrc)
165 u32BusClock = u32ClkSrc;
167 if(u32BusClock != 0 )
169 u32Div = (u32ClkSrc / u32BusClock) - 1;
176 spi->
CLKDIV = (spi->
CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div;
178 return ( u32ClkSrc / (u32Div+1) );
204 spi->
CTL &= ~SPI_CTL_FIFOM_Msk;
240 return (u32ClkSrc / (u32Div + 1));
295 spi->
CTL &= ~SPI_CTL_INTEN_Msk;
298 spi->
SSR &= ~SPI_SSR_SSTA_INTEN_Msk;
301 spi->
FFCTL &= ~SPI_FFCTL_TX_INTEN_Msk;
304 spi->
FFCTL &= ~SPI_FFCTL_RX_INTEN_Msk;
307 spi->
FFCTL &= ~SPI_FFCTL_RXOVR_INTEN_Msk;
310 spi->
FFCTL &= ~SPI_FFCTL_TIMEOUT_EN_Msk;
330 spi->
CTL &= ~SPI_CTL_WKEUP_EN_Msk;
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
#define SPI_FFCTL_TX_THRESHOLD_Msk
#define SYS_IPRST_CTL2_SPI1_RST_Msk
#define SPI_CTL_WKEUP_EN_Msk
#define SPI_FFCTL_RX_THRESHOLD_Pos
#define SPI_FFCTL_RX_INTEN_Msk
#define SYS_IPRST_CTL2_SPI0_RST_Msk
#define SPI_FFCTL_TX_INTEN_Msk
#define SPI_FFCTL_RXOVR_INTEN_Msk
#define SPI_CTL_INTEN_Msk
#define SPI_SSR_AUTOSS_Msk
#define SPI_SSR_SSTA_INTEN_Msk
#define SPI_CLKDIV_DIVIDER1_Msk
#define SPI_CTL_TX_BIT_LEN_Pos
#define SPI_FFCTL_TIMEOUT_EN_Msk
#define SPI_FFCTL_RX_CLR_Msk
#define SPI_FFCTL_RX_THRESHOLD_Msk
#define SPI_SSR_SS_LVL_Msk
#define SPI_CTL_FIFOM_Msk
#define SPI_FFCTL_TX_THRESHOLD_Pos
#define SYS_IPRST_CTL2_SPI2_RST_Msk
#define SPI_FFCTL_TX_CLR_Msk
#define CLK_CLKSEL2_SPI1_S_HCLK
#define CLK_CLKSEL2_SPI0_S_HCLK
#define CLK_CLKSEL2_SPI2_S_HCLK
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
#define CLK_CLKSEL2_SPI2_S_Msk
#define CLK_CLKSEL2_SPI0_S_Msk
#define CLK_CLKSEL2_SPI1_S_Msk
#define CLK
Pointer to CLK register structure.
#define SPI1
Pointer to SPI1 register structure.
#define SYS
Pointer to SYS register structure.
#define SPI0
Pointer to SPI0 register structure.
#define SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_RXOVR_INTEN_MASK
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.