| NUC029FAE_BSP V3.02.000 The Board Support Package for NUC029FAE MCU

Modules | Macros
PWM Exported Constants
NUC029FAE Device Driver » PWM Driver
Collaboration diagram for PWM Exported Constants:

## Modules
| PWM Exported Functions

## Macros
#define | PWM_CHANNEL_NUM (6)
#define | PWM_CLK_DIV_1 (4UL)
#define | PWM_CLK_DIV_2 (0UL)
#define | PWM_CLK_DIV_4 (1UL)
#define | PWM_CLK_DIV_8 (2UL)
#define | PWM_CLK_DIV_16 (3UL)
#define | PWM_EDGE_ALIGNED (0UL)
#define | PWM_CENTER_ALIGNED (PWM_PCR_PWMTYPE_Msk)
#define | PWM_TRIGGER_ADC_CNTR_IS_0 PWM_TRGCON0_P0TRGEN_Msk
#define | PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_TRGCON0_CM0TRGFEN_Msk
#define | PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_TRGCON0_CNT0TRGEN_Msk
#define | PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_TRGCON0_CM0TRGREN_Msk
#define | PWM_FB0_EINT0 (PWM_PFBCON_BKEN0_Msk)
#define | PWM_FB0_ACMP1 (PWM_PFBCON_BKEN0_Msk | PWM_PFBCON_CPO1BKEN_Msk)
#define | PWM_FB1_EINT1 (PWM_PFBCON_BKEN1_Msk)
#define | PWM_FB1_ACMP0 (PWM_PFBCON_BKEN1_Msk | PWM_PFBCON_CPO0BKEN_Msk)
#define | PWM_PERIOD_INT_UNDERFLOW (0)
#define | PWM_PERIOD_INT_MATCH_CNR (PWM_PIER_INT_TYPE_Msk)

## Detailed Description

## Macro Definition Documentation

## ◆ PWM_CENTER_ALIGNED

#define PWM_CENTER_ALIGNED (PWM_PCR_PWMTYPE_Msk)

PWM working in center aligned type

Definition at line 39 of file pwm.h.

## ◆ PWM_CHANNEL_NUM

#define PWM_CHANNEL_NUM (6)

PWM channel number

Definition at line 32 of file pwm.h.

## ◆ PWM_CLK_DIV_1

#define PWM_CLK_DIV_1 (4UL)

PWM clock divide by 1

Definition at line 33 of file pwm.h.

## ◆ PWM_CLK_DIV_16

#define PWM_CLK_DIV_16 (3UL)

PWM clock divide by 16

Definition at line 37 of file pwm.h.

## ◆ PWM_CLK_DIV_2

#define PWM_CLK_DIV_2 (0UL)

PWM clock divide by 2

Definition at line 34 of file pwm.h.

## ◆ PWM_CLK_DIV_4

#define PWM_CLK_DIV_4 (1UL)

PWM clock divide by 4

Definition at line 35 of file pwm.h.

## ◆ PWM_CLK_DIV_8

#define PWM_CLK_DIV_8 (2UL)

PWM clock divide by 8

Definition at line 36 of file pwm.h.

## ◆ PWM_EDGE_ALIGNED

#define PWM_EDGE_ALIGNED (0UL)

PWM working in edge aligned type

Definition at line 38 of file pwm.h.

## ◆ PWM_FB0_ACMP1

#define PWM_FB0_ACMP1 (PWM_PFBCON_BKEN0_Msk | PWM_PFBCON_CPO1BKEN_Msk)

Comparator 1 as fault brake 0 source

Definition at line 45 of file pwm.h.

## ◆ PWM_FB0_EINT0

#define PWM_FB0_EINT0 (PWM_PFBCON_BKEN0_Msk)

External interrupt 0 as fault brake 0 source

Definition at line 44 of file pwm.h.

## ◆ PWM_FB1_ACMP0

#define PWM_FB1_ACMP0 (PWM_PFBCON_BKEN1_Msk | PWM_PFBCON_CPO0BKEN_Msk)

Comparator 0 as fault brake 1 source

Definition at line 47 of file pwm.h.

## ◆ PWM_FB1_EINT1

#define PWM_FB1_EINT1 (PWM_PFBCON_BKEN1_Msk)

External interrupt 1 as fault brake 1 source

Definition at line 46 of file pwm.h.

## ◆ PWM_PERIOD_INT_MATCH_CNR

#define PWM_PERIOD_INT_MATCH_CNR (PWM_PIER_INT_TYPE_Msk)

PWM period interrupt trigger if counter match CNR

Definition at line 49 of file pwm.h.

## ◆ PWM_PERIOD_INT_UNDERFLOW

#define PWM_PERIOD_INT_UNDERFLOW (0)

PWM period interrupt trigger if counter underflow

Definition at line 48 of file pwm.h.

## ◆ PWM_TRIGGER_ADC_CNTR_IS_0

#define PWM_TRIGGER_ADC_CNTR_IS_0 PWM_TRGCON0_P0TRGEN_Msk

PWM trigger ADC while counter matches 0

Definition at line 40 of file pwm.h.

## ◆ PWM_TRIGGER_ADC_CNTR_IS_CMR_D

#define PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_TRGCON0_CM0TRGFEN_Msk

PWM trigger ADC while counter matches CMR during down count

Definition at line 41 of file pwm.h.

## ◆ PWM_TRIGGER_ADC_CNTR_IS_CMR_U

#define PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_TRGCON0_CM0TRGREN_Msk

PWM trigger ADC while counter matches CMR during up count

Definition at line 43 of file pwm.h.

## ◆ PWM_TRIGGER_ADC_CNTR_IS_CNR

#define PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_TRGCON0_CNT0TRGEN_Msk

PWM trigger ADC while counter matches CNR

Definition at line 42 of file pwm.h.