| NUC029FAE_BSP V3.02.000 The Board Support Package for NUC029FAE MCU

core_cm0.h
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1/**************************************************************************/
7/* Copyright (c) 2009 - 2015 ARM LIMITED
8
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
19 specific prior written permission.
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
33
34
35#if defined ( __ICCARM__ )
36 #pragma system_include /* treat file as system include file for MISRA check */
37#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38 #pragma clang system_header /* treat file as system include file */
39#endif
40
41#ifndef __CORE_CM0_H_GENERIC
42#define __CORE_CM0_H_GENERIC
43
44#include <stdint.h>
45
46#ifdef __cplusplus
47 extern "C" {
48#endif
49
65/*******************************************************************************
66 * CMSIS definitions
67 ******************************************************************************/
73/* CMSIS CM0 definitions */
74#define __CM0_CMSIS_VERSION_MAIN (0x04U)
75#define __CM0_CMSIS_VERSION_SUB (0x1EU)
76#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
77 __CM0_CMSIS_VERSION_SUB )
79#define __CORTEX_M (0x00U)
82#if defined ( __CC_ARM )
83 #define __ASM __asm
84 #define __INLINE __inline
85 #define __STATIC_INLINE static __inline
86
87#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88 #define __ASM __asm
89 #define __INLINE __inline
90 #define __STATIC_INLINE static __inline
91
92#elif defined ( __GNUC__ )
93 #define __ASM __asm
94 #define __INLINE inline
95 #define __STATIC_INLINE static inline
96
97#elif defined ( __ICCARM__ )
98 #define __ASM __asm
99 #define __INLINE inline
100 #define __STATIC_INLINE static inline
101
102#elif defined ( __TMS470__ )
103 #define __ASM __asm
104 #define __STATIC_INLINE static inline
105
106#elif defined ( __TASKING__ )
107 #define __ASM __asm
108 #define __INLINE inline
109 #define __STATIC_INLINE static inline
110
111#elif defined ( __CSMC__ )
112 #define __packed
113 #define __ASM _asm
114 #define __INLINE inline
115 #define __STATIC_INLINE static inline
116
117#else
118 #error Unknown compiler
119#endif
120
124#define __FPU_USED 0U
125
126#if defined ( __CC_ARM )
127 #if defined __TARGET_FPU_VFP
128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129 #endif
130
131#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132 #if defined __ARM_PCS_VFP
133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134 #endif
135
136#elif defined ( __GNUC__ )
137 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139 #endif
140
141#elif defined ( __ICCARM__ )
142 #if defined __ARMVFP__
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #endif
145
146#elif defined ( __TMS470__ )
147 #if defined __TI_VFP_SUPPORT__
148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149 #endif
150
151#elif defined ( __TASKING__ )
152 #if defined __FPU_VFP__
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #endif
155
156#elif defined ( __CSMC__ )
157 #if ( __CSMC__ & 0x400U)
158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159 #endif
160
161#endif
162
163#include "core_cmInstr.h" /* Core Instruction Access */
164#include "core_cmFunc.h" /* Core Function Access */
165
166#ifdef __cplusplus
167}
168#endif
169
170#endif /* __CORE_CM0_H_GENERIC */
171
172#ifndef __CMSIS_GENERIC
173
174#ifndef __CORE_CM0_H_DEPENDANT
175#define __CORE_CM0_H_DEPENDANT
176
177#ifdef __cplusplus
178 extern "C" {
179#endif
180
181/* check device defines and use defaults */
182#if defined __CHECK_DEVICE_DEFINES
183 #ifndef __CM0_REV
184 #define __CM0_REV 0x0000U
185 #warning "__CM0_REV not defined in device header file; using default!"
186 #endif
187
188 #ifndef __NVIC_PRIO_BITS
189 #define __NVIC_PRIO_BITS 2U
190 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
191 #endif
192
193 #ifndef __Vendor_SysTickConfig
194 #define __Vendor_SysTickConfig 0U
195 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
196 #endif
197#endif
198
199/* IO definitions (access restrictions to peripheral registers) */
207#ifdef __cplusplus
208 #define __I volatile
209#else
210 #define __I volatile const
211#endif
212#define __O volatile
213#define __IO volatile
215/* following defines should be used for structure members */
216#define __IM volatile const
217#define __OM volatile
218#define __IOM volatile
224/*******************************************************************************
225 * Register Abstraction
226 Core Register contain:
227 - Core Register
228 - Core NVIC Register
229 - Core SCB Register
230 - Core SysTick Register
231 ******************************************************************************/
247 typedef union
248{
249 struct
250 {
251 uint32_t _reserved0:28;
252 uint32_t V:1;
253 uint32_t C:1;
254 uint32_t Z:1;
255 uint32_t N:1;
256 } b;
257 uint32_t w;
258} APSR_Type;
259
260/* APSR Register Definitions */
261#define APSR_N_Pos 31U
262#define APSR_N_Msk (1UL << APSR_N_Pos)
264#define APSR_Z_Pos 30U
265#define APSR_Z_Msk (1UL << APSR_Z_Pos)
267#define APSR_C_Pos 29U
268#define APSR_C_Msk (1UL << APSR_C_Pos)
270#define APSR_V_Pos 28U
271#define APSR_V_Msk (1UL << APSR_V_Pos)
277 typedef union
278{
279 struct
280 {
281 uint32_t ISR:9;
282 uint32_t _reserved0:23;
283 } b;
284 uint32_t w;
285} IPSR_Type;
286
287/* IPSR Register Definitions */
288#define IPSR_ISR_Pos 0U
289#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
295 typedef union
296{
297 struct
298 {
299 uint32_t ISR:9;
300 uint32_t _reserved0:15;
301 uint32_t T:1;
302 uint32_t _reserved1:3;
303 uint32_t V:1;
304 uint32_t C:1;
305 uint32_t Z:1;
306 uint32_t N:1;
307 } b;
308 uint32_t w;
309} xPSR_Type;
310
311/* xPSR Register Definitions */
312#define xPSR_N_Pos 31U
313#define xPSR_N_Msk (1UL << xPSR_N_Pos)
315#define xPSR_Z_Pos 30U
316#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
318#define xPSR_C_Pos 29U
319#define xPSR_C_Msk (1UL << xPSR_C_Pos)
321#define xPSR_V_Pos 28U
322#define xPSR_V_Msk (1UL << xPSR_V_Pos)
324#define xPSR_T_Pos 24U
325#define xPSR_T_Msk (1UL << xPSR_T_Pos)
327#define xPSR_ISR_Pos 0U
328#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
334 typedef union
335{
336 struct
337 {
338 uint32_t _reserved0:1;
339 uint32_t SPSEL:1;
340 uint32_t _reserved1:30;
341 } b;
342 uint32_t w;
343} CONTROL_Type;
344
345/* CONTROL Register Definitions */
346#define CONTROL_SPSEL_Pos 1U
347#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
362 typedef struct
363{
364 __IOM uint32_t ISER[1U];
365 uint32_t RESERVED0[31U];
366 __IOM uint32_t ICER[1U];
367 uint32_t RSERVED1[31U];
368 __IOM uint32_t ISPR[1U];
369 uint32_t RESERVED2[31U];
370 __IOM uint32_t ICPR[1U];
371 uint32_t RESERVED3[31U];
372 uint32_t RESERVED4[64U];
373 __IOM uint32_t IP[8U];
374} NVIC_Type;
375
389 typedef struct
390{
391 __IM uint32_t CPUID;
392 __IOM uint32_t ICSR;
393 uint32_t RESERVED0;
394 __IOM uint32_t AIRCR;
395 __IOM uint32_t SCR;
396 __IOM uint32_t CCR;
397 uint32_t RESERVED1;
398 __IOM uint32_t SHP[2U];
399 __IOM uint32_t SHCSR;
400} SCB_Type;
401
402/* SCB CPUID Register Definitions */
403#define SCB_CPUID_IMPLEMENTER_Pos 24U
404#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
406#define SCB_CPUID_VARIANT_Pos 20U
407#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
409#define SCB_CPUID_ARCHITECTURE_Pos 16U
410#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
412#define SCB_CPUID_PARTNO_Pos 4U
413#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
415#define SCB_CPUID_REVISION_Pos 0U
416#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
418/* SCB Interrupt Control State Register Definitions */
419#define SCB_ICSR_NMIPENDSET_Pos 31U
420#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
422#define SCB_ICSR_PENDSVSET_Pos 28U
423#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
425#define SCB_ICSR_PENDSVCLR_Pos 27U
426#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
428#define SCB_ICSR_PENDSTSET_Pos 26U
429#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
431#define SCB_ICSR_PENDSTCLR_Pos 25U
432#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
434#define SCB_ICSR_ISRPREEMPT_Pos 23U
435#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
437#define SCB_ICSR_ISRPENDING_Pos 22U
438#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
440#define SCB_ICSR_VECTPENDING_Pos 12U
441#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
443#define SCB_ICSR_VECTACTIVE_Pos 0U
444#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
446/* SCB Application Interrupt and Reset Control Register Definitions */
447#define SCB_AIRCR_VECTKEY_Pos 16U
448#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
450#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
451#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
453#define SCB_AIRCR_ENDIANESS_Pos 15U
454#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
456#define SCB_AIRCR_SYSRESETREQ_Pos 2U
457#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
459#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
460#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
462/* SCB System Control Register Definitions */
463#define SCB_SCR_SEVONPEND_Pos 4U
464#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
466#define SCB_SCR_SLEEPDEEP_Pos 2U
467#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
469#define SCB_SCR_SLEEPONEXIT_Pos 1U
470#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
472/* SCB Configuration Control Register Definitions */
473#define SCB_CCR_STKALIGN_Pos 9U
474#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
476#define SCB_CCR_UNALIGN_TRP_Pos 3U
477#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
479/* SCB System Handler Control and State Register Definitions */
480#define SCB_SHCSR_SVCALLPENDED_Pos 15U
481#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
496 typedef struct
497{
498 __IOM uint32_t CTRL;
499 __IOM uint32_t LOAD;
500 __IOM uint32_t VAL;
501 __IM uint32_t CALIB;
502} SysTick_Type;
503
504/* SysTick Control / Status Register Definitions */
505#define SysTick_CTRL_COUNTFLAG_Pos 16U
506#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
508#define SysTick_CTRL_CLKSOURCE_Pos 2U
509#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
511#define SysTick_CTRL_TICKINT_Pos 1U
512#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
514#define SysTick_CTRL_ENABLE_Pos 0U
515#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
517/* SysTick Reload Register Definitions */
518#define SysTick_LOAD_RELOAD_Pos 0U
519#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
521/* SysTick Current Register Definitions */
522#define SysTick_VAL_CURRENT_Pos 0U
523#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
525/* SysTick Calibration Register Definitions */
526#define SysTick_CALIB_NOREF_Pos 31U
527#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
529#define SysTick_CALIB_SKEW_Pos 30U
530#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
532#define SysTick_CALIB_TENMS_Pos 0U
533#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
561#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
562
569#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
570
581/* Memory mapping of Cortex-M0 Hardware */
582#define SCS_BASE (0xE000E000UL)
583#define SysTick_BASE (SCS_BASE + 0x0010UL)
584#define NVIC_BASE (SCS_BASE + 0x0100UL)
585#define SCB_BASE (SCS_BASE + 0x0D00UL)
587#define SCB ((SCB_Type *) SCB_BASE )
588#define SysTick ((SysTick_Type *) SysTick_BASE )
589#define NVIC ((NVIC_Type *) NVIC_BASE )
596/*******************************************************************************
597 * Hardware Abstraction Layer
598 Core Function Interface contains:
599 - Core NVIC Functions
600 - Core SysTick Functions
601 - Core Register Access Functions
602 ******************************************************************************/
609/* ########################## NVIC functions #################################### */
617/* Interrupt Priorities are WORD accessible only under ARMv6M */
618/* The following MACROS handle generation of the register offset and byte masks */
619#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
620#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
621#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
622
623
629__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
630{
631 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
632}
633
634
640__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
641{
642 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
643}
644
645
653__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
654{
655 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
656}
657
658
664__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
665{
666 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
667}
668
669
675__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
676{
677 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
678}
679
680
688__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
689{
690 if ((int32_t)(IRQn) < 0)
691 {
692 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
693 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
694 }
695 else
696 {
697 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
699 }
700}
701
702
712__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
713{
714
715 if ((int32_t)(IRQn) < 0)
716 {
717 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
718 }
719 else
720 {
721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
722 }
723}
724
725
730__STATIC_INLINE void NVIC_SystemReset(void)
731{
732 __DSB(); /* Ensure all outstanding memory accesses included
733 buffered write are completed before reset */
734 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
735 SCB_AIRCR_SYSRESETREQ_Msk);
736 __DSB(); /* Ensure completion of memory access */
737
738 for(;;) /* wait until reset */
739 {
740 __NOP();
741 }
742}
743
748/* ################################## SysTick function ############################################ */
756#if (__Vendor_SysTickConfig == 0U)
757
769__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
770{
771 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
772 {
773 return (1UL); /* Reload value impossible */
774 }
775
776 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
777 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
778 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
779 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
780 SysTick_CTRL_TICKINT_Msk |
781 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
782 return (0UL); /* Function successful */
783}
784
785#endif
786
792#ifdef __cplusplus
793}
794#endif
795
796#endif /* __CORE_CM0_H_DEPENDANT */
797
798#endif /* __CMSIS_GENERIC */
__IM
#define __IM
Definition: core_cm0.h:216
__IOM
#define __IOM
Definition: core_cm0.h:218
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm0.h:730
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm0.h:712
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm0.h:688
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm0.h:640
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm0.h:675
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm0.h:629
_IP_IDX
#define _IP_IDX(IRQn)
Definition: core_cm0.h:621
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm0.h:664
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: core_cm0.h:619
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: core_cm0.h:620
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm0.h:653
SCB_Type::ICSR
__IOM uint32_t ICSR
Definition: core_cm0.h:392
SCB_Type::RESERVED0
uint32_t RESERVED0
Definition: core_cm0.h:393
xPSR_Type::w
uint32_t w
Definition: core_cm0.h:308
xPSR_Type::Z
uint32_t Z
Definition: core_cm0.h:305
SCB_Type::CPUID
__IM uint32_t CPUID
Definition: core_cm0.h:391
SCB_Type::CCR
__IOM uint32_t CCR
Definition: core_cm0.h:396
xPSR_Type::N
uint32_t N
Definition: core_cm0.h:306
SCB_Type::SCR
__IOM uint32_t SCR
Definition: core_cm0.h:395
APSR_Type::Z
uint32_t Z
Definition: core_cm0.h:254
xPSR_Type::ISR
uint32_t ISR
Definition: core_cm0.h:299
xPSR_Type::C
uint32_t C
Definition: core_cm0.h:304
SysTick_Type::LOAD
__IOM uint32_t LOAD
Definition: core_cm0.h:499
IPSR_Type::w
uint32_t w
Definition: core_cm0.h:284
CONTROL_Type::w
uint32_t w
Definition: core_cm0.h:342
xPSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm0.h:302
SCB_Type::SHCSR
__IOM uint32_t SHCSR
Definition: core_cm0.h:399
APSR_Type::N
uint32_t N
Definition: core_cm0.h:255
xPSR_Type::T
uint32_t T
Definition: core_cm0.h:301
APSR_Type::V
uint32_t V
Definition: core_cm0.h:252
APSR_Type::C
uint32_t C
Definition: core_cm0.h:253
SysTick_Type::CTRL
__IOM uint32_t CTRL
Definition: core_cm0.h:498
CONTROL_Type::SPSEL
uint32_t SPSEL
Definition: core_cm0.h:339
SysTick_Type::VAL
__IOM uint32_t VAL
Definition: core_cm0.h:500
CONTROL_Type::_reserved1
uint32_t _reserved1
Definition: core_cm0.h:340
IPSR_Type::ISR
uint32_t ISR
Definition: core_cm0.h:281
IPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm0.h:282
SCB_Type::AIRCR
__IOM uint32_t AIRCR
Definition: core_cm0.h:394
SCB_Type::RESERVED1
uint32_t RESERVED1
Definition: core_cm0.h:397
APSR_Type::w
uint32_t w
Definition: core_cm0.h:257
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm0.h:769
xPSR_Type::V
uint32_t V
Definition: core_cm0.h:303
xPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm0.h:300
CONTROL_Type::_reserved0
uint32_t _reserved0
Definition: core_cm0.h:338
APSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm0.h:251
SysTick_Type::CALIB
__IM uint32_t CALIB
Definition: core_cm0.h:501
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0.h:447
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0.h:457
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0.h:515
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0.h:519
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0.h:512
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0.h:509
SCB
#define SCB
Definition: core_cm0.h:587
NVIC
#define NVIC
Definition: core_cm0.h:589
SysTick
#define SysTick
Definition: core_cm0.h:588
IRQn_Type
enum IRQn IRQn_Type
IRQn
IRQn
Definition: NUC029FAE.h:74
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: NUC029FAE.h:116
SysTick_IRQn
@ SysTick_IRQn
Definition: NUC029FAE.h:81
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:363
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:390
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:497
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:248
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:335
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:278
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:296