| NUC029FAE_BSP V3.02.000 The Board Support Package for NUC029FAE MCU

Modules
Core Debug Registers (CoreDebug)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Tick Timer (SysTick)

Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. More...

Collaboration diagram for Core Debug Registers (CoreDebug):

## Modules
| Core register bit field macros
| Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

## Detailed Description

Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file.