| NUC029FAE_BSP V3.02.000 The Board Support Package for NUC029FAE MCU

Data Structures | Macros
core_cm0.h File Reference

CMSIS Cortex-M0 Core Peripheral Access Layer Header File. More...

`#include <stdint.h>`
`#include "core_cmInstr.h"`
`#include "core_cmFunc.h"`
Include dependency graph for core_cm0.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

## Data Structures
union | APSR_Type
| Union type to access the Application Program Status Register (APSR). More...
union | IPSR_Type
| Union type to access the Interrupt Program Status Register (IPSR). More...
union | xPSR_Type
| Union type to access the Special-Purpose Program Status Registers (xPSR). More...
union | CONTROL_Type
| Union type to access the Control Registers (CONTROL). More...
struct | NVIC_Type
| Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
struct | SCB_Type
| Structure type to access the System Control Block (SCB). More...
struct | SysTick_Type
| Structure type to access the System Timer (SysTick). More...

## Macros
#define | __CORE_CM0_H_GENERIC
#define | __CM0_CMSIS_VERSION_MAIN (0x04U)
#define | __CM0_CMSIS_VERSION_SUB (0x1EU)
#define | __CM0_CMSIS_VERSION
#define | __CORTEX_M (0x00U)
#define | __FPU_USED 0U
#define | __CORE_CM0_H_DEPENDANT
#define | __I volatile const
#define | __O volatile
#define | __IO volatile
#define | __IM volatile const /*! Defines 'read only' structure member permissions */
#define | __OM volatile /*! Defines 'write only' structure member permissions */
#define | __IOM volatile /*! Defines 'read / write' structure member permissions */
#define | APSR_N_Pos 31U
#define | APSR_N_Msk (1UL << APSR_N_Pos)
#define | APSR_Z_Pos 30U
#define | APSR_Z_Msk (1UL << APSR_Z_Pos)
#define | APSR_C_Pos 29U
#define | APSR_C_Msk (1UL << APSR_C_Pos)
#define | APSR_V_Pos 28U
#define | APSR_V_Msk (1UL << APSR_V_Pos)
#define | IPSR_ISR_Pos 0U
#define | IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
#define | xPSR_N_Pos 31U
#define | xPSR_N_Msk (1UL << xPSR_N_Pos)
#define | xPSR_Z_Pos 30U
#define | xPSR_Z_Msk (1UL << xPSR_Z_Pos)
#define | xPSR_C_Pos 29U
#define | xPSR_C_Msk (1UL << xPSR_C_Pos)
#define | xPSR_V_Pos 28U
#define | xPSR_V_Msk (1UL << xPSR_V_Pos)
#define | xPSR_T_Pos 24U
#define | xPSR_T_Msk (1UL << xPSR_T_Pos)
#define | xPSR_ISR_Pos 0U
#define | xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
#define | CONTROL_SPSEL_Pos 1U
#define | CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
#define | SCB_CPUID_IMPLEMENTER_Pos 24U
#define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
#define | SCB_CPUID_VARIANT_Pos 20U
#define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
#define | SCB_CPUID_ARCHITECTURE_Pos 16U
#define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
#define | SCB_CPUID_PARTNO_Pos 4U
#define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
#define | SCB_CPUID_REVISION_Pos 0U
#define | SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
#define | SCB_ICSR_NMIPENDSET_Pos 31U
#define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
#define | SCB_ICSR_PENDSVSET_Pos 28U
#define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
#define | SCB_ICSR_PENDSVCLR_Pos 27U
#define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define | SCB_ICSR_PENDSTSET_Pos 26U
#define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
#define | SCB_ICSR_PENDSTCLR_Pos 25U
#define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define | SCB_ICSR_ISRPREEMPT_Pos 23U
#define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define | SCB_ICSR_ISRPENDING_Pos 22U
#define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
#define | SCB_ICSR_VECTPENDING_Pos 12U
#define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
#define | SCB_ICSR_VECTACTIVE_Pos 0U
#define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
#define | SCB_AIRCR_VECTKEY_Pos 16U
#define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define | SCB_AIRCR_VECTKEYSTAT_Pos 16U
#define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
#define | SCB_AIRCR_ENDIANESS_Pos 15U
#define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
#define | SCB_AIRCR_SYSRESETREQ_Pos 2U
#define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define | SCB_AIRCR_VECTCLRACTIVE_Pos 1U
#define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define | SCB_SCR_SEVONPEND_Pos 4U
#define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
#define | SCB_SCR_SLEEPDEEP_Pos 2U
#define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define | SCB_SCR_SLEEPONEXIT_Pos 1U
#define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
#define | SCB_CCR_STKALIGN_Pos 9U
#define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
#define | SCB_CCR_UNALIGN_TRP_Pos 3U
#define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
#define | SCB_SHCSR_SVCALLPENDED_Pos 15U
#define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
#define | SysTick_CTRL_COUNTFLAG_Pos 16U
#define | SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
#define | SysTick_CTRL_CLKSOURCE_Pos 2U
#define | SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
#define | SysTick_CTRL_TICKINT_Pos 1U
#define | SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
#define | SysTick_CTRL_ENABLE_Pos 0U
#define | SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
#define | SysTick_LOAD_RELOAD_Pos 0U
#define | SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
#define | SysTick_VAL_CURRENT_Pos 0U
#define | SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
#define | SysTick_CALIB_NOREF_Pos 31U
#define | SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
#define | SysTick_CALIB_SKEW_Pos 30U
#define | SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
#define | SysTick_CALIB_TENMS_Pos 0U
#define | SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
#define | _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
| Mask and shift a bit field value for use in a register bit range. More...
#define | _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
| Mask and shift a register value to extract a bit filed value. More...
#define | SCS_BASE (0xE000E000UL)
#define | SysTick_BASE (SCS_BASE + 0x0010UL)
#define | NVIC_BASE (SCS_BASE + 0x0100UL)
#define | SCB_BASE (SCS_BASE + 0x0D00UL)
#define | SCB ((SCB_Type *) SCB_BASE )
#define | SysTick ((SysTick_Type *) SysTick_BASE )
#define | NVIC ((NVIC_Type *) NVIC_BASE )
#define | _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define | _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define | _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
__STATIC_INLINE void | NVIC_EnableIRQ (IRQn_Type IRQn)
| Enable External Interrupt. More...
__STATIC_INLINE void | NVIC_DisableIRQ (IRQn_Type IRQn)
| Disable External Interrupt. More...
__STATIC_INLINE uint32_t | NVIC_GetPendingIRQ (IRQn_Type IRQn)
| Get Pending Interrupt. More...
__STATIC_INLINE void | NVIC_SetPendingIRQ (IRQn_Type IRQn)
| Set Pending Interrupt. More...
__STATIC_INLINE void | NVIC_ClearPendingIRQ (IRQn_Type IRQn)
| Clear Pending Interrupt. More...
__STATIC_INLINE void | NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
| Set Interrupt Priority. More...
__STATIC_INLINE uint32_t | NVIC_GetPriority (IRQn_Type IRQn)
| Get Interrupt Priority. More...
__STATIC_INLINE void | NVIC_SystemReset (void)
| System Reset. More...
__STATIC_INLINE uint32_t | SysTick_Config (uint32_t ticks)
| System Tick Configuration. More...

## Detailed Description

CMSIS Cortex-M0 Core Peripheral Access Layer Header File.

Version
  V4.30

Date
  20. October 2015

Definition in file core_cm0.h.

## Macro Definition Documentation

## ◆ __CM0_CMSIS_VERSION

#define __CM0_CMSIS_VERSION

Value:
((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB )
__CM0_CMSIS_VERSION_SUB
#define __CM0_CMSIS_VERSION_SUB
Definition: core_cm0.h:75
__CM0_CMSIS_VERSION_MAIN
#define __CM0_CMSIS_VERSION_MAIN
Definition: core_cm0.h:74

CMSIS HAL version number

Definition at line 77 of file core_cm0.h.

## ◆ __CM0_CMSIS_VERSION_MAIN

#define __CM0_CMSIS_VERSION_MAIN (0x04U)

[31:16] CMSIS HAL main version

Definition at line 74 of file core_cm0.h.

## ◆ __CM0_CMSIS_VERSION_SUB

#define __CM0_CMSIS_VERSION_SUB (0x1EU)

[15:0] CMSIS HAL sub version

Definition at line 75 of file core_cm0.h.

## ◆ __CORE_CM0_H_DEPENDANT

#define __CORE_CM0_H_DEPENDANT

Definition at line 175 of file core_cm0.h.

## ◆ __CORE_CM0_H_GENERIC

#define __CORE_CM0_H_GENERIC

Definition at line 42 of file core_cm0.h.

## ◆ __CORTEX_M

#define __CORTEX_M (0x00U)

Cortex-M Core

Definition at line 79 of file core_cm0.h.

## ◆ __FPU_USED

#define __FPU_USED 0U

__FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all

Definition at line 124 of file core_cm0.h.

## ◆ __I

#define __I volatile const

Defines 'read only' permissions

Definition at line 210 of file core_cm0.h.

## ◆ __IM

#define __IM volatile const /*! Defines 'read only' structure member permissions */

Definition at line 216 of file core_cm0.h.

## ◆ __IO

#define __IO volatile

Defines 'read / write' permissions

Definition at line 213 of file core_cm0.h.

## ◆ __IOM

#define __IOM volatile /*! Defines 'read / write' structure member permissions */

Definition at line 218 of file core_cm0.h.

## ◆ __O

#define __O volatile

Defines 'write only' permissions

Definition at line 212 of file core_cm0.h.

## ◆ __OM

#define __OM volatile /*! Defines 'write only' structure member permissions */

Definition at line 217 of file core_cm0.h.