33 CLK->APBCLK &= (~CLK_APBCLK_CLKOCKEN_Msk);
54void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
63 CLK->CLKSEL2 = (
CLK->CLKSEL2 & (~CLK_CLKSEL2_CLKOSEL_Msk)) | u32ClkSrc;
72 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
158 CLK->CLKDIV &= (~CLK_CLKDIV_HCLKDIV_Msk);
181 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
200 CLK->CLKDIV = (
CLK->CLKDIV & ~CLK_CLKDIV_HCLKDIV_Msk) | u32ClkDiv;
203 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc;
260 uint32_t u32tmp=0,u32sel=0,u32div=0;
265 u32tmp = *(
volatile uint32_t *)(u32sel);
267 *(
volatile uint32_t *)(u32sel) = u32tmp;
273 u32tmp = *(
volatile uint32_t *)(u32div);
275 *(
volatile uint32_t *)(u32div) = u32tmp;
290 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
310 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
313 SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
314 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
316 SysTick->LOAD = u32Count;
318 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
342 CLK->PWRCTL = (
CLK->PWRCTL & ~CLK_PWRCTL_XTLEN_Msk) | u32ClkMask;
344 CLK->PWRCTL |= u32ClkMask;
357 CLK->PWRCTL &=~u32ClkMask;
422 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32NRT;
423 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR,u32Best;
466 u32PllFreq = u32PllFreq;
471 u32PllFreq = u32PllFreq << 1;
476 u32PllFreq = u32PllFreq << 2;
485 u32Min = (uint32_t) - 1;
488 for(u32NR=u32NRT; u32NR <= 33; u32NR++)
490 u32Tmp = u32PllSrcClk / u32NR;
491 if((u32Tmp > 1600000) && (u32Tmp < 15000000))
493 for(u32NF = 2; u32NF <= 513; u32NF++)
495 u32Tmp2 = u32Tmp * u32NF;
496 if((u32Tmp2 >= 100000000) && (u32Tmp2 <= 200000000))
498 u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
508 CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
514 return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
525 u32Min = (uint32_t) - 1;
528 for(u32NR=u32NRT; u32NR <= 33; u32NR++)
530 u32Tmp = u32PllSrcClk / u32NR;
531 if((u32Tmp > 1600000) && (u32Tmp < 15000000))
533 for(u32NF = 2; u32NF <= 513; u32NF++)
535 u32Tmp2 = u32Tmp * u32NF;
536 if((u32Tmp2 >= 100000000) && (u32Tmp2 <= 200000000))
538 u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
546 if(u32Min == u32Best)
549 CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
555 return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
605 SysTick->VAL = (0x00);
606 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
609 while (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) &&
611 if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0)
632 int32_t i32TimeOutCnt = 2160000;
634 while((
CLK->STATUS & u32ClkMask) != u32ClkMask)
636 if(i32TimeOutCnt-- <= 0)
Mini58 series peripheral access layer header file. This file contains all the peripheral register's d...
#define CLK_CLKSEL0_STCLKSEL_HCLK
#define CLK_PLLCTL_PLLSRC_HXT
#define CLK_PLLCTL_72MHz_HXT
#define MODULE_CLKSEL_Msk(x)
#define CLK_PWRCTL_XTLEN_HXT
#define CLK_CLKSEL0_HCLKSEL_PLL
#define CLK_PWRCTL_XTLEN_LXT
#define CLK_PLLCTL_PLLSRC_HIRC
#define MODULE_CLKSEL_Pos(x)
#define CLK_CLKDIV_HCLK(x)
#define MODULE_CLKDIV_Pos(x)
#define MODULE_IP_EN_Pos(x)
#define MODULE_CLKDIV_Msk(x)
#define CLK_PLLCTL_72MHz_HIRC
void CLK_Idle(void)
This function let system enter to Idle mode.
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
This function set SysTick clock source.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
Set PLL frequency.
void CLK_DisableCKO(void)
This function disable frequency output function.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
void CLK_DisablePLL(void)
Disable PLL.
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
int32_t CLK_SysTickDelay(uint32_t us)
This function execute delay function.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
void CLK_DisableSysTick(void)
Disable System Tick counter.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
#define CLK_STATUS_PLLSTB_Msk
#define CLK_PWRCTL_PDEN_Msk
#define CLK_CLKOCTL_CLKOEN_Msk
#define CLK_CLKSEL0_HCLKSEL_Msk
#define CLK_PLLCTL_PD_Msk
#define CLK_PWRCTL_HIRCEN_Msk
#define CLK_STATUS_XTLSTB_Msk
#define CLK_APBCLK_CLKOCKEN_Msk
#define CLK_PWRCTL_XTLEN_Msk
#define CLK_STATUS_HIRCSTB_Msk
#define CLK_CLKOCTL_DIV1EN_Pos
#define CLK_PWRCTL_PDWKIF_Msk
#define CLK
Pointer to CLK register structure.
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from CPU registers.