| MINI55_BSP V3.03.000 The Board Support Package for Mini55 Series MCU

Mini55Series.h
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1/**************************************************************************/
53#ifndef __MINI55SERIES_H__
54#define __MINI55SERIES_H__
55
56#ifdef __cplusplus
57 extern "C" {
58#endif
59
70/******************************************************************************/
71/* Processor and Core Peripherals */
72/******************************************************************************/
81 typedef enum IRQn
82{
83 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
84
85 NonMaskableInt_IRQn = -14,
86 HardFault_IRQn = -13,
87 SVCall_IRQn = -5,
88 PendSV_IRQn = -2,
89 SysTick_IRQn = -1,
91 /****** Mini55 specific Interrupt Numbers ***********************************************/
92
93 BOD_IRQn = 0,
94 WDT_IRQn = 1,
95 EINT0_IRQn = 2,
96 EINT1_IRQn = 3,
97 GPIO01_IRQn = 4,
98 GPIO234_IRQn = 5,
99 PWM_IRQn = 6,
100 FB_IRQn = 7,
101 TMR0_IRQn = 8,
102 TMR1_IRQn = 9,
103 UART0_IRQn = 12,
104 UART1_IRQn = 13,
105 SPI_IRQn = 14,
106 GPIO5_IRQn = 16,
107 HIRC_IRQn = 17,
108 I2C_IRQn = 18,
109 ACMP_IRQn = 25,
110 PDWU_IRQn = 28,
111 ADC_IRQn = 29
113} IRQn_Type;
114
115
116/*
117 * ==========================================================================
118 * ----------- Processor and Core Peripheral Section ------------------------
119 * ==========================================================================
120 */
121
122
123/* Configuration of the Cortex-M0 Processor and Core Peripherals */
124#define __CM0_REV 0x0201
125#define __NVIC_PRIO_BITS 2
126#define __Vendor_SysTickConfig 0
127#define __MPU_PRESENT 0
128#define __FPU_PRESENT 0 /* end of group MINI55_CMSIS */
131
132
133#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
134#include "system_Mini55Series.h" /* Mini55 Series System include file */
135#include <stdint.h>
136
137/******************************************************************************/
138/* Device Specific Peripheral registers structures */
139/******************************************************************************/
145#if defined ( __CC_ARM )
146#pragma anon_unions
147#endif
148
149
150/******************************************************************************/
151/* Device Specific Peripheral registers structures */
152/******************************************************************************/
153
154
155
156/*---------------------- Analog Comparator Controller -------------------------*/
162 typedef struct
163{
164
165
205 __IO uint32_t CTL[2];
206
237 __IO uint32_t STATUS;
238
252 __IO uint32_t VREF;
253
254} ACMP_T;
255
261#define ACMP_CTL_ACMPEN_Pos (0)
262#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos)
264#define ACMP_CTL_ACMPIE_Pos (1)
265#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos)
267#define ACMP_CTL_HYSSEL_Pos (2)
268#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos)
270#define ACMP_CTL_NEGSEL_Pos (4)
271#define ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos)
273#define ACMP_CTL_RTRGEN_Pos (8)
274#define ACMP_CTL_RTRGEN_Msk (0x1ul << ACMP_CTL_RTRGEN_Pos)
276#define ACMP_CTL_FTRGEN_Pos (9)
277#define ACMP_CTL_FTRGEN_Msk (0x1ul << ACMP_CTL_FTRGEN_Pos)
279#define ACMP_CTL_SMPTSEL_Pos (12)
280#define ACMP_CTL_SMPTSEL_Msk (0x1ul << ACMP_CTL_SMPTSEL_Pos)
282#define ACMP_CTL_POSSEL_Pos (29)
283#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos)
285#define ACMP_STATUS_ACMPIF0_Pos (0)
286#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos)
288#define ACMP_STATUS_ACMPIF1_Pos (1)
289#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos)
291#define ACMP_STATUS_ACMPO0_Pos (2)
292#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos)
294#define ACMP_STATUS_ACMPO1_Pos (3)
295#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos)
297#define ACMP_VREF_CRVCTL_Pos (0)
298#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
300#define ACMP_VREF_IREFSEL_Pos (7)
301#define ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos) /* ACMP_CONST */ /* end of ACMP register group */
305
306
307/*---------------------- Analog to Digital Converter -------------------------*/
313 typedef struct
314{
315
316
336 __I uint32_t DAT;
338 uint32_t RESERVED0[7];
340
341
382 __IO uint32_t CTL;
383
437 __IO uint32_t CHEN;
438
478 __IO uint32_t CMP[2];
479
512 __IO uint32_t STATUS;
514 uint32_t RESERVED1[4];
516
517
529 __IO uint32_t TRGDLY;
530
557 __IO uint32_t EXTSMPT;
558
601 __IO uint32_t SEQCTL;
602
622 __I uint32_t SEQDAT0;
623
643 __I uint32_t SEQDAT1;
644
645} ADC_T;
646
652#define ADC_DAT_RESULT_Pos (0)
653#define ADC_DAT_RESULT_Msk (0x3fful << ADC_DAT_RESULT_Pos)
655#define ADC_DAT_OV_Pos (16)
656#define ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
658#define ADC_DAT_VALID_Pos (17)
659#define ADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
661#define ADC_CTL_ADCEN_Pos (0)
662#define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
664#define ADC_CTL_ADCIEN_Pos (1)
665#define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
667#define ADC_CTL_HWTRGSEL_Pos (4)
668#define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
670#define ADC_CTL_HWTRGCOND_Pos (6)
671#define ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
673#define ADC_CTL_HWTRGEN_Pos (8)
674#define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
676#define ADC_CTL_SWTRG_Pos (11)
677#define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
679#define ADC_CTL_VREFSEL_Pos (12)
680#define ADC_CTL_VREFSEL_Msk (0x1ul << ADC_CTL_VREFSEL_Pos)
682#define ADC_CHEN_CHEN0_Pos (0)
683#define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
685#define ADC_CHEN_CHEN1_Pos (1)
686#define ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
688#define ADC_CHEN_CHEN2_Pos (2)
689#define ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
691#define ADC_CHEN_CHEN3_Pos (3)
692#define ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
694#define ADC_CHEN_CHEN4_Pos (4)
695#define ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
697#define ADC_CHEN_CHEN5_Pos (5)
698#define ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
700#define ADC_CHEN_CHEN6_Pos (6)
701#define ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
703#define ADC_CHEN_CHEN7_Pos (7)
704#define ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
706#define ADC_CHEN_CH7SEL_Pos (8)
707#define ADC_CHEN_CH7SEL_Msk (0x1ul << ADC_CHEN_CH7SEL_Pos)
709#define ADC_CHEN_CHEN8_Pos (9)
710#define ADC_CHEN_CHEN8_Msk (0x1ul << ADC_CHEN_CHEN8_Pos)
712#define ADC_CHEN_CHEN9_Pos (10)
713#define ADC_CHEN_CHEN9_Msk (0x1ul << ADC_CHEN_CHEN9_Pos)
715#define ADC_CHEN_CHEN10_Pos (11)
716#define ADC_CHEN_CHEN10_Msk (0x1ul << ADC_CHEN_CHEN10_Pos)
718#define ADC_CHEN_CHEN11_Pos (12)
719#define ADC_CHEN_CHEN11_Msk (0x1ul << ADC_CHEN_CHEN11_Pos)
721#define ADC_CHEN_BGEN_Pos (13)
722#define ADC_CHEN_BGEN_Msk (0x1ul << ADC_CHEN_BGEN_Pos)
724#define ADC_CMP_ADCMPEN_Pos (0)
725#define ADC_CMP_ADCMPEN_Msk (0x1ul << ADC_CMP_ADCMPEN_Pos)
727#define ADC_CMP_ADCMPIE_Pos (1)
728#define ADC_CMP_ADCMPIE_Msk (0x1ul << ADC_CMP_ADCMPIE_Pos)
730#define ADC_CMP_CMPCOND_Pos (2)
731#define ADC_CMP_CMPCOND_Msk (0x1ul << ADC_CMP_CMPCOND_Pos)
733#define ADC_CMP_CMPCH_Pos (3)
734#define ADC_CMP_CMPCH_Msk (0xful << ADC_CMP_CMPCH_Pos)
736#define ADC_CMP_CMPMCNT_Pos (8)
737#define ADC_CMP_CMPMCNT_Msk (0xful << ADC_CMP_CMPMCNT_Pos)
739#define ADC_CMP_CMPDAT_Pos (16)
740#define ADC_CMP_CMPDAT_Msk (0x3fful << ADC_CMP_CMPDAT_Pos)
742#define ADC_STATUS_ADIF_Pos (0)
743#define ADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
745#define ADC_STATUS_ADCMPF0_Pos (1)
746#define ADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos)
748#define ADC_STATUS_ADCMPF1_Pos (2)
749#define ADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos)
751#define ADC_STATUS_BUSY_Pos (3)
752#define ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos)
754#define ADC_STATUS_CHANNEL_Pos (4)
755#define ADC_STATUS_CHANNEL_Msk (0x7ul << ADC_STATUS_CHANNEL_Pos)
757#define ADC_STATUS_VALID_Pos (8)
758#define ADC_STATUS_VALID_Msk (0x1ul << ADC_STATUS_VALID_Pos)
760#define ADC_STATUS_OV_Pos (16)
761#define ADC_STATUS_OV_Msk (0x1ul << ADC_STATUS_OV_Pos)
763#define ADC_TRGDLY_DELAY_Pos (0)
764#define ADC_TRGDLY_DELAY_Msk (0xfful << ADC_TRGDLY_DELAY_Pos)
766#define ADC_EXTSMPT_EXTSMPT_Pos (0)
767#define ADC_EXTSMPT_EXTSMPT_Msk (0xful << ADC_EXTSMPT_EXTSMPT_Pos)
769#define ADC_SEQCTL_SEQEN_Pos (0)
770#define ADC_SEQCTL_SEQEN_Msk (0x1ul << ADC_SEQCTL_SEQEN_Pos)
772#define ADC_SEQCTL_SEQTYPE_Pos (1)
773#define ADC_SEQCTL_SEQTYPE_Msk (0x1ul << ADC_SEQCTL_SEQTYPE_Pos)
775#define ADC_SEQCTL_MODESEL_Pos (2)
776#define ADC_SEQCTL_MODESEL_Msk (0x3ul << ADC_SEQCTL_MODESEL_Pos)
778#define ADC_SEQCTL_TRG1TYPE_Pos (8)
779#define ADC_SEQCTL_TRG1TYPE_Msk (0x3ul << ADC_SEQCTL_TRG1TYPE_Pos)
781#define ADC_SEQCTL_TRG1SRC_Pos (10)
782#define ADC_SEQCTL_TRG1SRC_Msk (0x3ul << ADC_SEQCTL_TRG1SRC_Pos)
784#define ADC_SEQCTL_TRG2TYPE_Pos (16)
785#define ADC_SEQCTL_TRG2TYPE_Msk (0x3ul << ADC_SEQCTL_TRG2TYPE_Pos)
787#define ADC_SEQCTL_TRG2SRC_Pos (18)
788#define ADC_SEQCTL_TRG2SRC_Msk (0x3ul << ADC_SEQCTL_TRG2SRC_Pos)
790#define ADC_SEQDAT0_RESULT_Pos (0)
791#define ADC_SEQDAT0_RESULT_Msk (0x3fful << ADC_SEQDAT0_RESULT_Pos)
793#define ADC_SEQDAT0_OV_Pos (16)
794#define ADC_SEQDAT0_OV_Msk (0x1ul << ADC_SEQDAT0_OV_Pos)
796#define ADC_SEQDAT0_VALID_Pos (17)
797#define ADC_SEQDAT0_VALID_Msk (0x1ul << ADC_SEQDAT0_VALID_Pos)
799#define ADC_SEQDAT1_RESULT_Pos (0)
800#define ADC_SEQDAT1_RESULT_Msk (0x3fful << ADC_SEQDAT1_RESULT_Pos)
802#define ADC_SEQDAT1_OV_Pos (16)
803#define ADC_SEQDAT1_OV_Msk (0x1ul << ADC_SEQDAT1_OV_Pos)
805#define ADC_SEQDAT1_VALID_Pos (17)
806#define ADC_SEQDAT1_VALID_Msk (0x1ul << ADC_SEQDAT1_VALID_Pos) /* ADC_CONST */ /* end of ADC register group */
810
811
812/*---------------------- System Clock Controller -------------------------*/
818 typedef struct
819{
820
821
875 __IO uint32_t PWRCTL;
876
891 __IO uint32_t AHBCLK;
892
942 __IO uint32_t APBCLK;
943
969 __IO uint32_t STATUS;
970
1004 __IO uint32_t CLKSEL0;
1005
1060 __IO uint32_t CLKSEL1;
1061
1078 __IO uint32_t CLKDIV;
1079
1094 __IO uint32_t CLKSEL2;
1096 uint32_t RESERVED0[1];
1098
1099
1120 __IO uint32_t CLKOCTL;
1121
1122} CLK_T;
1123
1129#define CLK_PWRCTL_XTLEN_Pos (0)
1130#define CLK_PWRCTL_XTLEN_Msk (0x3ul << CLK_PWRCTL_XTLEN_Pos)
1132#define CLK_PWRCTL_HIRCEN_Pos (2)
1133#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos)
1135#define CLK_PWRCTL_LIRCEN_Pos (3)
1136#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
1138#define CLK_PWRCTL_PDWKDLY_Pos (4)
1139#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
1141#define CLK_PWRCTL_PDWKIEN_Pos (5)
1142#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
1144#define CLK_PWRCTL_PDWKIF_Pos (6)
1145#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos)
1147#define CLK_PWRCTL_PDEN_Pos (7)
1148#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
1150#define CLK_PWRCTL_PDLXT_Pos (9)
1151#define CLK_PWRCTL_PDLXT_Msk (0x1ul << CLK_PWRCTL_PDLXT_Pos)
1153#define CLK_PWRCTL_HXTGAIN_Pos (10)
1154#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)
1156#define CLK_AHBCLK_ISPCKEN_Pos (2)
1157#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
1159#define CLK_AHBCLK_HDIVCKEN_Pos (4)
1160#define CLK_AHBCLK_HDIVCKEN_Msk (0x1ul << CLK_AHBCLK_HDIVCKEN_Pos)
1162#define CLK_APBCLK_WDTCKEN_Pos (0)
1163#define CLK_APBCLK_WDTCKEN_Msk (0x1ul << CLK_APBCLK_WDTCKEN_Pos)
1165#define CLK_APBCLK_TMR0CKEN_Pos (2)
1166#define CLK_APBCLK_TMR0CKEN_Msk (0x1ul << CLK_APBCLK_TMR0CKEN_Pos)
1168#define CLK_APBCLK_TMR1CKEN_Pos (3)
1169#define CLK_APBCLK_TMR1CKEN_Msk (0x1ul << CLK_APBCLK_TMR1CKEN_Pos)
1171#define CLK_APBCLK_CLKOCKEN_Pos (6)
1172#define CLK_APBCLK_CLKOCKEN_Msk (0x1ul << CLK_APBCLK_CLKOCKEN_Pos)
1174#define CLK_APBCLK_I2CCKEN_Pos (8)
1175#define CLK_APBCLK_I2CCKEN_Msk (0x1ul << CLK_APBCLK_I2CCKEN_Pos)
1177#define CLK_APBCLK_SPICKEN_Pos (12)
1178#define CLK_APBCLK_SPICKEN_Msk (0x1ul << CLK_APBCLK_SPICKEN_Pos)
1180#define CLK_APBCLK_UART0CKEN_Pos (16)
1181#define CLK_APBCLK_UART0CKEN_Msk (0x1ul << CLK_APBCLK_UART0CKEN_Pos)
1183#define CLK_APBCLK_UART1CKEN_Pos (17)
1184#define CLK_APBCLK_UART1CKEN_Msk (0x1ul << CLK_APBCLK_UART1CKEN_Pos)
1186#define CLK_APBCLK_PWMCH01CKEN_Pos (20)
1187#define CLK_APBCLK_PWMCH01CKEN_Msk (0x1ul << CLK_APBCLK_PWMCH01CKEN_Pos)
1189#define CLK_APBCLK_PWMCH23CKEN_Pos (21)
1190#define CLK_APBCLK_PWMCH23CKEN_Msk (0x1ul << CLK_APBCLK_PWMCH23CKEN_Pos)
1192#define CLK_APBCLK_PWMCH45CKEN_Pos (22)
1193#define CLK_APBCLK_PWMCH45CKEN_Msk (0x1ul << CLK_APBCLK_PWMCH45CKEN_Pos)
1195#define CLK_APBCLK_ADCCKEN_Pos (28)
1196#define CLK_APBCLK_ADCCKEN_Msk (0x1ul << CLK_APBCLK_ADCCKEN_Pos)
1198#define CLK_APBCLK_ACMPCKEN_Pos (30)
1199#define CLK_APBCLK_ACMPCKEN_Msk (0x1ul << CLK_APBCLK_ACMPCKEN_Pos)
1201#define CLK_STATUS_XTLSTB_Pos (0)
1202#define CLK_STATUS_XTLSTB_Msk (0x1ul << CLK_STATUS_XTLSTB_Pos)
1204#define CLK_STATUS_LIRCSTB_Pos (3)
1205#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
1207#define CLK_STATUS_HIRCSTB_Pos (4)
1208#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos)
1210#define CLK_STATUS_CLKSFAIL_Pos (7)
1211#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
1213#define CLK_CLKSEL0_HCLKSEL_Pos (0)
1214#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
1216#define CLK_CLKSEL0_STCLKSEL_Pos (3)
1217#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)
1219#define CLK_CLKSEL1_WDTSEL_Pos (0)
1220#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
1222#define CLK_CLKSEL1_ADCSEL_Pos (2)
1223#define CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos)
1225#define CLK_CLKSEL1_SPISEL_Pos (4)
1226#define CLK_CLKSEL1_SPISEL_Msk (0x1ul << CLK_CLKSEL1_SPISEL_Pos)
1228#define CLK_CLKSEL1_TMR0SEL_Pos (8)
1229#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
1231#define CLK_CLKSEL1_TMR1SEL_Pos (12)
1232#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
1234#define CLK_CLKSEL1_UART0SEL_Pos (24)
1235#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos)
1237#define CLK_CLKSEL1_UART1SEL_Pos (26)
1238#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos)
1240#define CLK_CLKDIV_HCLKDIV_Pos (0)
1241#define CLK_CLKDIV_HCLKDIV_Msk (0xful << CLK_CLKDIV_HCLKDIV_Pos)
1243#define CLK_CLKDIV_UART0DIV_Pos (8)
1244#define CLK_CLKDIV_UART0DIV_Msk (0xful << CLK_CLKDIV_UART0DIV_Pos)
1246#define CLK_CLKDIV_UART1DIV_Pos (12)
1247#define CLK_CLKDIV_UART1DIV_Msk (0xful << CLK_CLKDIV_UART1DIV_Pos)
1249#define CLK_CLKDIV_ADCDIV_Pos (16)
1250#define CLK_CLKDIV_ADCDIV_Msk (0xfful << CLK_CLKDIV_ADCDIV_Pos)
1252#define CLK_CLKSEL2_FDIVSEL_Pos (2)
1253#define CLK_CLKSEL2_FDIVSEL_Msk (0x3ul << CLK_CLKSEL2_FDIVSEL_Pos)
1255#define CLK_CLKOCTL_FSEL_Pos (0)
1256#define CLK_CLKOCTL_FSEL_Msk (0xful << CLK_CLKOCTL_FSEL_Pos)
1258#define CLK_CLKOCTL_CLKOEN_Pos (4)
1259#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
1261#define CLK_CLKOCTL_DIV1EN_Pos (5)
1262#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /* CLK_CONST */ /* end of CLK register group */
1266
1267
1268/*---------------------- Flash Memory Controller -------------------------*/
1274 typedef struct
1275{
1276
1277
1312 __IO uint32_t ISPCTL;
1313
1324 __IO uint32_t ISPADDR;
1325
1337 __IO uint32_t ISPDAT;
1338
1355 __IO uint32_t ISPCMD;
1356
1369 __IO uint32_t ISPTRG;
1370
1383 __I uint32_t DFBA;
1385 uint32_t RESERVED0[10];
1387
1388
1414 __I uint32_t ISPSTS;
1415
1416} FMC_T;
1417
1423#define FMC_ISPCTL_ISPEN_Pos (0)
1424#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
1426#define FMC_ISPCTL_BS_Pos (1)
1427#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
1429#define FMC_ISPCTL_APUEN_Pos (3)
1430#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
1432#define FMC_ISPCTL_CFGUEN_Pos (4)
1433#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
1435#define FMC_ISPCTL_LDUEN_Pos (5)
1436#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
1438#define FMC_ISPCTL_ISPFF_Pos (6)
1439#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
1441#define FMC_ISPADDR_ISPADR_Pos (0)
1442#define FMC_ISPADDR_ISPADR_Msk (0xfffffffful << FMC_ISPADDR_ISPADR_Pos)
1444#define FMC_ISPDAT_ISPDAT_Pos (0)
1445#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
1447#define FMC_ISPCMD_CMD_Pos (0)
1448#define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos)
1450#define FMC_ISPTRG_ISPGO_Pos (0)
1451#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
1453#define FMC_DFBA_DFBA_Pos (0)
1454#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
1456#define FMC_ISPSTS_ISPBUSY_Pos (0)
1457#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
1459#define FMC_ISPSTS_CBS_Pos (1)
1460#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
1462#define FMC_ISPSTS_ISPFF_Pos (6)
1463#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
1465#define FMC_ISPSTS_VECMAP_Pos (9)
1466#define FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos) /* FMC_CONST */ /* end of FMC register group */
1470
1471
1472/*---------------------- General Purpose Input/Output Controller -------------------------*/
1478 typedef struct
1479{
1480
1481
1554 __IO uint32_t MODE;
1555
1568 __IO uint32_t DINOFF;
1569
1583 __IO uint32_t DOUT;
1584
1601 __IO uint32_t DATMSK;
1602
1615 __I uint32_t PIN;
1616
1635 __IO uint32_t DBEN;
1636
1656 __IO uint32_t INTTYPE;
1657
1684 __IO uint32_t INTEN;
1685
1702 __IO uint32_t INTSRC;
1703
1704} GPIO_T;
1705
1706
1707
1708 typedef struct
1709{
1710
1743 __IO uint32_t DBCTL;
1744
1745} GPIO_DB_T;
1746
1747
1753#define GP_MODE_MODE0_Pos (0)
1754#define GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
1756#define GP_MODE_MODE1_Pos (2)
1757#define GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
1759#define GP_MODE_MODE2_Pos (4)
1760#define GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
1762#define GP_MODE_MODE3_Pos (6)
1763#define GP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
1765#define GP_MODE_MODE4_Pos (8)
1766#define GP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
1768#define GP_MODE_MODE5_Pos (10)
1769#define GP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
1771#define GP_DINOFF_DINOFF0_Pos (16)
1772#define GP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
1774#define GP_DINOFF_DINOFF1_Pos (17)
1775#define GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
1777#define GP_DINOFF_DINOFF2_Pos (18)
1778#define GP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
1780#define GP_DINOFF_DINOFF3_Pos (19)
1781#define GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
1783#define GP_DINOFF_DINOFF4_Pos (20)
1784#define GP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
1786#define GP_DINOFF_DINOFF5_Pos (21)
1787#define GP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
1789#define GP_DINOFF_DINOFF6_Pos (22)
1790#define GP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
1792#define GP_DINOFF_DINOFF7_Pos (23)
1793#define GP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
1795#define GP_DOUT_DOUT0_Pos (0)
1796#define GP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
1798#define GP_DOUT_DOUT1_Pos (1)
1799#define GP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
1801#define GP_DOUT_DOUT2_Pos (2)
1802#define GP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
1804#define GP_DOUT_DOUT3_Pos (3)
1805#define GP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
1807#define GP_DOUT_DOUT4_Pos (4)
1808#define GP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
1810#define GP_DOUT_DOUT5_Pos (5)
1811#define GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
1813#define GP_DOUT_DOUT6_Pos (6)
1814#define GP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
1816#define GP_DOUT_DOUT7_Pos (7)
1817#define GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
1819#define GP_DATMSK_DATMSK0_Pos (0)
1820#define GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
1822#define GP_DATMSK_DATMSK1_Pos (1)
1823#define GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
1825#define GP_DATMSK_DATMSK2_Pos (2)
1826#define GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
1828#define GP_DATMSK_DATMSK3_Pos (3)
1829#define GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
1831#define GP_DATMSK_DATMSK4_Pos (4)
1832#define GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
1834#define GP_DATMSK_DATMSK5_Pos (5)
1835#define GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
1837#define GP_DATMSK_DATMSK6_Pos (6)
1838#define GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
1840#define GP_DATMSK_DATMSK7_Pos (7)
1841#define GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
1843#define GP_PIN_PIN0_Pos (0)
1844#define GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
1846#define GP_PIN_PIN1_Pos (1)
1847#define GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
1849#define GP_PIN_PIN2_Pos (2)
1850#define GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
1852#define GP_PIN_PIN3_Pos (3)
1853#define GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
1855#define GP_PIN_PIN4_Pos (4)
1856#define GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
1858#define GP_PIN_PIN5_Pos (5)
1859#define GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
1861#define GP_PIN_PIN6_Pos (6)
1862#define GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
1864#define GP_PIN_PIN7_Pos (7)
1865#define GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
1867#define GP_DBEN_DBEN0_Pos (0)
1868#define GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
1870#define GP_DBEN_DBEN1_Pos (1)
1871#define GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
1873#define GP_DBEN_DBEN2_Pos (2)
1874#define GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
1876#define GP_DBEN_DBEN3_Pos (3)
1877#define GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
1879#define GP_DBEN_DBEN4_Pos (4)
1880#define GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
1882#define GP_DBEN_DBEN5_Pos (5)
1883#define GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
1885#define GP_DBEN_DBEN6_Pos (6)
1886#define GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
1888#define GP_DBEN_DBEN7_Pos (7)
1889#define GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
1891#define GP_INTTYPE_TYPE0_Pos (0)
1892#define GP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
1894#define GP_INTTYPE_TYPE1_Pos (1)
1895#define GP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
1897#define GP_INTTYPE_TYPE2_Pos (2)
1898#define GP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
1900#define GP_INTTYPE_TYPE3_Pos (3)
1901#define GP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
1903#define GP_INTTYPE_TYPE4_Pos (4)
1904#define GP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
1906#define GP_INTTYPE_TYPE5_Pos (5)
1907#define GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
1909#define GP_INTTYPE_TYPE6_Pos (6)
1910#define GP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
1912#define GP_INTTYPE_TYPE7_Pos (7)
1913#define GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
1915#define GP_INTEN_FLIEN0_Pos (0)
1916#define GP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
1918#define GP_INTEN_FLIEN1_Pos (1)
1919#define GP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
1921#define GP_INTEN_FLIEN2_Pos (2)
1922#define GP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
1924#define GP_INTEN_FLIEN3_Pos (3)
1925#define GP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
1927#define GP_INTEN_FLIEN4_Pos (4)
1928#define GP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
1930#define GP_INTEN_FLIEN5_Pos (5)
1931#define GP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
1933#define GP_INTEN_FLIEN6_Pos (6)
1934#define GP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
1936#define GP_INTEN_FLIEN7_Pos (7)
1937#define GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
1939#define GP_INTEN_RHIEN0_Pos (16)
1940#define GP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
1942#define GP_INTEN_RHIEN1_Pos (17)
1943#define GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
1945#define GP_INTEN_RHIEN2_Pos (18)
1946#define GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
1948#define GP_INTEN_RHIEN3_Pos (19)
1949#define GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
1951#define GP_INTEN_RHIEN4_Pos (20)
1952#define GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
1954#define GP_INTEN_RHIEN5_Pos (21)
1955#define GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
1957#define GP_INTEN_RHIEN6_Pos (22)
1958#define GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
1960#define GP_INTEN_RHIEN7_Pos (23)
1961#define GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
1963#define GP_INTSRC_INTSRC0_Pos (0)
1964#define GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
1966#define GP_INTSRC_INTSRC1_Pos (1)
1967#define GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
1969#define GP_INTSRC_INTSRC2_Pos (2)
1970#define GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
1972#define GP_INTSRC_INTSRC3_Pos (3)
1973#define GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
1975#define GP_INTSRC_INTSRC4_Pos (4)
1976#define GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
1978#define GP_INTSRC_INTSRC5_Pos (5)
1979#define GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
1981#define GP_INTSRC_INTSRC6_Pos (6)
1982#define GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
1984#define GP_INTSRC_INTSRC7_Pos (7)
1985#define GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
1987#define GP_DBCTL_DBCLKSEL_Pos (0)
1988#define GP_DBCTL_DBCLKSEL_Msk (0xful << GP_DBCTL_DBCLKSEL_Pos)
1990#define GP_DBCTL_DBCLKSRC_Pos (4)
1991#define GP_DBCTL_DBCLKSRC_Msk (0x1ul << GP_DBCTL_DBCLKSRC_Pos)
1993#define GP_DBCTL_ICLKON_Pos (5)
1994#define GP_DBCTL_ICLKON_Msk (0x1ul << GP_DBCTL_ICLKON_Pos) /* GP_CONST */ /* end of GP register group */
1999
2000
2001/*---------------------- Hardware Divider -------------------------*/
2007 typedef struct
2008{
2009
2010
2021 __IO uint32_t DIVIDEND;
2022
2034 __IO uint32_t DIVISOR;
2035
2046 __IO uint32_t QUOTIENT;
2047
2058 __IO uint32_t REM;
2059
2073 __I uint32_t STATUS;
2074
2075} HDIV_T;
2076
2082#define HDIV_DIVIDEND_DIVIDEND_Pos (0)
2083#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos)
2085#define HDIV_DIVISOR_DIVISOR_Pos (0)
2086#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos)
2088#define HDIV_QUOTIENT_QUOTIENT_Pos (0)
2089#define HDIV_QUOTIENT_QUOTIENT_Msk (0xfffffffful << HDIV_QUOTIENT_QUOTIENT_Pos)
2091#define HDIV_REM_REM_Pos (0)
2092#define HDIV_REM_REM_Msk (0xfffffffful << HDIV_REM_REM_Pos)
2094#define HDIV_STATUS_DIVBYZERO_Pos (1)
2095#define HDIV_STATUS_DIVBYZERO_Msk (0x1ul << HDIV_STATUS_DIVBYZERO_Pos) /* HDIV_CONST */ /* end of HDIV register group */
2099
2100
2101/*---------------------- Inter-IC Bus Controller -------------------------*/
2107 typedef struct
2108{
2109
2110
2142 __IO uint32_t CTL;
2143
2159 __IO uint32_t ADDR0;
2160
2171 __IO uint32_t DAT;
2172
2192 __I uint32_t STATUS;
2193
2205 __IO uint32_t CLKDIV;
2206
2227 __IO uint32_t TOCTL;
2228
2244 __IO uint32_t ADDR1;
2245
2261 __IO uint32_t ADDR2;
2262
2278 __IO uint32_t ADDR3;
2279
2291 __IO uint32_t ADDRMSK0;
2292
2304 __IO uint32_t ADDRMSK1;
2305
2317 __IO uint32_t ADDRMSK2;
2318
2330 __IO uint32_t ADDRMSK3;
2332 uint32_t RESERVED0[2];
2334
2335
2368 __IO uint32_t CTL1;
2369
2389 __IO uint32_t STATUS1;
2390
2391} I2C_T;
2392
2398#define I2C_CTL_AA_Pos (2)
2399#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos)
2401#define I2C_CTL_SI_Pos (3)
2402#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos)
2404#define I2C_CTL_STO_Pos (4)
2405#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos)
2407#define I2C_CTL_STA_Pos (5)
2408#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos)
2410#define I2C_CTL_I2CEN_Pos (6)
2411#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos)
2413#define I2C_CTL_INTEN_Pos (7)
2414#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos)
2416#define I2C_ADDR0_GC_Pos (0)
2417#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
2419#define I2C_ADDR0_ADDR_Pos (1)
2420#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos)
2422#define I2C_DAT_DAT_Pos (0)
2423#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
2425#define I2C_STATUS_STATUS_Pos (0)
2426#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
2428#define I2C_CLKDIV_DIVIDER_Pos (0)
2429#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos)
2431#define I2C_TOCTL_TOIF_Pos (0)
2432#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos)
2434#define I2C_TOCTL_TOCDIV4_Pos (1)
2435#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos)
2437#define I2C_TOCTL_TOCEN_Pos (2)
2438#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
2440#define I2C_ADDR1_GC_Pos (0)
2441#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
2443#define I2C_ADDR1_ADDR_Pos (1)
2444#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos)
2446#define I2C_ADDR2_GC_Pos (0)
2447#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos)
2449#define I2C_ADDR2_ADDR_Pos (1)
2450#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos)
2452#define I2C_ADDR3_GC_Pos (0)
2453#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos)
2455#define I2C_ADDR3_ADDR_Pos (1)
2456#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos)
2458#define I2C_ADDRMSK0_ADDRMSK_Pos (1)
2459#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)
2461#define I2C_ADDRMSK1_ADDRMSK_Pos (1)
2462#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)
2464#define I2C_ADDRMSK2_ADDRMSK_Pos (1)
2465#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos)
2467#define I2C_ADDRMSK3_ADDRMSK_Pos (1)
2468#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos)
2470#define I2C_CTL1_WKEN_Pos (0)
2471#define I2C_CTL1_WKEN_Msk (0x1ul << I2C_CTL1_WKEN_Pos)
2473#define I2C_CTL1_FIFOEN_Pos (1)
2474#define I2C_CTL1_FIFOEN_Msk (0x1ul << I2C_CTL1_FIFOEN_Pos)
2476#define I2C_CTL1_NSTRETCH_Pos (2)
2477#define I2C_CTL1_NSTRETCH_Msk (0x1ul << I2C_CTL1_NSTRETCH_Pos)
2479#define I2C_CTL1_OVIEN_Pos (3)
2480#define I2C_CTL1_OVIEN_Msk (0x1ul << I2C_CTL1_OVIEN_Pos)
2482#define I2C_CTL1_URIEN_Pos (4)
2483#define I2C_CTL1_URIEN_Msk (0x1ul << I2C_CTL1_URIEN_Pos)
2485#define I2C_STATUS1_WKIF_Pos (0)
2486#define I2C_STATUS1_WKIF_Msk (0x1ul << I2C_STATUS1_WKIF_Pos)
2488#define I2C_STATUS1_FULL_Pos (1)
2489#define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos)
2491#define I2C_STATUS1_EMPTY_Pos (2)
2492#define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos)
2494#define I2C_STATUS1_OVIF_Pos (3)
2495#define I2C_STATUS1_OVIF_Msk (0x1ul << I2C_STATUS1_OVIF_Pos)
2497#define I2C_STATUS1_URIF_Pos (4)
2498#define I2C_STATUS1_URIF_Msk (0x1ul << I2C_STATUS1_URIF_Pos) /* I2C_CONST */ /* end of I2C register group */
2502
2503
2504/*---------------------- INT Controller -------------------------*/
2510 typedef struct
2511{
2512
2513
2524 __I uint32_t IRQ0SRC;
2525
2536 __I uint32_t IRQ1SRC;
2537
2548 __I uint32_t IRQ2SRC;
2549
2560 __I uint32_t IRQ3SRC;
2561
2572 __I uint32_t IRQ4SRC;
2573
2584 __I uint32_t IRQ5SRC;
2585
2596 __I uint32_t IRQ6SRC;
2597
2608 __I uint32_t IRQ7SRC;
2609
2620 __I uint32_t IRQ8SRC;
2621
2632 __I uint32_t IRQ9SRC;
2634 uint32_t RESERVED0[2];
2636
2637
2648 __I uint32_t IRQ12SRC;
2649
2660 __I uint32_t IRQ13SRC;
2661
2672 __I uint32_t IRQ14SRC;
2674 uint32_t RESERVED1[1];
2676
2677
2688 __I uint32_t IRQ16SRC;
2689
2700 __I uint32_t IRQ17SRC;
2701
2711 __I uint32_t IRQ18SRC;
2713 uint32_t RESERVED2[6];
2715
2716
2727 __I uint32_t IRQ25SRC;
2729 uint32_t RESERVED3[2];
2731
2732
2743 __I uint32_t IRQ28SRC;
2744
2755 __I uint32_t IRQ29SRC;
2757 uint32_t RESERVED4[2];
2759
2760
2776 __IO uint32_t NMICTL;
2777
2792 __IO uint32_t IRQSTS;
2793
2794} INTR_T;
2795
2801#define INT_IRQ0SRC_INT_SRC_Pos (0)
2802#define INT_IRQ0SRC_INT_SRC_Msk (0x7ul << INT_IRQ0SRC_INT_SRC_Pos)
2804#define INT_IRQ1SRC_INT_SRC_Pos (0)
2805#define INT_IRQ1SRC_INT_SRC_Msk (0x7ul << INT_IRQ1SRC_INT_SRC_Pos)
2807#define INT_IRQ2SRC_INT_SRC_Pos (0)
2808#define INT_IRQ2SRC_INT_SRC_Msk (0x7ul << INT_IRQ2SRC_INT_SRC_Pos)
2810#define INT_IRQ3SRC_INT_SRC_Pos (0)
2811#define INT_IRQ3SRC_INT_SRC_Msk (0x7ul << INT_IRQ3SRC_INT_SRC_Pos)
2813#define INT_IRQ4SRC_INT_SRC_Pos (0)
2814#define INT_IRQ4SRC_INT_SRC_Msk (0x7ul << INT_IRQ4SRC_INT_SRC_Pos)
2816#define INT_IRQ5SRC_INT_SRC_Pos (0)
2817#define INT_IRQ5SRC_INT_SRC_Msk (0x7ul << INT_IRQ5SRC_INT_SRC_Pos)
2819#define INT_IRQ6SRC_INT_SRC_Pos (0)
2820#define INT_IRQ6SRC_INT_SRC_Msk (0x7ul << INT_IRQ6SRC_INT_SRC_Pos)
2822#define INT_IRQ7SRC_INT_SRC_Pos (0)
2823#define INT_IRQ7SRC_INT_SRC_Msk (0x7ul << INT_IRQ7SRC_INT_SRC_Pos)
2825#define INT_IRQ8SRC_INT_SRC_Pos (0)
2826#define INT_IRQ8SRC_INT_SRC_Msk (0x7ul << INT_IRQ8SRC_INT_SRC_Pos)
2828#define INT_IRQ9SRC_INT_SRC_Pos (0)
2829#define INT_IRQ9SRC_INT_SRC_Msk (0x7ul << INT_IRQ9SRC_INT_SRC_Pos)
2831#define INT_IRQ12SRC_INT_SRC_Pos (0)
2832#define INT_IRQ12SRC_INT_SRC_Msk (0x7ul << INT_IRQ12SRC_INT_SRC_Pos)
2834#define INT_IRQ13SRC_INT_SRC_Pos (0)
2835#define INT_IRQ13SRC_INT_SRC_Msk (0x7ul << INT_IRQ13SRC_INT_SRC_Pos)
2837#define INT_IRQ14SRC_INT_SRC_Pos (0)
2838#define INT_IRQ14SRC_INT_SRC_Msk (0x7ul << INT_IRQ14SRC_INT_SRC_Pos)
2840#define INT_IRQ16SRC_INT_SRC_Pos (0)
2841#define INT_IRQ16SRC_INT_SRC_Msk (0x7ul << INT_IRQ16SRC_INT_SRC_Pos)
2843#define INT_IRQ17SRC_INT_SRC_Pos (0)
2844#define INT_IRQ17SRC_INT_SRC_Msk (0x7ul << INT_IRQ17SRC_INT_SRC_Pos)
2846#define INT_IRQ18SRC_INT_SRC_Pos (0)
2847#define INT_IRQ18SRC_INT_SRC_Msk (0x7ul << INT_IRQ18SRC_INT_SRC_Pos)
2849#define INT_IRQ25SRC_INT_SRC_Pos (0)
2850#define INT_IRQ25SRC_INT_SRC_Msk (0x7ul << INT_IRQ25SRC_INT_SRC_Pos)
2852#define INT_IRQ28SRC_INT_SRC_Pos (0)
2853#define INT_IRQ28SRC_INT_SRC_Msk (0x7ul << INT_IRQ28SRC_INT_SRC_Pos)
2855#define INT_IRQ29SRC_INT_SRC_Pos (0)
2856#define INT_IRQ29SRC_INT_SRC_Msk (0x7ul << INT_IRQ29SRC_INT_SRC_Pos)
2858#define INT_NMICTL_NMTSEL_Pos (0)
2859#define INT_NMICTL_NMTSEL_Msk (0x1ful << INT_NMICTL_NMTSEL_Pos)
2861#define INT_NMICTL_NMISELEN_Pos (8)
2862#define INT_NMICTL_NMISELEN_Msk (0x1ul << INT_NMICTL_NMISELEN_Pos)
2864#define INT_IRQSTS_IRQ_Pos (0)
2865#define INT_IRQSTS_IRQ_Msk (0xfffffffful << INT_IRQSTS_IRQ_Pos) /* INT_CONST */ /* end of INT register group */
2869
2870
2871/*---------------------- Pulse Width Modulation Controller -------------------------*/
2877 typedef struct
2878{
2879
2880
2901 __IO uint32_t CLKPSC;
2902
2935 __IO uint32_t CLKDIV;
2936
3042 __IO uint32_t CTL;
3043
3068 __IO uint32_t PERIOD[6];
3069
3098 __IO uint32_t CMPDAT[6];
3100 uint32_t RESERVED0[6];
3102
3190 __IO uint32_t INTEN;
3191
3281 __IO uint32_t INTSTS;
3282
3315 __IO uint32_t POEN;
3316
3371 __IO uint32_t BRKCTL;
3372
3390 __IO uint32_t DTCTL;
3391
3471 __IO uint32_t ADCTCTL0;
3472
3517 __IO uint32_t ADCTCTL1;
3518
3559 __IO uint32_t ADCTSTS0;
3560
3585 __IO uint32_t ADCTSTS1;
3586
3703 __IO uint32_t PHCHG;
3704
3821 __IO uint32_t PHCHGNXT;
3822
3845 __IO uint32_t PHCHGMSK;
3846
3860 __IO uint32_t IFA;
3861
3862} PWM_T;
3863
3869#define PWM_CLKPSC_CLKPSC01_Pos (0)
3870#define PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos)
3872#define PWM_CLKPSC_CLKPSC23_Pos (8)
3873#define PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos)
3875#define PWM_CLKPSC_CLKPSC45_Pos (16)
3876#define PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos)
3878#define PWM_CLKDIV_CLKDIV0_Pos (0)
3879#define PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos)
3881#define PWM_CLKDIV_CLKDIV1_Pos (4)
3882#define PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos)
3884#define PWM_CLKDIV_CLKDIV2_Pos (8)
3885#define PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos)
3887#define PWM_CLKDIV_CLKDIV3_Pos (12)
3888#define PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos)
3890#define PWM_CLKDIV_CLKDIV4_Pos (16)
3891#define PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos)
3893#define PWM_CLKDIV_CLKDIV5_Pos (20)
3894#define PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos)
3896#define PWM_CTL_CNTEN0_Pos (0)
3897#define PWM_CTL_CNTEN0_Msk (0x1ul << PWM_CTL_CNTEN0_Pos)
3899#define PWM_CTL_DBGTRIOFF_Pos (1)
3900#define PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos)
3902#define PWM_CTL_PINV0_Pos (2)
3903#define PWM_CTL_PINV0_Msk (0x1ul << PWM_CTL_PINV0_Pos)
3905#define PWM_CTL_CNTMODE0_Pos (3)
3906#define PWM_CTL_CNTMODE0_Msk (0x1ul << PWM_CTL_CNTMODE0_Pos)
3908#define PWM_CTL_CNTEN1_Pos (4)
3909#define PWM_CTL_CNTEN1_Msk (0x1ul << PWM_CTL_CNTEN1_Pos)
3911#define PWM_CTL_HCUPDT_Pos (5)
3912#define PWM_CTL_HCUPDT_Msk (0x1ul << PWM_CTL_HCUPDT_Pos)
3914#define PWM_CTL_PINV1_Pos (6)
3915#define PWM_CTL_PINV1_Msk (0x1ul << PWM_CTL_PINV1_Pos)
3917#define PWM_CTL_CNTMODE1_Pos (7)
3918#define PWM_CTL_CNTMODE1_Msk (0x1ul << PWM_CTL_CNTMODE1_Pos)
3920#define PWM_CTL_CNTEN2_Pos (8)
3921#define PWM_CTL_CNTEN2_Msk (0x1ul << PWM_CTL_CNTEN2_Pos)
3923#define PWM_CTL_PINV2_Pos (10)
3924#define PWM_CTL_PINV2_Msk (0x1ul << PWM_CTL_PINV2_Pos)
3926#define PWM_CTL_CNTMODE2_Pos (11)
3927#define PWM_CTL_CNTMODE2_Msk (0x1ul << PWM_CTL_CNTMODE2_Pos)
3929#define PWM_CTL_CNTEN3_Pos (12)
3930#define PWM_CTL_CNTEN3_Msk (0x1ul << PWM_CTL_CNTEN3_Pos)
3932#define PWM_CTL_PINV3_Pos (14)
3933#define PWM_CTL_PINV3_Msk (0x1ul << PWM_CTL_PINV3_Pos)
3935#define PWM_CTL_CNTMODE3_Pos (15)
3936#define PWM_CTL_CNTMODE3_Msk (0x1ul << PWM_CTL_CNTMODE3_Pos)
3938#define PWM_CTL_CNTEN4_Pos (16)
3939#define PWM_CTL_CNTEN4_Msk (0x1ul << PWM_CTL_CNTEN4_Pos)
3941#define PWM_CTL_PINV4_Pos (18)
3942#define PWM_CTL_PINV4_Msk (0x1ul << PWM_CTL_PINV4_Pos)
3944#define PWM_CTL_CNTMODE4_Pos (19)
3945#define PWM_CTL_CNTMODE4_Msk (0x1ul << PWM_CTL_CNTMODE4_Pos)
3947#define PWM_CTL_CNTEN5_Pos (20)
3948#define PWM_CTL_CNTEN5_Msk (0x1ul << PWM_CTL_CNTEN5_Pos)
3950#define PWM_CTL_ASYMEN_Pos (21)
3951#define PWM_CTL_ASYMEN_Msk (0x1ul << PWM_CTL_ASYMEN_Pos)
3953#define PWM_CTL_PINV5_Pos (22)
3954#define PWM_CTL_PINV5_Msk (0x1ul << PWM_CTL_PINV5_Pos)
3956#define PWM_CTL_CNTMODE5_Pos (23)
3957#define PWM_CTL_CNTMODE5_Msk (0x1ul << PWM_CTL_CNTMODE5_Pos)
3959#define PWM_CTL_DTCNT01_Pos (24)
3960#define PWM_CTL_DTCNT01_Msk (0x1ul << PWM_CTL_DTCNT01_Pos)
3962#define PWM_CTL_DTCNT23_Pos (25)
3963#define PWM_CTL_DTCNT23_Msk (0x1ul << PWM_CTL_DTCNT23_Pos)
3965#define PWM_CTL_DTCNT45_Pos (26)
3966#define PWM_CTL_DTCNT45_Msk (0x1ul << PWM_CTL_DTCNT45_Pos)
3968#define PWM_CTL_CNTCLR_Pos (27)
3969#define PWM_CTL_CNTCLR_Msk (0x1ul << PWM_CTL_CNTCLR_Pos)
3971#define PWM_CTL_MODE_Pos (28)
3972#define PWM_CTL_MODE_Msk (0x3ul << PWM_CTL_MODE_Pos)
3974#define PWM_CTL_GROUPEN_Pos (30)
3975#define PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos)
3977#define PWM_CTL_CNTTYPE_Pos (31)
3978#define PWM_CTL_CNTTYPE_Msk (0x1ul << PWM_CTL_CNTTYPE_Pos)
3980#define PWM_PERIOD_PERIOD_Pos (0)
3981#define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos)
3983#define PWM_CMPDAT_CMP_Pos (0)
3984#define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos)
3986#define PWM_CMPDAT_CMPD_Pos (16)
3987#define PWM_CMPDAT_CMPD_Msk (0xfffful << PWM_CMPDAT_CMPD_Pos)
3989#define PWM_INTEN_ZIEN0_Pos (0)
3990#define PWM_INTEN_ZIEN0_Msk (0x1ul << PWM_INTEN_ZIEN0_Pos)
3992#define PWM_INTEN_ZIEN1_Pos (1)
3993#define PWM_INTEN_ZIEN1_Msk (0x1ul << PWM_INTEN_ZIEN1_Pos)
3995#define PWM_INTEN_ZIEN2_Pos (2)
3996#define PWM_INTEN_ZIEN2_Msk (0x1ul << PWM_INTEN_ZIEN2_Pos)
3998#define PWM_INTEN_ZIEN3_Pos (3)
3999#define PWM_INTEN_ZIEN3_Msk (0x1ul << PWM_INTEN_ZIEN3_Pos)
4001#define PWM_INTEN_ZIEN4_Pos (4)
4002#define PWM_INTEN_ZIEN4_Msk (0x1ul << PWM_INTEN_ZIEN4_Pos)
4004#define PWM_INTEN_ZIEN5_Pos (5)
4005#define PWM_INTEN_ZIEN5_Msk (0x1ul << PWM_INTEN_ZIEN5_Pos)
4007#define PWM_INTEN_CMPDIEN0_Pos (8)
4008#define PWM_INTEN_CMPDIEN0_Msk (0x1ul << PWM_INTEN_CMPDIEN0_Pos)
4010#define PWM_INTEN_CMPDIEN1_Pos (9)
4011#define PWM_INTEN_CMPDIEN1_Msk (0x1ul << PWM_INTEN_CMPDIEN1_Pos)
4013#define PWM_INTEN_CMPDIEN2_Pos (10)
4014#define PWM_INTEN_CMPDIEN2_Msk (0x1ul << PWM_INTEN_CMPDIEN2_Pos)
4016#define PWM_INTEN_CMPDIEN3_Pos (11)
4017#define PWM_INTEN_CMPDIEN3_Msk (0x1ul << PWM_INTEN_CMPDIEN3_Pos)
4019#define PWM_INTEN_CMPDIEN4_Pos (12)
4020#define PWM_INTEN_CMPDIEN4_Msk (0x1ul << PWM_INTEN_CMPDIEN4_Pos)
4022#define PWM_INTEN_CMPDIEN5_Pos (13)
4023#define PWM_INTEN_CMPDIEN5_Msk (0x1ul << PWM_INTEN_CMPDIEN5_Pos)
4025#define PWM_INTEN_BRKIEN_Pos (16)
4026#define PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos)
4028#define PWM_INTEN_PINTTYPE_Pos (17)
4029#define PWM_INTEN_PINTTYPE_Msk (0x1ul << PWM_INTEN_PINTTYPE_Pos)
4031#define PWM_INTEN_PIEN0_Pos (18)
4032#define PWM_INTEN_PIEN0_Msk (0x1ul << PWM_INTEN_PIEN0_Pos)
4034#define PWM_INTEN_PIEN1_Pos (19)
4035#define PWM_INTEN_PIEN1_Msk (0x1ul << PWM_INTEN_PIEN1_Pos)
4037#define PWM_INTEN_PIEN2_Pos (20)
4038#define PWM_INTEN_PIEN2_Msk (0x1ul << PWM_INTEN_PIEN2_Pos)
4040#define PWM_INTEN_PIEN3_Pos (21)
4041#define PWM_INTEN_PIEN3_Msk (0x1ul << PWM_INTEN_PIEN3_Pos)
4043#define PWM_INTEN_PIEN4_Pos (22)
4044#define PWM_INTEN_PIEN4_Msk (0x1ul << PWM_INTEN_PIEN4_Pos)
4046#define PWM_INTEN_PIEN5_Pos (23)
4047#define PWM_INTEN_PIEN5_Msk (0x1ul << PWM_INTEN_PIEN5_Pos)
4049#define PWM_INTEN_CMPUIEN0_Pos (24)
4050#define PWM_INTEN_CMPUIEN0_Msk (0x1ul << PWM_INTEN_CMPUIEN0_Pos)
4052#define PWM_INTEN_CMPUIEN1_Pos (25)
4053#define PWM_INTEN_CMPUIEN1_Msk (0x1ul << PWM_INTEN_CMPUIEN1_Pos)
4055#define PWM_INTEN_CMPUIEN2_Pos (26)
4056#define PWM_INTEN_CMPUIEN2_Msk (0x1ul << PWM_INTEN_CMPUIEN2_Pos)
4058#define PWM_INTEN_CMPUIEN3_Pos (27)
4059#define PWM_INTEN_CMPUIEN3_Msk (0x1ul << PWM_INTEN_CMPUIEN3_Pos)
4061#define PWM_INTEN_CMPUIEN4_Pos (28)
4062#define PWM_INTEN_CMPUIEN4_Msk (0x1ul << PWM_INTEN_CMPUIEN4_Pos)
4064#define PWM_INTEN_CMPUIEN5_Pos (29)
4065#define PWM_INTEN_CMPUIEN5_Msk (0x1ul << PWM_INTEN_CMPUIEN5_Pos)
4067#define PWM_INTSTS_ZIF0_Pos (0)
4068#define PWM_INTSTS_ZIF0_Msk (0x1ul << PWM_INTSTS_ZIF0_Pos)
4070#define PWM_INTSTS_ZIF1_Pos (1)
4071#define PWM_INTSTS_ZIF1_Msk (0x1ul << PWM_INTSTS_ZIF1_Pos)
4073#define PWM_INTSTS_ZIF2_Pos (2)
4074#define PWM_INTSTS_ZIF2_Msk (0x1ul << PWM_INTSTS_ZIF2_Pos)
4076#define PWM_INTSTS_ZIF3_Pos (3)
4077#define PWM_INTSTS_ZIF3_Msk (0x1ul << PWM_INTSTS_ZIF3_Pos)
4079#define PWM_INTSTS_ZIF4_Pos (4)
4080#define PWM_INTSTS_ZIF4_Msk (0x1ul << PWM_INTSTS_ZIF4_Pos)
4082#define PWM_INTSTS_ZIF5_Pos (5)
4083#define PWM_INTSTS_ZIF5_Msk (0x1ul << PWM_INTSTS_ZIF5_Pos)
4085#define PWM_INTSTS_CMPDIF0_Pos (8)
4086#define PWM_INTSTS_CMPDIF0_Msk (0x1ul << PWM_INTSTS_CMPDIF0_Pos)
4088#define PWM_INTSTS_CMPDIF1_Pos (9)
4089#define PWM_INTSTS_CMPDIF1_Msk (0x1ul << PWM_INTSTS_CMPDIF1_Pos)
4091#define PWM_INTSTS_CMPDIF2_Pos (10)
4092#define PWM_INTSTS_CMPDIF2_Msk (0x1ul << PWM_INTSTS_CMPDIF2_Pos)
4094#define PWM_INTSTS_CMPDIF3_Pos (11)
4095#define PWM_INTSTS_CMPDIF3_Msk (0x1ul << PWM_INTSTS_CMPDIF3_Pos)
4097#define PWM_INTSTS_CMPDIF4_Pos (12)
4098#define PWM_INTSTS_CMPDIF4_Msk (0x1ul << PWM_INTSTS_CMPDIF4_Pos)
4100#define PWM_INTSTS_CMPDIF5_Pos (13)
4101#define PWM_INTSTS_CMPDIF5_Msk (0x1ul << PWM_INTSTS_CMPDIF5_Pos)
4103#define PWM_INTSTS_BRKIF0_Pos (16)
4104#define PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos)
4106#define PWM_INTSTS_BRKIF1_Pos (17)
4107#define PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos)
4109#define PWM_INTSTS_PIF0_Pos (18)
4110#define PWM_INTSTS_PIF0_Msk (0x1ul << PWM_INTSTS_PIF0_Pos)
4112#define PWM_INTSTS_PIF1_Pos (19)
4113#define PWM_INTSTS_PIF1_Msk (0x1ul << PWM_INTSTS_PIF1_Pos)
4115#define PWM_INTSTS_PIF2_Pos (20)
4116#define PWM_INTSTS_PIF2_Msk (0x1ul << PWM_INTSTS_PIF2_Pos)
4118#define PWM_INTSTS_PIF3_Pos (21)
4119#define PWM_INTSTS_PIF3_Msk (0x1ul << PWM_INTSTS_PIF3_Pos)
4121#define PWM_INTSTS_PIF4_Pos (22)
4122#define PWM_INTSTS_PIF4_Msk (0x1ul << PWM_INTSTS_PIF4_Pos)
4124#define PWM_INTSTS_PIF5_Pos (23)
4125#define PWM_INTSTS_PIF5_Msk (0x1ul << PWM_INTSTS_PIF5_Pos)
4127#define PWM_INTSTS_CMPUIF0_Pos (24)
4128#define PWM_INTSTS_CMPUIF0_Msk (0x1ul << PWM_INTSTS_CMPUIF0_Pos)
4130#define PWM_INTSTS_CMPUIF1_Pos (25)
4131#define PWM_INTSTS_CMPUIF1_Msk (0x1ul << PWM_INTSTS_CMPUIF1_Pos)
4133#define PWM_INTSTS_CMPUIF2_Pos (26)
4134#define PWM_INTSTS_CMPUIF2_Msk (0x1ul << PWM_INTSTS_CMPUIF2_Pos)
4136#define PWM_INTSTS_CMPUIF3_Pos (27)
4137#define PWM_INTSTS_CMPUIF3_Msk (0x1ul << PWM_INTSTS_CMPUIF3_Pos)
4139#define PWM_INTSTS_CMPUIF4_Pos (28)
4140#define PWM_INTSTS_CMPUIF4_Msk (0x1ul << PWM_INTSTS_CMPUIF4_Pos)
4142#define PWM_INTSTS_CMPUIF5_Pos (29)
4143#define PWM_INTSTS_CMPUIF5_Msk (0x1ul << PWM_INTSTS_CMPUIF5_Pos)
4145#define PWM_POEN_POEN0_Pos (0)
4146#define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos)
4148#define PWM_POEN_POEN1_Pos (1)
4149#define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos)
4151#define PWM_POEN_POEN2_Pos (2)
4152#define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos)
4154#define PWM_POEN_POEN3_Pos (3)
4155#define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos)
4157#define PWM_POEN_POEN4_Pos (4)
4158#define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos)
4160#define PWM_POEN_POEN5_Pos (5)
4161#define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos)
4163#define PWM_BRKCTL_BRK0EN_Pos (0)
4164#define PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos)
4166#define PWM_BRKCTL_BRK1EN_Pos (1)
4167#define PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos)
4169#define PWM_BRKCTL_BRK0SEL_Pos (2)
4170#define PWM_BRKCTL_BRK0SEL_Msk (0x1ul << PWM_BRKCTL_BRK0SEL_Pos)
4172#define PWM_BRKCTL_BRK1SEL_Pos (3)
4173#define PWM_BRKCTL_BRK1SEL_Msk (0x1ul << PWM_BRKCTL_BRK1SEL_Pos)
4175#define PWM_BRKCTL_BRKSTS_Pos (7)
4176#define PWM_BRKCTL_BRKSTS_Msk (0x1ul << PWM_BRKCTL_BRKSTS_Pos)
4178#define PWM_BRKCTL_BRKACT_Pos (8)
4179#define PWM_BRKCTL_BRKACT_Msk (0x1ul << PWM_BRKCTL_BRKACT_Pos)
4181#define PWM_BRKCTL_SWBRK_Pos (9)
4182#define PWM_BRKCTL_SWBRK_Msk (0x1ul << PWM_BRKCTL_SWBRK_Pos)
4184#define PWM_BRKCTL_BKOD0_Pos (24)
4185#define PWM_BRKCTL_BKOD0_Msk (0x1ul << PWM_BRKCTL_BKOD0_Pos)
4187#define PWM_BRKCTL_BKOD1_Pos (25)
4188#define PWM_BRKCTL_BKOD1_Msk (0x1ul << PWM_BRKCTL_BKOD1_Pos)
4190#define PWM_BRKCTL_BKOD2_Pos (26)
4191#define PWM_BRKCTL_BKOD2_Msk (0x1ul << PWM_BRKCTL_BKOD2_Pos)
4193#define PWM_BRKCTL_BKOD3_Pos (27)
4194#define PWM_BRKCTL_BKOD3_Msk (0x1ul << PWM_BRKCTL_BKOD3_Pos)
4196#define PWM_BRKCTL_BKOD4_Pos (28)
4197#define PWM_BRKCTL_BKOD4_Msk (0x1ul << PWM_BRKCTL_BKOD4_Pos)
4199#define PWM_BRKCTL_BKOD5_Pos (29)
4200#define PWM_BRKCTL_BKOD5_Msk (0x1ul << PWM_BRKCTL_BKOD5_Pos)
4202#define PWM_BRKCTL_D6BKOD_Pos (30)
4203#define PWM_BRKCTL_D6BKOD_Msk (0x1ul << PWM_BRKCTL_D6BKOD_Pos)
4205#define PWM_BRKCTL_D7BKOD_Pos (31)
4206#define PWM_BRKCTL_D7BKOD_Msk (0x1ul << PWM_BRKCTL_D7BKOD_Pos)
4208#define PWM_DTCTL_DTCNT01_Pos (0)
4209#define PWM_DTCTL_DTCNT01_Msk (0xfful << PWM_DTCTL_DTCNT01_Pos)
4211#define PWM_DTCTL_DTCNT23_Pos (8)
4212#define PWM_DTCTL_DTCNT23_Msk (0xfful << PWM_DTCTL_DTCNT23_Pos)
4214#define PWM_DTCTL_DTCNT45_Pos (16)
4215#define PWM_DTCTL_DTCNT45_Msk (0xfful << PWM_DTCTL_DTCNT45_Pos)
4217#define PWM_ADCTCTL0_CUTRGEN0_Pos (0)
4218#define PWM_ADCTCTL0_CUTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN0_Pos)
4220#define PWM_ADCTCTL0_CPTRGEN0_Pos (1)
4221#define PWM_ADCTCTL0_CPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN0_Pos)
4223#define PWM_ADCTCTL0_CDTRGEN0_Pos (2)
4224#define PWM_ADCTCTL0_CDTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN0_Pos)
4226#define PWM_ADCTCTL0_ZPTRGEN0_Pos (3)
4227#define PWM_ADCTCTL0_ZPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN0_Pos)
4229#define PWM_ADCTCTL0_CUTRGEN1_Pos (8)
4230#define PWM_ADCTCTL0_CUTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN1_Pos)
4232#define PWM_ADCTCTL0_CPTRGEN1_Pos (9)
4233#define PWM_ADCTCTL0_CPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN1_Pos)
4235#define PWM_ADCTCTL0_CDTRGEN1_Pos (10)
4236#define PWM_ADCTCTL0_CDTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN1_Pos)
4238#define PWM_ADCTCTL0_ZPTRGEN1_Pos (11)
4239#define PWM_ADCTCTL0_ZPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN1_Pos)
4241#define PWM_ADCTCTL0_CUTRGEN2_Pos (16)
4242#define PWM_ADCTCTL0_CUTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN2_Pos)
4244#define PWM_ADCTCTL0_CPTRGEN2_Pos (17)
4245#define PWM_ADCTCTL0_CPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN2_Pos)
4247#define PWM_ADCTCTL0_CDTRGEN2_Pos (18)
4248#define PWM_ADCTCTL0_CDTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN2_Pos)
4250#define PWM_ADCTCTL0_ZPTRGEN2_Pos (19)
4251#define PWM_ADCTCTL0_ZPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN2_Pos)
4253#define PWM_ADCTCTL0_CUTRGEN3_Pos (24)
4254#define PWM_ADCTCTL0_CUTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN3_Pos)
4256#define PWM_ADCTCTL0_CPTRGEN3_Pos (25)
4257#define PWM_ADCTCTL0_CPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN3_Pos)
4259#define PWM_ADCTCTL0_CDTRGEN3_Pos (26)
4260#define PWM_ADCTCTL0_CDTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN3_Pos)
4262#define PWM_ADCTCTL0_ZPTRGEN3_Pos (27)
4263#define PWM_ADCTCTL0_ZPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN3_Pos)
4265#define PWM_ADCTCTL1_CUTRGEN4_Pos (0)
4266#define PWM_ADCTCTL1_CUTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN4_Pos)
4268#define PWM_ADCTCTL1_CPTRGEN4_Pos (1)
4269#define PWM_ADCTCTL1_CPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN4_Pos)
4271#define PWM_ADCTCTL1_CDTRGEN4_Pos (2)
4272#define PWM_ADCTCTL1_CDTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN4_Pos)
4274#define PWM_ADCTCTL1_ZPTRGEN4_Pos (3)
4275#define PWM_ADCTCTL1_ZPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN4_Pos)
4277#define PWM_ADCTCTL1_CUTRGEN5_Pos (8)
4278#define PWM_ADCTCTL1_CUTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN5_Pos)
4280#define PWM_ADCTCTL1_CPTRGEN5_Pos (9)
4281#define PWM_ADCTCTL1_CPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN5_Pos)
4283#define PWM_ADCTCTL1_CDTRGEN5_Pos (10)
4284#define PWM_ADCTCTL1_CDTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN5_Pos)
4286#define PWM_ADCTCTL1_ZPTRGEN5_Pos (11)
4287#define PWM_ADCTCTL1_ZPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN5_Pos)
4289#define PWM_ADCTSTS0_CUTRGF0_Pos (0)
4290#define PWM_ADCTSTS0_CUTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF0_Pos)
4292#define PWM_ADCTSTS0_CPTRGF0_Pos (1)
4293#define PWM_ADCTSTS0_CPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF0_Pos)
4295#define PWM_ADCTSTS0_CDTRGF0_Pos (2)
4296#define PWM_ADCTSTS0_CDTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF0_Pos)
4298#define PWM_ADCTSTS0_ZPTRGF0_Pos (3)
4299#define PWM_ADCTSTS0_ZPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF0_Pos)
4301#define PWM_ADCTSTS0_CUTRGF1_Pos (8)
4302#define PWM_ADCTSTS0_CUTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF1_Pos)
4304#define PWM_ADCTSTS0_CPTRGF1_Pos (9)
4305#define PWM_ADCTSTS0_CPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF1_Pos)
4307#define PWM_ADCTSTS0_CDTRGF1_Pos (10)
4308#define PWM_ADCTSTS0_CDTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF1_Pos)
4310#define PWM_ADCTSTS0_ZPTRGF1_Pos (11)
4311#define PWM_ADCTSTS0_ZPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF1_Pos)
4313#define PWM_ADCTSTS0_CUTRGF2_Pos (16)
4314#define PWM_ADCTSTS0_CUTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF2_Pos)
4316#define PWM_ADCTSTS0_CPTRGF2_Pos (17)
4317#define PWM_ADCTSTS0_CPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF2_Pos)
4319#define PWM_ADCTSTS0_CDTRGF2_Pos (18)
4320#define PWM_ADCTSTS0_CDTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF2_Pos)
4322#define PWM_ADCTSTS0_ZPTRGF2_Pos (19)
4323#define PWM_ADCTSTS0_ZPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF2_Pos)
4325#define PWM_ADCTSTS0_CUTRGF3_Pos (24)
4326#define PWM_ADCTSTS0_CUTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF3_Pos)
4328#define PWM_ADCTSTS0_CPTRGF3_Pos (25)
4329#define PWM_ADCTSTS0_CPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF3_Pos)
4331#define PWM_ADCTSTS0_CDTRGF3_Pos (26)
4332#define PWM_ADCTSTS0_CDTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF3_Pos)
4334#define PWM_ADCTSTS0_ZPTRGF3_Pos (27)
4335#define PWM_ADCTSTS0_ZPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF3_Pos)
4337#define PWM_ADCTSTS1_CUTRGF4_Pos (0)
4338#define PWM_ADCTSTS1_CUTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF4_Pos)
4340#define PWM_ADCTSTS1_CPTRGF4_Pos (1)
4341#define PWM_ADCTSTS1_CPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF4_Pos)
4343#define PWM_ADCTSTS1_CDTRGF4_Pos (2)
4344#define PWM_ADCTSTS1_CDTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF4_Pos)
4346#define PWM_ADCTSTS1_ZPTRGF4_Pos (3)
4347#define PWM_ADCTSTS1_ZPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF4_Pos)
4349#define PWM_ADCTSTS1_CUTRGF5_Pos (8)
4350#define PWM_ADCTSTS1_CUTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF5_Pos)
4352#define PWM_ADCTSTS1_CPTRGF5_Pos (9)
4353#define PWM_ADCTSTS1_CPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF5_Pos)
4355#define PWM_ADCTSTS1_CDTRGF5_Pos (10)
4356#define PWM_ADCTSTS1_CDTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF5_Pos)
4358#define PWM_ADCTSTS1_ZPTRGF5_Pos (11)
4359#define PWM_ADCTSTS1_ZPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF5_Pos)
4361#define PWM_PHCHG_MSKDAT0_Pos (0)
4362#define PWM_PHCHG_MSKDAT0_Msk (0x1ul << PWM_PHCHG_MSKDAT0_Pos)
4364#define PWM_PHCHG_MSKDAT1_Pos (1)
4365#define PWM_PHCHG_MSKDAT1_Msk (0x1ul << PWM_PHCHG_MSKDAT1_Pos)
4367#define PWM_PHCHG_MSKDAT2_Pos (2)
4368#define PWM_PHCHG_MSKDAT2_Msk (0x1ul << PWM_PHCHG_MSKDAT2_Pos)
4370#define PWM_PHCHG_MSKDAT3_Pos (3)
4371#define PWM_PHCHG_MSKDAT3_Msk (0x1ul << PWM_PHCHG_MSKDAT3_Pos)
4373#define PWM_PHCHG_MSKDAT4_Pos (4)
4374#define PWM_PHCHG_MSKDAT4_Msk (0x1ul << PWM_PHCHG_MSKDAT4_Pos)
4376#define PWM_PHCHG_MSKDAT5_Pos (5)
4377#define PWM_PHCHG_MSKDAT5_Msk (0x1ul << PWM_PHCHG_MSKDAT5_Pos)
4379#define PWM_PHCHG_MSKDAT6_Pos (6)
4380#define PWM_PHCHG_MSKDAT6_Msk (0x1ul << PWM_PHCHG_MSKDAT6_Pos)
4382#define PWM_PHCHG_MSKDAT7_Pos (7)
4383#define PWM_PHCHG_MSKDAT7_Msk (0x1ul << PWM_PHCHG_MSKDAT7_Pos)
4385#define PWM_PHCHG_MSKEN0_Pos (8)
4386#define PWM_PHCHG_MSKEN0_Msk (0x1ul << PWM_PHCHG_MSKEN0_Pos)
4388#define PWM_PHCHG_MSKEN1_Pos (9)
4389#define PWM_PHCHG_MSKEN1_Msk (0x1ul << PWM_PHCHG_MSKEN1_Pos)
4391#define PWM_PHCHG_MSKEN2_Pos (10)
4392#define PWM_PHCHG_MSKEN2_Msk (0x1ul << PWM_PHCHG_MSKEN2_Pos)
4394#define PWM_PHCHG_MSKEN3_Pos (11)
4395#define PWM_PHCHG_MSKEN3_Msk (0x1ul << PWM_PHCHG_MSKEN3_Pos)
4397#define PWM_PHCHG_MSKEN4_Pos (12)
4398#define PWM_PHCHG_MSKEN4_Msk (0x1ul << PWM_PHCHG_MSKEN4_Pos)
4400#define PWM_PHCHG_MSKEN5_Pos (13)
4401#define PWM_PHCHG_MSKEN5_Msk (0x1ul << PWM_PHCHG_MSKEN5_Pos)
4403#define PWM_PHCHG_AUTOCLR0_Pos (14)
4404#define PWM_PHCHG_AUTOCLR0_Msk (0x1ul << PWM_PHCHG_AUTOCLR0_Pos)
4406#define PWM_PHCHG_AUTOCLR1_Pos (15)
4407#define PWM_PHCHG_AUTOCLR1_Msk (0x1ul << PWM_PHCHG_AUTOCLR1_Pos)
4409#define PWM_PHCHG_OFFEN01_Pos (16)
4410#define PWM_PHCHG_OFFEN01_Msk (0x1ul << PWM_PHCHG_OFFEN01_Pos)
4412#define PWM_PHCHG_OFFEN11_Pos (17)
4413#define PWM_PHCHG_OFFEN11_Msk (0x1ul << PWM_PHCHG_OFFEN11_Pos)
4415#define PWM_PHCHG_OFFEN21_Pos (18)
4416#define PWM_PHCHG_OFFEN21_Msk (0x1ul << PWM_PHCHG_OFFEN21_Pos)
4418#define PWM_PHCHG_OFFEN31_Pos (19)
4419#define PWM_PHCHG_OFFEN31_Msk (0x1ul << PWM_PHCHG_OFFEN31_Pos)
4421#define PWM_PHCHG_A1POSSEL_Pos (20)
4422#define PWM_PHCHG_A1POSSEL_Msk (0x3ul << PWM_PHCHG_A1POSSEL_Pos)
4424#define PWM_PHCHG_TMR1TEN_Pos (22)
4425#define PWM_PHCHG_TMR1TEN_Msk (0x1ul << PWM_PHCHG_TMR1TEN_Pos)
4427#define PWM_PHCHG_ACMP1TEN_Pos (23)
4428#define PWM_PHCHG_ACMP1TEN_Msk (0x1ul << PWM_PHCHG_ACMP1TEN_Pos)
4430#define PWM_PHCHG_OFFEN00_Pos (24)
4431#define PWM_PHCHG_OFFEN00_Msk (0x1ul << PWM_PHCHG_OFFEN00_Pos)
4433#define PWM_PHCHG_OFFEN10_Pos (25)
4434#define PWM_PHCHG_OFFEN10_Msk (0x1ul << PWM_PHCHG_OFFEN10_Pos)
4436#define PWM_PHCHG_OFFEN20_Pos (26)
4437#define PWM_PHCHG_OFFEN20_Msk (0x1ul << PWM_PHCHG_OFFEN20_Pos)
4439#define PWM_PHCHG_OFFEN30_Pos (27)
4440#define PWM_PHCHG_OFFEN30_Msk (0x1ul << PWM_PHCHG_OFFEN30_Pos)
4442#define PWM_PHCHG_A0POSSEL_Pos (28)
4443#define PWM_PHCHG_A0POSSEL_Msk (0x3ul << PWM_PHCHG_A0POSSEL_Pos)
4445#define PWM_PHCHG_T0_Pos (30)
4446#define PWM_PHCHG_T0_Msk (0x1ul << PWM_PHCHG_T0_Pos)
4448#define PWM_PHCHG_ACMP0TEN_Pos (31)
4449#define PWM_PHCHG_ACMP0TEN_Msk (0x1ul << PWM_PHCHG_ACMP0TEN_Pos)
4451#define PWM_PHCHGNXT_MSKDAT0_Pos (0)
4452#define PWM_PHCHGNXT_MSKDAT0_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT0_Pos)
4454#define PWM_PHCHGNXT_MSKDAT1_Pos (1)
4455#define PWM_PHCHGNXT_MSKDAT1_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT1_Pos)
4457#define PWM_PHCHGNXT_MSKDAT2_Pos (2)
4458#define PWM_PHCHGNXT_MSKDAT2_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT2_Pos)
4460#define PWM_PHCHGNXT_MSKDAT3_Pos (3)
4461#define PWM_PHCHGNXT_MSKDAT3_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT3_Pos)
4463#define PWM_PHCHGNXT_MSKDAT4_Pos (4)
4464#define PWM_PHCHGNXT_MSKDAT4_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT4_Pos)
4466#define PWM_PHCHGNXT_MSKDAT5_Pos (5)
4467#define PWM_PHCHGNXT_MSKDAT5_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT5_Pos)
4469#define PWM_PHCHGNXT_MSKDAT6_Pos (6)
4470#define PWM_PHCHGNXT_MSKDAT6_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT6_Pos)
4472#define PWM_PHCHGNXT_MSKDAT7_Pos (7)
4473#define PWM_PHCHGNXT_MSKDAT7_Msk (0x1ul << PWM_PHCHGNXT_MSKDAT7_Pos)
4475#define PWM_PHCHGNXT_MSKEN0_Pos (8)
4476#define PWM_PHCHGNXT_MSKEN0_Msk (0x1ul << PWM_PHCHGNXT_MSKEN0_Pos)
4478#define PWM_PHCHGNXT_MSKEN1_Pos (9)
4479#define PWM_PHCHGNXT_MSKEN1_Msk (0x1ul << PWM_PHCHGNXT_MSKEN1_Pos)
4481#define PWM_PHCHGNXT_MSKEN2_Pos (10)
4482#define PWM_PHCHGNXT_MSKEN2_Msk (0x1ul << PWM_PHCHGNXT_MSKEN2_Pos)
4484#define PWM_PHCHGNXT_MSKEN3_Pos (11)
4485#define PWM_PHCHGNXT_MSKEN3_Msk (0x1ul << PWM_PHCHGNXT_MSKEN3_Pos)
4487#define PWM_PHCHGNXT_MSKEN4_Pos (12)
4488#define PWM_PHCHGNXT_MSKEN4_Msk (0x1ul << PWM_PHCHGNXT_MSKEN4_Pos)
4490#define PWM_PHCHGNXT_MSKEN5_Pos (13)
4491#define PWM_PHCHGNXT_MSKEN5_Msk (0x1ul << PWM_PHCHGNXT_MSKEN5_Pos)
4493#define PWM_PHCHGNXT_AUTOCLR0_Pos (14)
4494#define PWM_PHCHGNXT_AUTOCLR0_Msk (0x1ul << PWM_PHCHGNXT_AUTOCLR0_Pos)
4496#define PWM_PHCHGNXT_AUTOCLR1_Pos (15)
4497#define PWM_PHCHGNXT_AUTOCLR1_Msk (0x1ul << PWM_PHCHGNXT_AUTOCLR1_Pos)
4499#define PWM_PHCHGNXT_OFFEN01_Pos (16)
4500#define PWM_PHCHGNXT_OFFEN01_Msk (0x1ul << PWM_PHCHGNXT_OFFEN01_Pos)
4502#define PWM_PHCHGNXT_OFFEN11_Pos (17)
4503#define PWM_PHCHGNXT_OFFEN11_Msk (0x1ul << PWM_PHCHGNXT_OFFEN11_Pos)
4505#define PWM_PHCHGNXT_OFFEN21_Pos (18)
4506#define PWM_PHCHGNXT_OFFEN21_Msk (0x1ul << PWM_PHCHGNXT_OFFEN21_Pos)
4508#define PWM_PHCHGNXT_OFFEN31_Pos (19)
4509#define PWM_PHCHGNXT_OFFEN31_Msk (0x1ul << PWM_PHCHGNXT_OFFEN31_Pos)
4511#define PWM_PHCHGNXT_A1POSSEL_Pos (20)
4512#define PWM_PHCHGNXT_A1POSSEL_Msk (0x3ul << PWM_PHCHGNXT_A1POSSEL_Pos)
4514#define PWM_PHCHGNXT_TMR1TEN_Pos (22)
4515#define PWM_PHCHGNXT_TMR1TEN_Msk (0x1ul << PWM_PHCHGNXT_TMR1TEN_Pos)
4517#define PWM_PHCHGNXT_ACMP1TEN_Pos (23)
4518#define PWM_PHCHGNXT_ACMP1TEN_Msk (0x1ul << PWM_PHCHGNXT_ACMP1TEN_Pos)
4520#define PWM_PHCHGNXT_OFFEN00_Pos (24)
4521#define PWM_PHCHGNXT_OFFEN00_Msk (0x1ul << PWM_PHCHGNXT_OFFEN00_Pos)
4523#define PWM_PHCHGNXT_OFFEN10_Pos (25)
4524#define PWM_PHCHGNXT_OFFEN10_Msk (0x1ul << PWM_PHCHGNXT_OFFEN10_Pos)
4526#define PWM_PHCHGNXT_OFFEN20_Pos (26)
4527#define PWM_PHCHGNXT_OFFEN20_Msk (0x1ul << PWM_PHCHGNXT_OFFEN20_Pos)
4529#define PWM_PHCHGNXT_OFFEN30_Pos (27)
4530#define PWM_PHCHGNXT_OFFEN30_Msk (0x1ul << PWM_PHCHGNXT_OFFEN30_Pos)
4532#define PWM_PHCHGNXT_A0POSSEL_Pos (28)
4533#define PWM_PHCHGNXT_A0POSSEL_Msk (0x3ul << PWM_PHCHGNXT_A0POSSEL_Pos)
4535#define PWM_PHCHGNXT_TMR0TEN_Pos (30)
4536#define PWM_PHCHGNXT_TMR0TEN_Msk (0x1ul << PWM_PHCHGNXT_TMR0TEN_Pos)
4538#define PWM_PHCHGNXT_ACMP0TEN_Pos (31)
4539#define PWM_PHCHGNXT_ACMP0TEN_Msk (0x1ul << PWM_PHCHGNXT_ACMP0TEN_Pos)
4541#define PWM_PHCHGMSK_MASKEND6_Pos (6)
4542#define PWM_PHCHGMSK_MASKEND6_Msk (0x1ul << PWM_PHCHGMSK_MASKEND6_Pos)
4544#define PWM_PHCHGMSK_MASKEND7_Pos (7)
4545#define PWM_PHCHGMSK_MASKEND7_Msk (0x1ul << PWM_PHCHGMSK_MASKEND7_Pos)
4547#define PWM_PHCHGMSK_POSCTL0_Pos (8)
4548#define PWM_PHCHGMSK_POSCTL0_Msk (0x1ul << PWM_PHCHGMSK_POSCTL0_Pos)
4550#define PWM_PHCHGMSK_POSCTL1_Pos (9)
4551#define PWM_PHCHGMSK_POSCTL1_Msk (0x1ul << PWM_PHCHGMSK_POSCTL1_Pos)
4553#define PWM_IFA_IFAEN_Pos (0)
4554#define PWM_IFA_IFAEN_Msk (0x1ul << PWM_IFA_IFAEN_Pos)
4556#define PWM_IFA_IFCNT_Pos (4)
4557#define PWM_IFA_IFCNT_Msk (0xful << PWM_IFA_IFCNT_Pos) /* PWM_CONST */ /* end of PWM register group */
4561
4562
4563/*---------------------- Serial Peripheral Interface Controller -------------------------*/
4569 typedef struct
4570{
4571
4572
4658 __IO uint32_t CTL;
4659
4675 __IO uint32_t CLKDIV;
4676
4711 __IO uint32_t SSCTL;
4713 uint32_t RESERVED0[1];
4715
4716
4731 __I uint32_t RX;
4733 uint32_t RESERVED1[3];
4735
4736
4749 __O uint32_t TX;
4751 uint32_t RESERVED2[6];
4753
4754
4795 __IO uint32_t SLVCTL;
4796
4829 __IO uint32_t FIFOCTL;
4830
4889 __IO uint32_t STATUS;
4890
4891} SPI_T;
4892
4898#define SPI_CTL_SPIEN_Pos (0)
4899#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos)
4901#define SPI_CTL_RXNEG_Pos (1)
4902#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos)
4904#define SPI_CTL_TXNEG_Pos (2)
4905#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos)
4907#define SPI_CTL_DWIDTH_Pos (3)
4908#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos)
4910#define SPI_CTL_LSB_Pos (10)
4911#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
4913#define SPI_CTL_CLKPOL_Pos (11)
4914#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos)
4916#define SPI_CTL_SUSPITV_Pos (12)
4917#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos)
4919#define SPI_CTL_UNITIF_Pos (16)
4920#define SPI_CTL_UNITIF_Msk (0x1ul << SPI_CTL_UNITIF_Pos)
4922#define SPI_CTL_UNITIEN_Pos (17)
4923#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos)
4925#define SPI_CTL_SLAVE_Pos (18)
4926#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
4928#define SPI_CTL_REORDER_Pos (19)
4929#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
4931#define SPI_CTL_FIFOEN_Pos (21)
4932#define SPI_CTL_FIFOEN_Msk (0x1ul << SPI_CTL_FIFOEN_Pos)
4934#define SPI_CTL_RXEMPTY_Pos (24)
4935#define SPI_CTL_RXEMPTY_Msk (0x1ul << SPI_CTL_RXEMPTY_Pos)
4937#define SPI_CTL_RXFULL_Pos (25)
4938#define SPI_CTL_RXFULL_Msk (0x1ul << SPI_CTL_RXFULL_Pos)
4940#define SPI_CTL_TXEMPTY_Pos (26)
4941#define SPI_CTL_TXEMPTY_Msk (0x1ul << SPI_CTL_TXEMPTY_Pos)
4943#define SPI_CTL_TXFULL_Pos (27)
4944#define SPI_CTL_TXFULL_Msk (0x1ul << SPI_CTL_TXFULL_Pos)
4946#define SPI_CLKDIV_DIVIDER_Pos (0)
4947#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos)
4949#define SPI_SSCTL_SS_Pos (0)
4950#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos)
4952#define SPI_SSCTL_SSACTPOL_Pos (2)
4953#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos)
4955#define SPI_SSCTL_AUTOSS_Pos (3)
4956#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos)
4958#define SPI_SSCTL_SSLTEN_Pos (4)
4959#define SPI_SSCTL_SSLTEN_Msk (0x1ul << SPI_SSCTL_SSLTEN_Pos)
4961#define SPI_SSCTL_LTF_Pos (5)
4962#define SPI_SSCTL_LTF_Msk (0x1ul << SPI_SSCTL_LTF_Pos)
4964#define SPI_RX_RX_Pos (0)
4965#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos)
4967#define SPI_TX_TX_Pos (0)
4968#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos)
4970#define SPI_SLVCTL_SLV3WIRE_Pos (8)
4971#define SPI_SLVCTL_SLV3WIRE_Msk (0x1ul << SPI_SLVCTL_SLV3WIRE_Pos)
4973#define SPI_SLVCTL_SLVABT_Pos (9)
4974#define SPI_SLVCTL_SLVABT_Msk (0x1ul << SPI_SLVCTL_SLVABT_Pos)
4976#define SPI_SLVCTL_SLVSTIEN_Pos (10)
4977#define SPI_SLVCTL_SLVSTIEN_Msk (0x1ul << SPI_SLVCTL_SLVSTIEN_Pos)
4979#define SPI_SLVCTL_SLVSTIF_Pos (11)
4980#define SPI_SLVCTL_SLVSTIF_Msk (0x1ul << SPI_SLVCTL_SLVSTIF_Pos)
4982#define SPI_SLVCTL_SSINAIEN_Pos (16)
4983#define SPI_SLVCTL_SSINAIEN_Msk (0x1ul << SPI_SLVCTL_SSINAIEN_Pos)
4985#define SPI_SLVCTL_DIVMOD_Pos (31)
4986#define SPI_SLVCTL_DIVMOD_Msk (0x1ul << SPI_SLVCTL_DIVMOD_Pos)
4988#define SPI_FIFOCTL_RXRST_Pos (0)
4989#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos)
4991#define SPI_FIFOCTL_TXRST_Pos (1)
4992#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos)
4994#define SPI_FIFOCTL_RXTHIEN_Pos (2)
4995#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)
4997#define SPI_FIFOCTL_TXTHIEN_Pos (3)
4998#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)
5000#define SPI_FIFOCTL_RXOVIEN_Pos (6)
5001#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)
5003#define SPI_FIFOCTL_RXTOIEN_Pos (21)
5004#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)
5006#define SPI_FIFOCTL_RXTH_Pos (24)
5007#define SPI_FIFOCTL_RXTH_Msk (0x3ul << SPI_FIFOCTL_RXTH_Pos)
5009#define SPI_FIFOCTL_TXTH_Pos (28)
5010#define SPI_FIFOCTL_TXTH_Msk (0x3ul << SPI_FIFOCTL_TXTH_Pos)
5012#define SPI_STATUS_RXTHIF_Pos (0)
5013#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos)
5015#define SPI_STATUS_RXOVIF_Pos (2)
5016#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos)
5018#define SPI_STATUS_TXTHIF_Pos (4)
5019#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos)
5021#define SPI_STATUS_SLVSTIF_Pos (11)
5022#define SPI_STATUS_SLVSTIF_Msk (0x1ul << SPI_STATUS_SLVSTIF_Pos)
5024#define SPI_STATUS_RXCNT_Pos (12)
5025#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos)
5027#define SPI_STATUS_UNITIF_Pos (16)
5028#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos)
5030#define SPI_STATUS_SLVTOIF_Pos (20)
5031#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos)
5033#define SPI_STATUS_RXEMPTY_Pos (24)
5034#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos)
5036#define SPI_STATUS_RXFULL_Pos (25)
5037#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos)
5039#define SPI_STATUS_TXEMPTY_Pos (26)
5040#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos)
5042#define SPI_STATUS_TXFULL_Pos (27)
5043#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos)
5045#define SPI_STATUS_TXCNT_Pos (28)
5046#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /* SPI_CONST */ /* end of SPI register group */
5050
5051
5052/*---------------------- System Manger Controller -------------------------*/
5058 typedef struct
5059{
5060
5061
5073 __I uint32_t PDID;
5074
5113 __IO uint32_t RSTSTS;
5114
5140 __IO uint32_t IPRST0;
5141
5180 __IO uint32_t IPRST1;
5182 uint32_t RESERVED0[2];
5184
5185
5239 __IO uint32_t BODCTL;
5241 uint32_t RESERVED1[5];
5243
5244
5263 __IO uint32_t P0_MFP;
5264
5284 __IO uint32_t P1_MFP;
5285
5305 __IO uint32_t P2_MFP;
5306
5329 __IO uint32_t P3_MFP;
5330
5350 __IO uint32_t P4_MFP;
5351
5371 __IO uint32_t P5_MFP;
5372
5384 __IO uint32_t EINT0SEL;
5386 uint32_t RESERVED2[13];
5388
5389
5414 __IO uint32_t IRCTCTL;
5415
5434 __IO uint32_t IRCTIEN;
5435
5461 __IO uint32_t IRCTISTS;
5463 uint32_t RESERVED3[29];
5465
5466
5486 __IO uint32_t REGLCTL;
5487
5488} SYS_T;
5489
5495#define SYS_PDID_PDID_Pos (0)
5496#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
5498#define SYS_RSTSTS_PORF_Pos (0)
5499#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos)
5501#define SYS_RSTSTS_PINRF_Pos (1)
5502#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos)
5504#define SYS_RSTSTS_WDTRF_Pos (2)
5505#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos)
5507#define SYS_RSTSTS_BODRF_Pos (4)
5508#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos)
5510#define SYS_RSTSTS_SYSRF_Pos (5)
5511#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos)
5513#define SYS_RSTSTS_CPURF_Pos (7)
5514#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos)
5516#define SYS_IPRST0_CHIPRST_Pos (0)
5517#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos)
5519#define SYS_IPRST0_CPURST_Pos (1)
5520#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos)
5522#define SYS_IPRST0_CPUWS_Pos (2)
5523#define SYS_IPRST0_CPUWS_Msk (0x1ul << SYS_IPRST0_CPUWS_Pos)
5525#define SYS_IPRST1_GPIORST_Pos (1)
5526#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos)
5528#define SYS_IPRST1_TMR0RST_Pos (2)
5529#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos)
5531#define SYS_IPRST1_TMR1RST_Pos (3)
5532#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos)
5534#define SYS_IPRST1_I2C_RST_Pos (8)
5535#define SYS_IPRST1_I2C_RST_Msk (0x1ul << SYS_IPRST1_I2C_RST_Pos)
5537#define SYS_IPRST1_SPIRST_Pos (12)
5538#define SYS_IPRST1_SPIRST_Msk (0x1ul << SYS_IPRST1_SPIRST_Pos)
5540#define SYS_IPRST1_UART0RST_Pos (16)
5541#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos)
5543#define SYS_IPRST1_UART1RST_Pos (17)
5544#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos)
5546#define SYS_IPRST1_PWMRST_Pos (20)
5547#define SYS_IPRST1_PWMRST_Msk (0x1ul << SYS_IPRST1_PWMRST_Pos)
5549#define SYS_IPRST1_ACMPRST_Pos (22)
5550#define SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos)
5552#define SYS_IPRST1_ADCRST_Pos (28)
5553#define SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos)
5555#define SYS_BODCTL_BODEN_Pos (0)
5556#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos)
5558#define SYS_BODCTL_BODVL1_0_Pos (1)
5559#define SYS_BODCTL_BODVL1_0_Msk (0x3ul << SYS_BODCTL_BODVL1_0_Pos)
5561#define SYS_BODCTL_BODRSTEN_Pos (3)
5562#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos)
5564#define SYS_BODCTL_BODIF_Pos (4)
5565#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos)
5567#define SYS_BODCTL_BODLPM_Pos (5)
5568#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos)
5570#define SYS_BODCTL_BODOUT_Pos (6)
5571#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos)
5573#define SYS_BODCTL_BODVL2_Pos (7)
5574#define SYS_BODCTL_BODVL2_Msk (0x1ul << SYS_BODCTL_BODVL2_Pos)
5576#define SYS_BODCTL_BOREN_Pos (8)
5577#define SYS_BODCTL_BOREN_Msk (0x1ul << SYS_BODCTL_BOREN_Pos)
5579#define SYS_P0_MFP_MFP_Pos (0)
5580#define SYS_P0_MFP_MFP_Msk (0xfful << SYS_P0_MFP_MFP_Pos)
5582#define SYS_P0_MFP_ALT0_Pos (8)
5583#define SYS_P0_MFP_ALT0_Msk (0x1ul << SYS_P0_MFP_ALT0_Pos)
5585#define SYS_P0_MFP_ALT1_Pos (9)
5586#define SYS_P0_MFP_ALT1_Msk (0x1ul << SYS_P0_MFP_ALT1_Pos)
5588#define SYS_P0_MFP_ALT2_Pos (10)
5589#define SYS_P0_MFP_ALT2_Msk (0x1ul << SYS_P0_MFP_ALT2_Pos)
5591#define SYS_P0_MFP_ALT4_Pos (12)
5592#define SYS_P0_MFP_ALT4_Msk (0x1ul << SYS_P0_MFP_ALT4_Pos)
5594#define SYS_P0_MFP_ALT5_Pos (13)
5595#define SYS_P0_MFP_ALT5_Msk (0x1ul << SYS_P0_MFP_ALT5_Pos)
5597#define SYS_P0_MFP_ALT6_Pos (14)
5598#define SYS_P0_MFP_ALT6_Msk (0x1ul << SYS_P0_MFP_ALT6_Pos)
5600#define SYS_P0_MFP_ALT7_Pos (15)
5601#define SYS_P0_MFP_ALT7_Msk (0x1ul << SYS_P0_MFP_ALT7_Pos)
5603#define SYS_P0_MFP_TYPE_Pos (16)
5604#define SYS_P0_MFP_TYPE_Msk (0xfful << SYS_P0_MFP_TYPE_Pos)
5606#define SYS_P0_MFP_HS_Pos (24)
5607#define SYS_P0_MFP_HS_Msk (0xfful << SYS_P0_MFP_HS_Pos)
5609#define SYS_P1_MFP_MFP_Pos (0)
5610#define SYS_P1_MFP_MFP_Msk (0xfful << SYS_P1_MFP_MFP_Pos)
5612#define SYS_P1_MFP_ALT0_Pos (8)
5613#define SYS_P1_MFP_ALT0_Msk (0x1ul << SYS_P1_MFP_ALT0_Pos)
5615#define SYS_P1_MFP_ALT2_Pos (10)
5616#define SYS_P1_MFP_ALT2_Msk (0x1ul << SYS_P1_MFP_ALT2_Pos)
5618#define SYS_P1_MFP_ALT3_Pos (11)
5619#define SYS_P1_MFP_ALT3_Msk (0x1ul << SYS_P1_MFP_ALT3_Pos)
5621#define SYS_P1_MFP_ALT4_Pos (12)
5622#define SYS_P1_MFP_ALT4_Msk (0x1ul << SYS_P1_MFP_ALT4_Pos)
5624#define SYS_P1_MFP_ALT5_Pos (13)
5625#define SYS_P1_MFP_ALT5_Msk (0x1ul << SYS_P1_MFP_ALT5_Pos)
5627#define SYS_P1_MFP_ALT6_Pos (14)
5628#define SYS_P1_MFP_ALT6_Msk (0x1ul << SYS_P1_MFP_ALT6_Pos)
5630#define SYS_P1_MFP_TYPE_Pos (16)
5631#define SYS_P1_MFP_TYPE_Msk (0xfful << SYS_P1_MFP_TYPE_Pos)
5633#define SYS_P1_MFP_HS_Pos (24)
5634#define SYS_P1_MFP_HS_Msk (0xfful << SYS_P1_MFP_HS_Pos)
5636#define SYS_P2_MFP_MFP_Pos (0)
5637#define SYS_P2_MFP_MFP_Msk (0xfful << SYS_P2_MFP_MFP_Pos)
5639#define SYS_P2_MFP_ALT2_Pos (10)
5640#define SYS_P2_MFP_ALT2_Msk (0x1ul << SYS_P2_MFP_ALT2_Pos)
5642#define SYS_P2_MFP_ALT3_Pos (11)
5643#define SYS_P2_MFP_ALT3_Msk (0x1ul << SYS_P2_MFP_ALT3_Pos)
5645#define SYS_P2_MFP_ALT4_Pos (12)
5646#define SYS_P2_MFP_ALT4_Msk (0x1ul << SYS_P2_MFP_ALT4_Pos)
5648#define SYS_P2_MFP_ALT5_Pos (13)
5649#define SYS_P2_MFP_ALT5_Msk (0x1ul << SYS_P2_MFP_ALT5_Pos)
5651#define SYS_P2_MFP_ALT6_Pos (14)
5652#define SYS_P2_MFP_ALT6_Msk (0x1ul << SYS_P2_MFP_ALT6_Pos)
5654#define SYS_P2_MFP_ALT7_Pos (15)
5655#define SYS_P2_MFP_ALT7_Msk (0x1ul << SYS_P2_MFP_ALT7_Pos)
5657#define SYS_P2_MFP_TYPE_Pos (16)
5658#define SYS_P2_MFP_TYPE_Msk (0xfful << SYS_P2_MFP_TYPE_Pos)
5660#define SYS_P2_MFP_HS_Pos (24)
5661#define SYS_P2_MFP_HS_Msk (0xfful << SYS_P2_MFP_HS_Pos)
5663#define SYS_P3_MFP_MFP_Pos (0)
5664#define SYS_P3_MFP_MFP_Msk (0xfful << SYS_P3_MFP_MFP_Pos)
5666#define SYS_P3_MFP_ALT0_Pos (8)
5667#define SYS_P3_MFP_ALT0_Msk (0x1ul << SYS_P3_MFP_ALT0_Pos)
5669#define SYS_P3_MFP_ALT1_Pos (9)
5670#define SYS_P3_MFP_ALT1_Msk (0x1ul << SYS_P3_MFP_ALT1_Pos)
5672#define SYS_P3_MFP_ALT2_Pos (10)
5673#define SYS_P3_MFP_ALT2_Msk (0x1ul << SYS_P3_MFP_ALT2_Pos)
5675#define SYS_P3_MFP_ALT4_Pos (12)
5676#define SYS_P3_MFP_ALT4_Msk (0x1ul << SYS_P3_MFP_ALT4_Pos)
5678#define SYS_P3_MFP_ALT5_Pos (13)
5679#define SYS_P3_MFP_ALT5_Msk (0x1ul << SYS_P3_MFP_ALT5_Pos)
5681#define SYS_P3_MFP_ALT6_Pos (14)
5682#define SYS_P3_MFP_ALT6_Msk (0x1ul << SYS_P3_MFP_ALT6_Pos)
5684#define SYS_P3_MFP_ALT7_Pos (15)
5685#define SYS_P3_MFP_ALT7_Msk (0x1ul << SYS_P3_MFP_ALT7_Pos)
5687#define SYS_P3_MFP_TYPE_Pos (16)
5688#define SYS_P3_MFP_TYPE_Msk (0xfful << SYS_P3_MFP_TYPE_Pos)
5690#define SYS_P3_MFP_P32CTL_Pos (24)
5691#define SYS_P3_MFP_P32CTL_Msk (0x1ul << SYS_P3_MFP_P32CTL_Pos)
5693#define SYS_P3_MFP_HS_Pos (25)
5694#define SYS_P3_MFP_HS_Msk (0x7ful << SYS_P3_MFP_HS_Pos)
5696#define SYS_P4_MFP_MFP_Pos (0)
5697#define SYS_P4_MFP_MFP_Msk (0xfful << SYS_P4_MFP_MFP_Pos)
5699#define SYS_P4_MFP_ALT6_Pos (14)
5700#define SYS_P4_MFP_ALT6_Msk (0x1ul << SYS_P4_MFP_ALT6_Pos)
5702#define SYS_P4_MFP_ALT7_Pos (15)
5703#define SYS_P4_MFP_ALT7_Msk (0x1ul << SYS_P4_MFP_ALT7_Pos)
5705#define SYS_P4_MFP_TYPE_Pos (16)
5706#define SYS_P4_MFP_TYPE_Msk (0xfful << SYS_P4_MFP_TYPE_Pos)
5708#define SYS_P4_MFP_HS_Pos (24)
5709#define SYS_P4_MFP_HS_Msk (0xfful << SYS_P4_MFP_HS_Pos)
5711#define SYS_P5_MFP_MFP_Pos (0)
5712#define SYS_P5_MFP_MFP_Msk (0xfful << SYS_P5_MFP_MFP_Pos)
5714#define SYS_P5_MFP_ALT0_Pos (8)
5715#define SYS_P5_MFP_ALT0_Msk (0x1ul << SYS_P5_MFP_ALT0_Pos)
5717#define SYS_P5_MFP_ALT1_Pos (9)
5718#define SYS_P5_MFP_ALT1_Msk (0x1ul << SYS_P5_MFP_ALT1_Pos)
5720#define SYS_P5_MFP_ALT2_Pos (10)
5721#define SYS_P5_MFP_ALT2_Msk (0x1ul << SYS_P5_MFP_ALT2_Pos)
5723#define SYS_P5_MFP_ALT3_Pos (11)
5724#define SYS_P5_MFP_ALT3_Msk (0x1ul << SYS_P5_MFP_ALT3_Pos)
5726#define SYS_P5_MFP_ALT4_Pos (12)
5727#define SYS_P5_MFP_ALT4_Msk (0x1ul << SYS_P5_MFP_ALT4_Pos)
5729#define SYS_P5_MFP_ALT5_Pos (13)
5730#define SYS_P5_MFP_ALT5_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos)
5732#define SYS_P5_MFP_TYPE_Pos (16)
5733#define SYS_P5_MFP_TYPE_Msk (0xfful << SYS_P5_MFP_TYPE_Pos)
5735#define SYS_P5_MFP_HS_Pos (24)
5736#define SYS_P5_MFP_HS_Msk (0xfful << SYS_P5_MFP_HS_Pos)
5738#define SYS_EINT0SEL_SEL_Pos (0)
5739#define SYS_EINT0SEL_SEL_Msk (0x1ul << SYS_EINT0SEL_SEL_Pos)
5741#define SYS_IRCTCTL_FREQSEL_Pos (0)
5742#define SYS_IRCTCTL_FREQSEL_Msk (0x1ul << SYS_IRCTCTL_FREQSEL_Pos)
5744#define SYS_IRCTCTL_LOOPSEL_Pos (4)
5745#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos)
5747#define SYS_IRCTIEN_TFAILIEN_Pos (1)
5748#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos)
5750#define SYS_IRCTIEN_CLKEIEN_Pos (2)
5751#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos)
5753#define SYS_IRCTISTS_FREQLOCK_Pos (0)
5754#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos)
5756#define SYS_IRCTISTS_TFAILIF_Pos (1)
5757#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos)
5759#define SYS_IRCTISTS_CLKERRIF_Pos (2)
5760#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos)
5762#define SYS_REGLCTL_REGWRPROT_Pos (0)
5763#define SYS_REGLCTL_REGWRPROT_Msk (0x1ul << SYS_REGLCTL_REGWRPROT_Pos)
5765#define SYS_REGLCTL_REGPROTDIS_Pos (0)
5766#define SYS_REGLCTL_REGPROTDIS_Msk (0x1ul << SYS_REGLCTL_REGPROTDIS_Pos) /* SYS_CONST */ /* end of SYS register group */
5770
5771
5772/*---------------------- Timer Controller -------------------------*/
5778 typedef struct
5779{
5780
5781
5851 __IO uint32_t CTL;
5852
5868 __IO uint32_t CMP;
5869
5888 __IO uint32_t INTSTS;
5889
5900 __I uint32_t CNT;
5901
5914 __I uint32_t CAP;
5915
5955 __IO uint32_t EXTCTL;
5956
5971 __IO uint32_t EINTSTS;
5972
5973} TIMER_T;
5974
5975 typedef struct
5976{
6030 __IO uint32_t CCAPCTL;
6031
6044 __I uint32_t CCAP[3];
6045} TIMER_AC_T;
6051#define TIMER_CTL_PSC_Pos (0)
6052#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos)
6054#define TIMER_CTL_CNTDATEN_Pos (16)
6055#define TIMER_CTL_CNTDATEN_Msk (0x1ul << TIMER_CTL_CNTDATEN_Pos)
6057#define TIMER_CTL_CMPCTL_Pos (17)
6058#define TIMER_CTL_CMPCTL_Msk (0x1ul << TIMER_CTL_CMPCTL_Pos)
6060#define TIMER_CTL_TGLPINSEL_Pos (18)
6061#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos)
6063#define TIMER_CTL_CAPPINSEL_Pos (19)
6064#define TIMER_CTL_CAPPINSEL_Msk (0x1ul << TIMER_CTL_CAPPINSEL_Pos)
6066#define TIMER_CTL_WKEN_Pos (23)
6067#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
6069#define TIMER_CTL_EXTCNTEN_Pos (24)
6070#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
6072#define TIMER_CTL_ACTSTS_Pos (25)
6073#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
6075#define TIMER_CTL_RSTCNT_Pos (26)
6076#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
6078#define TIMER_CTL_OPMODE_Pos (27)
6079#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
6081#define TIMER_CTL_INTEN_Pos (29)
6082#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos)
6084#define TIMER_CTL_CNTEN_Pos (30)
6085#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
6087#define TIMER_CTL_ICEDEBUG_Pos (31)
6088#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
6090#define TIMER_CMP_CMPDAT_Pos (0)
6091#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos)
6093#define TIMER_INTSTS_TIF_Pos (0)
6094#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos)
6096#define TIMER_INTSTS_TWKF_Pos (1)
6097#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos)
6099#define TIMER_CNT_CNT_Pos (0)
6100#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos)
6102#define TIMER_CAP_CAPDAT_Pos (0)
6103#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos)
6105#define TIMER_EXTCTL_CNTPHASE_Pos (0)
6106#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)
6108#define TIMER_EXTCTL_CAPEDGE_Pos (1)
6109#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)
6111#define TIMER_EXTCTL_CAPEN_Pos (3)
6112#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos)
6114#define TIMER_EXTCTL_CAPFUNCS_Pos (4)
6115#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)
6117#define TIMER_EXTCTL_CAPIEN_Pos (5)
6118#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)
6120#define TIMER_EXTCTL_CAPDBEN_Pos (6)
6121#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)
6123#define TIMER_EXTCTL_ECNTDBEN_Pos (7)
6124#define TIMER_EXTCTL_ECNTDBEN_Msk (0x1ul << TIMER_EXTCTL_ECNTDBEN_Pos)
6126#define TIMER_EXTCTL_CAPMODE_Pos (8)
6127#define TIMER_EXTCTL_CAPMODE_Msk (0x1ul << TIMER_EXTCTL_CAPMODE_Pos)
6129#define TIMER_EINTSTS_CAPIF_Pos (0)
6130#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos)
6132#define TIMER_CCAPCTL_CCAPEN_Pos (0)
6133#define TIMER_CCAPCTL_CCAPEN_Msk (0x1ul << TIMER_CCAPCTL_CCAPEN_Pos)
6135#define TIMER_CCAPCTL_INV_Pos (1)
6136#define TIMER_CCAPCTL_INV_Msk (0x1ul << TIMER_CCAPCTL_INV_Pos)
6138#define TIMER_CCAPCTL_TMRSEL_Pos (2)
6139#define TIMER_CCAPCTL_TMRSEL_Msk (0x1ul << TIMER_CCAPCTL_TMRSEL_Pos)
6141#define TIMER_CCAPCTL_CAPCHSEL_Pos (3)
6142#define TIMER_CCAPCTL_CAPCHSEL_Msk (0x7ul << TIMER_CCAPCTL_CAPCHSEL_Pos)
6144#define TIMER_CCAPCTL_CAPR1F_Pos (8)
6145#define TIMER_CCAPCTL_CAPR1F_Msk (0x1ul << TIMER_CCAPCTL_CAPR1F_Pos)
6147#define TIMER_CCAPCTL_CAPF1F_Pos (9)
6148#define TIMER_CCAPCTL_CAPF1F_Msk (0x1ul << TIMER_CCAPCTL_CAPF1F_Pos)
6150#define TIMER_CCAPCTL_CAPR2F_Pos (10)
6151#define TIMER_CCAPCTL_CAPR2F_Msk (0x1ul << TIMER_CCAPCTL_CAPR2F_Pos)
6153#define TIMER_CCAPCTL_CAPF2F_Pos (11)
6154#define TIMER_CCAPCTL_CAPF2F_Msk (0x1ul << TIMER_CCAPCTL_CAPF2F_Pos)
6156#define TIMER_CCAP_CAPDAT_Pos (0)
6157#define TIMER_CCAP_CAPDAT_Msk (0xfffffful << TIMER_CCAP_CAPDAT_Pos) /* TIMER_CONST */ /* end of TIMER register group */
6162
6163
6164/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
6170 typedef struct
6171{
6172
6173
6186 __IO uint32_t DAT;
6187
6229 __IO uint32_t INTEN;
6230
6268 __IO uint32_t FIFO;
6269
6303 __IO uint32_t LINE;
6304
6327 __IO uint32_t MODEM;
6328
6352 __IO uint32_t MODEMSTS;
6353
6431 __IO uint32_t FIFOSTS;
6432
6505 __IO uint32_t INTSTS;
6506
6523 __IO uint32_t TOUT;
6524
6547 __IO uint32_t BAUD;
6548
6566 __IO uint32_t IRDA;
6567
6596 __IO uint32_t ALTCTL;
6597
6611 __IO uint32_t FUNCSEL;
6612
6613} UART_T;
6614
6620#define UART_DAT_DAT_Pos (0)
6621#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos)
6623#define UART_INTEN_RDAIEN_Pos (0)
6624#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos)
6626#define UART_INTEN_THREIEN_Pos (1)
6627#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos)
6629#define UART_INTEN_RLSIEN_Pos (2)
6630#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos)
6632#define UART_INTEN_MODEMIEN_Pos (3)
6633#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos)
6635#define UART_INTEN_RXTOIEN_Pos (4)
6636#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos)
6638#define UART_INTEN_BUFERRIEN_Pos (5)
6639#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos)
6641#define UART_INTEN_WKCTSIEN_Pos (6)
6642#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos)
6644#define UART_INTEN_TOCNTEN_Pos (11)
6645#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos)
6647#define UART_INTEN_ATORTSEN_Pos (12)
6648#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos)
6650#define UART_INTEN_ATOCTSEN_Pos (13)
6651#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos)
6653#define UART_FIFO_RXRST_Pos (1)
6654#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos)
6656#define UART_FIFO_TXRST_Pos (2)
6657#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos)
6659#define UART_FIFO_RFITL_Pos (4)
6660#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos)
6662#define UART_FIFO_RXOFF_Pos (8)
6663#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos)
6665#define UART_FIFO_RTSTRGLV_Pos (16)
6666#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos)
6668#define UART_LINE_WLS_Pos (0)
6669#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos)
6671#define UART_LINE_NSB_Pos (2)
6672#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos)
6674#define UART_LINE_PBE_Pos (3)
6675#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos)
6677#define UART_LINE_EPE_Pos (4)
6678#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos)
6680#define UART_LINE_SPE_Pos (5)
6681#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos)
6683#define UART_LINE_BCB_Pos (6)
6684#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos)
6686#define UART_MODEM_RTS_Pos (1)
6687#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos)
6689#define UART_MODEM_RTSACTLV_Pos (9)
6690#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos)
6692#define UART_MODEM_RTSSTS_Pos (13)
6693#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos)
6695#define UART_MODEMSTS_CTSDETF_Pos (0)
6696#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos)
6698#define UART_MODEMSTS_CTSSTS_Pos (4)
6699#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos)
6701#define UART_MODEMSTS_CTSACTLV_Pos (8)
6702#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)
6704#define UART_FIFOSTS_RXOVIF_Pos (0)
6705#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos)
6707#define UART_FIFOSTS_ADDRDETF_Pos (3)
6708#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)
6710#define UART_FIFOSTS_PEF_Pos (4)
6711#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos)
6713#define UART_FIFOSTS_FEF_Pos (5)
6714#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos)
6716#define UART_FIFOSTS_BIF_Pos (6)
6717#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos)
6719#define UART_FIFOSTS_RXPTR_Pos (8)
6720#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos)
6722#define UART_FIFOSTS_RXEMPTY_Pos (14)
6723#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)
6725#define UART_FIFOSTS_RXFULL_Pos (15)
6726#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos)
6728#define UART_FIFOSTS_TXPTR_Pos (16)
6729#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos)
6731#define UART_FIFOSTS_TXEMPTY_Pos (22)
6732#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)
6734#define UART_FIFOSTS_TXFULL_Pos (23)
6735#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos)
6737#define UART_FIFOSTS_TXOVIF_Pos (24)
6738#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos)
6740#define UART_FIFOSTS_TXEMPTYF_Pos (28)
6741#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)
6743#define UART_INTSTS_RDAIF_Pos (0)
6744#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos)
6746#define UART_INTSTS_THREIF_Pos (1)
6747#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos)
6749#define UART_INTSTS_RLSIF_Pos (2)
6750#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos)
6752#define UART_INTSTS_MODEMIF_Pos (3)
6753#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos)
6755#define UART_INTSTS_RXTOIF_Pos (4)
6756#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos)
6758#define UART_INTSTS_BUFERRIF_Pos (5)
6759#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos)
6761#define UART_INTSTS_RDAINT_Pos (8)
6762#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos)
6764#define UART_INTSTS_THREINT_Pos (9)
6765#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos)
6767#define UART_INTSTS_RLSINT_Pos (10)
6768#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos)
6770#define UART_INTSTS_MODEMINT_Pos (11)
6771#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos)
6773#define UART_INTSTS_RXTOINT_Pos (12)
6774#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos)
6776#define UART_INTSTS_BUFERRINT_Pos (13)
6777#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos)
6779#define UART_TOUT_TOIC_Pos (0)
6780#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos)
6782#define UART_TOUT_DLY_Pos (8)
6783#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos)
6785#define UART_BAUD_BRD_Pos (0)
6786#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
6788#define UART_BAUD_EDIVM1_Pos (24)
6789#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos)
6791#define UART_BAUD_BAUDM0_Pos (28)
6792#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos)
6794#define UART_BAUD_BAUDM1_Pos (29)
6795#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos)
6797#define UART_IRDA_TXEN_Pos (1)
6798#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos)
6800#define UART_IRDA_TXINV_Pos (5)
6801#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos)
6803#define UART_IRDA_RXINV_Pos (6)
6804#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos)
6806#define UART_ALTCTL_RS485NMM_Pos (8)
6807#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos)
6809#define UART_ALTCTL_RS485AAD_Pos (9)
6810#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos)
6812#define UART_ALTCTL_RS485AUD_Pos (10)
6813#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos)
6815#define UART_ALTCTL_ADDRDEN_Pos (15)
6816#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos)
6818#define UART_ALTCTL_ADDRMV_Pos (24)
6819#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos)
6821#define UART_FUNCSEL_FUNCSEL_Pos (0)
6822#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /* UART_CONST */ /* end of UART register group */
6826
6827
6828/*---------------------- Watch Dog Timer Controller -------------------------*/
6834 typedef struct
6835{
6836
6837
6896 __IO uint32_t CTL;
6897
6898} WDT_T;
6899
6905#define WDT_CTL_RSTCNT_Pos (0)
6906#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)
6908#define WDT_CTL_RSTEN_Pos (1)
6909#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)
6911#define WDT_CTL_RSTF_Pos (2)
6912#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos)
6914#define WDT_CTL_IF_Pos (3)
6915#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos)
6917#define WDT_CTL_WKEN_Pos (4)
6918#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)
6920#define WDT_CTL_WKF_Pos (5)
6921#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos)
6923#define WDT_CTL_INTEN_Pos (6)
6924#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos)
6926#define WDT_CTL_WDTEN_Pos (7)
6927#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)
6929#define WDT_CTL_TOUTSEL_Pos (8)
6930#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos)
6932#define WDT_CTL_ICEDEBUG_Pos (31)
6933#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /* WDT_CONST */ /* end of WDT register group */
6937
6938
6939#if defined ( __CC_ARM )
6940#pragma no_anon_unions
6941#endif
6942
6947/* Peripheral and SRAM base address */
6948#define FLASH_BASE ((uint32_t)0x00000000)
6949#define SRAM_BASE ((uint32_t)0x20000000)
6950#define APB1PERIPH_BASE ((uint32_t)0x40000000)
6951#define APB2PERIPH_BASE ((uint32_t)0x40100000)
6952#define AHBPERIPH_BASE ((uint32_t)0x50000000)
6953
6954/* Peripheral memory map */
6955#define WDT_BASE (APB1PERIPH_BASE + 0x04000)
6956#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
6957#define TIMER1_BASE (APB1PERIPH_BASE + 0x10020)
6958#define TIMER_AC_BASE (APB1PERIPH_BASE + 0x10040)
6959#define I2C_BASE (APB1PERIPH_BASE + 0x20000)
6960#define SPI_BASE (APB1PERIPH_BASE + 0x30000)
6961#define PWM_BASE (APB1PERIPH_BASE + 0x40000)
6962#define UART0_BASE (APB1PERIPH_BASE + 0x50000)
6963#define UART1_BASE (APB2PERIPH_BASE + 0x50000)
6964#define ACMP_BASE (APB1PERIPH_BASE + 0xD0000)
6965#define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
6966
6967#define SYS_BASE (AHBPERIPH_BASE + 0x00000)
6968#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
6969#define INTR_BASE (AHBPERIPH_BASE + 0x00300)
6970#define P0_BASE (AHBPERIPH_BASE + 0x04000)
6971#define P1_BASE (AHBPERIPH_BASE + 0x04040)
6972#define P2_BASE (AHBPERIPH_BASE + 0x04080)
6973#define P3_BASE (AHBPERIPH_BASE + 0x040C0)
6974#define P4_BASE (AHBPERIPH_BASE + 0x04100)
6975#define P5_BASE (AHBPERIPH_BASE + 0x04140)
6976#define GPIO_DBNCECON_BASE (AHBPERIPH_BASE + 0x04180)
6977#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
6978#define GPIOBIT0_BASE (AHBPERIPH_BASE + 0x04200)
6979#define GPIOBIT1_BASE (AHBPERIPH_BASE + 0x04220)
6980#define GPIOBIT2_BASE (AHBPERIPH_BASE + 0x04240)
6981#define GPIOBIT3_BASE (AHBPERIPH_BASE + 0x04260)
6982#define GPIOBIT4_BASE (AHBPERIPH_BASE + 0x04280)
6983#define GPIOBIT5_BASE (AHBPERIPH_BASE + 0x042A0)
6984#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
6985#define HDIV_BASE (AHBPERIPH_BASE + 0x14000)
6986 /* end of group Mini55_PERIPHERAL_MEM_MAP */
6988
6989
6994#define WDT ((WDT_T *) WDT_BASE)
6995#define TIMER0 ((TIMER_T *) TIMER0_BASE)
6996#define TIMER1 ((TIMER_T *) TIMER1_BASE)
6997#define TIMERAC ((TIMER_AC_T *) TIMER_AC_BASE)
6998#define I2C ((I2C_T *) I2C_BASE)
6999#define I2C0 ((I2C_T *) I2C_BASE)
7000#define SPI ((SPI_T *) SPI_BASE)
7001#define SPI0 ((SPI_T *) SPI_BASE)
7002#define PWM ((PWM_T *) PWM_BASE)
7003#define UART ((UART_T *) UART0_BASE)
7004#define UART0 ((UART_T *) UART0_BASE)
7005#define UART1 ((UART_T *) UART1_BASE)
7006#define ADC ((ADC_T *) ADC_BASE)
7007#define ACMP ((ACMP_T *) ACMP_BASE)
7008
7009#define SYS ((SYS_T *) SYS_BASE)
7010#define CLK ((CLK_T *) CLK_BASE)
7011#define INTR ((INTR_T *) INTR_BASE)
7012#define P0 ((GPIO_T *) P0_BASE)
7013#define P1 ((GPIO_T *) P1_BASE)
7014#define P2 ((GPIO_T *) P2_BASE)
7015#define P3 ((GPIO_T *) P3_BASE)
7016#define P4 ((GPIO_T *) P4_BASE)
7017#define P5 ((GPIO_T *) P5_BASE)
7018#define GPIO ((GPIO_DB_T *) GPIO_DBNCECON_BASE)
7019#define FMC ((FMC_T *) FMC_BASE)
7020#define HDIV ((HDIV_T *) HDIV_BASE)
7021 /* end of group Mini55_PERIPHERAL_DECLARATION */ /* end of group Mini55_Peripherals */
7024
7030 typedef volatile unsigned char vu8;
7031 typedef volatile unsigned short vu16;
7032 typedef volatile unsigned long vu32;
7033
7039#define M8(addr) (*((vu8 *) (addr)))
7040
7047#define M16(addr) (*((vu16 *) (addr)))
7048
7055#define M32(addr) (*((vu32 *) (addr)))
7056
7064#define outpw(port,value) *((volatile unsigned int *)(port)) = value
7065
7072#define inpw(port) (*((volatile unsigned int *)(port)))
7073
7081#define outps(port,value) *((volatile unsigned short *)(port)) = value
7082
7089#define inps(port) (*((volatile unsigned short *)(port)))
7090
7097#define outpb(port,value) *((volatile unsigned char *)(port)) = value
7098
7104#define inpb(port) (*((volatile unsigned char *)(port)))
7105
7113#define outp32(port,value) *((volatile unsigned int *)(port)) = value
7114
7121#define inp32(port) (*((volatile unsigned int *)(port)))
7122
7130#define outp16(port,value) *((volatile unsigned short *)(port)) = value
7131
7138#define inp16(port) (*((volatile unsigned short *)(port)))
7139
7146#define outp8(port,value) *((volatile unsigned char *)(port)) = value
7147
7153#define inp8(port) (*((volatile unsigned char *)(port)))
7154
7155 /* end of group Mini55_IO_ROUTINE */
7157
7158/******************************************************************************/
7159/* Legacy Constants */
7160/******************************************************************************/
7166#ifndef NULL
7167#define NULL (0)
7168#endif
7169
7170#define TRUE (1)
7171#define FALSE (0)
7172
7173#define ENABLE (1)
7174#define DISABLE (0)
7175
7176/* Define one bit mask */
7177#define BIT0 (0x00000001)
7178#define BIT1 (0x00000002)
7179#define BIT2 (0x00000004)
7180#define BIT3 (0x00000008)
7181#define BIT4 (0x00000010)
7182#define BIT5 (0x00000020)
7183#define BIT6 (0x00000040)
7184#define BIT7 (0x00000080)
7185#define BIT8 (0x00000100)
7186#define BIT9 (0x00000200)
7187#define BIT10 (0x00000400)
7188#define BIT11 (0x00000800)
7189#define BIT12 (0x00001000)
7190#define BIT13 (0x00002000)
7191#define BIT14 (0x00004000)
7192#define BIT15 (0x00008000)
7193#define BIT16 (0x00010000)
7194#define BIT17 (0x00020000)
7195#define BIT18 (0x00040000)
7196#define BIT19 (0x00080000)
7197#define BIT20 (0x00100000)
7198#define BIT21 (0x00200000)
7199#define BIT22 (0x00400000)
7200#define BIT23 (0x00800000)
7201#define BIT24 (0x01000000)
7202#define BIT25 (0x02000000)
7203#define BIT26 (0x04000000)
7204#define BIT27 (0x08000000)
7205#define BIT28 (0x10000000)
7206#define BIT29 (0x20000000)
7207#define BIT30 (0x40000000)
7208#define BIT31 (0x80000000)
7209
7210/* Byte Mask Definitions */
7211#define BYTE0_Msk (0x000000FF)
7212#define BYTE1_Msk (0x0000FF00)
7213#define BYTE2_Msk (0x00FF0000)
7214#define BYTE3_Msk (0xFF000000)
7215
7216#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
7217#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
7218#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
7219#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /* end of group Mini55_legacy_Constants */
7222 /* end of group Mini55_Definitions */
7224
7225#ifdef __cplusplus
7226}
7227#endif
7228
7229
7230/******************************************************************************/
7231/* Peripheral header files */
7232/******************************************************************************/
7233#include "sys.h"
7234#include "clk.h"
7235#include "acmp.h"
7236#include "adc.h"
7237#include "fmc.h"
7238#include "gpio.h"
7239#include "hdiv.h"
7240#include "i2c.h"
7241#include "pwm.h"
7242#include "spi.h"
7243#include "timer.h"
7244#include "uart.h"
7245#include "wdt.h"
7246
7247#endif // __MINI55SERIES_H__
7248
acmp.h
MINI55 series Analog Comparator(ACMP) driver header file.
adc.h
MINI55 series ADC driver header file.
clk.h
MINI55 series CLK driver header file.
fmc.h
MINI55 series FMC driver header file.
gpio.h
MINI55 series GPIO driver header file.
IRQn_Type
enum IRQn IRQn_Type
IRQn
IRQn
Definition: Mini55Series.h:82
PendSV_IRQn
@ PendSV_IRQn
Definition: Mini55Series.h:88
GPIO5_IRQn
@ GPIO5_IRQn
Definition: Mini55Series.h:106
EINT0_IRQn
@ EINT0_IRQn
Definition: Mini55Series.h:95
SVCall_IRQn
@ SVCall_IRQn
Definition: Mini55Series.h:87
ADC_IRQn
@ ADC_IRQn
Definition: Mini55Series.h:111
PDWU_IRQn
@ PDWU_IRQn
Definition: Mini55Series.h:110
SysTick_IRQn
@ SysTick_IRQn
Definition: Mini55Series.h:89
ACMP_IRQn
@ ACMP_IRQn
Definition: Mini55Series.h:109
WDT_IRQn
@ WDT_IRQn
Definition: Mini55Series.h:94
TMR1_IRQn
@ TMR1_IRQn
Definition: Mini55Series.h:102
SPI_IRQn
@ SPI_IRQn
Definition: Mini55Series.h:105
GPIO234_IRQn
@ GPIO234_IRQn
Definition: Mini55Series.h:98
UART1_IRQn
@ UART1_IRQn
Definition: Mini55Series.h:104
GPIO01_IRQn
@ GPIO01_IRQn
Definition: Mini55Series.h:97
PWM_IRQn
@ PWM_IRQn
Definition: Mini55Series.h:99
HardFault_IRQn
@ HardFault_IRQn
Definition: Mini55Series.h:86
TMR0_IRQn
@ TMR0_IRQn
Definition: Mini55Series.h:101
HIRC_IRQn
@ HIRC_IRQn
Definition: Mini55Series.h:107
BOD_IRQn
@ BOD_IRQn
Definition: Mini55Series.h:93
EINT1_IRQn
@ EINT1_IRQn
Definition: Mini55Series.h:96
FB_IRQn
@ FB_IRQn
Definition: Mini55Series.h:100
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: Mini55Series.h:85
I2C_IRQn
@ I2C_IRQn
Definition: Mini55Series.h:108
UART0_IRQn
@ UART0_IRQn
Definition: Mini55Series.h:103
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Mini55Series.h:7032
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Mini55Series.h:7031
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Mini55Series.h:7030
ADC_T::STATUS
__IO uint32_t STATUS
Definition: Mini55Series.h:512
SYS_T::IRCTIEN
__IO uint32_t IRCTIEN
Definition: Mini55Series.h:5434
SPI_T::RX
__I uint32_t RX
Definition: Mini55Series.h:4731
UART_T::INTEN
__IO uint32_t INTEN
Definition: Mini55Series.h:6229
FMC_T::ISPCTL
__IO uint32_t ISPCTL
Definition: Mini55Series.h:1312
SPI_T::CTL
__IO uint32_t CTL
Definition: Mini55Series.h:4658
I2C_T::ADDR3
__IO uint32_t ADDR3
Definition: Mini55Series.h:2278
SYS_T::P2_MFP
__IO uint32_t P2_MFP
Definition: Mini55Series.h:5305
PWM_T::CTL
__IO uint32_t CTL
Definition: Mini55Series.h:3042
I2C_T::ADDR0
__IO uint32_t ADDR0
Definition: Mini55Series.h:2159
UART_T::BAUD
__IO uint32_t BAUD
Definition: Mini55Series.h:6547
INTR_T::IRQ7SRC
__I uint32_t IRQ7SRC
Definition: Mini55Series.h:2608
INTR_T::IRQ13SRC
__I uint32_t IRQ13SRC
Definition: Mini55Series.h:2660
UART_T::IRDA
__IO uint32_t IRDA
Definition: Mini55Series.h:6566
INTR_T::IRQ25SRC
__I uint32_t IRQ25SRC
Definition: Mini55Series.h:2727
I2C_T::DAT
__IO uint32_t DAT
Definition: Mini55Series.h:2171
PWM_T::ADCTCTL1
__IO uint32_t ADCTCTL1
Definition: Mini55Series.h:3517
HDIV_T::REM
__IO uint32_t REM
Definition: Mini55Series.h:2058
INTR_T::IRQ18SRC
__I uint32_t IRQ18SRC
Definition: Mini55Series.h:2711
INTR_T::IRQ2SRC
__I uint32_t IRQ2SRC
Definition: Mini55Series.h:2548
PWM_T::INTEN
__IO uint32_t INTEN
Definition: Mini55Series.h:3190
GPIO_T::DATMSK
__IO uint32_t DATMSK
Definition: Mini55Series.h:1601
TIMER_T::EINTSTS
__IO uint32_t EINTSTS
Definition: Mini55Series.h:5971
INTR_T::IRQ29SRC
__I uint32_t IRQ29SRC
Definition: Mini55Series.h:2755
UART_T::DAT
__IO uint32_t DAT
Definition: Mini55Series.h:6186
ADC_T::TRGDLY
__IO uint32_t TRGDLY
Definition: Mini55Series.h:529
SYS_T::P5_MFP
__IO uint32_t P5_MFP
Definition: Mini55Series.h:5371
I2C_T::ADDRMSK3
__IO uint32_t ADDRMSK3
Definition: Mini55Series.h:2330
TIMER_T::CMP
__IO uint32_t CMP
Definition: Mini55Series.h:5868
INTR_T::IRQ12SRC
__I uint32_t IRQ12SRC
Definition: Mini55Series.h:2648
GPIO_T::INTEN
__IO uint32_t INTEN
Definition: Mini55Series.h:1684
INTR_T::NMICTL
__IO uint32_t NMICTL
Definition: Mini55Series.h:2776
ADC_T::SEQDAT0
__I uint32_t SEQDAT0
Definition: Mini55Series.h:622
UART_T::MODEMSTS
__IO uint32_t MODEMSTS
Definition: Mini55Series.h:6352
PWM_T::BRKCTL
__IO uint32_t BRKCTL
Definition: Mini55Series.h:3371
GPIO_T::INTTYPE
__IO uint32_t INTTYPE
Definition: Mini55Series.h:1656
PWM_T::POEN
__IO uint32_t POEN
Definition: Mini55Series.h:3315
I2C_T::TOCTL
__IO uint32_t TOCTL
Definition: Mini55Series.h:2227
INTR_T::IRQ17SRC
__I uint32_t IRQ17SRC
Definition: Mini55Series.h:2700
INTR_T::IRQ16SRC
__I uint32_t IRQ16SRC
Definition: Mini55Series.h:2688
UART_T::LINE
__IO uint32_t LINE
Definition: Mini55Series.h:6303
PWM_T::PHCHGMSK
__IO uint32_t PHCHGMSK
Definition: Mini55Series.h:3845
SPI_T::TX
__O uint32_t TX
Definition: Mini55Series.h:4749
FMC_T::ISPADDR
__IO uint32_t ISPADDR
Definition: Mini55Series.h:1324
PWM_T::ADCTSTS1
__IO uint32_t ADCTSTS1
Definition: Mini55Series.h:3585
I2C_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Mini55Series.h:2205
SYS_T::IRCTISTS
__IO uint32_t IRCTISTS
Definition: Mini55Series.h:5461
ADC_T::SEQDAT1
__I uint32_t SEQDAT1
Definition: Mini55Series.h:643
I2C_T::STATUS
__I uint32_t STATUS
Definition: Mini55Series.h:2192
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Mini55Series.h:4889
TIMER_T::CAP
__I uint32_t CAP
Definition: Mini55Series.h:5914
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: Mini55Series.h:1094
INTR_T::IRQ6SRC
__I uint32_t IRQ6SRC
Definition: Mini55Series.h:2596
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: Mini55Series.h:1355
ADC_T::DAT
__I uint32_t DAT
Definition: Mini55Series.h:336
SYS_T::REGLCTL
__IO uint32_t REGLCTL
Definition: Mini55Series.h:5486
PWM_T::ADCTCTL0
__IO uint32_t ADCTCTL0
Definition: Mini55Series.h:3471
ADC_T::SEQCTL
__IO uint32_t SEQCTL
Definition: Mini55Series.h:601
PWM_T::ADCTSTS0
__IO uint32_t ADCTSTS0
Definition: Mini55Series.h:3559
UART_T::FIFOSTS
__IO uint32_t FIFOSTS
Definition: Mini55Series.h:6431
SYS_T::PDID
__I uint32_t PDID
Definition: Mini55Series.h:5073
SYS_T::IPRST1
__IO uint32_t IPRST1
Definition: Mini55Series.h:5180
ACMP_T::STATUS
__IO uint32_t STATUS
Definition: Mini55Series.h:237
I2C_T::STATUS1
__IO uint32_t STATUS1
Definition: Mini55Series.h:2389
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Mini55Series.h:4675
I2C_T::CTL1
__IO uint32_t CTL1
Definition: Mini55Series.h:2368
INTR_T::IRQ1SRC
__I uint32_t IRQ1SRC
Definition: Mini55Series.h:2536
SYS_T::P3_MFP
__IO uint32_t P3_MFP
Definition: Mini55Series.h:5329
GPIO_T::INTSRC
__IO uint32_t INTSRC
Definition: Mini55Series.h:1702
I2C_T::ADDRMSK1
__IO uint32_t ADDRMSK1
Definition: Mini55Series.h:2304
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: Mini55Series.h:891
FMC_T::DFBA
__I uint32_t DFBA
Definition: Mini55Series.h:1383
I2C_T::ADDR1
__IO uint32_t ADDR1
Definition: Mini55Series.h:2244
FMC_T::ISPSTS
__I uint32_t ISPSTS
Definition: Mini55Series.h:1414
GPIO_DB_T::DBCTL
__IO uint32_t DBCTL
Definition: Mini55Series.h:1743
UART_T::TOUT
__IO uint32_t TOUT
Definition: Mini55Series.h:6523
CLK_T::STATUS
__IO uint32_t STATUS
Definition: Mini55Series.h:969
UART_T::FIFO
__IO uint32_t FIFO
Definition: Mini55Series.h:6268
ADC_T::CHEN
__IO uint32_t CHEN
Definition: Mini55Series.h:437
CLK_T::PWRCTL
__IO uint32_t PWRCTL
Definition: Mini55Series.h:875
SYS_T::P0_MFP
__IO uint32_t P0_MFP
Definition: Mini55Series.h:5263
SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: Mini55Series.h:4829
INTR_T::IRQ3SRC
__I uint32_t IRQ3SRC
Definition: Mini55Series.h:2560
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: Mini55Series.h:1337
INTR_T::IRQ8SRC
__I uint32_t IRQ8SRC
Definition: Mini55Series.h:2620
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: Mini55Series.h:1060
CLK_T::CLKOCTL
__IO uint32_t CLKOCTL
Definition: Mini55Series.h:1120
HDIV_T::DIVIDEND
__IO uint32_t DIVIDEND
Definition: Mini55Series.h:2021
ADC_T::EXTSMPT
__IO uint32_t EXTSMPT
Definition: Mini55Series.h:557
TIMER_AC_T::CCAPCTL
__IO uint32_t CCAPCTL
Definition: Mini55Series.h:6030
ADC_T::CTL
__IO uint32_t CTL
Definition: Mini55Series.h:382
GPIO_T::DINOFF
__IO uint32_t DINOFF
Definition: Mini55Series.h:1568
INTR_T::IRQ9SRC
__I uint32_t IRQ9SRC
Definition: Mini55Series.h:2632
INTR_T::IRQ5SRC
__I uint32_t IRQ5SRC
Definition: Mini55Series.h:2584
UART_T::MODEM
__IO uint32_t MODEM
Definition: Mini55Series.h:6327
SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: Mini55Series.h:4711
I2C_T::ADDR2
__IO uint32_t ADDR2
Definition: Mini55Series.h:2261
CLK_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Mini55Series.h:1078
SPI_T::SLVCTL
__IO uint32_t SLVCTL
Definition: Mini55Series.h:4795
INTR_T::IRQ0SRC
__I uint32_t IRQ0SRC
Definition: Mini55Series.h:2524
HDIV_T::STATUS
__I uint32_t STATUS
Definition: Mini55Series.h:2073
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: Mini55Series.h:942
TIMER_T::CTL
__IO uint32_t CTL
Definition: Mini55Series.h:5851
PWM_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Mini55Series.h:2935
SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: Mini55Series.h:5239
SYS_T::IPRST0
__IO uint32_t IPRST0
Definition: Mini55Series.h:5140
I2C_T::CTL
__IO uint32_t CTL
Definition: Mini55Series.h:2142
TIMER_T::INTSTS
__IO uint32_t INTSTS
Definition: Mini55Series.h:5888
PWM_T::PHCHG
__IO uint32_t PHCHG
Definition: Mini55Series.h:3703
PWM_T::CLKPSC
__IO uint32_t CLKPSC
Definition: Mini55Series.h:2901
PWM_T::INTSTS
__IO uint32_t INTSTS
Definition: Mini55Series.h:3281
HDIV_T::QUOTIENT
__IO uint32_t QUOTIENT
Definition: Mini55Series.h:2046
PWM_T::PHCHGNXT
__IO uint32_t PHCHGNXT
Definition: Mini55Series.h:3821
GPIO_T::PIN
__I uint32_t PIN
Definition: Mini55Series.h:1615
I2C_T::ADDRMSK0
__IO uint32_t ADDRMSK0
Definition: Mini55Series.h:2291
SYS_T::IRCTCTL
__IO uint32_t IRCTCTL
Definition: Mini55Series.h:5414
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: Mini55Series.h:1583
UART_T::ALTCTL
__IO uint32_t ALTCTL
Definition: Mini55Series.h:6596
SYS_T::P4_MFP
__IO uint32_t P4_MFP
Definition: Mini55Series.h:5350
INTR_T::IRQSTS
__IO uint32_t IRQSTS
Definition: Mini55Series.h:2792
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: Mini55Series.h:1635
INTR_T::IRQ14SRC
__I uint32_t IRQ14SRC
Definition: Mini55Series.h:2672
SYS_T::EINT0SEL
__IO uint32_t EINT0SEL
Definition: Mini55Series.h:5384
INTR_T::IRQ4SRC
__I uint32_t IRQ4SRC
Definition: Mini55Series.h:2572
ACMP_T::VREF
__IO uint32_t VREF
Definition: Mini55Series.h:252
INTR_T::IRQ28SRC
__I uint32_t IRQ28SRC
Definition: Mini55Series.h:2743
SYS_T::RSTSTS
__IO uint32_t RSTSTS
Definition: Mini55Series.h:5113
GPIO_T::MODE
__IO uint32_t MODE
Definition: Mini55Series.h:1554
SYS_T::P1_MFP
__IO uint32_t P1_MFP
Definition: Mini55Series.h:5284
PWM_T::DTCTL
__IO uint32_t DTCTL
Definition: Mini55Series.h:3390
HDIV_T::DIVISOR
__IO uint32_t DIVISOR
Definition: Mini55Series.h:2034
TIMER_T::EXTCTL
__IO uint32_t EXTCTL
Definition: Mini55Series.h:5955
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: Mini55Series.h:1004
UART_T::FUNCSEL
__IO uint32_t FUNCSEL
Definition: Mini55Series.h:6611
UART_T::INTSTS
__IO uint32_t INTSTS
Definition: Mini55Series.h:6505
WDT_T::CTL
__IO uint32_t CTL
Definition: Mini55Series.h:6896
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: Mini55Series.h:1369
PWM_T::IFA
__IO uint32_t IFA
Definition: Mini55Series.h:3860
TIMER_T::CNT
__I uint32_t CNT
Definition: Mini55Series.h:5900
I2C_T::ADDRMSK2
__IO uint32_t ADDRMSK2
Definition: Mini55Series.h:2317
hdiv.h
MINI55 series HDIV driver header file.
i2c.h
MINI55 series I2C driver header file.
pwm.h
MINI55 series PWM driver header file.
spi.h
MINI55 series SPI driver header file.
ACMP_T
Definition: Mini55Series.h:163
ADC_T
Definition: Mini55Series.h:314
CLK_T
Definition: Mini55Series.h:819
FMC_T
Definition: Mini55Series.h:1275
GPIO_DB_T
Definition: Mini55Series.h:1709
GPIO_T
Definition: Mini55Series.h:1479
HDIV_T
Definition: Mini55Series.h:2008
I2C_T
Definition: Mini55Series.h:2108
INTR_T
Definition: Mini55Series.h:2511
PWM_T
Definition: Mini55Series.h:2878
SPI_T
Definition: Mini55Series.h:4570
SYS_T
Definition: Mini55Series.h:5059
TIMER_AC_T
Definition: Mini55Series.h:5976
TIMER_T
Definition: Mini55Series.h:5779
UART_T
Definition: Mini55Series.h:6171
WDT_T
Definition: Mini55Series.h:6835
sys.h
MINI55 series SYS driver header file.
system_Mini55Series.h
Mini55 series system clock definition file.
timer.h
MINI55 series TIMER driver header file.
uart.h
MINI55 series UART driver header file.
wdt.h
MINI55 series WDT driver header file.