| MINI55_BSP V3.03.000 The Board Support Package for Mini55 Series MCU

clk.h
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1/**************************************************************************/
12#ifndef __CLK_H__
13#define __CLK_H__
14
15#ifdef __cplusplus
16 extern "C"
17{
18#endif
19
20
35/*---------------------------------------------------------------------------------------------------------*/
36/* PWRCTL constant definitions. */
37/*---------------------------------------------------------------------------------------------------------*/
38#define CLK_PWRCTL_XTL12M 0x01UL
39#define CLK_PWRCTL_HXT 0x01UL
40#define CLK_PWRCTL_XTL32K 0x02UL
41#define CLK_PWRCTL_LXT 0x02UL
43/*---------------------------------------------------------------------------------------------------------*/
44/* CLKSEL0 constant definitions. */
45/*---------------------------------------------------------------------------------------------------------*/
46#define CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
47#define CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
48#define CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
49#define CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
50#define CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
51#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
52#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
53#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)
55/*---------------------------------------------------------------------------------------------------------*/
56/* CLKSEL1 constant definitions. */
57/*---------------------------------------------------------------------------------------------------------*/
58#define CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
59#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
60#define CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
61#define CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
62#define CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
63#define CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
64#define CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
65#define CLK_CLKSEL1_SPISEL_HXTorLXT 0x00000000UL
66#define CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
67#define CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
68#define CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
69#define CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
70#define CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
71#define CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
72#define CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
73#define CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
74#define CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
75#define CLK_CLKSEL1_UART0SEL_XTAL 0x00000000UL
76#define CLK_CLKSEL1_UART0SEL_HIRC 0x02000000UL
77#define CLK_CLKSEL1_UART1SEL_XTAL 0x00000000UL
78#define CLK_CLKSEL1_UART1SEL_HIRC 0x08000000UL
79#define CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
80#define CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
83/*---------------------------------------------------------------------------------------------------------*/
84/* CLKSEL2 constant definitions. */
85/*---------------------------------------------------------------------------------------------------------*/
86#define CLK_CLKSEL2_FDIVSEL_XTAL 0x00000000UL
87#define CLK_CLKSEL2_FDIVSEL_HXT 0x00000000UL
88#define CLK_CLKSEL2_FDIVSEL_LXT 0x00000000UL
89#define CLK_CLKSEL2_FDIVSEL_HCLK 0x00000008UL
90#define CLK_CLKSEL2_FDIVSEL_HIRC 0x0000000CUL
91#define CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
94/*---------------------------------------------------------------------------------------------------------*/
95/* CLKDIV constant definitions. */
96/*---------------------------------------------------------------------------------------------------------*/
97#define CLK_CLKDIV_ADC(x) (((x)-1) << 16)
98#define CLK_CLKDIV_UART(x) (((x)-1) << 8)
99#define CLK_CLKDIV_UART0(x) (((x)-1) << 8)
100#define CLK_CLKDIV_UART1(x) (((x)-1) << 12)
101#define CLK_CLKDIV_HCLK(x) ((x)-1)
103/*---------------------------------------------------------------------------------------------------------*/
104/* MODULE constant definitions. */
105/*---------------------------------------------------------------------------------------------------------*/
106#define MODULE_APBCLK(x) ((x >>31) & 0x1)
107#define MODULE_CLKSEL(x) ((x >>29) & 0x3)
108#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
109#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
110#define MODULE_CLKDIV(x) ((x >>18) & 0x3)
111#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
112#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
113#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
114#define MODULE_NoMsk 0x0
115#define NA MODULE_NoMsk
117#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
118#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
119#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
120#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
121#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
122#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
123#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
124#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
125/*-------------------------------------------------------------------------------------------------------------------------------*/
126/* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
127/*-------------------------------------------------------------------------------------------------------------------------------*/
128#define WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDTCKEN_Pos )
129#define TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0CKEN_Pos)
130#define TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1CKEN_Pos)
131#define FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_CLKOCKEN_Pos)
132#define I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2CCKEN_Pos)
133#define SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPICKEN_Pos)
134#define UART0_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART0CKEN_Pos)
135#define UART1_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(26<<20)|(0x0<<18)|(0x0F<<10)|(12<<5)|CLK_APBCLK_UART1CKEN_Pos)
136#define PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH01CKEN_Pos)
137#define PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH23CKEN_Pos)
138#define PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWMCH45CKEN_Pos)
139#define ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADCCKEN_Pos)
140#define ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMPCKEN_Pos) /* end of group MINI55_CLK_EXPORTED_CONSTANTS */
143
144
156__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
157{
158 SysTick->LOAD = us * CyclesPerUs;
159 SysTick->VAL = (0x00);
160 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
161
162 /* Waiting for down-count to zero */
163 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
164
165 /* Disable SysTick counter */
166 SysTick->CTRL = 0;
167}
168
169 void CLK_DisableCKO(void);
170 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
171 void CLK_PowerDown(void);
172 void CLK_Idle(void);
173uint32_t CLK_GetHXTFreq(void);
174uint32_t CLK_GetLXTFreq(void);
175uint32_t CLK_GetHCLKFreq(void);
176uint32_t CLK_GetCPUFreq(void);
177 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
178 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
179 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
180 void CLK_EnableXtalRC(uint32_t u32ClkMask);
181 void CLK_DisableXtalRC(uint32_t u32ClkMask);
182 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
183 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
184uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
185 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
186 void CLK_DisableSysTick(void);
187
188
189 /* end of group MINI55_CLK_EXPORTED_FUNCTIONS */
191 /* end of group MINI55_CLK_Driver */
193 /* end of group MINI55_Device_Driver */
195
196#ifdef __cplusplus
197}
198#endif
199
200#endif //__CLK_H__
201
202/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
CLK_Idle
void CLK_Idle(void)
This function let system enter to Idle mode.
Definition: clk.c:80
CLK_SetSysTickClockSrc
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
This function set SysTick clock source.
Definition: clk.c:217
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:114
CLK_DisableCKO
void CLK_DisableCKO(void)
This function disable frequency output function.
Definition: clk.c:30
CLK_EnableModuleClock
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
Definition: clk.c:268
CLK_EnableCKO
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:53
CLK_DisableModuleClock
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
Definition: clk.c:291
CLK_WaitClockReady
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:309
CLK_GetLXTFreq
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:102
CLK_PowerDown
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
Definition: clk.c:69
CLK_SysTickDelay
__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
Definition: clk.h:156
CLK_GetCPUFreq
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
Definition: clk.c:125
CLK_SetHCLK
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:141
CLK_DisableXtalRC
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
Definition: clk.c:245
CLK_DisableSysTick
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:363
CLK_SetModuleClock
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:187
CLK_EnableXtalRC
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
Definition: clk.c:230
CLK_EnableSysTick
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:336
CLK_GetHXTFreq
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:90
CyclesPerUs
uint32_t CyclesPerUs
Definition: system_Mini55Series.c:23