| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
CLK_T Struct Reference

`#include <Mini51Series.h>`

## Data Fields
__IO uint32_t | PWRCON
__IO uint32_t | AHBCLK
__IO uint32_t | APBCLK
__IO uint32_t | CLKSTATUS
__IO uint32_t | CLKSEL0
__IO uint32_t | CLKSEL1
__IO uint32_t | CLKDIV
__IO uint32_t | CLKSEL2
__IO uint32_t | FRQDIV

## Detailed Description

    @addtogroup CLK System Clock Controller(CLK)
    Memory Mapped Structure for CLK Controller

Definition at line 926 of file Mini51Series.h.

## Field Documentation

## ◆ AHBCLK

CLK_T::AHBCLK

AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits | Field | Descriptions
[2] | ISP_EN | Flash ISP Controller Clock Enable Control 0 = Flash ISP peripheral clock Disabled. 1 = Flash ISP peripheral clock Enabled.

Definition at line 1463 of file Mini51Series.h.

## ◆ APBCLK

CLK_T::APBCLK

APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits | Field | Descriptions
[0] | WDT_EN | Watchdog Timer Clock Enable Control (Write Protect) 0 = Watchdog Timer clock Disabled. 1 = Watchdog Timer clock Enabled. Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.
[2] | TMR0_EN | Timer0 Clock Enable Control 0 = Timer0 clock Disabled. 1 = Timer0 clock Enabled.
[3] | TMR1_EN | Timer1 Clock Enable Control 0 = Timer1 clock Disabled. 1 = Timer1 clock Enabled.
[6] | FDIV_EN | Frequency Divider Output Clock Enable Control 0 = FDIV clock Disabled. 1 = FDIV clock Enabled.
[8] | I2C_EN | I2C Clock Enable Control 0 = I2C clock Disabled. 1 = I2C clock Enabled.
[12] | SPI_EN | SPI Peripheral Clock Enable Control 0 = SPI peripheral clock Disabled. 1 = SPI peripheral clock Enabled.
[16] | UART_EN | UART Clock Enable Control 0 = UART clock Disabled. 1 = UART clock Enabled.
[20] | PWM01_EN | PWM_01 Clock Enable Control 0 = PWM01 clock Disabled. 1 = PWM01 clock Enabled.
[21] | PWM23_EN | PWM_23 Clock Enable Control 0 = PWM23 clock Disabled. 1 = PWM23 clock Enabled.
[22] | PWM45_EN | PWM_45 Clock Enable Control 0 = PWM45 clock Disabled. 1 = PWM45 clock Enabled.
[28] | ADC_EN | Analog-digital-converter (ADC) Clock Enable Control 0 = ADC peripheral clock Disabled. 1 = ADC peripheral clock Enabled.
[30] | ACMP_EN | Analog Comparator Clock Enable Control 0 = Analog Comparator clock Disabled. 1 = Analog Comparator clock Enabled.

Definition at line 1464 of file Mini51Series.h.

## ◆ CLKDIV

CLK_T::CLKDIV

CLKDIV

Offset: 0x18 Clock Divider Number Register

Bits | Field | Descriptions
[3:0] | HCLK_N | HCLK Clock Divide Number From HCLK Clock Source HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1).
[11:8] | UART_N | UART Clock Divide Number From UART Clock Source UART clock frequency = (UART clock source frequency) / (UART_N + 1).
[23:16] | ADC_N | ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source ADC peripheral clock frequency = (ADC peripheral clock source frequency) / (ADC_N + 1).

Definition at line 1468 of file Mini51Series.h.

## ◆ CLKSEL0

CLK_T::CLKSEL0

CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits | Field | Descriptions
[2:0] | HCLK_S | HCLK Clock Source Selection (Write Protect) 000 = Clock source is from HXT or LXT. 001 = Reserved. 010 = Reserved. 011 = Clock source is from LIRC. 111 = Clock source is from HIRC. Others = Reserved. Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable. Note2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100. Note3: To set PWRCON[1:0], select HXT or LXT crystal clock.
[5:3] | STCLK_S | Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect) If SYST_CSR[2] = 1, SysTick clock source is from HCLK. If SYST_CSR[2] = 0, SysTick clock source is defined by below settings. 000 = Clock source is from HXT or LXT. 001 = Reserved. 010 = Clock source is from HXT/2 or LXT/2. 011 = Clock source is from HCLK/2. 111 = Clock source is from HIRC /2. Others = Reserved. Note1: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100. Note2: If the SysTick clock source is not from HCLK (i.e. SYST_CSR[2] = 0), SysTick clock source must less than or equal to HCLK/2. Note3: To set PWRCON[1:0], select HXT or LXT crystal clock.

Definition at line 1466 of file Mini51Series.h.

## ◆ CLKSEL1

CLK_T::CLKSEL1

CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits | Field | Descriptions
[1:0] | WDT_S | WDT CLK Clock Source Selection (Write Protect) 00 = Clock source is from HXT or LXT. 01 = Reserved. 10 = Clock source is from HCLK/2048 clock. 11 = Clock source is from LIRC. Note1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100. Note2: To set PWRCON[1:0], select HXT or LXT crystal clock.
[3:2] | ADC_S | ADC Peripheral Clock Source Selection 00 = Clock source is from HXT or LXT. 01 = Reserved. 10 = Clock source is from HCLK. 11 = Clock source is from HIRC. Note: To set PWRCON[1:0], select HXT or LXT crystal clock.
[4] | SPI_S | SPI Clock Source Selection 0 = Clock source is from HXT or LXT. 1 = Clock source is from HCLK. Note: To set PWRCON[1:0], select HXT or LXT crystal clock.
[10:8] | TMR0_S | TIMER0 Clock Source Selection 000 = Clock source is from HXT or LXT. 001 = Clock source is from LIRC. 010 = Clock source is from HCLK. 011 = Clock source is from external trigger. 111 = Clock source is from HIRC. Others = Reserved. Note: To set PWRCON[1:0], select HXT or LXT crystal clock.
[14:12] | TMR1_S | TIMER1 Clock Source Selection 000 = Clock source is from HXT or LXT. 001 = Clock source is from LIRC. 010 = Clock source is from HCLK. 011 = Clock source is from external trigger. 111 = Clock source is from HIRC. Others = Reserved. Note: To set PWRCON[1:0], select HXT or LXT crystal clock.
[25:24] | UART_S | UART Clock Source Selection 00 = Clock source is from HXT or LXT. 01 = Reserved. 10 = Clock source is from HIRC. 11 = Clock source is from HIRC . Note: To set PWRCON[1:0], select HXT or LXT crystal clock.

Definition at line 1467 of file Mini51Series.h.

## ◆ CLKSEL2

CLK_T::CLKSEL2

CLKSEL2

Offset: 0x1C Clock Source Select Control Register 2

Bits | Field | Descriptions
[3:2] | FRQDIV_S | Clock Divider Clock Source Selection 00 = Clock source is from HXT or LXT. 01 = Reserved. 10 = Clock source is from HCLK. 11 = Clock source is from HIRC. Note: To set PWRCON[1:0], select HXT or LXT crystal clock.

Definition at line 1469 of file Mini51Series.h.

## ◆ CLKSTATUS

CLK_T::CLKSTATUS

CLKSTATUS

Offset: 0x0C Clock Status Monitor Register

Bits | Field | Descriptions
[0] | XTL_STB | HXT Or LXT Clock Source Stable Flag 0 = HXT or LXT clock is not stable or disabled. 1 = HXT or LXT clock is stable.
[3] | OSC10K_STB | LIRC Clock Source Stable Flag (Read Only) 0 = LIRC clock is not stable or disabled. 1 = LIRC clock is stable.
[4] | OSC22M_STB | HIRC Clock Source Stable Flag (Read Only) 0 = HIRC clock is not stable or disabled. 1 = HIRC clock is stable.
[7] | CLK_SW_FAIL | Clock Switch Fail Flag 0 = Clock switching success. 1 = Clock switching failed. Note1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. Note2: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SE_FAIL will be cleared automatically by hardware.

Definition at line 1465 of file Mini51Series.h.

## ◆ FRQDIV

CLK_T::FRQDIV

FRQDIV

Offset: 0x24 Frequency Divider Control Register

Bits | Field | Descriptions
[3:0] | FSEL | Divider Output Frequency Selection The formula of output frequency is Fout = Fin/2(N+1),. Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FSEL[3:0].
[4] | DIVIDER_EN | Frequency Divider Enable Control 0 = Frequency Divider Disabled. 1 = Frequency Divider Enabled.
[5] | DIVIDER1 | Frequency Divider 1 Enable Control 0 = Divider output frequency is depended on FSEL value. 1 = Divider output frequency is the same as input clock frequency.

Definition at line 1473 of file Mini51Series.h.

## ◆ PWRCON

CLK_T::PWRCON

PWRCON

Offset: 0x00 System Power-down Control Register

Bits | Field | Descriptions
[1:0] | XTLCLK_EN | External Crystal HXT Or LXT Enable Control (Write Protect) The default clock source is from HIRC. These two bits are default set to "00" and the XTAL1 and XTAL2 pins are GPIO. 00 = XTAL1 and XTAL2 are GPIO, disable both LXT & HXT (default). 01 = HXT Enabled. 10 = LXT Enabled. 11 = XTAL1 is external clock input pin, XTAL2 is GPIO. Note: To enable the external XTAL function, the P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
[2] | OSC22M_EN | 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect) 0 = 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled. 1 = 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled. Note: The default of OSC22M_EN bit is 1.
[3] | OSC10K_EN | 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect) 0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. 1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled.
[4] | PD_WU_DLY | Wake-up Delay Counter Enable Control (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC). 0 = Clock cycles delay Disabled. 1 = Clock cycles delay Enabled.
[5] | PD_WU_INT_EN | Power-down Mode Wake-up Interrupt Enable Control (Write Protect) 0 = Disabled. 1 = Enabled. Note: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
[6] | PD_WU_STS | Power-down Mode Wake-up Interrupt Status Set by "Power-down wake-up event", which indicates that resume from Power-down mode. The flag is set if the GPIO, UART, WDT, I2C, ACMP, Timer or BOD wake-up occurred. Note: This bit works only if PD_WU_INT_EN (PWRCON[5]) set to 1. Write 1 to clear the bit to 0.
[7] | PWR_DOWN_EN | System Power-down Enable Bit (Write Protect) When chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down. In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode. In Power-down mode, the system clock is disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator. 0 = Chip operating normally or chip in Idle mode because of WFI command. 1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI.
[9] | PD_32K | Enable LXT In Power-down Mode This bit controls the crystal oscillator active or not in Power-down mode. 0 = No effect to Power-down mode. 1 = If XTLCLK_EN[1:0] = 10, LXT is still active in Power-down mode.

Definition at line 1462 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h