| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
I2C_T Struct Reference

`#include <Mini51Series.h>`

## Data Fields
__IO uint32_t | I2CON
__IO uint32_t | I2CADDR0
__IO uint32_t | I2CDAT
__I uint32_t | I2CSTATUS
__IO uint32_t | I2CLK
__IO uint32_t | I2CTOC
__IO uint32_t | I2CADDR1
__IO uint32_t | I2CADDR2
__IO uint32_t | I2CADDR3
__IO uint32_t | I2CADM0
__IO uint32_t | I2CADM1
__IO uint32_t | I2CADM2
__IO uint32_t | I2CADM3
__IO uint32_t | I2CON2
__IO uint32_t | I2CSTATUS2

## Detailed Description

    @addtogroup I2C Inter-IC Bus Controller(I2C)
    Memory Mapped Structure for I2C Controller

Definition at line 3733 of file Mini51Series.h.

## Field Documentation

## ◆ I2CADDR0

I2C_T::I2CADDR0

I2CADDR0

Offset: 0x04 I2C Slave Address Register 0

Bits | Field | Descriptions
[0] | GC | General Call Function 0 = General Call Function Disabled. 1 = General Call Function Enabled.
[7:1] | I2CADDR | I2C Address Bits The content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.

Definition at line 4222 of file Mini51Series.h.

## ◆ I2CADDR1

I2C_T::I2CADDR1

I2CADDR1

Offset: 0x18 I2C Slave Address Register 1

Bits | Field | Descriptions
[0] | GC | General Call Function 0 = General Call Function Disabled. 1 = General Call Function Enabled.
[7:1] | I2CADDR | I2C Address Bits The content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.

Definition at line 4227 of file Mini51Series.h.

## ◆ I2CADDR2

I2C_T::I2CADDR2

I2CADDR2

Offset: 0x1C I2C Slave Address Register 2

Bits | Field | Descriptions
[0] | GC | General Call Function 0 = General Call Function Disabled. 1 = General Call Function Enabled.
[7:1] | I2CADDR | I2C Address Bits The content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.

Definition at line 4228 of file Mini51Series.h.

## ◆ I2CADDR3

I2C_T::I2CADDR3

I2CADDR3

Offset: 0x20 I2C Slave Address Register 3

Bits | Field | Descriptions
[0] | GC | General Call Function 0 = General Call Function Disabled. 1 = General Call Function Enabled.
[7:1] | I2CADDR | I2C Address Bits The content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.

Definition at line 4229 of file Mini51Series.h.

## ◆ I2CADM0

I2C_T::I2CADM0

I2CADM0

Offset: 0x24 I2C Slave Address Mask Register 0

Bits | Field | Descriptions
[7:1] | I2CADM | I2C Address Mask Bits 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4230 of file Mini51Series.h.

## ◆ I2CADM1

I2C_T::I2CADM1

I2CADM1

Offset: 0x28 I2C Slave Address Mask Register 1

Bits | Field | Descriptions
[7:1] | I2CADM | I2C Address Mask Bits 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4231 of file Mini51Series.h.

## ◆ I2CADM2

I2C_T::I2CADM2

I2CADM2

Offset: 0x2C I2C Slave Address Mask Register 2

Bits | Field | Descriptions
[7:1] | I2CADM | I2C Address Mask Bits 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4232 of file Mini51Series.h.

## ◆ I2CADM3

I2C_T::I2CADM3

I2CADM3

Offset: 0x30 I2C Slave Address Mask Register 3

Bits | Field | Descriptions
[7:1] | I2CADM | I2C Address Mask Bits 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care").

Definition at line 4233 of file Mini51Series.h.

## ◆ I2CDAT

I2C_T::I2CDAT

I2CDAT

Offset: 0x08 I2C DATA Register

Bits | Field | Descriptions
[7:0] | I2CDAT | I2C Data Bits Bit [7:0] is located with the 8-bit transferred data of the I2C serial port.

Definition at line 4223 of file Mini51Series.h.

## ◆ I2CLK

I2C_T::I2CLK

I2CLK

Offset: 0x10 I2C Clock Divided Register

Bits | Field | Descriptions
[7:0] | I2CLK | I2C Clock Divided Bits The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4x (I2CLK+1)). Note: The minimum value of I2CLK is 4.

Definition at line 4225 of file Mini51Series.h.

## ◆ I2CON

I2C_T::I2CON

I2CON

Offset: 0x00 I2C Control Register

Bits | Field | Descriptions
[2] | AA | Assert Acknowledge Control Bit When AA=1 is prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter. When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
[3] | SI | I2C Interrupt Flag When a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit.
[4] | STO | I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
[5] | STA | I2C START Control Bit Setting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
[6] | ENS1 | I2C Controller Enable Control 0 = I2C Controller Disabled. 1 = I2C Controller Enabled. Set to enable I2C serial function controller. When ENS1=1 the I2C serial function enables. The function of multi-function pin must be set to I2C first.
[7] | EI | Interrupt Enable Control 0 = I2C interrupt Disabled. 1 = I2C interrupt Enabled.

Definition at line 4221 of file Mini51Series.h.

## ◆ I2CON2

I2C_T::I2CON2

I2CON2

Offset: 0x3C I2C Control Register 2

Bits | Field | Descriptions
[0] | WAKEUPEN | Wake-up Enable Control 0 = I2C wake-up function Disabled. 1 = I2C wake-up function Enabled. The system can be wake-up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register.
[1] | TWOFF_EN | TWO LEVEL FIFO Enable Control 0 = Disabled. 1 = Enabled. Set to enable the two-level FIFO for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus. If this bit is set = 1, the control bit of STA for repeat start or STO bit should be set after the current SI is clear. For example: if there are 4 data shall be transmitted and then stop it. The STO bit shall be set after the 3rd data's SI event being clear. In this time, the 4th data can be transmitted and the I2C stop after the 4th data transmission done.
[2] | NOSTRETCH | NO STRETCH The I2C BUS 0 = The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode. 1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode.
[3] | OVER_INTEN | I2C OVER RUN Interrupt Control Bit Setting OVER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO. 0 = Disabled. 1 = Enabled.
[4] | UNDER_INTEN | I2C UNDER RUN Interrupt Control Bit Setting UNDER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO. 0 = Disabled. 1 = Enabled.

Definition at line 4237 of file Mini51Series.h.

## ◆ I2CSTATUS

I2C_T::I2CSTATUS

I2CSTATUS

Offset: 0x0C I2C Status Register

Bits | Field | Descriptions
[7:0] | I2CSTATUS | I2C Status Bits The three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2CSTATUS contains F8H, no serial interrupt is requested. All the other I2CSTATUS values correspond to defined I2C states. When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is present in I2CSTATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software. In addition, the states 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. Examples of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.

Definition at line 4224 of file Mini51Series.h.

## ◆ I2CSTATUS2

I2C_T::I2CSTATUS2

I2CSTATUS2

Offset: 0x40 I2C Status Register 2

Bits | Field | Descriptions
[0] | WAKEUP | I2C Wake-up Interrupt Flag When chip is woken up from Power-Down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
[1] | FULL | I2C TWO LEVEL FIFO FULL This bit indicates TX FIFO full or not when the TWOFF_EN = 1.
[2] | EMPTY | I2C TWO LEVEL FIFO EMPTY This bit indicates RX FIFO empty or not when the TWOFF_EN = 1.
[3] | OVERUN | I2C OVER RUN Status Bit This bit indicates the received FIFO is over run when the TWOFF_EN = 1.
[4] | UNDERUN | I2C UNDER RUN Status Bit This bit indicates the transmitted FIFO is under run when the TWOFF_EN = 1.

Definition at line 4238 of file Mini51Series.h.

## ◆ I2CTOC

I2C_T::I2CTOC

I2CTOC

Offset: 0x14 I2C Time-Out Counter Register

Bits | Field | Descriptions
[0] | TIF | Time-out Flag This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1. Note: Software can write 1 to clear this bit.
[1] | DIV4 | Time-out Counter Input Clock Divided By 4 0 = Time-out counter input clock divided by 4 Disabled. 1 = Time-out counter input clock divided by 4 Enabled. Note: When enabled, the time-out period is extended 4 times.
[2] | ENTI | Time-out Counter Enable Control 0 = Time-out counter Disabled. 1 = Time-out counter Enabled. Note: When the 14-bit time-out counter is enabled, it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared.

Definition at line 4226 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h