| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
UART_T Struct Reference

`#include <Mini51Series.h>`

## Data Fields
union {
__I uint32_t RBR
__O uint32_t THR
}; |
__IO uint32_t | IER
__IO uint32_t | FCR
__IO uint32_t | LCR
__IO uint32_t | MCR
__IO uint32_t | MSR
__IO uint32_t | FSR
__IO uint32_t | ISR
__IO uint32_t | TOR
__IO uint32_t | BAUD
__IO uint32_t | IRCR
__IO uint32_t | ALT_CSR
__IO uint32_t | FUN_SEL

## Detailed Description

    @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
    Memory Mapped Structure for UART Controller

Definition at line 8567 of file Mini51Series.h.

## Field Documentation

## ◆ @1

union { ... }

## ◆ ALT_CSR

UART_T::ALT_CSR

ALT_CSR

Offset: 0x2C UART Alternate Control/Status Register

Bits | Field | Descriptions
[8] | RS485_NMM | RS-485 Normal Multi-drop Operation Mode (NMM) Control 0 = RS-485 Normal Multi-drop Operation Mode (NMM) Disabled. 1 = RS-485 Normal Multi-drop Operation Mode (NMM) Enabled. Note: This bit cannot be active with RS485_AAD operation mode.
[9] | RS485_AAD | RS-485 Auto Address Detection Operation Mode (AAD) 0 = RS-485 Auto Address Detection Operation Mode (AAD) Disabled. 1 = RS-485 Auto Address Detection Operation Mode (AAD) Enabled. Note: This bit cannot be active with RS485_NMM operation mode.
[10] | RS485_AUD | RS-485 Auto Direction Mode (AUD) Control 0 = RS-485 Auto Address Detection Operation Mode (AAD) Disabled. 1 = RS-485 Auto Address Detection Operation Mode (AAD) Enabled. Note: This bit cannot be active with RS485_NMM operation mode.
[15] | RS485_ADD_EN | RS-485 Address Detection Enable Control This bit is used to enable RS-485 Address Detection mode. 0 = RS-485 address detection mode Disabled. 1 = RS-485 address detection mode Enabled. Note: This field is used for RS-485 any operation mode.
[31:24] | ADDR_MATCH | Address Match Value This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode.

Definition at line 9466 of file Mini51Series.h.

## ◆ BAUD

UART_T::BAUD

BAUD

Offset: 0x24 UART Baud Rate Divisor Register

Bits | Field | Descriptions
[15:0] | BRD | Baud Rate Divider The field indicates the baud rate divider.
[27:24] | DIVIDER_X | Divider X The baud rate divider M = X+1.
[28] | DIV_X_ONE | Divider X Equal 1 0 = Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must >= 8). 1 = Divider M = 1 (the equation of M = 1, but BRD [15:0] must >= 8). Refer to section "UART Controller Baud Rate Generator" for more information.
[29] | DIV_X_EN | Divider X Enable Control The BRD = Baud Rate Divider, and the baud rate equation is: Baud Rate = Clock / [M * (BRD + 2)], The default value of M is 16. 0 = Divider X Disabled (the equation of M = 16). 1 = Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must >= 8). Note: When in IrDA mode, this bit must be disabled.

Definition at line 9464 of file Mini51Series.h.

## ◆ FCR

UART_T::FCR

FCR

Offset: 0x08 UART FIFO Control Register

Bits | Field | Descriptions
[1] | RFR | RX Field Software Reset When RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared. 0 = No effect. 1 = The RX internal state machine and pointers reset. Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
[2] | TFR | TX Field Software Reset When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared. 0 = No effect. 1 = The TX internal state machine and pointers reset. Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles.
[7:4] | RFITL | RX FIFO Interrupt (RDA_INT) Trigger Level When the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable, an interrupt will generated). 0000 = RX FIFO Interrupt Trigger Level is 1 byte. 0001 = RX FIFO Interrupt Trigger Level is 4 bytes. 0010 = RX FIFO Interrupt Trigger Level is 8 bytes. 0011 = RX FIFO Interrupt Trigger Level is 14 bytes. Other = Reserved.
[8] | RX_DIS | Receiver Disable Control The receiver is disabled or not (setting 1 to disable the receiver). 0 = Receiver Enabled. 1 = Receiver Disabled. Note1: This field is only used for RS-485 Normal Multi-drop mode. It should be programmed firstly to avoid receiving unknown data before RS-485_NMM (UA_ALT_CSR [8]) is programmed. Note2: After RS-485 receives an address byte in RS-485 Normal Multi-drop mode, this bit (RX_DIS) will be cleared to "0" by hardware.
[19:16] | RTS_TRI_LEV | RTS Trigger Level (For Auto-flow Control Use) 0000 = RTS Trigger Level is 1 byte. 0001 = RTS Trigger Level is 4 bytes. 0010 = RTS Trigger Level is 8 bytes. 0011 = RTS Trigger Level is 14 bytes. Other = Reserved. Note: This field is used for RTS auto-flow control.

Definition at line 9457 of file Mini51Series.h.

## ◆ FSR

UART_T::FSR

FSR

Offset: 0x18 UART FIFO Status Register

Bits | Field | Descriptions
[0] | RX_OVER_IF | RX Overflow Error Interrupt Flag This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes, this bit will be set. 0 = RX FIFO is not overflow. 1 = RX FIFO is overflow. Note: This bit is cleared by writing 1 to it.
[3] | RS485_ADD_DETF | RS-485 Address Byte Detection Flag This bit is set to 1 while RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode and receive detect a data with an address bit (bit 9 = 1). Note1: This field is used for RS-485 function mode. Note2: This bit is cleared by writing 1 to it.
[4] | PEF | Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid "parity bit". 0 = No parity error is generated. 1 = Parity error is generated.Note: This bit is read only, but can be cleared by writing '1' to it .
[5] | FEF | Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit follows the last data bit or parity bit is detected as as logic 0). 0 = No framing error is generated. 1 = Framing error is generated. Note: This bit is read only, but can be cleared by writing '1' to it .
[6] | BIF | Break Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). 0 = No Break interrupt is generated. 1 = Break interrupt is generated. Note: This bit is read only, but software can write 1 to clear it.
[13:8] | RX_POINTER | RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. The Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15.
[14] | RX_EMPTY | Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. 0 = RX FIFO is not empty. 1 = RX FIFO is empty. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
[15] | RX_FULL | Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. 0 = RX FIFO is not full. 1 = RX FIFO is full. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[21:16] | TX_POINTER | TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. The Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15.
[22] | TX_EMPTY | Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO is empty or not. 0 = TX FIFO is not empty. 1 = TX FIFO is empty. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
[23] | TX_FULL | Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. 0 = TX FIFO is not full. 1 = TX FIFO is full. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[24] | TX_OVER_IF | TX Overflow Error Interrupt Flag If TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. 0 = TX FIFO is not overflow. 1 = TX FIFO is overflow. Note: This bit is cleared by writing 1 to it.
[28] | TE_FLAG | Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. 0 = TX FIFO is not empty. 1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.

Definition at line 9461 of file Mini51Series.h.

## ◆ FUN_SEL

UART_T::FUN_SEL

FUN_SEL

Offset: 0x30 UART Function Select Register

Bits | Field | Descriptions
[1:0] | FUN_SEL | Function Selection 00 = UART function mode. 01 = Reserved. 10 = IrDA function mode. 11 = RS-485 function mode.

Definition at line 9467 of file Mini51Series.h.

## ◆ IER

UART_T::IER

IER

Offset: 0x04 UART Interrupt Enable Control Register

Bits | Field | Descriptions
[0] | RDA_IEN | Receive Data Available Interrupt Enable Control 0 = RDA_INT Masked off. 1 = RDA_INT Enabled.
[1] | THRE_IEN | Transmit Holding Register Empty Interrupt Enable Control 0 = THRE_INT Masked off. 1 = THRE_INT Enabled.
[2] | RLS_IEN | Receive Line Status Interrupt Enable Control 0 = RLS_INT Masked off. 1 = RLS_INT Enabled.
[3] | MODEM_IEN | Modem Status Interrupt Enable Control 0 = MODEM_INT Masked off. 1 = MODEM_INT Enabled.
[4] | RTO_IEN | RX Time-out Interrupt Enable Control 0 = TOUT_INT Masked off. 1 = TOUT_INT Enabled.
[5] | BUF_ERR_IEN | Buffer Error Interrupt Enable Control 0 = INT_BUF_ERR Masked Disabled. 1 = INT_BUF_ERR Enabled.
[6] | WAKE_EN | Wake-up CPU Function Enable Control 0 = UART wake-up function Disabled. 1 = UART Wake-up function Enabled. Note: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode.
[11] | TIME_OUT_EN | Time-out Counter Enable Control 0 = Time-out counter Disabled. 1 = Time-out counter Enabled.
[12] | AUTO_RTS_EN | RTS Auto Flow Control Enable Control 0 = RTS auto flow control Disabled. 1 = RTS auto flow control Enabled. Note: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal.
[13] | AUTO_CTS_EN | CTS Auto Flow Control Enable Control 0 = CTS auto flow control Disabled. 1 = CTS auto flow control Enabled. Note: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).

Definition at line 9456 of file Mini51Series.h.

## ◆ IRCR

UART_T::IRCR

IRCR

Offset: 0x28 UART IrDA Control Register

Bits | Field | Descriptions
[1] | TX_SELECT | TX_SELECT 0 = IrDA receiver Enabled. 1 = IrDA transmitter Enabled.
[5] | INV_TX | INV_TX 0 = No inversion. 1 = Inverse TX output signal.
[6] | INV_RX | INV_RX 0 = No inversion. 1 = Inverse RX input signal.

Definition at line 9465 of file Mini51Series.h.

## ◆ ISR

UART_T::ISR

ISR

Offset: 0x1C UART Interrupt Status Register

Bits | Field | Descriptions
[0] | RDA_IF | Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. 0 = No RDA interrupt flag is generated. 1 = RDA interrupt flag is generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
[1] | THRE_IF | Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated. 0 = No THRE interrupt flag is generated. 1 = THRE interrupt flag is generated. Note: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
[2] | RLS_IF | Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated. 0 = No RLS interrupt flag is generated. 1 = RLS interrupt flag is generated. Note1: In RS-485 function mode, this field is set including "receiver detect and received address byte character (bit 9 = 1) bit". At the same time, the bit of RS485_ADD_DETF (UA_FSR[3]) is also set. Note2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS485_ADD_DETF are cleared.
[3] | MODEM_IF | MODEM Interrupt Flag (Read Only) This bit is set when the CTS pin has state change (DCTSF = 1). If UA_IER [MODEM_IEN] is enabled, the Modem interrupt will be generated. 0 = No Modem interrupt flag is generated. 1 = Modem interrupt flag is generated. Note: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
[4] | TOUT_IF | Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RTO_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated. 0 = No Time-out interrupt flag is generated. 1 = Time-out interrupt flag is generated. Note: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
[5] | BUF_ERR_IF | Buffer Error Interrupt Flag (Read Only) This bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set. When BUF_ERR_IF is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated. 0 = No buffer error interrupt flag is generated. 1 = Buffer error interrupt flag is generated. Note: This bit is read only and reset to 0 when all bits of TX_OVER_IF and RX_OVER_IF are cleared.
[8] | RDA_INT | Receive Data Available Interrupt Indicator (Read Only) This bit is set if RDA_IEN and RDA_IF are both set to 1. This bit is set if RDA_IEN and RDA_IF are both set to 1. 0 = No RDA interrupt is generated. 1 = RDA interrupt is generated.
[9] | THRE_INT | Transmit Holding Register Empty Interrupt Indicator (Read Only) This bit is set if THRE_IEN and THRE_IF are both set to 1. 0 = No THRE interrupt is generated. 1 = THRE interrupt is generated.
[10] | RLS_INT | Receive Line Status Interrupt (Read Only) This bit is set if RLS_IEN and RLS_IF are both set to 1. 0 = No RLS interrupt is generated. 1 = RLS interrupt is generated.
[11] | MODEM_INT | MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEM_IEN and MODEM_IF are both set to 1. 0 = No Modem interrupt is generated. 1 = Modem interrupt is generated.
[12] | TOUT_INT | Time-out Interrupt Indicator (Read Only) This bit is set if RTO_IEN and TOUT_IF are both set to 1. 0 = No Time-out interrupt is generated. 1 = Time-out interrupt is generated.
[13] | BUF_ERR_INT | Buffer Error Interrupt Indicator (Read Only) This bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1. 0 = No buffer error interrupt is generated. 1 = buffer error interrupt is generated.

Definition at line 9462 of file Mini51Series.h.

## ◆ LCR

UART_T::LCR

LCR

Offset: 0x0C UART Line Control Register

Bits | Field | Descriptions
[1:0] | WLS | Word Length Selection 00 = Word length is 5-bit. 01 = Word length is 6-bit. 10 = Word length is 7-bit. 11 = Word length is 8-bit.
[2] | NSB | Number Of "STOP Bit" 0 = One "STOP bit" is generated in the transmitted data. 1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
[3] | PBE | Parity Bit Enable Control 0 = No parity bit. 1 = Parity bit is generated on each outgoing character and is checked on each incoming data.
[4] | EPE | Even Parity Enable Control 0 = Odd number of logic 1's is transmitted and checked in each word. 1 = Even number of logic 1's is transmitted and checked in each word. This bit has effect only when PBE (UA_LCR[3]) is set.
[5] | SPE | Stick Parity Enable Control 0 = Stick parity Disabled. 1 = If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1.
[6] | BCB | Break Control Bit When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 0 = Break control Disabled. 1 = Break control Enabled.

Definition at line 9458 of file Mini51Series.h.

## ◆ MCR

UART_T::MCR

MCR

Offset: 0x10 UART Modem Control Register

Bits | Field | Descriptions
[1] | RTS | RTS (Request-to-send) Signal Control This bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration. 0 = RTS signal is active. 1 = RTS signal is inactive. Note1: This RTS signal control bit is not effective when RTS auto-flow control (AUTO_RTS_EN) is enabled in UART function mode. Note2: This RTS signal control bit is not effective when RS-485 auto direction mode (RS485_AUD) is enabled in RS-485 function mode.
[9] | LEV_RTS | RTS Pin Active Level This bit defines the active level state of RTS pin output. 0 = RTS pin output is high level active. 1 = RTS pin output is low level active. Note1: Refer to and UART function mode. Note2: Refer to and for RS-485 function mode.
[13] | RTS_ST | RTS Pin State (Read Only) This bit mirror from RTS pin output of voltage logic status. 0 = RTS pin output is low level voltage logic state. 1 = RTS pin output is high level voltage logic state.

Definition at line 9459 of file Mini51Series.h.

## ◆ MSR

UART_T::MSR

MSR

Offset: 0x14 UART Modem Status Register

Bits | Field | Descriptions
[0] | DCTSF | Detect CTS State Change Flag This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1. 0 = CTS input has not change state. 1 = CTS input has change state. Note: This bit is cleared by writing 1 to it.
[4] | CTS_ST | CTS Pin Status (Read Only) This bit mirror from CTS pin input of voltage logic status. 0 = CTS pin input is low level voltage logic state. 1 = CTS pin input is high level voltage logic state. Note: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected.
[8] | LEV_CTS | CTS Pin Active Level This bit defines the active level state of CTS pin input. 0 = CTS pin input is high level active. 1 = CTS pin input is low level active. Note: Refer to

Definition at line 9460 of file Mini51Series.h.

## ◆ RBR

UART_T::RBR

RBR

Offset: 0x00 UART Receive Buffer Register

Bits | Field | Descriptions
[7:0] | RBR | Receive Buffer Bits (Read Only) By reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first).

Definition at line 9453 of file Mini51Series.h.

## ◆ THR

UART_T::THR

THR

Offset: 0x00 UART Transmit Holding Register

Bits | Field | Descriptions
[7:0] | THR | Transmit Holding Bits By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first).

Definition at line 9454 of file Mini51Series.h.

## ◆ TOR

UART_T::TOR

TOR

Offset: 0x20 UART Time-out Register

Bits | Field | Descriptions
[7:0] | TOIC | Time-out Interrupt Comparator The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (TOUT_INT) is generated if RTO_IEN (UA_IER [4]). A new incoming data word or RX FIFO empty clears TOUT_INT. In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
[15:8] | DLY | TX Delay Time Value This field is used to program the transfer delay time between the last stop bit and next start bit.

Definition at line 9463 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h