| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
GPIO_T Struct Reference

`#include <Mini51Series.h>`

## Data Fields
__IO uint32_t | PMD
__IO uint32_t | OFFD
__IO uint32_t | DOUT
__IO uint32_t | DMASK
__I uint32_t | PIN
__IO uint32_t | DBEN
__IO uint32_t | IMD
__IO uint32_t | IEN
__IO uint32_t | ISRC

## Detailed Description

    @addtogroup GP General Purpose Input/Output Controller(GP)
    Memory Mapped Structure for GP Controller

Definition at line 2971 of file Mini51Series.h.

## Field Documentation

## ◆ DBEN

GPIO_T::DBEN

DBEN

Offset: 0x14 Px De-bounce Enable Control

Bits | Field | Descriptions
[7:0] | DBEN | Port 0-5 Pin [N] Input Signal De-bounce Enable Control DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]. 0 = Px.n de-bounce function Disabled. 1 = Px.n de-bounce function Enabled. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note1: x = 0~5, n = 0~7. Note2: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system woken up caused by the Px.n de-bounce function. Note3: P0_DBEN[3:2] are reserved. P1_DBEN[7:6], [1] are reserved. P2_DBEN[7], [1:0] are reserved. P3_DBEN[7], [3] are reserved. P4_DBEN[5:0] are reserved. P5_DBEN[7:6] are reserved.

Definition at line 3574 of file Mini51Series.h.

## ◆ DMASK

GPIO_T::DMASK

DMASK

Offset: 0x0C Px Data Output Write Mask

Bits | Field | Descriptions
[7:0] | DMASK | Port 0-5 Pin [N] Data Output Write Mask These bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding Px_DOUT[n] bit is protected. If the write signal is masked, writing data to the protect bit is ignored. 0 = Corresponding Px_DOUT[n] bit can be updated. 1 = Corresponding Px_DOUT[n] bit is protected. Note1: x = 0~5, n = 0~7. Note2: This function only protects the corresponding Px_DOUT[n] bit, and will not protect the corresponding Pxn_PDIO bit. Note3: P0_DMASK[3:2] are reserved. P1_DMASK[7:6], [1] are reserved. P2_DMASK[7], [1:0] are reserved. P3_DMASK[7], [3] are reserved. P4_DMASK[5:0] are reserved. P5_DMASK[7:6] are reserved.

Definition at line 3572 of file Mini51Series.h.

## ◆ DOUT

GPIO_T::DOUT

DOUT

Offset: 0x08 Px Data Output Value

Bits | Field | Descriptions
[7:0] | DOUT | Port 0-5 Pin [N] Output Value Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output and Quasi-bidirectional mode. 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. Note1: x = 0~5, n = 0~7. Note2: P0_DOUT[3:2] are reserved. P1_DOUT[7:6], [1] are reserved. P2_DOUT[7], [1:0] are reserved. P3_DOUT[7], [3] are reserved. P4_DOUT[5:0] are reserved. P5_DOUT[7:6] are reserved.

Definition at line 3571 of file Mini51Series.h.

## ◆ IEN

GPIO_T::IEN

IEN

Offset: 0x1C Px Interrupt Enable Control

Bits | Field | Descriptions
[0] | IF_EN | Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the IF_EB[n] bit to 1: If the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at low level. If the interrupt is edge mode trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 0 = Px.n low level or high to low interrupt Disabled. 1 = Px.n low level or high to low interrupt Enabled. Note1: x = 0~5, n = 0~7. Note2: P0_IEN[19:18], [3:2] are reserved. P1_IEN[23:22], [17], [7:6], [1] are reserved. P2_IEN[23], [17:16], [7], [1:0] are reserved. P3_IEN[23], [19], [7], [3] are reserved. P4_IEN[21:16], [5:0] are reserved. P5_IEN[23:22], [7:6] are reserved.
[23:16] | IR_EN | Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High IR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. When setting the IR_EN[n] bit to 1: If the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at high level. If the interrupt is edge trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 0 = Px.n level high or low to high interrupt Disabled. 1 = Px.n level high or low to high interrupt Enabled. Note: x = 0~5, n = 0~7.

Definition at line 3576 of file Mini51Series.h.

## ◆ IMD

GPIO_T::IMD

IMD

Offset: 0x18 Px Interrupt Mode Control

Bits | Field | Descriptions
[7:0] | IMD | Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control IMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. 0 = Edge trigger interrupt. 1 = Level trigger interrupt. If pin is set as the level trigger interrupt, only one level can be set on the registers Px_IEN. If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note1: x = 0~5, n = 0~7. Note2: P0_IMD[3:2] are reserved. P1_IMD[7:6], [1] are reserved. P2_IMD[7], [1:0] are reserved. P3_IMD[7], [3] are reserved. P4_IMD[5:0] are reserved. P5_IMD[7:6] are reserved.

Definition at line 3575 of file Mini51Series.h.

## ◆ ISRC

GPIO_T::ISRC

ISRC

Offset: 0x20 Px Interrupt Source Flag

Bits | Field | Descriptions
[7:0] | ISRC | Port 0-5 Pin [N] Interrupt Source Flag Write : 0 = No action. 1 = Clear the corresponding pending interrupt. Read : 0 = No interrupt at Px.n. 1 = Px.n generates an interrupt. Note1: x = 0~5, n = 0~7. Note2: P0_ISRC[3:2] are reserved. P1_ISRC[7:6], [1] are reserved. P2_ISRC[7], [1:0] are reserved. P3_ISRC[7], [3] are reserved. P4_ISRC[5:0] are reserved. P5_ISRC[7:6] are reserved.

Definition at line 3577 of file Mini51Series.h.

## ◆ OFFD

GPIO_T::OFFD

OFFD

Offset: 0x04 Px Digital Input Path Disable Control

Bits | Field | Descriptions
[23:16] | OFFD | Port 0-5 Pin [N] Digital Input Path Disable Control 0 = Px.n digital input path Enabled. 1 = Px.n digital input path Disabled (digital input tied to low). Note: x = 0~5, n = 0~7.

Definition at line 3570 of file Mini51Series.h.

## ◆ PIN

GPIO_T::PIN

PIN

Offset: 0x10 Px Pin Value

Bits | Field | Descriptions
[7:0] | PIN | Port 0-5 Pin [N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. Note1: x = 0~5, n = 0~7. Note2: P0_PIN[3:2] are reserved. P1_PIN[7:6], [1] are reserved. P2_PIN[7], [1:0] are reserved. P3_PIN[7], [3] are reserved. P4_PIN[5:0] are reserved. P5_PIN[7:6] are reserved.

Definition at line 3573 of file Mini51Series.h.

## ◆ PMD

GPIO_T::PMD

PMD

Offset: 0x00 Px I/O Mode Control

Bits | Field | Descriptions
[1:0] | PMD0 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.
[3:2] | PMD1 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.
[5:4] | PMD2 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.
[7:6] | PMD3 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.
[9:8] | PMD4 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.
[11:10] | PMD5 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.
[13:12] | PMD6 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.
[15:14] | PMD7 | Port 0-5 I/O Pin [N] Mode Control Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). 00 = Px.n is in Input mode. 01 = Px.n is in Push-pull Output mode. 10 = Px.n is in Open-drain Output mode. 11 = Px.n is in Quasi-bidirectional mode. Note1: x = 0~4, n = 0~7. Note2: P0_PMD[7:4] are reserved. P1_PMD[15:12], [3:2] are reserved. P2_PMD[15:14], [3:0] are reserved. P3_PMD[15:14], [7:6] are reserved. P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved.

Definition at line 3569 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h