| MINI51DE_BSP V3.02.004 The Board Support Package for Mini51DE Series MCU

Mini51Series.h
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1/**************************************************************************/
52#ifndef __MINI51SERIES_H__
53#define __MINI51SERIES_H__
54
55#ifdef __cplusplus
56 extern "C" {
57#endif
58
69/******************************************************************************/
70/* Processor and Core Peripherals */
71/******************************************************************************/
80 typedef enum IRQn
81{
82 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
83
84 NonMaskableInt_IRQn = -14,
85 HardFault_IRQn = -13,
86 SVCall_IRQn = -5,
87 PendSV_IRQn = -2,
88 SysTick_IRQn = -1,
90 /****** Mini51 specific Interrupt Numbers ***********************************************/
91
92 BOD_IRQn = 0,
93 WDT_IRQn = 1,
94 EINT0_IRQn = 2,
95 EINT1_IRQn = 3,
96 GPIO01_IRQn = 4,
97 GPIO234_IRQn = 5,
98 PWM_IRQn = 6,
99 FB_IRQn = 7,
100 TMR0_IRQn = 8,
101 TMR1_IRQn = 9,
102 UART_IRQn = 12,
103 SPI_IRQn = 14,
104 GPIO5_IRQn = 16,
105 HIRC_IRQn = 17,
106 I2C_IRQn = 18,
107 ACMP_IRQn = 25,
108 PDWU_IRQn = 28,
109 ADC_IRQn = 29
111} IRQn_Type;
112
113
114/*
115 * ==========================================================================
116 * ----------- Processor and Core Peripheral Section ------------------------
117 * ==========================================================================
118 */
119
120
121/* Configuration of the Cortex-M0 Processor and Core Peripherals */
122#define __CM0_REV 0x0201
123#define __NVIC_PRIO_BITS 2
124#define __Vendor_SysTickConfig 0
125#define __MPU_PRESENT 0
126#define __FPU_PRESENT 0 /* end of group MINI51_CMSIS */
129
130
131#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
132#include "system_Mini51Series.h" /* Mini51 Series System include file */
133#include <stdint.h>
134
135/******************************************************************************/
136/* Device Specific Peripheral registers structures */
137/******************************************************************************/
143#if defined ( __CC_ARM )
144#pragma anon_unions
145#endif
146
147
148
149/*---------------------- Analog Comparator Controller -------------------------*/
156 typedef struct
157{
158
226 __IO uint32_t CMPCR[2]; /* Offset: 0x00 ~0x04 Analog Comparator 0 & 1Control Register */
227 __IO uint32_t CMPSR; /* Offset: 0x08 Analog Comparator 0/1 Status Register */
228 __IO uint32_t CMPRVCR; /* Offset: 0x0C Analog Comparator Reference Voltage Control Register */
229
230} ACMP_T;
231
232
233
239#define ACMP_CMPCR_ACMPEN_Pos (0)
240#define ACMP_CMPCR_ACMPEN_Msk (0x1ul << ACMP_CMPCR_ACMPEN_Pos)
242#define ACMP_CMPCR_ACMPIE_Pos (1)
243#define ACMP_CMPCR_ACMPIE_Msk (0x1ul << ACMP_CMPCR_ACMPIE_Pos)
245#define ACMP_CMPCR_HYSEN_Pos (2)
246#define ACMP_CMPCR_HYSEN_Msk (0x1ul << ACMP_CMPCR_HYSEN_Pos)
248#define ACMP_CMPCR_NEGSEL_Pos (4)
249#define ACMP_CMPCR_NEGSEL_Msk (0x1ul << ACMP_CMPCR_NEGSEL_Pos)
251#define ACMP_CMPCR_RISING_Pos (8)
252#define ACMP_CMPCR_RISING_Msk (0x1ul << ACMP_CMPCR_RISING_Pos)
254#define ACMP_CMPCR_FALLING_Pos (9)
255#define ACMP_CMPCR_FALLING_Msk (0x1ul << ACMP_CMPCR_FALLING_Pos)
257#define ACMP_CMPCR_CPPSEL_Pos (29)
258#define ACMP_CMPCR_CPPSEL_Msk (0x3ul << ACMP_CMPCR_CPPSEL_Pos)
260#define ACMP_CMPSR_ACMPF0_Pos (0)
261#define ACMP_CMPSR_ACMPF0_Msk (0x1ul << ACMP_CMPSR_ACMPF0_Pos)
263#define ACMP_CMPSR_ACMPF1_Pos (1)
264#define ACMP_CMPSR_ACMPF1_Msk (0x1ul << ACMP_CMPSR_ACMPF1_Pos)
266#define ACMP_CMPSR_ACMPCO0_Pos (2)
267#define ACMP_CMPSR_ACMPCO0_Msk (0x1ul << ACMP_CMPSR_ACMPCO0_Pos)
269#define ACMP_CMPSR_ACMPCO1_Pos (3)
270#define ACMP_CMPSR_ACMPCO1_Msk (0x1ul << ACMP_CMPSR_ACMPCO1_Pos)
272#define ACMP_CMPRVCR_CRVS_Pos (0)
273#define ACMP_CMPRVCR_CRVS_Msk (0xful << ACMP_CMPRVCR_CRVS_Pos)
275#define ACMP_CMPRVCR_OUT_SEL_Pos (7)
276#define ACMP_CMPRVCR_OUT_SEL_Msk (0x1ul << ACMP_CMPRVCR_OUT_SEL_Pos) /* ACMP_CONST */ /* end of ACMP register group */
280
281
282/*---------------------- Analog to Digital Converter -------------------------*/
289 typedef struct
290{
471 __I uint32_t ADDR; /* Offset: 0x00 ADC Data Register */
473 __I uint32_t RESERVE0[7];
475 __IO uint32_t ADCR; /* Offset: 0x20 ADC Control Register */
476 __IO uint32_t ADCHER; /* Offset: 0x24 ADC Channel Enable Control Register */
477 __IO uint32_t ADCMPR[2]; /* Offset: 0x28, 0x2C A/D Compare Register 0 & 1 */
478 __IO uint32_t ADSR; /* Offset: 0x30 ADC Status Register */
480 __I uint32_t RESERVE1[4];
482 __IO uint32_t ADTDCR; /* Offset: 0x44 ADC Trigger Delay Control Register */
483 __IO uint32_t ADSAMP; /* Offset: 0x48 ADC Sampling Time Counter Register */
484
485} ADC_T;
486
487
488
494#define ADC_ADDR_RSLT_Pos (0)
495#define ADC_ADDR_RSLT_Msk (0x3fful << ADC_ADDR_RSLT_Pos)
497#define ADC_ADDR_OVERRUN_Pos (16)
498#define ADC_ADDR_OVERRUN_Msk (0x1ul << ADC_ADDR_OVERRUN_Pos)
500#define ADC_ADDR_VALID_Pos (17)
501#define ADC_ADDR_VALID_Msk (0x1ul << ADC_ADDR_VALID_Pos)
503#define ADC_ADCR_ADEN_Pos (0)
504#define ADC_ADCR_ADEN_Msk (0x1ul << ADC_ADCR_ADEN_Pos)
506#define ADC_ADCR_ADIE_Pos (1)
507#define ADC_ADCR_ADIE_Msk (0x1ul << ADC_ADCR_ADIE_Pos)
509#define ADC_ADCR_TRGS_Pos (4)
510#define ADC_ADCR_TRGS_Msk (0x3ul << ADC_ADCR_TRGS_Pos)
512#define ADC_ADCR_TRGCOND_Pos (6)
513#define ADC_ADCR_TRGCOND_Msk (0x1ul << ADC_ADCR_TRGCOND_Pos)
515#define ADC_ADCR_TRGEN_Pos (8)
516#define ADC_ADCR_TRGEN_Msk (0x1ul << ADC_ADCR_TRGEN_Pos)
518#define ADC_ADCR_ADST_Pos (11)
519#define ADC_ADCR_ADST_Msk (0x1ul << ADC_ADCR_ADST_Pos)
521#define ADC_ADCHER_CHEN_Pos (0)
522#define ADC_ADCHER_CHEN_Msk (0xfful << ADC_ADCHER_CHEN_Pos)
524#define ADC_ADCHER_CHEN0_Pos (0)
525#define ADC_ADCHER_CHEN0_Msk (0x1ul << ADC_ADCHER_CHEN0_Pos)
527#define ADC_ADCHER_CHEN1_Pos (1)
528#define ADC_ADCHER_CHEN1_Msk (0x1ul << ADC_ADCHER_CHEN1_Pos)
530#define ADC_ADCHER_CHEN2_Pos (2)
531#define ADC_ADCHER_CHEN2_Msk (0x1ul << ADC_ADCHER_CHEN2_Pos)
533#define ADC_ADCHER_CHEN3_Pos (3)
534#define ADC_ADCHER_CHEN3_Msk (0x1ul << ADC_ADCHER_CHEN3_Pos)
536#define ADC_ADCHER_CHEN4_Pos (4)
537#define ADC_ADCHER_CHEN4_Msk (0x1ul << ADC_ADCHER_CHEN4_Pos)
539#define ADC_ADCHER_CHEN5_Pos (5)
540#define ADC_ADCHER_CHEN5_Msk (0x1ul << ADC_ADCHER_CHEN5_Pos)
542#define ADC_ADCHER_CHEN6_Pos (6)
543#define ADC_ADCHER_CHEN6_Msk (0x1ul << ADC_ADCHER_CHEN6_Pos)
545#define ADC_ADCHER_CHEN7_Pos (7)
546#define ADC_ADCHER_CHEN7_Msk (0x1ul << ADC_ADCHER_CHEN7_Pos)
548#define ADC_ADCHER_PRESEL_Pos (8)
549#define ADC_ADCHER_PRESEL_Msk (0x1ul << ADC_ADCHER_PRESEL_Pos)
551#define ADC_ADCMPR_CMPEN_Pos (0)
552#define ADC_ADCMPR_CMPEN_Msk (0x1ul << ADC_ADCMPR_CMPEN_Pos)
554#define ADC_ADCMPR_CMPIE_Pos (1)
555#define ADC_ADCMPR_CMPIE_Msk (0x1ul << ADC_ADCMPR_CMPIE_Pos)
557#define ADC_ADCMPR_CMPCOND_Pos (2)
558#define ADC_ADCMPR_CMPCOND_Msk (0x1ul << ADC_ADCMPR_CMPCOND_Pos)
560#define ADC_ADCMPR_CMPCH_Pos (3)
561#define ADC_ADCMPR_CMPCH_Msk (0x7ul << ADC_ADCMPR_CMPCH_Pos)
563#define ADC_ADCMPR_CMPMATCNT_Pos (8)
564#define ADC_ADCMPR_CMPMATCNT_Msk (0xful << ADC_ADCMPR_CMPMATCNT_Pos)
566#define ADC_ADCMPR_CMPD_Pos (16)
567#define ADC_ADCMPR_CMPD_Msk (0x3fful << ADC_ADCMPR_CMPD_Pos)
569#define ADC_ADSR_ADF_Pos (0)
570#define ADC_ADSR_ADF_Msk (0x1ul << ADC_ADSR_ADF_Pos)
572#define ADC_ADSR_CMPF0_Pos (1)
573#define ADC_ADSR_CMPF0_Msk (0x1ul << ADC_ADSR_CMPF0_Pos)
575#define ADC_ADSR_CMPF1_Pos (2)
576#define ADC_ADSR_CMPF1_Msk (0x1ul << ADC_ADSR_CMPF1_Pos)
578#define ADC_ADSR_BUSY_Pos (3)
579#define ADC_ADSR_BUSY_Msk (0x1ul << ADC_ADSR_BUSY_Pos)
581#define ADC_ADSR_CHANNEL_Pos (4)
582#define ADC_ADSR_CHANNEL_Msk (0x7ul << ADC_ADSR_CHANNEL_Pos)
584#define ADC_ADSR_VALID_Pos (8)
585#define ADC_ADSR_VALID_Msk (0x1ul << ADC_ADSR_VALID_Pos)
587#define ADC_ADSR_OVERRUN_Pos (16)
588#define ADC_ADSR_OVERRUN_Msk (0x1ul << ADC_ADSR_OVERRUN_Pos)
590#define ADC_ADTDCR_PTDT_Pos (0)
591#define ADC_ADTDCR_PTDT_Msk (0xfful << ADC_ADTDCR_PTDT_Pos)
593#define ADC_ADSAMP_SAMPCNT_Pos (0)
594#define ADC_ADSAMP_SAMPCNT_Msk (0xful << ADC_ADSAMP_SAMPCNT_Pos) /* ADC_CONST */ /* end of ADC register group */
598
599
600/*---------------------- System Clock Controller -------------------------*/
607 typedef struct
608{
609
844 __IO uint32_t PWRCON; /* Offset: 0x00 System Power-down Control Register */
845 __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
846 __IO uint32_t APBCLK; /* Offset: 0x08 APB Devices Clock Enable Control Register */
847 __IO uint32_t CLKSTATUS; /* Offset: 0x0C Clock Status Monitor Register */
848 __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
849 __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
850 __IO uint32_t CLKDIV; /* Offset: 0x18 Clock Divider Number Register */
851 __IO uint32_t CLKSEL2; /* Offset: 0x1C Clock Source Select Control Register 2 */
853 __I uint32_t RESERVE0[1];
855 __IO uint32_t FRQDIV; /* Offset: 0x24 Frequency Divider Control Register */
856
857} CLK_T;
858
859
860
866#define CLK_PWRCON_XTLCLK_EN_Pos (0)
867#define CLK_PWRCON_XTLCLK_EN_Msk (0x3ul << CLK_PWRCON_XTLCLK_EN_Pos)
869#define CLK_PWRCON_OSC22M_EN_Pos (2)
870#define CLK_PWRCON_OSC22M_EN_Msk (0x1ul << CLK_PWRCON_OSC22M_EN_Pos)
871#define CLK_PWRCON_IRC22M_EN_Pos (2)
872#define CLK_PWRCON_IRC22M_EN_Msk (0x1ul << CLK_PWRCON_IRC22M_EN_Pos)
873#define CLK_PWRCON_HIRC_EN_Pos (2)
874#define CLK_PWRCON_HIRC_EN_Msk (0x1ul << CLK_PWRCON_HIRC_EN_Pos)
876#define CLK_PWRCON_OSC10K_EN_Pos (3)
877#define CLK_PWRCON_OSC10K_EN_Msk (0x1ul << CLK_PWRCON_OSC10K_EN_Pos)
878#define CLK_PWRCON_IRC10K_EN_Pos (3)
879#define CLK_PWRCON_IRC10K_EN_Msk (0x1ul << CLK_PWRCON_IRC10K_EN_Pos)
880#define CLK_PWRCON_LIRC_EN_Pos (3)
881#define CLK_PWRCON_LIRC_EN_Msk (0x1ul << CLK_PWRCON_LIRC_EN_Pos)
883#define CLK_PWRCON_WU_DLY_Pos (4)
884#define CLK_PWRCON_WU_DLY_Msk (0x1ul << CLK_PWRCON_WU_DLY_Pos)
886#define CLK_PWRCON_WINT_EN_Pos (5)
887#define CLK_PWRCON_WINT_EN_Msk (0x1ul << CLK_PWRCON_WINT_EN_Pos)
889#define CLK_PWRCON_PD_WU_STS_Pos (6)
890#define CLK_PWRCON_PD_WU_STS_Msk (0x1ul << CLK_PWRCON_PD_WU_STS_Pos)
892#define CLK_PWRCON_PWR_DOWN_EN_Pos (7)
893#define CLK_PWRCON_PWR_DOWN_EN_Msk (0x1ul << CLK_PWRCON_PWR_DOWN_EN_Pos)
895#define CLK_PWRCON_PD_32K_Pos (9)
896#define CLK_PWRCON_PD_32K_Msk (0x1ul << CLK_PWRCON_PD_32K_Pos)
898#define CLK_AHBCLK_ISP_EN_Pos (2)
899#define CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos)
901#define CLK_APBCLK_WDT_EN_Pos (0)
902#define CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos)
904#define CLK_APBCLK_TMR0_EN_Pos (2)
905#define CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos)
907#define CLK_APBCLK_TMR1_EN_Pos (3)
908#define CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos)
910#define CLK_APBCLK_FDIV_EN_Pos (6)
911#define CLK_APBCLK_FDIV_EN_Msk (0x1ul << CLK_APBCLK_FDIV_EN_Pos)
913#define CLK_APBCLK_I2C_EN_Pos (8)
914#define CLK_APBCLK_I2C_EN_Msk (0x1ul << CLK_APBCLK_I2C_EN_Pos)
916#define CLK_APBCLK_SPI_EN_Pos (12)
917#define CLK_APBCLK_SPI_EN_Msk (0x1ul << CLK_APBCLK_SPI_EN_Pos)
919#define CLK_APBCLK_UART_EN_Pos (16)
920#define CLK_APBCLK_UART_EN_Msk (0x1ul << CLK_APBCLK_UART_EN_Pos)
922#define CLK_APBCLK_PWM01_EN_Pos (20)
923#define CLK_APBCLK_PWM01_EN_Msk (0x1ul << CLK_APBCLK_PWM01_EN_Pos)
925#define CLK_APBCLK_PWM23_EN_Pos (21)
926#define CLK_APBCLK_PWM23_EN_Msk (0x1ul << CLK_APBCLK_PWM23_EN_Pos)
928#define CLK_APBCLK_PWM45_EN_Pos (22)
929#define CLK_APBCLK_PWM45_EN_Msk (0x1ul << CLK_APBCLK_PWM45_EN_Pos)
931#define CLK_APBCLK_ADC_EN_Pos (28)
932#define CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos)
934#define CLK_APBCLK_CMP_EN_Pos (30)
935#define CLK_APBCLK_CMP_EN_Msk (0x1ul << CLK_APBCLK_CMP_EN_Pos)
937#define CLK_CLKSTATUS_XTL_STB_Pos (0)
938#define CLK_CLKSTATUS_XTL_STB_Msk (0x1ul << CLK_CLKSTATUS_XTL_STB_Pos)
939#define CLK_CLKSTATUS_HXT_STB_Pos (0)
940#define CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos)
941#define CLK_CLKSTATUS_LXT_STB_Pos (0)
942#define CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos)
944#define CLK_CLKSTATUS_OSC10K_STB_Pos (3)
945#define CLK_CLKSTATUS_OSC10K_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC10K_STB_Pos)
946#define CLK_CLKSTATUS_IRC10K_STB_Pos (3)
947#define CLK_CLKSTATUS_IRC10K_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC10K_STB_Pos)
948#define CLK_CLKSTATUS_LIRC_STB_Pos (3)
949#define CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos)
951#define CLK_CLKSTATUS_OSC22M_STB_Pos (4)
952#define CLK_CLKSTATUS_OSC22M_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC22M_STB_Pos)
953#define CLK_CLKSTATUS_IRC22M_STB_Pos (4)
954#define CLK_CLKSTATUS_IRC22M_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC22M_STB_Pos)
955#define CLK_CLKSTATUS_HIRC_STB_Pos (4)
956#define CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos)
958#define CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7)
959#define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos)
961#define CLK_CLKSEL0_HCLK_S_Pos (0)
962#define CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos)
964#define CLK_CLKSEL0_STCLK_S_Pos (3)
965#define CLK_CLKSEL0_STCLK_S_Msk (0x7ul << CLK_CLKSEL0_STCLK_S_Pos)
967#define CLK_CLKSEL1_WDT_S_Pos (0)
968#define CLK_CLKSEL1_WDT_S_Msk (0x3ul << CLK_CLKSEL1_WDT_S_Pos)
970#define CLK_CLKSEL1_ADC_S_Pos (2)
971#define CLK_CLKSEL1_ADC_S_Msk (0x3ul << CLK_CLKSEL1_ADC_S_Pos)
973#define CLK_CLKSEL1_SPI_S_Pos (4)
974#define CLK_CLKSEL1_SPI_S_Msk (0x1ul << CLK_CLKSEL1_SPI_S_Pos)
976#define CLK_CLKSEL1_TMR0_S_Pos (8)
977#define CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos)
979#define CLK_CLKSEL1_TMR1_S_Pos (12)
980#define CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos)
982#define CLK_CLKSEL1_UART_S_Pos (24)
983#define CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos)
985#define CLK_CLKDIV_HCLK_N_Pos (0)
986#define CLK_CLKDIV_HCLK_N_Msk (0xful << CLK_CLKDIV_HCLK_N_Pos)
988#define CLK_CLKDIV_UART_N_Pos (8)
989#define CLK_CLKDIV_UART_N_Msk (0xful << CLK_CLKDIV_UART_N_Pos)
991#define CLK_CLKDIV_ADC_N_Pos (16)
992#define CLK_CLKDIV_ADC_N_Msk (0xfful << CLK_CLKDIV_ADC_N_Pos)
994#define CLK_CLKSEL2_FRQDIV_S_Pos (2)
995#define CLK_CLKSEL2_FRQDIV_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV_S_Pos)
997#define CLK_FRQDIV_FSEL_Pos (0)
998#define CLK_FRQDIV_FSEL_Msk (0xful << CLK_FRQDIV_FSEL_Pos)
1000#define CLK_FRQDIV_DIVIDER_EN_Pos (4)
1001#define CLK_FRQDIV_DIVIDER_EN_Msk (0x1ul << CLK_FRQDIV_DIVIDER_EN_Pos)
1003#define CLK_FRQDIV_DIVIDER1_Pos (5)
1004#define CLK_FRQDIV_DIVIDER1_Msk (0x1ul << CLK_FRQDIV_DIVIDER1_Pos) /* CLK_CONST */ /* end of CLK register group */
1008
1009
1010/*---------------------- Flash Memory Controller -------------------------*/
1017 typedef struct
1018{
1019
1123 __IO uint32_t ISPCON; /* Offset: 0x00 ISP Control Register */
1124 __IO uint32_t ISPADR; /* Offset: 0x04 ISP Address Register */
1125 __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
1126 __IO uint32_t ISPCMD; /* Offset: 0x0C ISP Command Register */
1127 __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Register */
1128 __I uint32_t DFBADR; /* Offset: 0x14 Data Flash Start Address */
1130 __I uint32_t RESERVE0[10];
1132 __I uint32_t ISPSTA; /* Offset: 0x40 ISP Status Register */
1133
1134} FMC_T;
1135
1136
1137
1143#define FMC_ISPCON_ISPEN_Pos (0)
1144#define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos)
1146#define FMC_ISPCON_BS_Pos (1)
1147#define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos)
1149#define FMC_ISPCON_APUEN_Pos (3)
1150#define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos)
1152#define FMC_ISPCON_CFGUEN_Pos (4)
1153#define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos)
1155#define FMC_ISPCON_LDUEN_Pos (5)
1156#define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos)
1158#define FMC_ISPCON_ISPFF_Pos (6)
1159#define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos)
1161#define FMC_ISPADR_ISPADR_Pos (0)
1162#define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos)
1164#define FMC_ISPDAT_ISPDAT_Pos (0)
1165#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
1167#define FMC_ISPCMD_ISPCMD_Pos (0)
1168#define FMC_ISPCMD_ISPCMD_Msk (0x3ful << FMC_ISPCMD_ISPCMD_Pos)
1170#define FMC_ISPTRG_ISPGO_Pos (0)
1171#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
1173#define FMC_DFBADR_DFBA_Pos (0)
1174#define FMC_DFBADR_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
1176#define FMC_ISPSTA_ISPGO_Pos (0)
1177#define FMC_ISPSTA_ISPGO_Msk (0x1ul << FMC_ISPSTA_ISPGO_Pos)
1179#define FMC_ISPSTA_CBS_Pos (1)
1180#define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos)
1182#define FMC_ISPSTA_ISPFF_Pos (6)
1183#define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos)
1185#define FMC_ISPSTA_VECMAP_Pos (9)
1186#define FMC_ISPSTA_VECMAP_Msk (0xffful << FMC_ISPSTA_VECMAP_Pos) /* FMC_CONST */ /* end of FMC register group */
1190
1191
1192/*---------------------- System Global Control Registers -------------------------*/
1199 typedef struct
1200{
1201
1504 __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
1505 __IO uint32_t RSTSRC; /* Offset: 0x04 System Reset Source Register */
1506 __IO uint32_t IPRSTC1; /* Offset: 0x08 Peripheral Reset Control Resister 1 */
1507 __IO uint32_t IPRSTC2; /* Offset: 0x0C Peripheral Reset Control Resister 2 */
1509 __I uint32_t RESERVE0[2];
1511 __IO uint32_t BODCTL; /* Offset: 0x18 Brown-out Detector Control Register */
1513 __I uint32_t RESERVE1[5];
1515 __IO uint32_t P0_MFP; /* Offset: 0x30 P0 Multiple Function and Input Type Control Register */
1516 __IO uint32_t P1_MFP; /* Offset: 0x34 P1 Multiple Function and Input Type Control Register */
1517 __IO uint32_t P2_MFP; /* Offset: 0x38 P2 Multiple Function and Input Type Control Register */
1518 __IO uint32_t P3_MFP; /* Offset: 0x3C P3 Multiple Function and Input Type Control Register */
1519 __IO uint32_t P4_MFP; /* Offset: 0x40 P4 Multiple Function and Input Type Control Register */
1520 __IO uint32_t P5_MFP; /* Offset: 0x44 P5 Multiple Function and Input Type Control Register */
1522 __I uint32_t RESERVE2[14];
1524 __IO uint32_t IRCTRIMCTL; /* Offset: 0x80 HIRC Trim Control Register */
1525 __IO uint32_t IRCTRIMIER; /* Offset: 0x84 HIRC Trim Interrupt Enable Control Register */
1526 __IO uint32_t IRCTRIMISR; /* Offset: 0x88 HIRC Trim Interrupt Status Register */
1528 __IO uint32_t RESERVE3[29];
1530 __IO uint32_t RegLockAddr; /* Offset: 0x100 Register Write-Protection Control Register */
1531
1532} GCR_T;
1533
1534
1535
1541#define SYS_PDID_PDID_Pos (0)
1542#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
1544#define SYS_RSTSRC_RSTS_POR_Pos (0)
1545#define SYS_RSTSRC_RSTS_POR_Msk (0x1ul << SYS_RSTSRC_RSTS_POR_Pos)
1547#define SYS_RSTSRC_RSTS_RESET_Pos (1)
1548#define SYS_RSTSRC_RSTS_RESET_Msk (0x1ul << SYS_RSTSRC_RSTS_RESET_Pos)
1550#define SYS_RSTSRC_RSTS_WDT_Pos (2)
1551#define SYS_RSTSRC_RSTS_WDT_Msk (0x1ul << SYS_RSTSRC_RSTS_WDT_Pos)
1553#define SYS_RSTSRC_RSTS_BOD_Pos (4)
1554#define SYS_RSTSRC_RSTS_BOD_Msk (0x1ul << SYS_RSTSRC_RSTS_BOD_Pos)
1556#define SYS_RSTSRC_RSTS_MCU_Pos (5)
1557#define SYS_RSTSRC_RSTS_MCU_Msk (0x1ul << SYS_RSTSRC_RSTS_MCU_Pos)
1559#define SYS_RSTSRC_RSTS_CPU_Pos (7)
1560#define SYS_RSTSRC_RSTS_CPU_Msk (0x1ul << SYS_RSTSRC_RSTS_CPU_Pos)
1562#define SYS_IPRSTC1_CHIP_RST_Pos (0)
1563#define SYS_IPRSTC1_CHIP_RST_Msk (0x1ul << SYS_IPRSTC1_CHIP_RST_Pos)
1565#define SYS_IPRSTC1_CPU_RST_Pos (1)
1566#define SYS_IPRSTC1_CPU_RST_Msk (0x1ul << SYS_IPRSTC1_CPU_RST_Pos)
1568#define SYS_IPRSTC2_GPIO_RST_Pos (1)
1569#define SYS_IPRSTC2_GPIO_RST_Msk (0x1ul << SYS_IPRSTC2_GPIO_RST_Pos)
1571#define SYS_IPRSTC2_TMR0_RST_Pos (2)
1572#define SYS_IPRSTC2_TMR0_RST_Msk (0x1ul << SYS_IPRSTC2_TMR0_RST_Pos)
1574#define SYS_IPRSTC2_TMR1_RST_Pos (3)
1575#define SYS_IPRSTC2_TMR1_RST_Msk (0x1ul << SYS_IPRSTC2_TMR1_RST_Pos)
1577#define SYS_IPRSTC2_I2C_RST_Pos (8)
1578#define SYS_IPRSTC2_I2C_RST_Msk (0x1ul << SYS_IPRSTC2_I2C_RST_Pos)
1580#define SYS_IPRSTC2_SPI_RST_Pos (12)
1581#define SYS_IPRSTC2_SPI_RST_Msk (0x1ul << SYS_IPRSTC2_SPI_RST_Pos)
1583#define SYS_IPRSTC2_UART_RST_Pos (16)
1584#define SYS_IPRSTC2_UART_RST_Msk (0x1ul << SYS_IPRSTC2_UART_RST_Pos)
1586#define SYS_IPRSTC2_PWM_RST_Pos (20)
1587#define SYS_IPRSTC2_PWM_RST_Msk (0x1ul << SYS_IPRSTC2_PWM_RST_Pos)
1589#define SYS_IPRSTC2_ACMP_RST_Pos (22)
1590#define SYS_IPRSTC2_ACMP_RST_Msk (0x1ul << SYS_IPRSTC2_ACMP_RST_Pos)
1592#define SYS_IPRSTC2_ADC_RST_Pos (28)
1593#define SYS_IPRSTC2_ADC_RST_Msk (0x1ul << SYS_IPRSTC2_ADC_RST_Pos)
1595#define SYS_BODCR_BOD_VL_EXT_Pos (0)
1596#define SYS_BODCR_BOD_VL_EXT_Msk (0x1ul << SYS_BODCR_BOD_VL_EXT_Pos)
1598#define SYS_BODCR_BOD_VL_Pos (1)
1599#define SYS_BODCR_BOD_VL_Msk (0x3ul << SYS_BODCR_BOD_VL_Pos)
1601#define SYS_BODCR_BOD_RSTEN_Pos (3)
1602#define SYS_BODCR_BOD_RSTEN_Msk (0x1ul << SYS_BODCR_BOD_RSTEN_Pos)
1604#define SYS_BODCR_BOD_INTF_Pos (4)
1605#define SYS_BODCR_BOD_INTF_Msk (0x1ul << SYS_BODCR_BOD_INTF_Pos)
1607#define SYS_BODCR_BOD_LPM_Pos (5)
1608#define SYS_BODCR_BOD_LPM_Msk (0x1ul << SYS_BODCR_BOD_LPM_Pos)
1610#define SYS_BODCR_BOD_OUT_Pos (6)
1611#define SYS_BODCR_BOD_OUT_Msk (0x1ul << SYS_BODCR_BOD_OUT_Pos)
1613#define SYS_P0_MFP_P0_MFP_Pos (0)
1614#define SYS_P0_MFP_P0_MFP_Msk (0xfful << SYS_P0_MFP_P0_MFP_Pos)
1616#define SYS_P0_MFP_P0_ALT_Pos (8)
1617#define SYS_P0_MFP_P0_ALT_Msk (0xfful << SYS_P0_MFP_P0_ALT_Pos)
1619#define SYS_P0_MFP_P0_ALT0_Pos (8)
1620#define SYS_P0_MFP_P0_ALT0_Msk (0x1ul << SYS_P0_MFP_P0_ALT0_Pos)
1622#define SYS_P0_MFP_P0_ALT1_Pos (9)
1623#define SYS_P0_MFP_P0_ALT1_Msk (0x1ul << SYS_P0_MFP_P0_ALT1_Pos)
1625#define SYS_P0_MFP_P0_ALT4_Pos (12)
1626#define SYS_P0_MFP_P0_ALT4_Msk (0x1ul << SYS_P0_MFP_P0_ALT4_Pos)
1628#define SYS_P0_MFP_P0_ALT5_Pos (13)
1629#define SYS_P0_MFP_P0_ALT5_Msk (0x1ul << SYS_P0_MFP_P0_ALT5_Pos)
1631#define SYS_P0_MFP_P0_ALT6_Pos (14)
1632#define SYS_P0_MFP_P0_ALT6_Msk (0x1ul << SYS_P0_MFP_P0_ALT6_Pos)
1634#define SYS_P0_MFP_P0_ALT7_Pos (15)
1635#define SYS_P0_MFP_P0_ALT7_Msk (0x1ul << SYS_P0_MFP_P0_ALT7_Pos)
1637#define SYS_P0_MFP_P0_TYPE_Pos (16)
1638#define SYS_P0_MFP_P0_TYPE_Msk (0xfful << SYS_P0_MFP_P0_TYPE_Pos)
1640#define SYS_P1_MFP_P1_MFP_Pos (0)
1641#define SYS_P1_MFP_P1_MFP_Msk (0xfful << SYS_P1_MFP_P1_MFP_Pos)
1643#define SYS_P1_MFP_P1_ALT_Pos (8)
1644#define SYS_P1_MFP_P1_ALT_Msk (0xfful << SYS_P1_MFP_P1_ALT_Pos)
1646#define SYS_P1_MFP_P1_ALT0_Pos (8)
1647#define SYS_P1_MFP_P1_ALT0_Msk (0x1ul << SYS_P1_MFP_P1_ALT0_Pos)
1649#define SYS_P1_MFP_P1_ALT2_Pos (10)
1650#define SYS_P1_MFP_P1_ALT2_Msk (0x1ul << SYS_P1_MFP_P1_ALT2_Pos)
1652#define SYS_P1_MFP_P1_ALT3_Pos (11)
1653#define SYS_P1_MFP_P1_ALT3_Msk (0x1ul << SYS_P1_MFP_P1_ALT3_Pos)
1655#define SYS_P1_MFP_P1_ALT4_Pos (12)
1656#define SYS_P1_MFP_P1_ALT4_Msk (0x1ul << SYS_P1_MFP_P1_ALT4_Pos)
1658#define SYS_P1_MFP_P1_ALT5_Pos (13)
1659#define SYS_P1_MFP_P1_ALT5_Msk (0x1ul << SYS_P1_MFP_P1_ALT5_Pos)
1661#define SYS_P1_MFP_P1_TYPE_Pos (16)
1662#define SYS_P1_MFP_P1_TYPE_Msk (0xfful << SYS_P1_MFP_P1_TYPE_Pos)
1664#define SYS_P2_MFP_P2_MFP_Pos (0)
1665#define SYS_P2_MFP_P2_MFP_Msk (0xfful << SYS_P2_MFP_P2_MFP_Pos)
1667#define SYS_P2_MFP_P2_ALT_Pos (8)
1668#define SYS_P2_MFP_P2_ALT_Msk (0xfful << SYS_P2_MFP_P2_ALT_Pos)
1670#define SYS_P2_MFP_P2_ALT2_Pos (10)
1671#define SYS_P2_MFP_P2_ALT2_Msk (0x1ul << SYS_P2_MFP_P2_ALT2_Pos)
1673#define SYS_P2_MFP_P2_ALT3_Pos (11)
1674#define SYS_P2_MFP_P2_ALT3_Msk (0x1ul << SYS_P2_MFP_P2_ALT3_Pos)
1676#define SYS_P2_MFP_P2_ALT4_Pos (12)
1677#define SYS_P2_MFP_P2_ALT4_Msk (0x1ul << SYS_P2_MFP_P2_ALT4_Pos)
1679#define SYS_P2_MFP_P2_ALT5_Pos (13)
1680#define SYS_P2_MFP_P2_ALT5_Msk (0x1ul << SYS_P2_MFP_P2_ALT5_Pos)
1682#define SYS_P2_MFP_P2_ALT6_Pos (14)
1683#define SYS_P2_MFP_P2_ALT6_Msk (0x1ul << SYS_P2_MFP_P2_ALT6_Pos)
1685#define SYS_P2_MFP_P2_TYPE_Pos (16)
1686#define SYS_P2_MFP_P2_TYPE_Msk (0xfful << SYS_P2_MFP_P2_TYPE_Pos)
1688#define SYS_P3_MFP_P3_MFP_Pos (0)
1689#define SYS_P3_MFP_P3_MFP_Msk (0xfful << SYS_P3_MFP_P3_MFP_Pos)
1691#define SYS_P3_MFP_P3_ALT_Pos (8)
1692#define SYS_P3_MFP_P3_ALT_Msk (0xfful << SYS_P3_MFP_P3_ALT_Pos)
1694#define SYS_P3_MFP_P3_ALT0_Pos (8)
1695#define SYS_P3_MFP_P3_ALT0_Msk (0x1ul << SYS_P3_MFP_P3_ALT0_Pos)
1697#define SYS_P3_MFP_P3_ALT1_Pos (9)
1698#define SYS_P3_MFP_P3_ALT1_Msk (0x1ul << SYS_P3_MFP_P3_ALT1_Pos)
1700#define SYS_P3_MFP_P3_ALT2_Pos (10)
1701#define SYS_P3_MFP_P3_ALT2_Msk (0x1ul << SYS_P3_MFP_P3_ALT2_Pos)
1703#define SYS_P3_MFP_P3_ALT4_Pos (12)
1704#define SYS_P3_MFP_P3_ALT4_Msk (0x1ul << SYS_P3_MFP_P3_ALT4_Pos)
1706#define SYS_P3_MFP_P3_ALT5_Pos (13)
1707#define SYS_P3_MFP_P3_ALT5_Msk (0x1ul << SYS_P3_MFP_P3_ALT5_Pos)
1709#define SYS_P3_MFP_P3_ALT6_Pos (14)
1710#define SYS_P3_MFP_P3_ALT6_Msk (0x1ul << SYS_P3_MFP_P3_ALT6_Pos)
1712#define SYS_P3_MFP_P3_TYPE_Pos (16)
1713#define SYS_P3_MFP_P3_TYPE_Msk (0xfful << SYS_P3_MFP_P3_TYPE_Pos)
1715#define SYS_P3_MFP_P32CPP1_Pos (24)
1716#define SYS_P3_MFP_P32CPP1_Msk (0x1ul << SYS_P3_MFP_P32CPP1_Pos)
1718#define SYS_P4_MFP_P4_MFP_Pos (0)
1719#define SYS_P4_MFP_P4_MFP_Msk (0xfful << SYS_P4_MFP_P4_MFP_Pos)
1721#define SYS_P4_MFP_P4_ALT_Pos (8)
1722#define SYS_P4_MFP_P4_ALT_Msk (0xfful << SYS_P4_MFP_P4_ALT_Pos)
1724#define SYS_P4_MFP_P4_ALT6_Pos (14)
1725#define SYS_P4_MFP_P4_ALT6_Msk (0x1ul << SYS_P4_MFP_P4_ALT6_Pos)
1727#define SYS_P4_MFP_P4_ALT7_Pos (15)
1728#define SYS_P4_MFP_P4_ALT7_Msk (0x1ul << SYS_P4_MFP_P4_ALT7_Pos)
1730#define SYS_P4_MFP_P4_TYPE_Pos (16)
1731#define SYS_P4_MFP_P4_TYPE_Msk (0xfful << SYS_P4_MFP_P4_TYPE_Pos)
1733#define SYS_P5_MFP_P5_MFP_Pos (0)
1734#define SYS_P5_MFP_P5_MFP_Msk (0xfful << SYS_P5_MFP_P5_MFP_Pos)
1736#define SYS_P5_MFP_P5_ALT_Pos (8)
1737#define SYS_P5_MFP_P5_ALT_Msk (0xFFul << SYS_P5_MFP_P5_ALT_Pos)
1739#define SYS_P5_MFP_P5_ALT0_Pos (8)
1740#define SYS_P5_MFP_P5_ALT0_Msk (0x1ul << SYS_P5_MFP_P5_ALT0_Pos)
1742#define SYS_P5_MFP_P5_ALT1_Pos (9)
1743#define SYS_P5_MFP_P5_ALT1_Msk (0x1ul << SYS_P5_MFP_P5_ALT1_Pos)
1745#define SYS_P5_MFP_P5_ALT2_Pos (10)
1746#define SYS_P5_MFP_P5_ALT2_Msk (0x1ul << SYS_P5_MFP_P5_ALT2_Pos)
1748#define SYS_P5_MFP_P5_ALT3_Pos (11)
1749#define SYS_P5_MFP_P5_ALT3_Msk (0x1ul << SYS_P5_MFP_P5_ALT3_Pos)
1751#define SYS_P5_MFP_P5_ALT4_Pos (12)
1752#define SYS_P5_MFP_P5_ALT4_Msk (0x1ul << SYS_P5_MFP_P5_ALT4_Pos)
1754#define SYS_P5_MFP_P5_ALT5_Pos (13)
1755#define SYS_P5_MFP_P5_ALT5_Msk (0x1ul << SYS_P5_MFP_P5_ALT5_Pos)
1757#define SYS_P5_MFP_P5_TYPE_Pos (16)
1758#define SYS_P5_MFP_P5_TYPE_Msk (0xfful << SYS_P5_MFP_P5_TYPE_Pos)
1760#define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0)
1761#define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x1ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos)
1763#define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4)
1764#define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos)
1766#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1)
1767#define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos)
1769#define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2)
1770#define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos)
1772#define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0)
1773#define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos)
1775#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1)
1776#define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos)
1778#define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2)
1779#define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos)
1781#define SYS_RegLockAddr_RegUnLock_Pos 0
1782#define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) /* GCR_CONST */ /* end of GCR register group */
1786
1787
1788/*---------------------- General Purpose Input/Output Controller -------------------------*/
1795 typedef struct
1796{
1797
2074 __IO uint32_t PMD; /* Offset: 0x00 Px I/O Mode Control */
2075 __IO uint32_t OFFD; /* Offset: 0x04 Px Digital Input Path Disable Control */
2076 __IO uint32_t DOUT; /* Offset: 0x08 Px Data Output Value */
2077 __IO uint32_t DMASK; /* Offset: 0x0C Px Data Output Write Mask */
2078 __I uint32_t PIN; /* Offset: 0x10 Px Pin Value */
2079 __IO uint32_t DBEN; /* Offset: 0x14 Px De-bounce Enable Control */
2080 __IO uint32_t IMD; /* Offset: 0x18 Px Interrupt Mode Control */
2081 __IO uint32_t IEN; /* Offset: 0x1C Px Interrupt Enable Control */
2082 __IO uint32_t ISRC; /* Offset: 0x20 Px Interrupt Source Flag */
2083} GPIO_T;
2084
2088 typedef struct
2089{
2121 __IO uint32_t DBNCECON; /* Offset: 0x00 Interrupt De-bounce Control */
2122} GPIO_DBNCECON_T;
2123
2124
2125
2131#define GPIO_PMD_PMD0_Pos (0)
2132#define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos)
2134#define GPIO_PMD_PMD1_Pos (2)
2135#define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos)
2137#define GPIO_PMD_PMD2_Pos (4)
2138#define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos)
2140#define GPIO_PMD_PMD3_Pos (6)
2141#define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos)
2143#define GPIO_PMD_PMD4_Pos (8)
2144#define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos)
2146#define GPIO_PMD_PMD5_Pos (10)
2147#define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos)
2149#define GPIO_PMD_PMD6_Pos (12)
2150#define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos)
2152#define GPIO_PMD_PMD7_Pos (14)
2153#define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos)
2155#define GPIO_OFFD_OFFD_Pos (16)
2156#define GPIO_OFFD_OFFD_Msk (0xfful << GPIO_OFFD_OFFD_Pos)
2158#define GPIO_DOUT_DOUT_Pos (0)
2159#define GPIO_DOUT_DOUT_Msk (0xfful << GPIO_DOUT_DOUT_Pos)
2161#define GPIO_DMASK_DMASK_Pos (0)
2162#define GPIO_DMASK_DMASK_Msk (0xfful << GPIO_DMASK_DMASK_Pos)
2164#define GPIO_PIN_PIN_Pos (0)
2165#define GPIO_PIN_PIN_Msk (0xfful << GPIO_PIN_PIN_Pos)
2167#define GPIO_DBEN_DBEN_Pos (0)
2168#define GPIO_DBEN_DBEN_Msk (0xfful << GPIO_DBEN_DBEN_Pos)
2170#define GPIO_IMD_IMD_Pos (0)
2171#define GPIO_IMD_IMD_Msk (0xfful << GPIO_IMD_IMD_Pos)
2173#define GPIO_IEN_IF_EN_Pos (0)
2174#define GPIO_IEN_IF_EN_Msk (0x1ul << GPIO_IEN_IF_EN_Pos)
2176#define GPIO_IEN_IR_EN_Pos (16)
2177#define GPIO_IEN_IR_EN_Msk (0xfful << GPIO_IEN_IR_EN_Pos)
2179#define GPIO_ISRC_ISRC_Pos (0)
2180#define GPIO_ISRC_ISRC_Msk (0xfful << GPIO_ISRC_ISRC_Pos)
2182#define GPIO_DBNCECON_DBCLKSEL_Pos (0)
2183#define GPIO_DBNCECON_DBCLKSEL_Msk (0xful << GPIO_DBNCECON_DBCLKSEL_Pos)
2185#define GPIO_DBNCECON_DBCLKSRC_Pos (4)
2186#define GPIO_DBNCECON_DBCLKSRC_Msk (0x1ul << GPIO_DBNCECON_DBCLKSRC_Pos)
2188#define GPIO_DBNCECON_ICLK_ON_Pos (5)
2189#define GPIO_DBNCECON_ICLK_ON_Msk (0x1ul << GPIO_DBNCECON_ICLK_ON_Pos) /* GP_CONST */ /* end of GP register group */
2193
2194
2195/*---------------------- Inter-IC Bus Controller -------------------------*/
2202 typedef struct
2203{
2204
2409 __IO uint32_t I2CON; /* Offset: 0x00 I2C Control Register */
2410 __IO uint32_t I2CADDR0; /* Offset: 0x04 I2C Slave Address Register 0 */
2411 __IO uint32_t I2CDAT; /* Offset: 0x08 I2C DATA Register */
2412 __I uint32_t I2CSTATUS; /* Offset: 0x0C I2C Status Register */
2413 __IO uint32_t I2CLK; /* Offset: 0x10 I2C Clock Divided Register */
2414 __IO uint32_t I2CTOC; /* Offset: 0x14 I2C Time-Out Counter Register */
2415 __IO uint32_t I2CADDR1; /* Offset: 0x18 I2C Slave Address Register 1 */
2416 __IO uint32_t I2CADDR2; /* Offset: 0x1C I2C Slave Address Register 2 */
2417 __IO uint32_t I2CADDR3; /* Offset: 0x20 I2C Slave Address Register 3 */
2418 __IO uint32_t I2CADM0; /* Offset: 0x24 I2C Slave Address Mask Register 0 */
2419 __IO uint32_t I2CADM1; /* Offset: 0x28 I2C Slave Address Mask Register 1 */
2420 __IO uint32_t I2CADM2; /* Offset: 0x2C I2C Slave Address Mask Register 2 */
2421 __IO uint32_t I2CADM3; /* Offset: 0x30 I2C Slave Address Mask Register 3 */
2423 __I uint32_t RESERVE0[2];
2425 __IO uint32_t I2CON2; /* Offset: 0x3C I2C Control Register 2 */
2426 __IO uint32_t I2CSTATUS2; /* Offset: 0x40 I2C Status Register 2 */
2427
2428} I2C_T;
2429
2430
2431
2437#define I2C_I2CON_AA_Pos (2)
2438#define I2C_I2CON_AA_Msk (0x1ul << I2C_I2CON_AA_Pos)
2440#define I2C_I2CON_SI_Pos (3)
2441#define I2C_I2CON_SI_Msk (0x1ul << I2C_I2CON_SI_Pos)
2443#define I2C_I2CON_STO_Pos (4)
2444#define I2C_I2CON_STO_Msk (0x1ul << I2C_I2CON_STO_Pos)
2446#define I2C_I2CON_STA_Pos (5)
2447#define I2C_I2CON_STA_Msk (0x1ul << I2C_I2CON_STA_Pos)
2449#define I2C_I2CON_ENSI_Pos (6)
2450#define I2C_I2CON_ENSI_Msk (0x1ul << I2C_I2CON_ENSI_Pos)
2452#define I2C_I2CON_EI_Pos (7)
2453#define I2C_I2CON_EI_Msk (0x1ul << I2C_I2CON_EI_Pos)
2455#define I2C_I2CADDR_GC_Pos (0)
2456#define I2C_I2CADDR_GC_Msk (0x1ul << I2C_I2CADDR_GC_Pos)
2458#define I2C_I2CADDR_I2CADDR_Pos (1)
2459#define I2C_I2CADDR_I2CADDR_Msk (0x7ful << I2C_I2CADDR_I2CADDR_Pos)
2461#define I2C_I2CDAT_I2CDAT_Pos (0)
2462#define I2C_I2CDAT_I2CDAT_Msk (0xfful << I2C_I2CDAT_I2CDAT_Pos)
2464#define I2C_I2CSTATUS_I2CSTATUS_Pos (0)
2465#define I2C_I2CSTATUS_I2CSTATUS_Msk (0xfful << I2C_I2CSTATUS_I2CSTATUS_Pos)
2467#define I2C_I2CLK_I2CLK_Pos (0)
2468#define I2C_I2CLK_I2CLK_Msk (0xfful << I2C_I2CLK_I2CLK_Pos)
2470#define I2C_I2CTOC_TIF_Pos (0)
2471#define I2C_I2CTOC_TIF_Msk (0x1ul << I2C_I2CTOC_TIF_Pos)
2473#define I2C_I2CTOC_DIV4_Pos (1)
2474#define I2C_I2CTOC_DIV4_Msk (0x1ul << I2C_I2CTOC_DIV4_Pos)
2476#define I2C_I2CTOC_ENTI_Pos (2)
2477#define I2C_I2CTOC_ENTI_Msk (0x1ul << I2C_I2CTOC_ENTI_Pos)
2479#define I2C_I2CADM_I2CADM_Pos (1)
2480#define I2C_I2CADM_I2CADM_Msk (0x7ful << I2C_I2CADM_I2CADM_Pos)
2482#define I2C_I2CON2_WKUPEN_Pos (0)
2483#define I2C_I2CON2_WKUPEN_Msk (0x1ul << I2C_I2CON2_WKUPEN_Pos)
2485#define I2C_I2CON2_TWOFF_EN_Pos (1)
2486#define I2C_I2CON2_TWOFF_EN_Msk (0x1ul << I2C_I2CON2_TWOFF_EN_Pos)
2488#define I2C_I2CON2_NOSTRETCH_Pos (2)
2489#define I2C_I2CON2_NOSTRETCH_Msk (0x1ul << I2C_I2CON2_NOSTRETCH_Pos)
2491#define I2C_I2CON2_OVER_INTEN_Pos (3)
2492#define I2C_I2CON2_OVER_INTEN_Msk (0x1ul << I2C_I2CON2_OVER_INTEN_Pos)
2494#define I2C_I2CON2_UNDER_INTEN_Pos (4)
2495#define I2C_I2CON2_UNDER_INTEN_Msk (0x1ul << I2C_I2CON2_UNDER_INTEN_Pos)
2497#define I2C_I2CSTATUS2_WAKEUP_Pos (0)
2498#define I2C_I2CSTATUS2_WAKEUP_Msk (0x1ul << I2C_I2CSTATUS2_WAKEUP_Pos)
2500#define I2C_I2CSTATUS2_FULL_Pos (1)
2501#define I2C_I2CSTATUS2_FULL_Msk (0x1ul << I2C_I2CSTATUS2_FULL_Pos)
2503#define I2C_I2CSTATUS2_EMPTY_Pos (2)
2504#define I2C_I2CSTATUS2_EMPTY_Msk (0x1ul << I2C_I2CSTATUS2_EMPTY_Pos)
2506#define I2C_I2CSTATUS2_OVERUN_Pos (3)
2507#define I2C_I2CSTATUS2_OVERUN_Msk (0x1ul << I2C_I2CSTATUS2_OVERUN_Pos)
2509#define I2C_I2CSTATUS2_UNDERUN_Pos (4)
2510#define I2C_I2CSTATUS2_UNDERUN_Msk (0x1ul << I2C_I2CSTATUS2_UNDERUN_Pos) /* I2C_CONST */ /* end of I2C register group */
2514
2515
2516/*---------------------- INT Controller -------------------------*/
2524 typedef struct
2525{
2526
2680 __I uint32_t SRC0; /* Offset: 0x00 IRQ0 (BOD) Interrupt Source Identity */
2681 __I uint32_t SRC1; /* Offset: 0x04 IRQ1 (WDT) Interrupt Source Identity */
2682 __I uint32_t SRC2; /* Offset: 0x08 IRQ2 (EINT0) Interrupt Source Identity */
2683 __I uint32_t SRC3; /* Offset: 0x0C IRQ3 (EINT1) Interrupt Source Identity */
2684 __I uint32_t SRC4; /* Offset: 0x10 IRQ4 (GP0/1) Interrupt Source Identity */
2685 __I uint32_t SRC5; /* Offset: 0x14 IRQ5 (GP2/3/4) Interrupt Source Identity */
2686 __I uint32_t SRC6; /* Offset: 0x18 IRQ6 (PWM) Interrupt Source Identity */
2687 __I uint32_t SRC7; /* Offset: 0x1C IRQ7 (BRAKE) Interrupt Source Identity */
2688 __I uint32_t SRC8; /* Offset: 0x20 IRQ8 (TMR0) Interrupt Source Identity */
2689 __I uint32_t SRC9; /* Offset: 0x24 IRQ9 (TMR1) Interrupt Source Identity */
2691 __I uint32_t RESERVED0[2];
2693 __I uint32_t SRC12; /* Offset: 0x30 IRQ12 (UART) Interrupt Source Identity */
2695 __I uint32_t RESERVED1;
2697 __I uint32_t SRC14; /* Offset: 0x38 IRQ14 (SPI) Interrupt Source Identity */
2699 __I uint32_t RESERVED2;
2701 __I uint32_t SRC16; /* Offset: 0x40 IRQ16 (GP5) Interrupt Source Identity */
2702 __I uint32_t SRC17; /* Offset: 0x44 IRQ17 (HIRC trim) Interrupt Source Identity */
2703 __I uint32_t SRC18; /* Offset: 0x48 IRQ18 (I2C) Interrupt Source Identity */
2705 __I uint32_t RESERVED3[6];
2707 __I uint32_t SRC25; /* Offset: 0x64 IRQ25 (ACMP) Interrupt Source Identity */
2709 __I uint32_t RESERVED4[2];
2711 __I uint32_t SRC28; /* Offset: 0x70 IRQ28 (PWRWU) Interrupt Source Identity */
2712 __I uint32_t SRC29; /* Offset: 0x74 IRQ29 (ADC) Interrupt Source Identity */
2714 __I uint32_t RESERVED5[2];
2716 __IO uint32_t NMICON; /* Offset: 0x80 NMI Source Interrupt Select Control Register */
2717 __IO uint32_t MCUIRQ; /* Offset: 0x84 MCU IRQ Number Identity Register */
2718
2719} INT_T;
2720
2721
2722
2728#define INT_SRC_INT_SRC_Pos (0)
2729#define INT_SRC_INT_SRC_Msk (0x7ul << INT_SRC_INT_SRC_Pos)
2731#define INT_CON_NMI_SEL_Pos (0)
2732#define INT_CON_NMI_SEL_Msk (0x1ful << INT_CON_NMI_SEL_Pos)
2734#define INT_CON_NMI_SEL_EN_Pos (8)
2735#define INT_CON_NMI_SEL_EN_Msk (0x1ul << INT_CON_NMI_SEL_EN_Pos)
2737#define INT_IRQ_MCU_IRQ_Pos (0)
2738#define INT_IRQ_MCU_IRQ_Msk (0xfffffffful << INT_IRQ_MCU_IRQ_Pos) /* INT_CONST */ /* end of INT register group */
2742
2743
2744/*---------------------- Pulse Width Modulation Controller -------------------------*/
2751 typedef struct
2752{
2753
3555 __IO uint32_t PPR; /* Offset: 0x00 PWM Pre-scale Register */
3556 __IO uint32_t CSR; /* Offset: 0x04 PWM Clock Select Register */
3557 __IO uint32_t PCR; /* Offset: 0x08 PWM Control Register */
3558 __IO uint32_t CNR[6]; /* Offset: 0x000C ~ 0x0020 PWM Counter Register 0 ~ 5 */
3559 __IO uint32_t CMR[6]; /* Offset: 0x0024 ~ 0x0038 PWM Comparator Register 0 ~ 5 */
3561 __I uint32_t RESERVE0[6];
3563 __IO uint32_t PIER; /* Offset: 0x54 PWM Interrupt Enable Control Register */
3564 __IO uint32_t PIIR; /* Offset: 0x58 PWM Interrupt Indication Register */
3565 __IO uint32_t POE; /* Offset: 0x5C PWM Output Enable for Channel 0~5 */
3566 __IO uint32_t PFBCON; /* Offset: 0x60 PWM Fault Brake Control Register */
3567 __IO uint32_t PDZIR; /* Offset: 0x64 PWM Dead-zone Interval Register */
3568 __IO uint32_t TRGCON0; /* Offset: 0x68 PWM Trigger Control Register 0 */
3569 __IO uint32_t TRGCON1; /* Offset: 0x6C PWM Trigger Control Register 1 */
3570 __IO uint32_t TRGSTS0; /* Offset: 0x70 PWM Trigger Status Register 0 */
3571 __IO uint32_t TRGSTS1; /* Offset: 0x74 PWM Trigger Status Register 1 */
3572 __IO uint32_t PHCHG; /* Offset: 0x78 Phase Change Register */
3573 __IO uint32_t PHCHGNXT; /* Offset: 0x7C Next Phase Change Register */
3574 __IO uint32_t PHCHGMASK; /* Offset: 0x80 Phase Change MASK Register */
3575 __IO uint32_t INTACCUCTL; /* Offset: 0x84 Period Interrupt Accumulation Control Register */
3576
3577} PWM_T;
3578
3579
3580
3586#define PWM_PPR_CP01_Pos (0)
3587#define PWM_PPR_CP01_Msk (0xfful << PWM_PPR_CP01_Pos)
3589#define PWM_PPR_CP23_Pos (8)
3590#define PWM_PPR_CP23_Msk (0xfful << PWM_PPR_CP23_Pos)
3592#define PWM_PPR_CP45_Pos (16)
3593#define PWM_PPR_CP45_Msk (0xfful << PWM_PPR_CP45_Pos)
3595#define PWM_CSR_CSR0_Pos (0)
3596#define PWM_CSR_CSR0_Msk (0x7ul << PWM_CSR_CSR0_Pos)
3598#define PWM_CSR_CSR1_Pos (4)
3599#define PWM_CSR_CSR1_Msk (0x7ul << PWM_CSR_CSR1_Pos)
3601#define PWM_CSR_CSR2_Pos (8)
3602#define PWM_CSR_CSR2_Msk (0x7ul << PWM_CSR_CSR2_Pos)
3604#define PWM_CSR_CSR3_Pos (12)
3605#define PWM_CSR_CSR3_Msk (0x7ul << PWM_CSR_CSR3_Pos)
3607#define PWM_CSR_CSR4_Pos (16)
3608#define PWM_CSR_CSR4_Msk (0x7ul << PWM_CSR_CSR4_Pos)
3610#define PWM_CSR_CSR5_Pos (20)
3611#define PWM_CSR_CSR5_Msk (0x7ul << PWM_CSR_CSR5_Pos)
3613#define PWM_PCR_CH0EN_Pos (0)
3614#define PWM_PCR_CH0EN_Msk (0x1ul << PWM_PCR_CH0EN_Pos)
3616#define PWM_PCR_DB_MOD_Pos (1)
3617#define PWM_PCR_DB_MOD_Msk (0x1ul << PWM_PCR_DB_MOD_Pos)
3619#define PWM_PCR_CH0INV_Pos (2)
3620#define PWM_PCR_CH0INV_Msk (0x1ul << PWM_PCR_CH0INV_Pos)
3622#define PWM_PCR_CH0MOD_Pos (3)
3623#define PWM_PCR_CH0MOD_Msk (0x1ul << PWM_PCR_CH0MOD_Pos)
3625#define PWM_PCR_CH1EN_Pos (4)
3626#define PWM_PCR_CH1EN_Msk (0x1ul << PWM_PCR_CH1EN_Pos)
3628#define PWM_PCR_CH1INV_Pos (6)
3629#define PWM_PCR_CH1INV_Msk (0x1ul << PWM_PCR_CH1INV_Pos)
3631#define PWM_PCR_CH1MOD_Pos (7)
3632#define PWM_PCR_CH1MOD_Msk (0x1ul << PWM_PCR_CH1MOD_Pos)
3634#define PWM_PCR_CH2EN_Pos (8)
3635#define PWM_PCR_CH2EN_Msk (0x1ul << PWM_PCR_CH2EN_Pos)
3637#define PWM_PCR_CH2INV_Pos (10)
3638#define PWM_PCR_CH2INV_Msk (0x1ul << PWM_PCR_CH2INV_Pos)
3640#define PWM_PCR_CH2MOD_Pos (11)
3641#define PWM_PCR_CH2MOD_Msk (0x1ul << PWM_PCR_CH2MOD_Pos)
3643#define PWM_PCR_CH3EN_Pos (12)
3644#define PWM_PCR_CH3EN_Msk (0x1ul << PWM_PCR_CH3EN_Pos)
3646#define PWM_PCR_CH3INV_Pos (14)
3647#define PWM_PCR_CH3INV_Msk (0x1ul << PWM_PCR_CH3INV_Pos)
3649#define PWM_PCR_CH3MOD_Pos (15)
3650#define PWM_PCR_CH3MOD_Msk (0x1ul << PWM_PCR_CH3MOD_Pos)
3652#define PWM_PCR_CH4EN_Pos (16)
3653#define PWM_PCR_CH4EN_Msk (0x1ul << PWM_PCR_CH4EN_Pos)
3655#define PWM_PCR_CH4INV_Pos (18)
3656#define PWM_PCR_CH4INV_Msk (0x1ul << PWM_PCR_CH4INV_Pos)
3658#define PWM_PCR_CH4MOD_Pos (19)
3659#define PWM_PCR_CH4MOD_Msk (0x1ul << PWM_PCR_CH4MOD_Pos)
3661#define PWM_PCR_CH5EN_Pos (20)
3662#define PWM_PCR_CH5EN_Msk (0x1ul << PWM_PCR_CH5EN_Pos)
3664#define PWM_PCR_CH5INV_Pos (22)
3665#define PWM_PCR_CH5INV_Msk (0x1ul << PWM_PCR_CH5INV_Pos)
3667#define PWM_PCR_CH5MOD_Pos (23)
3668#define PWM_PCR_CH5MOD_Msk (0x1ul << PWM_PCR_CH5MOD_Pos)
3670#define PWM_PCR_DZEN01_Pos (24)
3671#define PWM_PCR_DZEN01_Msk (0x1ul << PWM_PCR_DZEN01_Pos)
3673#define PWM_PCR_DZEN23_Pos (25)
3674#define PWM_PCR_DZEN23_Msk (0x1ul << PWM_PCR_DZEN23_Pos)
3676#define PWM_PCR_DZEN45_Pos (26)
3677#define PWM_PCR_DZEN45_Msk (0x1ul << PWM_PCR_DZEN45_Pos)
3679#define PWM_PCR_CLRPWM_Pos (27)
3680#define PWM_PCR_CLRPWM_Msk (0x1ul << PWM_PCR_CLRPWM_Pos)
3682#define PWM_PCR_PWMMOD_Pos (28)
3683#define PWM_PCR_PWMMOD_Msk (0x3ul << PWM_PCR_PWMMOD_Pos)
3685#define PWM_PCR_GRP_Pos (30)
3686#define PWM_PCR_GRP_Msk (0x1ul << PWM_PCR_GRP_Pos)
3688#define PWM_PCR_PWMTYPE_Pos (31)
3689#define PWM_PCR_PWMTYPE_Msk (0x1ul << PWM_PCR_PWMTYPE_Pos)
3691#define PWM_CNR_CNR_Pos 0
3692#define PWM_CNR_CNR_Msk (0xfffful << PWM_CNR_CNR_Pos)
3694#define PWM_CMR_CMR_Pos 0
3695#define PWM_CMR_CMR_Msk (0xfffful << PWM_CMR_CMR_Pos)
3697#define PWM_PIER_PWMPIE0_Pos (0)
3698#define PWM_PIER_PWMPIE0_Msk (0x1ul << PWM_PIER_PWMPIE0_Pos)
3700#define PWM_PIER_PWMPIE1_Pos (1)
3701#define PWM_PIER_PWMPIE1_Msk (0x1ul << PWM_PIER_PWMPIE1_Pos)
3703#define PWM_PIER_PWMPIE2_Pos (2)
3704#define PWM_PIER_PWMPIE2_Msk (0x1ul << PWM_PIER_PWMPIE2_Pos)
3706#define PWM_PIER_PWMPIE3_Pos (3)
3707#define PWM_PIER_PWMPIE3_Msk (0x1ul << PWM_PIER_PWMPIE3_Pos)
3709#define PWM_PIER_PWMPIE4_Pos (4)
3710#define PWM_PIER_PWMPIE4_Msk (0x1ul << PWM_PIER_PWMPIE4_Pos)
3712#define PWM_PIER_PWMPIE5_Pos (5)
3713#define PWM_PIER_PWMPIE5_Msk (0x1ul << PWM_PIER_PWMPIE5_Pos)
3715#define PWM_PIER_PWMDIE0_Pos (8)
3716#define PWM_PIER_PWMDIE0_Msk (0x1ul << PWM_PIER_PWMDIE0_Pos)
3718#define PWM_PIER_PWMDIE1_Pos (9)
3719#define PWM_PIER_PWMDIE1_Msk (0x1ul << PWM_PIER_PWMDIE1_Pos)
3721#define PWM_PIER_PWMDIE2_Pos (10)
3722#define PWM_PIER_PWMDIE2_Msk (0x1ul << PWM_PIER_PWMDIE2_Pos)
3724#define PWM_PIER_PWMDIE3_Pos (11)
3725#define PWM_PIER_PWMDIE3_Msk (0x1ul << PWM_PIER_PWMDIE3_Pos)
3727#define PWM_PIER_PWMDIE4_Pos (12)
3728#define PWM_PIER_PWMDIE4_Msk (0x1ul << PWM_PIER_PWMDIE4_Pos)
3730#define PWM_PIER_PWMDIE5_Pos (13)
3731#define PWM_PIER_PWMDIE5_Msk (0x1ul << PWM_PIER_PWMDIE5_Pos)
3733#define PWM_PIER_BRKIE_Pos (16)
3734#define PWM_PIER_BRKIE_Msk (0x1ul << PWM_PIER_BRKIE_Pos)
3736#define PWM_PIER_INT_TYPE_Pos (17)
3737#define PWM_PIER_INT_TYPE_Msk (0x1ul << PWM_PIER_INT_TYPE_Pos)
3739#define PWM_PIIR_PWMPIF0_Pos (0)
3740#define PWM_PIIR_PWMPIF0_Msk (0x1ul << PWM_PIIR_PWMPIF0_Pos)
3742#define PWM_PIIR_PWMPIF1_Pos (1)
3743#define PWM_PIIR_PWMPIF1_Msk (0x1ul << PWM_PIIR_PWMPIF1_Pos)
3745#define PWM_PIIR_PWMPIF2_Pos (2)
3746#define PWM_PIIR_PWMPIF2_Msk (0x1ul << PWM_PIIR_PWMPIF2_Pos)
3748#define PWM_PIIR_PWMPIF3_Pos (3)
3749#define PWM_PIIR_PWMPIF3_Msk (0x1ul << PWM_PIIR_PWMPIF3_Pos)
3751#define PWM_PIIR_PWMPIF4_Pos (4)
3752#define PWM_PIIR_PWMPIF4_Msk (0x1ul << PWM_PIIR_PWMPIF4_Pos)
3754#define PWM_PIIR_PWMPIF5_Pos (5)
3755#define PWM_PIIR_PWMPIF5_Msk (0x1ul << PWM_PIIR_PWMPIF5_Pos)
3757#define PWM_PIIR_PWMDIF0_Pos (8)
3758#define PWM_PIIR_PWMDIF0_Msk (0x1ul << PWM_PIIR_PWMDIF0_Pos)
3760#define PWM_PIIR_PWMDIF1_Pos (9)
3761#define PWM_PIIR_PWMDIF1_Msk (0x1ul << PWM_PIIR_PWMDIF1_Pos)
3763#define PWM_PIIR_PWMDIF2_Pos (10)
3764#define PWM_PIIR_PWMDIF2_Msk (0x1ul << PWM_PIIR_PWMDIF2_Pos)
3766#define PWM_PIIR_PWMDIF3_Pos (11)
3767#define PWM_PIIR_PWMDIF3_Msk (0x1ul << PWM_PIIR_PWMDIF3_Pos)
3769#define PWM_PIIR_PWMDIF4_Pos (12)
3770#define PWM_PIIR_PWMDIF4_Msk (0x1ul << PWM_PIIR_PWMDIF4_Pos)
3772#define PWM_PIIR_PWMDIF5_Pos (13)
3773#define PWM_PIIR_PWMDIF5_Msk (0x1ul << PWM_PIIR_PWMDIF5_Pos)
3775#define PWM_PIIR_BKF0_Pos (16)
3776#define PWM_PIIR_BKF0_Msk (0x1ul << PWM_PIIR_BKF0_Pos)
3778#define PWM_PIIR_BKF1_Pos (17)
3779#define PWM_PIIR_BKF1_Msk (0x1ul << PWM_PIIR_BKF1_Pos)
3781#define PWM_POE_PWM0_Pos (0)
3782#define PWM_POE_PWM0_Msk (0x1ul << PWM_POE_PWM0_Pos)
3784#define PWM_POE_PWM1_Pos (1)
3785#define PWM_POE_PWM1_Msk (0x1ul << PWM_POE_PWM1_Pos)
3787#define PWM_POE_PWM2_Pos (2)
3788#define PWM_POE_PWM2_Msk (0x1ul << PWM_POE_PWM2_Pos)
3790#define PWM_POE_PWM3_Pos (3)
3791#define PWM_POE_PWM3_Msk (0x1ul << PWM_POE_PWM3_Pos)
3793#define PWM_POE_PWM4_Pos (4)
3794#define PWM_POE_PWM4_Msk (0x1ul << PWM_POE_PWM4_Pos)
3796#define PWM_POE_PWM5_Pos (5)
3797#define PWM_POE_PWM5_Msk (0x1ul << PWM_POE_PWM5_Pos)
3799#define PWM_PFBCON_BKEN0_Pos (0)
3800#define PWM_PFBCON_BKEN0_Msk (0x1ul << PWM_PFBCON_BKEN0_Pos)
3802#define PWM_PFBCON_BKEN1_Pos (1)
3803#define PWM_PFBCON_BKEN1_Msk (0x1ul << PWM_PFBCON_BKEN1_Pos)
3805#define PWM_PFBCON_CPO0BKEN_Pos (2)
3806#define PWM_PFBCON_CPO0BKEN_Msk (0x1ul << PWM_PFBCON_CPO0BKEN_Pos)
3808#define PWM_PFBCON_CPO1BKEN_Pos (3)
3809#define PWM_PFBCON_CPO1BKEN_Msk (0x1ul << PWM_PFBCON_CPO1BKEN_Pos)
3811#define PWM_PFBCON_BKF_Pos (7)
3812#define PWM_PFBCON_BKF_Msk (0x1ul << PWM_PFBCON_BKF_Pos)
3814#define PWM_PFBCON_PWMBKO0_Pos (24)
3815#define PWM_PFBCON_PWMBKO0_Msk (0x1ul << PWM_PFBCON_PWMBKO0_Pos)
3817#define PWM_PFBCON_PWMBKO1_Pos (25)
3818#define PWM_PFBCON_PWMBKO1_Msk (0x1ul << PWM_PFBCON_PWMBKO1_Pos)
3820#define PWM_PFBCON_PWMBKO2_Pos (26)
3821#define PWM_PFBCON_PWMBKO2_Msk (0x1ul << PWM_PFBCON_PWMBKO2_Pos)
3823#define PWM_PFBCON_PWMBKO3_Pos (27)
3824#define PWM_PFBCON_PWMBKO3_Msk (0x1ul << PWM_PFBCON_PWMBKO3_Pos)
3826#define PWM_PFBCON_PWMBKO4_Pos (28)
3827#define PWM_PFBCON_PWMBKO4_Msk (0x1ul << PWM_PFBCON_PWMBKO4_Pos)
3829#define PWM_PFBCON_PWMBKO5_Pos (29)
3830#define PWM_PFBCON_PWMBKO5_Msk (0x1ul << PWM_PFBCON_PWMBKO5_Pos)
3832#define PWM_PFBCON_D6BKO6_Pos (30)
3833#define PWM_PFBCON_D6BKO6_Msk (0x1ul << PWM_PFBCON_D6BKO6_Pos)
3835#define PWM_PFBCON_D7BKO7_Pos (31)
3836#define PWM_PFBCON_D7BKO7_Msk (0x1ul << PWM_PFBCON_D7BKO7_Pos)
3838#define PWM_DZIR_DZI01_Pos (0)
3839#define PWM_DZIR_DZI01_Msk (0xfful << PWM_DZIR_DZI01_Pos)
3841#define PWM_DZIR_DZI23_Pos (8)
3842#define PWM_DZIR_DZI23_Msk (0xfful << PWM_DZIR_DZI23_Pos)
3844#define PWM_DZIR_DZI45_Pos (16)
3845#define PWM_DZIR_DZI45_Msk (0xfful << PWM_DZIR_DZI45_Pos)
3847#define PWM_TRGCON0_CM0TRGREN_Pos (0)
3848#define PWM_TRGCON0_CM0TRGREN_Msk (0x1ul << PWM_TRGCON0_CM0TRGREN_Pos)
3850#define PWM_TRGCON0_CNT0TRGEN_Pos (1)
3851#define PWM_TRGCON0_CNT0TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT0TRGEN_Pos)
3853#define PWM_TRGCON0_CM0TRGFEN_Pos (2)
3854#define PWM_TRGCON0_CM0TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM0TRGFEN_Pos)
3856#define PWM_TRGCON0_P0TRGEN_Pos (3)
3857#define PWM_TRGCON0_P0TRGEN_Msk (0x1ul << PWM_TRGCON0_P0TRGEN_Pos)
3859#define PWM_TRGCON0_CM1TRGREN_Pos (8)
3860#define PWM_TRGCON0_CM1TRGREN_Msk (0x1ul << PWM_TRGCON0_CM1TRGREN_Pos)
3862#define PWM_TRGCON0_CNT1TRGEN_Pos (9)
3863#define PWM_TRGCON0_CNT1TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT1TRGEN_Pos)
3865#define PWM_TRGCON0_CM1TRGFEN_Pos (10)
3866#define PWM_TRGCON0_CM1TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM1TRGFEN_Pos)
3868#define PWM_TRGCON0_P1TRGEN_Pos (11)
3869#define PWM_TRGCON0_P1TRGEN_Msk (0x1ul << PWM_TRGCON0_P1TRGEN_Pos)
3871#define PWM_TRGCON0_CM2TRGREN_Pos (16)
3872#define PWM_TRGCON0_CM2TRGREN_Msk (0x1ul << PWM_TRGCON0_CM2TRGREN_Pos)
3874#define PWM_TRGCON0_CNT2TRGEN_Pos (17)
3875#define PWM_TRGCON0_CNT2TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT2TRGEN_Pos)
3877#define PWM_TRGCON0_CM2TRGFEN_Pos (18)
3878#define PWM_TRGCON0_CM2TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM2TRGFEN_Pos)
3880#define PWM_TRGCON0_P2TRGEN_Pos (19)
3881#define PWM_TRGCON0_P2TRGEN_Msk (0x1ul << PWM_TRGCON0_P2TRGEN_Pos)
3883#define PWM_TRGCON0_CM3TRGREN_Pos (24)
3884#define PWM_TRGCON0_CM3TRGREN_Msk (0x1ul << PWM_TRGCON0_CM3TRGREN_Pos)
3886#define PWM_TRGCON0_CNT3TRGEN_Pos (25)
3887#define PWM_TRGCON0_CNT3TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT3TRGEN_Pos)
3889#define PWM_TRGCON0_CM3TRGFEN_Pos (26)
3890#define PWM_TRGCON0_CM3TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM3TRGFEN_Pos)
3892#define PWM_TRGCON0_P3TRGEN_Pos (27)
3893#define PWM_TRGCON0_P3TRGEN_Msk (0x1ul << PWM_TRGCON0_P3TRGEN_Pos)
3895#define PWM_TRGCON1_CM4TRGREN_Pos (0)
3896#define PWM_TRGCON1_CM4TRGREN_Msk (0x1ul << PWM_TRGCON1_CM4TRGREN_Pos)
3898#define PWM_TRGCON1_CNT4TRGEN_Pos (1)
3899#define PWM_TRGCON1_CNT4TRGEN_Msk (0x1ul << PWM_TRGCON1_CNT4TRGEN_Pos)
3901#define PWM_TRGCON1_CM4TRGFEN_Pos (2)
3902#define PWM_TRGCON1_CM4TRGFEN_Msk (0x1ul << PWM_TRGCON1_CM4TRGFEN_Pos)
3904#define PWM_TRGCON1_P4TRGEN_Pos (3)
3905#define PWM_TRGCON1_P4TRGEN_Msk (0x1ul << PWM_TRGCON1_P4TRGEN_Pos)
3907#define PWM_TRGCON1_CM5TRGREN_Pos (8)
3908#define PWM_TRGCON1_CM5TRGREN_Msk (0x1ul << PWM_TRGCON1_CM5TRGREN_Pos)
3910#define PWM_TRGCON1_CNT5TRGEN_Pos (9)
3911#define PWM_TRGCON1_CNT5TRGEN_Msk (0x1ul << PWM_TRGCON1_CNT5TRGEN_Pos)
3913#define PWM_TRGCON1_CM5TRGFEN_Pos (10)
3914#define PWM_TRGCON1_CM5TRGFEN_Msk (0x1ul << PWM_TRGCON1_CM5TRGFEN_Pos)
3916#define PWM_TRGCON1_P5TRGEN_Pos (11)
3917#define PWM_TRGCON1_P5TRGEN_Msk (0x1ul << PWM_TRGCON1_P5TRGEN_Pos)
3919#define PWM_TRGSTS0_CMR0FLAG_R_Pos (0)
3920#define PWM_TRGSTS0_CMR0FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR0FLAG_R_Pos)
3922#define PWM_TRGSTS0_CNT0FLAG_Pos (1)
3923#define PWM_TRGSTS0_CNT0FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT0FLAG_Pos)
3925#define PWM_TRGSTS0_CMR0FLAG_F_Pos (2)
3926#define PWM_TRGSTS0_CMR0FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR0FLAG_F_Pos)
3928#define PWM_TRGSTS0_PERID0FLAG_Pos (3)
3929#define PWM_TRGSTS0_PERID0FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID0FLAG_Pos)
3931#define PWM_TRGSTS0_CMR1FLAG_R_Pos (8)
3932#define PWM_TRGSTS0_CMR1FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR1FLAG_R_Pos)
3934#define PWM_TRGSTS0_CNT1FLAG_Pos (9)
3935#define PWM_TRGSTS0_CNT1FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT1FLAG_Pos)
3937#define PWM_TRGSTS0_CMR1FLAG_F_Pos (10)
3938#define PWM_TRGSTS0_CMR1FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR1FLAG_F_Pos)
3940#define PWM_TRGSTS0_PERID1FLAG_Pos (11)
3941#define PWM_TRGSTS0_PERID1FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID1FLAG_Pos)
3943#define PWM_TRGSTS0_CMR2FLAG_R_Pos (16)
3944#define PWM_TRGSTS0_CMR2FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR2FLAG_R_Pos)
3946#define PWM_TRGSTS0_CNT2FLAG_Pos (17)
3947#define PWM_TRGSTS0_CNT2FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT2FLAG_Pos)
3949#define PWM_TRGSTS0_CMR2FLAG_F_Pos (18)
3950#define PWM_TRGSTS0_CMR2FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR2FLAG_F_Pos)
3952#define PWM_TRGSTS0_PERID2FLAG_Pos (19)
3953#define PWM_TRGSTS0_PERID2FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID2FLAG_Pos)
3955#define PWM_TRGSTS0_CMR3FLAG_R_Pos (24)
3956#define PWM_TRGSTS0_CMR3FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR3FLAG_R_Pos)
3958#define PWM_TRGSTS0_CNT3FLAG_Pos (25)
3959#define PWM_TRGSTS0_CNT3FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT3FLAG_Pos)
3961#define PWM_TRGSTS0_CMR3FLAG_F_Pos (26)
3962#define PWM_TRGSTS0_CMR3FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR3FLAG_F_Pos)
3964#define PWM_TRGSTS0_PERID3FLAG_Pos (27)
3965#define PWM_TRGSTS0_PERID3FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID3FLAG_Pos)
3967#define PWM_TRGSTS1_CMR4FLAG_R_Pos (0)
3968#define PWM_TRGSTS1_CMR4FLAG_R_Msk (0x1ul << PWM_TRGSTS1_CMR4FLAG_R_Pos)
3970#define PWM_TRGSTS1_CNT4FLAG_Pos (1)
3971#define PWM_TRGSTS1_CNT4FLAG_Msk (0x1ul << PWM_TRGSTS1_CNT4FLAG_Pos)
3973#define PWM_TRGSTS1_CMR4FLAG_F_Pos (2)
3974#define PWM_TRGSTS1_CMR4FLAG_F_Msk (0x1ul << PWM_TRGSTS1_CMR4FLAG_F_Pos)
3976#define PWM_TRGSTS1_PERID4FLAG_Pos (3)
3977#define PWM_TRGSTS1_PERID4FLAG_Msk (0x1ul << PWM_TRGSTS1_PERID4FLAG_Pos)
3979#define PWM_TRGSTS1_CMR5FLAG_R_Pos (8)
3980#define PWM_TRGSTS1_CMR5FLAG_R_Msk (0x1ul << PWM_TRGSTS1_CMR5FLAG_R_Pos)
3982#define PWM_TRGSTS1_CNT5FLAG_Pos (9)
3983#define PWM_TRGSTS1_CNT5FLAG_Msk (0x1ul << PWM_TRGSTS1_CNT5FLAG_Pos)
3985#define PWM_TRGSTS1_CMR5FLAG_F_Pos (10)
3986#define PWM_TRGSTS1_CMR5FLAG_F_Msk (0x1ul << PWM_TRGSTS1_CMR5FLAG_F_Pos)
3988#define PWM_TRGSTS1_PERID5FLAG_Pos (11)
3989#define PWM_TRGSTS1_PERID5FLAG_Msk (0x1ul << PWM_TRGSTS1_PERID5FLAG_Pos)
3991#define PWM_PHCHG_D0_Pos (0)
3992#define PWM_PHCHG_D0_Msk (0x1ul << PWM_PHCHG_D0_Pos)
3994#define PWM_PHCHG_D1_Pos (1)
3995#define PWM_PHCHG_D1_Msk (0x1ul << PWM_PHCHG_D1_Pos)
3997#define PWM_PHCHG_D2_Pos (2)
3998#define PWM_PHCHG_D2_Msk (0x1ul << PWM_PHCHG_D2_Pos)
4000#define PWM_PHCHG_D3_Pos (3)
4001#define PWM_PHCHG_D3_Msk (0x1ul << PWM_PHCHG_D3_Pos)
4003#define PWM_PHCHG_D4_Pos (4)
4004#define PWM_PHCHG_D4_Msk (0x1ul << PWM_PHCHG_D4_Pos)
4006#define PWM_PHCHG_D5_Pos (5)
4007#define PWM_PHCHG_D5_Msk (0x1ul << PWM_PHCHG_D5_Pos)
4009#define PWM_PHCHG_D6_Pos (6)
4010#define PWM_PHCHG_D6_Msk (0x1ul << PWM_PHCHG_D6_Pos)
4012#define PWM_PHCHG_D7_Pos (7)
4013#define PWM_PHCHG_D7_Msk (0x1ul << PWM_PHCHG_D7_Pos)
4015#define PWM_PHCHG_PWM0_Pos (8)
4016#define PWM_PHCHG_PWM0_Msk (0x1ul << PWM_PHCHG_PWM0_Pos)
4018#define PWM_PHCHG_PWM1_Pos (9)
4019#define PWM_PHCHG_PWM1_Msk (0x1ul << PWM_PHCHG_PWM1_Pos)
4021#define PWM_PHCHG_PWM2_Pos (10)
4022#define PWM_PHCHG_PWM2_Msk (0x1ul << PWM_PHCHG_PWM2_Pos)
4024#define PWM_PHCHG_PWM3_Pos (11)
4025#define PWM_PHCHG_PWM3_Msk (0x1ul << PWM_PHCHG_PWM3_Pos)
4027#define PWM_PHCHG_PWM4_Pos (12)
4028#define PWM_PHCHG_PWM4_Msk (0x1ul << PWM_PHCHG_PWM4_Pos)
4030#define PWM_PHCHG_PWM5_Pos (13)
4031#define PWM_PHCHG_PWM5_Msk (0x1ul << PWM_PHCHG_PWM5_Pos)
4033#define PWM_PHCHG_ACCNT0_Pos (14)
4034#define PWM_PHCHG_ACCNT0_Msk (0x1ul << PWM_PHCHG_ACCNT0_Pos)
4036#define PWM_PHCHG_ACCNT1_Pos (15)
4037#define PWM_PHCHG_ACCNT1_Msk (0x1ul << PWM_PHCHG_ACCNT1_Pos)
4039#define PWM_PHCHG_CH01TOFF1_Pos (16)
4040#define PWM_PHCHG_CH01TOFF1_Msk (0x1ul << PWM_PHCHG_CH01TOFF1_Pos)
4042#define PWM_PHCHG_CH11TOFF1_Pos (17)
4043#define PWM_PHCHG_CH11TOFF1_Msk (0x1ul << PWM_PHCHG_CH11TOFF1_Pos)
4045#define PWM_PHCHG_CH21TOFF1_Pos (18)
4046#define PWM_PHCHG_CH21TOFF1_Msk (0x1ul << PWM_PHCHG_CH21TOFF1_Pos)
4048#define PWM_PHCHG_CH31TOFF1_Pos (19)
4049#define PWM_PHCHG_CH31TOFF1_Msk (0x1ul << PWM_PHCHG_CH31TOFF1_Pos)
4051#define PWM_PHCHG_CMP1SEL_Pos (20)
4052#define PWM_PHCHG_CMP1SEL_Msk (0x3ul << PWM_PHCHG_CMP1SEL_Pos)
4054#define PWM_PHCHG_T1_Pos (22)
4055#define PWM_PHCHG_T1_Msk (0x1ul << PWM_PHCHG_T1_Pos)
4057#define PWM_PHCHG_CE1_Pos (23)
4058#define PWM_PHCHG_CE1_Msk (0x1ul << PWM_PHCHG_CE1_Pos)
4060#define PWM_PHCHG_CH01TOFF0_Pos (24)
4061#define PWM_PHCHG_CH01TOFF0_Msk (0x1ul << PWM_PHCHG_CH01TOFF0_Pos)
4063#define PWM_PHCHG_CH11TOFF0_Pos (25)
4064#define PWM_PHCHG_CH11TOFF0_Msk (0x1ul << PWM_PHCHG_CH11TOFF0_Pos)
4066#define PWM_PHCHG_CH21TOFF0_Pos (26)
4067#define PWM_PHCHG_CH21TOFF0_Msk (0x1ul << PWM_PHCHG_CH21TOFF0_Pos)
4069#define PWM_PHCHG_CH31TOFF0_Pos (27)
4070#define PWM_PHCHG_CH31TOFF0_Msk (0x1ul << PWM_PHCHG_CH31TOFF0_Pos)
4072#define PWM_PHCHG_CMP0SEL_Pos (28)
4073#define PWM_PHCHG_CMP0SEL_Msk (0x3ul << PWM_PHCHG_CMP0SEL_Pos)
4075#define PWM_PHCHG_T0_Pos (30)
4076#define PWM_PHCHG_T0_Msk (0x1ul << PWM_PHCHG_T0_Pos)
4078#define PWM_PHCHG_CE0_Pos (31)
4079#define PWM_PHCHG_CE0_Msk (0x1ul << PWM_PHCHG_CE0_Pos)
4081#define PWM_PHCHGNXT_D0_Pos (0)
4082#define PWM_PHCHGNXT_D0_Msk (0x1ul << PWM_PHCHGNXT_D0_Pos)
4084#define PWM_PHCHGNXT_D1_Pos (1)
4085#define PWM_PHCHGNXT_D1_Msk (0x1ul << PWM_PHCHGNXT_D1_Pos)
4087#define PWM_PHCHGNXT_D2_Pos (2)
4088#define PWM_PHCHGNXT_D2_Msk (0x1ul << PWM_PHCHGNXT_D2_Pos)
4090#define PWM_PHCHGNXT_D3_Pos (3)
4091#define PWM_PHCHGNXT_D3_Msk (0x1ul << PWM_PHCHGNXT_D3_Pos)
4093#define PWM_PHCHGNXT_D4_Pos (4)
4094#define PWM_PHCHGNXT_D4_Msk (0x1ul << PWM_PHCHGNXT_D4_Pos)
4096#define PWM_PHCHGNXT_D5_Pos (5)
4097#define PWM_PHCHGNXT_D5_Msk (0x1ul << PWM_PHCHGNXT_D5_Pos)
4099#define PWM_PHCHGNXT_D6_Pos (6)
4100#define PWM_PHCHGNXT_D6_Msk (0x1ul << PWM_PHCHGNXT_D6_Pos)
4102#define PWM_PHCHGNXT_D7_Pos (7)
4103#define PWM_PHCHGNXT_D7_Msk (0x1ul << PWM_PHCHGNXT_D7_Pos)
4105#define PWM_PHCHGNXT_PWM0_Pos (8)
4106#define PWM_PHCHGNXT_PWM0_Msk (0x1ul << PWM_PHCHGNXT_PWM0_Pos)
4108#define PWM_PHCHGNXT_PWM1_Pos (9)
4109#define PWM_PHCHGNXT_PWM1_Msk (0x1ul << PWM_PHCHGNXT_PWM1_Pos)
4111#define PWM_PHCHGNXT_PWM2_Pos (10)
4112#define PWM_PHCHGNXT_PWM2_Msk (0x1ul << PWM_PHCHGNXT_PWM2_Pos)
4114#define PWM_PHCHGNXT_PWM3_Pos (11)
4115#define PWM_PHCHGNXT_PWM3_Msk (0x1ul << PWM_PHCHGNXT_PWM3_Pos)
4117#define PWM_PHCHGNXT_PWM4_Pos (12)
4118#define PWM_PHCHGNXT_PWM4_Msk (0x1ul << PWM_PHCHGNXT_PWM4_Pos)
4120#define PWM_PHCHGNXT_PWM5_Pos (13)
4121#define PWM_PHCHGNXT_PWM5_Msk (0x1ul << PWM_PHCHGNXT_PWM5_Pos)
4123#define PWM_PHCHGNXT_ACCNT0_Pos (14)
4124#define PWM_PHCHGNXT_ACCNT0_Msk (0x1ul << PWM_PHCHGNXT_ACCNT0_Pos)
4126#define PWM_PHCHGNXT_ACCNT1_Pos (15)
4127#define PWM_PHCHGNXT_ACCNT1_Msk (0x1ul << PWM_PHCHGNXT_ACCNT1_Pos)
4129#define PWM_PHCHGNXT_CH01TOFF1_Pos (16)
4130#define PWM_PHCHGNXT_CH01TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH01TOFF1_Pos)
4132#define PWM_PHCHGNXT_CH11TOFF1_Pos (17)
4133#define PWM_PHCHGNXT_CH11TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH11TOFF1_Pos)
4135#define PWM_PHCHGNXT_CH21TOFF1_Pos (18)
4136#define PWM_PHCHGNXT_CH21TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH21TOFF1_Pos)
4138#define PWM_PHCHGNXT_CH31TOFF1_Pos (19)
4139#define PWM_PHCHGNXT_CH31TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH31TOFF1_Pos)
4141#define PWM_PHCHGNXT_CMP1SEL_Pos (20)
4142#define PWM_PHCHGNXT_CMP1SEL_Msk (0x3ul << PWM_PHCHGNXT_CMP1SEL_Pos)
4144#define PWM_PHCHGNXT_T1_Pos (22)
4145#define PWM_PHCHGNXT_T1_Msk (0x1ul << PWM_PHCHGNXT_T1_Pos)
4147#define PWM_PHCHGNXT_CE1_Pos (23)
4148#define PWM_PHCHGNXT_CE1_Msk (0x1ul << PWM_PHCHGNXT_CE1_Pos)
4150#define PWM_PHCHGNXT_CH01TOFF0_Pos (24)
4151#define PWM_PHCHGNXT_CH01TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH01TOFF0_Pos)
4153#define PWM_PHCHGNXT_CH11TOFF0_Pos (25)
4154#define PWM_PHCHGNXT_CH11TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH11TOFF0_Pos)
4156#define PWM_PHCHGNXT_CH21TOFF0_Pos (26)
4157#define PWM_PHCHGNXT_CH21TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH21TOFF0_Pos)
4159#define PWM_PHCHGNXT_CH31TOFF0_Pos (27)
4160#define PWM_PHCHGNXT_CH31TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH31TOFF0_Pos)
4162#define PWM_PHCHGNXT_CMP0SEL_Pos (28)
4163#define PWM_PHCHGNXT_CMP0SEL_Msk (0x3ul << PWM_PHCHGNXT_CMP0SEL_Pos)
4165#define PWM_PHCHGNXT_T0_Pos (30)
4166#define PWM_PHCHGNXT_T0_Msk (0x1ul << PWM_PHCHGNXT_T0_Pos)
4168#define PWM_PHCHGNXT_CE0_Pos (31)
4169#define PWM_PHCHGNXT_CE0_Msk (0x1ul << PWM_PHCHGNXT_CE0_Pos)
4171#define PWM_PHCHGMASK_MASK6_Pos (6)
4172#define PWM_PHCHGMASK_MASK6_Msk (0x1ul << PWM_PHCHGMASK_MASK6_Pos)
4174#define PWM_PHCHGMASK_MASK7_Pos (7)
4175#define PWM_PHCHGMASK_MASK7_Msk (0x1ul << PWM_PHCHGMASK_MASK7_Pos)
4177#define PWM_PHCHGMASK_CMPMASK_Pos (8)
4178#define PWM_PHCHGMASK_CMPMASK_Msk (0x3ul << PWM_PHCHGMASK_CMPMASK_Pos)
4180#define PWM_PHCHGMASK_CMPMASK0_Pos (8)
4181#define PWM_PHCHGMASK_CMPMASK0_Msk (0x1ul << PWM_PHCHGMASK_CMPMASK0_Pos)
4183#define PWM_PHCHGMASK_CMPMASK1_Pos (9)
4184#define PWM_PHCHGMASK_CMPMASK1_Msk (0x1ul << PWM_PHCHGMASK_CMPMASK1_Pos)
4186#define PWM_INTACCUCTL_INTACCUEN0_Pos (0)
4187#define PWM_INTACCUCTL_INTACCUEN0_Msk (0x1ul << PWM_INTACCUCTL_INTACCUEN0_Pos)
4189#define PWM_INTACCUCTL_PERIODCNT_Pos (4)
4190#define PWM_INTACCUCTL_PERIODCNT_Msk (0xful << PWM_INTACCUCTL_PERIODCNT_Pos) /* PWM_CONST */ /* end of PWM register group */
4194
4195
4196/*---------------------- Serial Peripheral Interface Controller -------------------------*/
4203 typedef struct
4204{
4205
4473 __IO uint32_t CNTRL; /* Offset: 0x00 SPI Control and Status Register */
4474 __IO uint32_t DIVIDER; /* Offset: 0x04 SPI Clock Divider Register */
4475 __IO uint32_t SSR; /* Offset: 0x08 SPI Slave Select Register */
4477 __I uint32_t RESERVE0[1];
4479 __I uint32_t RX; /* Offset: 0x10 SPI Data Receive Register */
4481 __I uint32_t RESERVE1[3];
4483 __O uint32_t TX; /* Offset: 0x20 SPI Data Transmit Register */
4485 __I uint32_t RESERVE2[6];
4487 __IO uint32_t CNTRL2; /* Offset: 0x3C SPI Control and Status Register 2 */
4488 __IO uint32_t FIFO_CTL; /* Offset: 0x40 SPI FIFO Control Register */
4489 __IO uint32_t STATUS; /* Offset: 0x44 SPI Status Register */
4490
4491} SPI_T;
4492
4493
4494
4500#define SPI_CNTRL_GO_BUSY_Pos (0)
4501#define SPI_CNTRL_GO_BUSY_Msk (0x1ul << SPI_CNTRL_GO_BUSY_Pos)
4503#define SPI_CNTRL_RX_NEG_Pos (1)
4504#define SPI_CNTRL_RX_NEG_Msk (0x1ul << SPI_CNTRL_RX_NEG_Pos)
4506#define SPI_CNTRL_TX_NEG_Pos (2)
4507#define SPI_CNTRL_TX_NEG_Msk (0x1ul << SPI_CNTRL_TX_NEG_Pos)
4509#define SPI_CNTRL_TX_BIT_LEN_Pos (3)
4510#define SPI_CNTRL_TX_BIT_LEN_Msk (0x1ful << SPI_CNTRL_TX_BIT_LEN_Pos)
4512#define SPI_CNTRL_LSB_Pos (10)
4513#define SPI_CNTRL_LSB_Msk (0x1ul << SPI_CNTRL_LSB_Pos)
4515#define SPI_CNTRL_CLKP_Pos (11)
4516#define SPI_CNTRL_CLKP_Msk (0x1ul << SPI_CNTRL_CLKP_Pos)
4518#define SPI_CNTRL_SP_CYCLE_Pos (12)
4519#define SPI_CNTRL_SP_CYCLE_Msk (0xful << SPI_CNTRL_SP_CYCLE_Pos)
4521#define SPI_CNTRL_IF_Pos (16)
4522#define SPI_CNTRL_IF_Msk (0x1ul << SPI_CNTRL_IF_Pos)
4524#define SPI_CNTRL_IE_Pos (17)
4525#define SPI_CNTRL_IE_Msk (0x1ul << SPI_CNTRL_IE_Pos)
4527#define SPI_CNTRL_SLAVE_Pos (18)
4528#define SPI_CNTRL_SLAVE_Msk (0x1ul << SPI_CNTRL_SLAVE_Pos)
4530#define SPI_CNTRL_REORDER_Pos (19)
4531#define SPI_CNTRL_REORDER_Msk (0x1ul << SPI_CNTRL_REORDER_Pos)
4533#define SPI_CNTRL_FIFO_Pos (21)
4534#define SPI_CNTRL_FIFO_Msk (0x1ul << SPI_CNTRL_FIFO_Pos)
4536#define SPI_CNTRL_RX_EMPTY_Pos (24)
4537#define SPI_CNTRL_RX_EMPTY_Msk (0x1ul << SPI_CNTRL_RX_EMPTY_Pos)
4539#define SPI_CNTRL_RX_FULL_Pos (25)
4540#define SPI_CNTRL_RX_FULL_Msk (0x1ul << SPI_CNTRL_RX_FULL_Pos)
4542#define SPI_CNTRL_TX_EMPTY_Pos (26)
4543#define SPI_CNTRL_TX_EMPTY_Msk (0x1ul << SPI_CNTRL_TX_EMPTY_Pos)
4545#define SPI_CNTRL_TX_FULL_Pos (27)
4546#define SPI_CNTRL_TX_FULL_Msk (0x1ul << SPI_CNTRL_TX_FULL_Pos)
4548#define SPI_DIVIDER_DIVIDER_Pos (0)
4549#define SPI_DIVIDER_DIVIDER_Msk (0xfful << SPI_DIVIDER_DIVIDER_Pos)
4551#define SPI_SSR_SSR_Pos (0)
4552#define SPI_SSR_SSR_Msk (0x1ul << SPI_SSR_SSR_Pos)
4554#define SPI_SSR_SS_LVL_Pos (2)
4555#define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos)
4557#define SPI_SSR_AUTOSS_Pos (3)
4558#define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos)
4560#define SPI_SSR_SS_LTRIG_Pos (4)
4561#define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos)
4563#define SPI_SSR_LTRIG_FLAG_Pos (5)
4564#define SPI_SSR_LTRIG_FLAG_Msk (0x1ul << SPI_SSR_LTRIG_FLAG_Pos)
4566#define SPI_RX_RX_Pos (0)
4567#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos)
4569#define SPI_TX_TX_Pos (0)
4570#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos)
4572#define SPI_CNTRL2_NOSLVSEL_Pos (8)
4573#define SPI_CNTRL2_NOSLVSEL_Msk (0x1ul << SPI_CNTRL2_NOSLVSEL_Pos)
4575#define SPI_CNTRL2_SLV_ABORT_Pos (9)
4576#define SPI_CNTRL2_SLV_ABORT_Msk (0x1ul << SPI_CNTRL2_SLV_ABORT_Pos)
4578#define SPI_CNTRL2_SSTA_INTEN_Pos (10)
4579#define SPI_CNTRL2_SSTA_INTEN_Msk (0x1ul << SPI_CNTRL2_SSTA_INTEN_Pos)
4581#define SPI_CNTRL2_SLV_START_INTSTS_Pos (11)
4582#define SPI_CNTRL2_SLV_START_INTSTS_Msk (0x1ul << SPI_CNTRL2_SLV_START_INTSTS_Pos)
4584#define SPI_CNTRL2_SS_INT_OPT_Pos (16)
4585#define SPI_CNTRL2_SS_INT_OPT_Msk (0x1ul << SPI_CNTRL2_SS_INT_OPT_Pos)
4587#define SPI_CNTRL2_BCn_Pos (31)
4588#define SPI_CNTRL2_BCn_Msk (0x1ul << SPI_CNTRL2_BCn_Pos)
4590#define SPI_FIFO_CTL_RX_CLR_Pos (0)
4591#define SPI_FIFO_CTL_RX_CLR_Msk (0x1ul << SPI_FIFO_CTL_RX_CLR_Pos)
4593#define SPI_FIFO_CTL_TX_CLR_Pos (1)
4594#define SPI_FIFO_CTL_TX_CLR_Msk (0x1ul << SPI_FIFO_CTL_TX_CLR_Pos)
4596#define SPI_FIFO_CTL_RX_INTEN_Pos (2)
4597#define SPI_FIFO_CTL_RX_INTEN_Msk (0x1ul << SPI_FIFO_CTL_RX_INTEN_Pos)
4599#define SPI_FIFO_CTL_TX_INTEN_Pos (3)
4600#define SPI_FIFO_CTL_TX_INTEN_Msk (0x1ul << SPI_FIFO_CTL_TX_INTEN_Pos)
4602#define SPI_FIFO_CTL_RXOV_INTEN_Pos (6)
4603#define SPI_FIFO_CTL_RXOV_INTEN_Msk (0x1ul << SPI_FIFO_CTL_RXOV_INTEN_Pos)
4605#define SPI_FIFO_CTL_TIMEOUT_INTEN_Pos (21)
4606#define SPI_FIFO_CTL_TIMEOUT_INTEN_Msk (0x1ul << SPI_FIFO_CTL_TIMEOUT_INTEN_Pos)
4608#define SPI_FIFO_CTL_RX_THRESHOLD_Pos (24)
4609#define SPI_FIFO_CTL_RX_THRESHOLD_Msk (0x3ul << SPI_FIFO_CTL_RX_THRESHOLD_Pos)
4611#define SPI_FIFO_CTL_TX_THRESHOLD_Pos (28)
4612#define SPI_FIFO_CTL_TX_THRESHOLD_Msk (0x3ul << SPI_FIFO_CTL_TX_THRESHOLD_Pos)
4614#define SPI_STATUS_RX_INTSTS_Pos (0)
4615#define SPI_STATUS_RX_INTSTS_Msk (0x1ul << SPI_STATUS_RX_INTSTS_Pos)
4617#define SPI_STATUS_RX_OVERRUN_Pos (2)
4618#define SPI_STATUS_RX_OVERRUN_Msk (0x1ul << SPI_STATUS_RX_OVERRUN_Pos)
4620#define SPI_STATUS_TX_INTSTS_Pos (4)
4621#define SPI_STATUS_TX_INTSTS_Msk (0x1ul << SPI_STATUS_TX_INTSTS_Pos)
4623#define SPI_STATUS_SLV_START_INTSTS_Pos (11)
4624#define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos)
4626#define SPI_STATUS_RX_FIFO_COUNT_Pos (12)
4627#define SPI_STATUS_RX_FIFO_COUNT_Msk (0xful << SPI_STATUS_RX_FIFO_COUNT_Pos)
4629#define SPI_STATUS_IF_Pos (16)
4630#define SPI_STATUS_IF_Msk (0x1ul << SPI_STATUS_IF_Pos)
4632#define SPI_STATUS_TIMEOUT_Pos (20)
4633#define SPI_STATUS_TIMEOUT_Msk (0x1ul << SPI_STATUS_TIMEOUT_Pos)
4635#define SPI_STATUS_RX_EMPTY_Pos (24)
4636#define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos)
4638#define SPI_STATUS_RX_FULL_Pos (25)
4639#define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos)
4641#define SPI_STATUS_TX_EMPTY_Pos (26)
4642#define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos)
4644#define SPI_STATUS_TX_FULL_Pos (27)
4645#define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos)
4647#define SPI_STATUS_TX_FIFO_COUNT_Pos (28)
4648#define SPI_STATUS_TX_FIFO_COUNT_Msk (0xful << SPI_STATUS_TX_FIFO_COUNT_Pos) /* SPI_CONST */ /* end of SPI register group */
4652
4653
4654/*---------------------- Timer Controller -------------------------*/
4661 typedef struct
4662{
4663
4819 __IO uint32_t TCSR; /* Offset: 0x00 Timer Control and Status Register */
4820 __IO uint32_t TCMPR; /* Offset: 0x04 Timer Compare Register */
4821 __IO uint32_t TISR; /* Offset: 0x08 Timer Interrupt Status Register */
4822 __I uint32_t TDR; /* Offset: 0x0C Timer Data Register */
4823 __I uint32_t TCAP; /* Offset: 0x10 Timer Capture Data Register */
4824 __IO uint32_t TEXCON; /* Offset: 0x14 Timer External Control Register */
4825 __IO uint32_t TEXISR; /* Offset: 0x18 Timer External Interrupt Status Register */
4826} TIMER_T;
4827
4828
4829
4835#define TIMER_TCSR_PRESCALE_Pos (0)
4836#define TIMER_TCSR_PRESCALE_Msk (0xfful << TIMER_TCSR_PRESCALE_Pos)
4838#define TIMER_TCSR_TDR_EN_Pos (16)
4839#define TIMER_TCSR_TDR_EN_Msk (0x1ul << TIMER_TCSR_TDR_EN_Pos)
4841#define TIMER_TCSR_PERIODIC_SEL_Pos (17)
4842#define TIMER_TCSR_PERIODIC_SEL_Msk (0x1ul << TIMER_TCSR_PERIODIC_SEL_Pos)
4844#define TIMER_TCSR_TOGGLE_PIN_Pos (18)
4845#define TIMER_TCSR_TOGGLE_PIN_Msk (0x1ul << TIMER_TCSR_TOGGLE_PIN_Pos)
4847#define TIMER_TCSR_TOUT_PIN_Pos (18)
4848#define TIMER_TCSR_TOUT_PIN_Msk (0x1ul << TIMER_TCSR_TOUT_PIN_Pos)
4850#define TIMER_TCSR_CAP_SRC_Pos (19)
4851#define TIMER_TCSR_CAP_SRC_Msk (0x1ul << TIMER_TCSR_CAP_SRC_Pos)
4853#define TIMER_TCSR_WAKE_EN_Pos (23)
4854#define TIMER_TCSR_WAKE_EN_Msk (0x1ul << TIMER_TCSR_WAKE_EN_Pos)
4856#define TIMER_TCSR_CTB_Pos (24)
4857#define TIMER_TCSR_CTB_Msk (0x1ul << TIMER_TCSR_CTB_Pos)
4859#define TIMER_TCSR_CACT_Pos (25)
4860#define TIMER_TCSR_CACT_Msk (0x1ul << TIMER_TCSR_CACT_Pos)
4862#define TIMER_TCSR_CRST_Pos (26)
4863#define TIMER_TCSR_CRST_Msk (0x1ul << TIMER_TCSR_CRST_Pos)
4865#define TIMER_TCSR_MODE_Pos (27)
4866#define TIMER_TCSR_MODE_Msk (0x3ul << TIMER_TCSR_MODE_Pos)
4868#define TIMER_TCSR_IE_Pos (29)
4869#define TIMER_TCSR_IE_Msk (0x1ul << TIMER_TCSR_IE_Pos)
4871#define TIMER_TCSR_CEN_Pos (30)
4872#define TIMER_TCSR_CEN_Msk (0x1ul << TIMER_TCSR_CEN_Pos)
4874#define TIMER_TCSR_DBGACK_TMR_Pos (31)
4875#define TIMER_TCSR_DBGACK_TMR_Msk (0x1ul << TIMER_TCSR_DBGACK_TMR_Pos)
4877#define TIMER_TCMP_TCMP_Pos (0)
4878#define TIMER_TCMP_TCMP_Msk (0xfffffful << TIMER_TCMP_TCMP_Pos)
4880#define TIMER_TISR_TIF_Pos (0)
4881#define TIMER_TISR_TIF_Msk (0x1ul << TIMER_TISR_TIF_Pos)
4883#define TIMER_TISR_TWF_Pos (1)
4884#define TIMER_TISR_TWF_Msk (0x1ul << TIMER_TISR_TWF_Pos)
4886#define TIMER_TDR_TDR_Pos (0)
4887#define TIMER_TDR_TDR_Msk (0xfffffful << TIMER_TDR_TDR_Pos)
4889#define TIMER_TCAP_TCAP_Pos (0)
4890#define TIMER_TCAP_TCAP_Msk (0xfffffful << TIMER_TCAP_TCAP_Pos)
4892#define TIMER_TEXCON_TX_PHASE_Pos (0)
4893#define TIMER_TEXCON_TX_PHASE_Msk (0x1ul << TIMER_TEXCON_TX_PHASE_Pos)
4895#define TIMER_TEXCON_TEX_EDGE_Pos (1)
4896#define TIMER_TEXCON_TEX_EDGE_Msk (0x3ul << TIMER_TEXCON_TEX_EDGE_Pos)
4898#define TIMER_TEXCON_TEXEN_Pos (3)
4899#define TIMER_TEXCON_TEXEN_Msk (0x1ul << TIMER_TEXCON_TEXEN_Pos)
4901#define TIMER_TEXCON_RSTCAPSEL_Pos (4)
4902#define TIMER_TEXCON_RSTCAPSEL_Msk (0x1ul << TIMER_TEXCON_RSTCAPSEL_Pos)
4904#define TIMER_TEXCON_TEXIEN_Pos (5)
4905#define TIMER_TEXCON_TEXIEN_Msk (0x1ul << TIMER_TEXCON_TEXIEN_Pos)
4907#define TIMER_TEXCON_TEXDB_Pos (6)
4908#define TIMER_TEXCON_TEXDB_Msk (0x1ul << TIMER_TEXCON_TEXDB_Pos)
4910#define TIMER_TEXCON_TCDB_Pos (7)
4911#define TIMER_TEXCON_TCDB_Msk (0x1ul << TIMER_TEXCON_TCDB_Pos)
4913#define TIMER_TEXCON_CAP_MODE_Pos (8)
4914#define TIMER_TEXCON_CAP_MODE_Msk (0x1ul << TIMER_TEXCON_CAP_MODE_Pos)
4916#define TIMER_TEXISR_TEXIF_Pos (0)
4917#define TIMER_TEXISR_TEXIF_Msk (0x1ul << TIMER_TEXISR_TEXIF_Pos) /* TMR_CONST */ /* end of TMR register group */
4921
4922
4923/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
4930 typedef struct
4931{
4932
5319 union
5320 {
5321 __I uint32_t RBR; /* Offset: 0x00 UART Receive Buffer Register */
5322 __O uint32_t THR; /* Offset: 0x00 UART Transmit Holding Register */
5323 };
5324 __IO uint32_t IER; /* Offset: 0x04 UART Interrupt Enable Control Register */
5325 __IO uint32_t FCR; /* Offset: 0x08 UART FIFO Control Register */
5326 __IO uint32_t LCR; /* Offset: 0x0C UART Line Control Register */
5327 __IO uint32_t MCR; /* Offset: 0x10 UART Modem Control Register */
5328 __IO uint32_t MSR; /* Offset: 0x14 UART Modem Status Register */
5329 __IO uint32_t FSR; /* Offset: 0x18 UART FIFO Status Register */
5330 __IO uint32_t ISR; /* Offset: 0x1C UART Interrupt Status Register */
5331 __IO uint32_t TOR; /* Offset: 0x20 UART Time-out Register */
5332 __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
5333 __IO uint32_t IRCR; /* Offset: 0x28 UART IrDA Control Register */
5334 __IO uint32_t ALT_CSR; /* Offset: 0x2C UART Alternate Control/Status Register */
5335 __IO uint32_t FUN_SEL; /* Offset: 0x30 UART Function Select Register */
5336
5337} UART_T;
5338
5339
5340
5346#define UART_RBR_RBR_Pos (0)
5347#define UART_RBR_RBR_Msk (0xfful << UART_RBR_RBR_Pos)
5349#define UART_THR_THR_Pos (0)
5350#define UART_THR_THR_Msk (0xfful << UART_THR_THR_Pos)
5352#define UART_IER_RDA_IEN_Pos (0)
5353#define UART_IER_RDA_IEN_Msk (0x1ul << UART_IER_RDA_IEN_Pos)
5355#define UART_IER_THRE_IEN_Pos (1)
5356#define UART_IER_THRE_IEN_Msk (0x1ul << UART_IER_THRE_IEN_Pos)
5358#define UART_IER_RLS_IEN_Pos (2)
5359#define UART_IER_RLS_IEN_Msk (0x1ul << UART_IER_RLS_IEN_Pos)
5361#define UART_IER_MODEM_IEN_Pos (3)
5362#define UART_IER_MODEM_IEN_Msk (0x1ul << UART_IER_MODEM_IEN_Pos)
5364#define UART_IER_RTO_IEN_Pos (4)
5365#define UART_IER_RTO_IEN_Msk (0x1ul << UART_IER_RTO_IEN_Pos)
5367#define UART_IER_BUF_ERR_IEN_Pos (5)
5368#define UART_IER_BUF_ERR_IEN_Msk (0x1ul << UART_IER_BUF_ERR_IEN_Pos)
5370#define UART_IER_WAKE_EN_Pos (6)
5371#define UART_IER_WAKE_EN_Msk (0x1ul << UART_IER_WAKE_EN_Pos)
5373#define UART_IER_TIME_OUT_EN_Pos (11)
5374#define UART_IER_TIME_OUT_EN_Msk (0x1ul << UART_IER_TIME_OUT_EN_Pos)
5376#define UART_IER_AUTO_RTS_EN_Pos (12)
5377#define UART_IER_AUTO_RTS_EN_Msk (0x1ul << UART_IER_AUTO_RTS_EN_Pos)
5379#define UART_IER_AUTO_CTS_EN_Pos (13)
5380#define UART_IER_AUTO_CTS_EN_Msk (0x1ul << UART_IER_AUTO_CTS_EN_Pos)
5382#define UART_FCR_RFR_Pos (1)
5383#define UART_FCR_RFR_Msk (0x1ul << UART_FCR_RFR_Pos)
5385#define UART_FCR_TFR_Pos (2)
5386#define UART_FCR_TFR_Msk (0x1ul << UART_FCR_TFR_Pos)
5388#define UART_FCR_RFITL_Pos (4)
5389#define UART_FCR_RFITL_Msk (0xful << UART_FCR_RFITL_Pos)
5391#define UART_FCR_RX_DIS_Pos (8)
5392#define UART_FCR_RX_DIS_Msk (0x1ul << UART_FCR_RX_DIS_Pos)
5394#define UART_FCR_RTS_TRI_LEV_Pos (16)
5395#define UART_FCR_RTS_TRI_LEV_Msk (0xful << UART_FCR_RTS_TRI_LEV_Pos)
5397#define UART_LCR_WLS_Pos (0)
5398#define UART_LCR_WLS_Msk (0x3ul << UART_LCR_WLS_Pos)
5400#define UART_LCR_NSB_Pos (2)
5401#define UART_LCR_NSB_Msk (0x1ul << UART_LCR_NSB_Pos)
5403#define UART_LCR_PBE_Pos (3)
5404#define UART_LCR_PBE_Msk (0x1ul << UART_LCR_PBE_Pos)
5406#define UART_LCR_EPE_Pos (4)
5407#define UART_LCR_EPE_Msk (0x1ul << UART_LCR_EPE_Pos)
5409#define UART_LCR_SPE_Pos (5)
5410#define UART_LCR_SPE_Msk (0x1ul << UART_LCR_SPE_Pos)
5412#define UART_LCR_BCB_Pos (6)
5413#define UART_LCR_BCB_Msk (0x1ul << UART_LCR_BCB_Pos)
5415#define UART_MCR_RTS_Pos (1)
5416#define UART_MCR_RTS_Msk (0x1ul << UART_MCR_RTS_Pos)
5418#define UART_MCR_LEV_RTS_Pos (9)
5419#define UART_MCR_LEV_RTS_Msk (0x1ul << UART_MCR_LEV_RTS_Pos)
5421#define UART_MCR_RTS_ST_Pos (13)
5422#define UART_MCR_RTS_ST_Msk (0x1ul << UART_MCR_RTS_ST_Pos)
5424#define UART_MSR_DCTSF_Pos (0)
5425#define UART_MSR_DCTSF_Msk (0x1ul << UART_MSR_DCTSF_Pos)
5427#define UART_MSR_CTS_ST_Pos (4)
5428#define UART_MSR_CTS_ST_Msk (0x1ul << UART_MSR_CTS_ST_Pos)
5430#define UART_MSR_LEV_CTS_Pos (8)
5431#define UART_MSR_LEV_CTS_Msk (0x1ul << UART_MSR_LEV_CTS_Pos)
5433#define UART_FSR_RX_OVER_IF_Pos (0)
5434#define UART_FSR_RX_OVER_IF_Msk (0x1ul << UART_FSR_RX_OVER_IF_Pos)
5436#define UART_FSR_RS485_ADD_DETF_Pos (3)
5437#define UART_FSR_RS485_ADD_DETF_Msk (0x1ul << UART_FSR_RS485_ADD_DETF_Pos)
5439#define UART_FSR_PEF_Pos (4)
5440#define UART_FSR_PEF_Msk (0x1ul << UART_FSR_PEF_Pos)
5442#define UART_FSR_FEF_Pos (5)
5443#define UART_FSR_FEF_Msk (0x1ul << UART_FSR_FEF_Pos)
5445#define UART_FSR_BIF_Pos (6)
5446#define UART_FSR_BIF_Msk (0x1ul << UART_FSR_BIF_Pos)
5448#define UART_FSR_RX_POINTER_Pos (8)
5449#define UART_FSR_RX_POINTER_Msk (0x3ful << UART_FSR_RX_POINTER_Pos)
5451#define UART_FSR_RX_EMPTY_Pos (14)
5452#define UART_FSR_RX_EMPTY_Msk (0x1ul << UART_FSR_RX_EMPTY_Pos)
5454#define UART_FSR_RX_FULL_Pos (15)
5455#define UART_FSR_RX_FULL_Msk (0x1ul << UART_FSR_RX_FULL_Pos)
5457#define UART_FSR_TX_POINTER_Pos (16)
5458#define UART_FSR_TX_POINTER_Msk (0x3ful << UART_FSR_TX_POINTER_Pos)
5460#define UART_FSR_TX_EMPTY_Pos (22)
5461#define UART_FSR_TX_EMPTY_Msk (0x1ul << UART_FSR_TX_EMPTY_Pos)
5463#define UART_FSR_TX_FULL_Pos (23)
5464#define UART_FSR_TX_FULL_Msk (0x1ul << UART_FSR_TX_FULL_Pos)
5466#define UART_FSR_TX_OVER_IF_Pos (24)
5467#define UART_FSR_TX_OVER_IF_Msk (0x1ul << UART_FSR_TX_OVER_IF_Pos)
5469#define UART_FSR_TE_FLAG_Pos (28)
5470#define UART_FSR_TE_FLAG_Msk (0x1ul << UART_FSR_TE_FLAG_Pos)
5472#define UART_ISR_RDA_IF_Pos (0)
5473#define UART_ISR_RDA_IF_Msk (0x1ul << UART_ISR_RDA_IF_Pos)
5475#define UART_ISR_THRE_IF_Pos (1)
5476#define UART_ISR_THRE_IF_Msk (0x1ul << UART_ISR_THRE_IF_Pos)
5478#define UART_ISR_RLS_IF_Pos (2)
5479#define UART_ISR_RLS_IF_Msk (0x1ul << UART_ISR_RLS_IF_Pos)
5481#define UART_ISR_MODEM_IF_Pos (3)
5482#define UART_ISR_MODEM_IF_Msk (0x1ul << UART_ISR_MODEM_IF_Pos)
5484#define UART_ISR_TOUT_IF_Pos (4)
5485#define UART_ISR_TOUT_IF_Msk (0x1ul << UART_ISR_TOUT_IF_Pos)
5487#define UART_ISR_BUF_ERR_IF_Pos (5)
5488#define UART_ISR_BUF_ERR_IF_Msk (0x1ul << UART_ISR_BUF_ERR_IF_Pos)
5490#define UART_ISR_RDA_INT_Pos (8)
5491#define UART_ISR_RDA_INT_Msk (0x1ul << UART_ISR_RDA_INT_Pos)
5493#define UART_ISR_THRE_INT_Pos (9)
5494#define UART_ISR_THRE_INT_Msk (0x1ul << UART_ISR_THRE_INT_Pos)
5496#define UART_ISR_RLS_INT_Pos (10)
5497#define UART_ISR_RLS_INT_Msk (0x1ul << UART_ISR_RLS_INT_Pos)
5499#define UART_ISR_MODEM_INT_Pos (11)
5500#define UART_ISR_MODEM_INT_Msk (0x1ul << UART_ISR_MODEM_INT_Pos)
5502#define UART_ISR_TOUT_INT_Pos (12)
5503#define UART_ISR_TOUT_INT_Msk (0x1ul << UART_ISR_TOUT_INT_Pos)
5505#define UART_ISR_BUF_ERR_INT_Pos (13)
5506#define UART_ISR_BUF_ERR_INT_Msk (0x1ul << UART_ISR_BUF_ERR_INT_Pos)
5508#define UART_TOR_TOIC_Pos (0)
5509#define UART_TOR_TOIC_Msk (0xfful << UART_TOR_TOIC_Pos)
5511#define UART_TOR_DLY_Pos (8)
5512#define UART_TOR_DLY_Msk (0xfful << UART_TOR_DLY_Pos)
5514#define UART_BAUD_BRD_Pos (0)
5515#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
5517#define UART_BAUD_DIVIDER_X_Pos (24)
5518#define UART_BAUD_DIVIDER_X_Msk (0xful << UART_BAUD_DIVIDER_X_Pos)
5520#define UART_BAUD_DIV_X_ONE_Pos (28)
5521#define UART_BAUD_DIV_X_ONE_Msk (0x1ul << UART_BAUD_DIV_X_ONE_Pos)
5523#define UART_BAUD_DIV_X_EN_Pos (29)
5524#define UART_BAUD_DIV_X_EN_Msk (0x1ul << UART_BAUD_DIV_X_EN_Pos)
5526#define UART_IRCR_TX_SELECT_Pos (1)
5527#define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos)
5529#define UART_IRCR_INV_TX_Pos (5)
5530#define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos)
5532#define UART_IRCR_INV_RX_Pos (6)
5533#define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos)
5535#define UART_ALT_CSR_RS485_NMM_Pos (8)
5536#define UART_ALT_CSR_RS485_NMM_Msk (0x1ul << UART_ALT_CSR_RS485_NMM_Pos)
5538#define UART_ALT_CSR_RS485_AAD_Pos (9)
5539#define UART_ALT_CSR_RS485_AAD_Msk (0x1ul << UART_ALT_CSR_RS485_AAD_Pos)
5541#define UART_ALT_CSR_RS485_AUD_Pos (10)
5542#define UART_ALT_CSR_RS485_AUD_Msk (0x1ul << UART_ALT_CSR_RS485_AUD_Pos)
5544#define UART_ALT_CSR_RS485_ADD_EN_Pos (15)
5545#define UART_ALT_CSR_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CSR_RS485_ADD_EN_Pos)
5547#define UART_ALT_CSR_ADDR_MATCH_Pos (24)
5548#define UART_ALT_CSR_ADDR_MATCH_Msk (0xfful << UART_ALT_CSR_ADDR_MATCH_Pos)
5550#define UART_FUN_SEL_FUN_SEL_Pos (0)
5551#define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /* UART_CONST */ /* end of UART register group */
5555
5556
5557/*---------------------- Watch Dog Timer Controller -------------------------*/
5564 typedef struct
5565{
5566
5625 __IO uint32_t WTCR; /* Offset: 0x00 Watchdog Timer Control Register */
5626
5627} WDT_T;
5628
5629
5630
5636#define WDT_WTCR_WTR_Pos (0)
5637#define WDT_WTCR_WTR_Msk (0x1ul << WDT_WTCR_WTR_Pos)
5639#define WDT_WTCR_WTRE_Pos (1)
5640#define WDT_WTCR_WTRE_Msk (0x1ul << WDT_WTCR_WTRE_Pos)
5642#define WDT_WTCR_WTRF_Pos (2)
5643#define WDT_WTCR_WTRF_Msk (0x1ul << WDT_WTCR_WTRF_Pos)
5645#define WDT_WTCR_WTIF_Pos (3)
5646#define WDT_WTCR_WTIF_Msk (0x1ul << WDT_WTCR_WTIF_Pos)
5648#define WDT_WTCR_WTWKE_Pos (4)
5649#define WDT_WTCR_WTWKE_Msk (0x1ul << WDT_WTCR_WTWKE_Pos)
5651#define WDT_WTCR_WTWKF_Pos (5)
5652#define WDT_WTCR_WTWKF_Msk (0x1ul << WDT_WTCR_WTWKF_Pos)
5654#define WDT_WTCR_WTIE_Pos (6)
5655#define WDT_WTCR_WTIE_Msk (0x1ul << WDT_WTCR_WTIE_Pos)
5657#define WDT_WTCR_WTE_Pos (7)
5658#define WDT_WTCR_WTE_Msk (0x1ul << WDT_WTCR_WTE_Pos)
5660#define WDT_WTCR_WTIS_Pos (8)
5661#define WDT_WTCR_WTIS_Msk (0x7ul << WDT_WTCR_WTIS_Pos)
5663#define WDT_WTCR_DBGACK_WDT_Pos (31)
5664#define WDT_WTCR_DBGACK_WDT_Msk (0x1ul << WDT_WTCR_DBGACK_WDT_Pos) /* WDT_CONST */ /* end of WDT register group */
5668
5669
5670#if defined ( __CC_ARM )
5671#pragma no_anon_unions
5672#endif
5673
5678/* Peripheral and SRAM base address */
5679#define FLASH_BASE ((uint32_t)0x00000000)
5680#define SRAM_BASE ((uint32_t)0x20000000)
5681#define APB1PERIPH_BASE ((uint32_t)0x40000000)
5682#define APB2PERIPH_BASE ((uint32_t)0x40100000)
5683#define AHBPERIPH_BASE ((uint32_t)0x50000000)
5684
5685/* Peripheral memory map */
5686#define WDT_BASE (APB1PERIPH_BASE + 0x04000)
5687#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
5688#define TIMER1_BASE (APB1PERIPH_BASE + 0x10020)
5689#define I2C_BASE (APB1PERIPH_BASE + 0x20000)
5690#define SPI_BASE (APB1PERIPH_BASE + 0x30000)
5691#define PWM_BASE (APB1PERIPH_BASE + 0x40000)
5692#define UART_BASE (APB1PERIPH_BASE + 0x50000)
5693#define ACMP_BASE (APB1PERIPH_BASE + 0xD0000)
5694#define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
5695
5696#define GCR_BASE (AHBPERIPH_BASE + 0x00000)
5697#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
5698#define INT_BASE (AHBPERIPH_BASE + 0x00300)
5699#define P0_BASE (AHBPERIPH_BASE + 0x04000)
5700#define P1_BASE (AHBPERIPH_BASE + 0x04040)
5701#define P2_BASE (AHBPERIPH_BASE + 0x04080)
5702#define P3_BASE (AHBPERIPH_BASE + 0x040C0)
5703#define P4_BASE (AHBPERIPH_BASE + 0x04100)
5704#define P5_BASE (AHBPERIPH_BASE + 0x04140)
5705#define GPIO_DBNCECON_BASE (AHBPERIPH_BASE + 0x04180)
5706#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
5707#define GPIOBIT0_BASE (AHBPERIPH_BASE + 0x04200)
5708#define GPIOBIT1_BASE (AHBPERIPH_BASE + 0x04220)
5709#define GPIOBIT2_BASE (AHBPERIPH_BASE + 0x04240)
5710#define GPIOBIT3_BASE (AHBPERIPH_BASE + 0x04260)
5711#define GPIOBIT4_BASE (AHBPERIPH_BASE + 0x04280)
5712#define GPIOBIT5_BASE (AHBPERIPH_BASE + 0x042A0)
5713#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
5714 /* end of group MINI51_PERIPHERAL_MEM_MAP */
5716
5717
5722#define WDT ((WDT_T *) WDT_BASE)
5723#define TIMER0 ((TIMER_T *) TIMER0_BASE)
5724#define TIMER1 ((TIMER_T *) TIMER1_BASE)
5725#define I2C ((I2C_T *) I2C_BASE)
5726#define I2C0 ((I2C_T *) I2C_BASE)
5727#define SPI ((SPI_T *) SPI_BASE)
5728#define SPI0 ((SPI_T *) SPI_BASE)
5729#define PWM ((PWM_T *) PWM_BASE)
5730#define UART ((UART_T *) UART_BASE)
5731#define UART0 ((UART_T *) UART_BASE)
5732#define ADC ((ADC_T *) ADC_BASE)
5733#define ACMP ((ACMP_T *) ACMP_BASE)
5734
5735#define SYS ((GCR_T *) GCR_BASE)
5736#define CLK ((CLK_T *) CLK_BASE)
5737#define INT ((INT_T *) INT_BASE)
5738#define P0 ((GPIO_T *) P0_BASE)
5739#define P1 ((GPIO_T *) P1_BASE)
5740#define P2 ((GPIO_T *) P2_BASE)
5741#define P3 ((GPIO_T *) P3_BASE)
5742#define P4 ((GPIO_T *) P4_BASE)
5743#define P5 ((GPIO_T *) P5_BASE)
5744#define GPIO ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE)
5745#define FMC ((FMC_T *) FMC_BASE)
5746 /* end of group MINI51_PERIPHERAL_DECLARATION */ /* end of group MINI51_Peripherals */
5749
5755 typedef volatile unsigned char vu8;
5756 typedef volatile unsigned short vu16;
5757 typedef volatile unsigned long vu32;
5758
5764#define M8(addr) (*((vu8 *) (addr)))
5765
5772#define M16(addr) (*((vu16 *) (addr)))
5773
5780#define M32(addr) (*((vu32 *) (addr)))
5781
5789#define outpw(port,value) *((volatile unsigned int *)(port)) = value
5790
5797#define inpw(port) (*((volatile unsigned int *)(port)))
5798
5806#define outps(port,value) *((volatile unsigned short *)(port)) = value
5807
5814#define inps(port) (*((volatile unsigned short *)(port)))
5815
5822#define outpb(port,value) *((volatile unsigned char *)(port)) = value
5823
5829#define inpb(port) (*((volatile unsigned char *)(port)))
5830
5838#define outp32(port,value) *((volatile unsigned int *)(port)) = value
5839
5846#define inp32(port) (*((volatile unsigned int *)(port)))
5847
5855#define outp16(port,value) *((volatile unsigned short *)(port)) = value
5856
5863#define inp16(port) (*((volatile unsigned short *)(port)))
5864
5871#define outp8(port,value) *((volatile unsigned char *)(port)) = value
5872
5878#define inp8(port) (*((volatile unsigned char *)(port)))
5879
5880 /* end of group MINI51_IO_ROUTINE */
5882
5883/******************************************************************************/
5884/* Legacy Constants */
5885/******************************************************************************/
5891#ifndef NULL
5892#define NULL (0)
5893#endif
5894
5895#define TRUE (1)
5896#define FALSE (0)
5897
5898#define ENABLE (1)
5899#define DISABLE (0)
5900
5901/* Define one bit mask */
5902#define BIT0 (0x00000001)
5903#define BIT1 (0x00000002)
5904#define BIT2 (0x00000004)
5905#define BIT3 (0x00000008)
5906#define BIT4 (0x00000010)
5907#define BIT5 (0x00000020)
5908#define BIT6 (0x00000040)
5909#define BIT7 (0x00000080)
5910#define BIT8 (0x00000100)
5911#define BIT9 (0x00000200)
5912#define BIT10 (0x00000400)
5913#define BIT11 (0x00000800)
5914#define BIT12 (0x00001000)
5915#define BIT13 (0x00002000)
5916#define BIT14 (0x00004000)
5917#define BIT15 (0x00008000)
5918#define BIT16 (0x00010000)
5919#define BIT17 (0x00020000)
5920#define BIT18 (0x00040000)
5921#define BIT19 (0x00080000)
5922#define BIT20 (0x00100000)
5923#define BIT21 (0x00200000)
5924#define BIT22 (0x00400000)
5925#define BIT23 (0x00800000)
5926#define BIT24 (0x01000000)
5927#define BIT25 (0x02000000)
5928#define BIT26 (0x04000000)
5929#define BIT27 (0x08000000)
5930#define BIT28 (0x10000000)
5931#define BIT29 (0x20000000)
5932#define BIT30 (0x40000000)
5933#define BIT31 (0x80000000)
5934
5935/* Byte Mask Definitions */
5936#define BYTE0_Msk (0x000000FF)
5937#define BYTE1_Msk (0x0000FF00)
5938#define BYTE2_Msk (0x00FF0000)
5939#define BYTE3_Msk (0xFF000000)
5940
5941#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
5942#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
5943#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
5944#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /* end of group MINI51_legacy_Constants */
5947 /* end of group MINI51_Definitions */
5949
5950#ifdef __cplusplus
5951}
5952#endif
5953
5954
5955/******************************************************************************/
5956/* Peripheral header files */
5957/******************************************************************************/
5958#include "sys.h"
5959#include "clk.h"
5960#include "acmp.h"
5961#include "adc.h"
5962#include "fmc.h"
5963#include "gpio.h"
5964#include "i2c.h"
5965#include "pwm.h"
5966#include "spi.h"
5967#include "timer.h"
5968#include "uart.h"
5969#include "wdt.h"
5970
5971#endif // __MINI51SERIES_H__
5972
acmp.h
Mini51 series Analog Comparator(ACMP) driver header file.
adc.h
Mini51 series ADC driver header file.
clk.h
Mini51 series CLK driver header file.
fmc.h
MINI51 series FMC driver header file.
gpio.h
Mini51 series GPIO driver header file.
IRQn_Type
enum IRQn IRQn_Type
IRQn
IRQn
Definition: Mini51Series.h:81
PendSV_IRQn
@ PendSV_IRQn
Definition: Mini51Series.h:87
GPIO5_IRQn
@ GPIO5_IRQn
Definition: Mini51Series.h:104
EINT0_IRQn
@ EINT0_IRQn
Definition: Mini51Series.h:94
SVCall_IRQn
@ SVCall_IRQn
Definition: Mini51Series.h:86
ADC_IRQn
@ ADC_IRQn
Definition: Mini51Series.h:109
PDWU_IRQn
@ PDWU_IRQn
Definition: Mini51Series.h:108
SysTick_IRQn
@ SysTick_IRQn
Definition: Mini51Series.h:88
ACMP_IRQn
@ ACMP_IRQn
Definition: Mini51Series.h:107
WDT_IRQn
@ WDT_IRQn
Definition: Mini51Series.h:93
TMR1_IRQn
@ TMR1_IRQn
Definition: Mini51Series.h:101
SPI_IRQn
@ SPI_IRQn
Definition: Mini51Series.h:103
GPIO234_IRQn
@ GPIO234_IRQn
Definition: Mini51Series.h:97
GPIO01_IRQn
@ GPIO01_IRQn
Definition: Mini51Series.h:96
UART_IRQn
@ UART_IRQn
Definition: Mini51Series.h:102
PWM_IRQn
@ PWM_IRQn
Definition: Mini51Series.h:98
HardFault_IRQn
@ HardFault_IRQn
Definition: Mini51Series.h:85
TMR0_IRQn
@ TMR0_IRQn
Definition: Mini51Series.h:100
HIRC_IRQn
@ HIRC_IRQn
Definition: Mini51Series.h:105
BOD_IRQn
@ BOD_IRQn
Definition: Mini51Series.h:92
EINT1_IRQn
@ EINT1_IRQn
Definition: Mini51Series.h:95
FB_IRQn
@ FB_IRQn
Definition: Mini51Series.h:99
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: Mini51Series.h:84
I2C_IRQn
@ I2C_IRQn
Definition: Mini51Series.h:106
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Mini51Series.h:5757
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Mini51Series.h:5756
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Mini51Series.h:5755
UART_T::LCR
__IO uint32_t LCR
Definition: Mini51Series.h:5326
GCR_T::P3_MFP
__IO uint32_t P3_MFP
Definition: Mini51Series.h:1518
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: Mini51Series.h:1126
GCR_T::BODCTL
__IO uint32_t BODCTL
Definition: Mini51Series.h:1511
GPIO_T::IMD
__IO uint32_t IMD
Definition: Mini51Series.h:2080
ACMP_T::CMPRVCR
__IO uint32_t CMPRVCR
Definition: Mini51Series.h:228
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: Mini51Series.h:1127
INT_T::SRC0
__I uint32_t SRC0
Definition: Mini51Series.h:2680
PWM_T::PHCHG
__IO uint32_t PHCHG
Definition: Mini51Series.h:3572
GCR_T::IPRSTC1
__IO uint32_t IPRSTC1
Definition: Mini51Series.h:1506
I2C_T::I2CSTATUS
__I uint32_t I2CSTATUS
Definition: Mini51Series.h:2412
ADC_T::ADCR
__IO uint32_t ADCR
Definition: Mini51Series.h:475
UART_T::FCR
__IO uint32_t FCR
Definition: Mini51Series.h:5325
GPIO_T::IEN
__IO uint32_t IEN
Definition: Mini51Series.h:2081
UART_T::THR
__O uint32_t THR
Definition: Mini51Series.h:5322
PWM_T::PIIR
__IO uint32_t PIIR
Definition: Mini51Series.h:3564
TIMER_T::TCMPR
__IO uint32_t TCMPR
Definition: Mini51Series.h:4820
UART_T::TOR
__IO uint32_t TOR
Definition: Mini51Series.h:5331
PWM_T::PIER
__IO uint32_t PIER
Definition: Mini51Series.h:3563
PWM_T::PHCHGMASK
__IO uint32_t PHCHGMASK
Definition: Mini51Series.h:3574
I2C_T::I2CSTATUS2
__IO uint32_t I2CSTATUS2
Definition: Mini51Series.h:2426
TIMER_T::TEXCON
__IO uint32_t TEXCON
Definition: Mini51Series.h:4824
SPI_T::CNTRL
__IO uint32_t CNTRL
Definition: Mini51Series.h:4473
I2C_T::I2CLK
__IO uint32_t I2CLK
Definition: Mini51Series.h:2413
TIMER_T::TCAP
__I uint32_t TCAP
Definition: Mini51Series.h:4823
INT_T::SRC8
__I uint32_t SRC8
Definition: Mini51Series.h:2688
UART_T::FSR
__IO uint32_t FSR
Definition: Mini51Series.h:5329
WDT_T::WTCR
__IO uint32_t WTCR
Definition: Mini51Series.h:5625
GPIO_T::ISRC
__IO uint32_t ISRC
Definition: Mini51Series.h:2082
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: Mini51Series.h:849
INT_T::SRC16
__I uint32_t SRC16
Definition: Mini51Series.h:2701
INT_T::SRC18
__I uint32_t SRC18
Definition: Mini51Series.h:2703
SPI_T::CNTRL2
__IO uint32_t CNTRL2
Definition: Mini51Series.h:4487
ADC_T::ADDR
__I uint32_t ADDR
Definition: Mini51Series.h:471
GCR_T::P5_MFP
__IO uint32_t P5_MFP
Definition: Mini51Series.h:1520
FMC_T::ISPCON
__IO uint32_t ISPCON
Definition: Mini51Series.h:1123
INT_T::SRC29
__I uint32_t SRC29
Definition: Mini51Series.h:2712
UART_T::RBR
__I uint32_t RBR
Definition: Mini51Series.h:5321
CLK_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Mini51Series.h:850
INT_T::SRC7
__I uint32_t SRC7
Definition: Mini51Series.h:2687
GCR_T::IPRSTC2
__IO uint32_t IPRSTC2
Definition: Mini51Series.h:1507
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Mini51Series.h:4489
TIMER_T::TCSR
__IO uint32_t TCSR
Definition: Mini51Series.h:4819
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: Mini51Series.h:2079
ADC_T::ADSAMP
__IO uint32_t ADSAMP
Definition: Mini51Series.h:483
I2C_T::I2CADDR2
__IO uint32_t I2CADDR2
Definition: Mini51Series.h:2416
I2C_T::I2CADDR0
__IO uint32_t I2CADDR0
Definition: Mini51Series.h:2410
SPI_T::RX
__I uint32_t RX
Definition: Mini51Series.h:4479
GPIO_T::PMD
__IO uint32_t PMD
Definition: Mini51Series.h:2074
GCR_T::RegLockAddr
__IO uint32_t RegLockAddr
Definition: Mini51Series.h:1530
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: Mini51Series.h:848
PWM_T::CSR
__IO uint32_t CSR
Definition: Mini51Series.h:3556
INT_T::SRC4
__I uint32_t SRC4
Definition: Mini51Series.h:2684
PWM_T::PFBCON
__IO uint32_t PFBCON
Definition: Mini51Series.h:3566
UART_T::BAUD
__IO uint32_t BAUD
Definition: Mini51Series.h:5332
GPIO_DBNCECON_T::DBNCECON
__IO uint32_t DBNCECON
Definition: Mini51Series.h:2121
PWM_T::TRGSTS1
__IO uint32_t TRGSTS1
Definition: Mini51Series.h:3571
I2C_T::I2CTOC
__IO uint32_t I2CTOC
Definition: Mini51Series.h:2414
GPIO_T::PIN
__I uint32_t PIN
Definition: Mini51Series.h:2078
I2C_T::I2CON2
__IO uint32_t I2CON2
Definition: Mini51Series.h:2425
UART_T::FUN_SEL
__IO uint32_t FUN_SEL
Definition: Mini51Series.h:5335
SPI_T::FIFO_CTL
__IO uint32_t FIFO_CTL
Definition: Mini51Series.h:4488
SPI_T::SSR
__IO uint32_t SSR
Definition: Mini51Series.h:4475
CLK_T::CLKSTATUS
__IO uint32_t CLKSTATUS
Definition: Mini51Series.h:847
INT_T::SRC17
__I uint32_t SRC17
Definition: Mini51Series.h:2702
GCR_T::IRCTRIMCTL
__IO uint32_t IRCTRIMCTL
Definition: Mini51Series.h:1524
UART_T::MSR
__IO uint32_t MSR
Definition: Mini51Series.h:5328
INT_T::SRC25
__I uint32_t SRC25
Definition: Mini51Series.h:2707
ACMP_T::CMPSR
__IO uint32_t CMPSR
Definition: Mini51Series.h:227
FMC_T::ISPSTA
__I uint32_t ISPSTA
Definition: Mini51Series.h:1132
INT_T::SRC2
__I uint32_t SRC2
Definition: Mini51Series.h:2682
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: Mini51Series.h:845
INT_T::SRC14
__I uint32_t SRC14
Definition: Mini51Series.h:2697
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: Mini51Series.h:2076
GPIO_T::DMASK
__IO uint32_t DMASK
Definition: Mini51Series.h:2077
SPI_T::DIVIDER
__IO uint32_t DIVIDER
Definition: Mini51Series.h:4474
PWM_T::TRGSTS0
__IO uint32_t TRGSTS0
Definition: Mini51Series.h:3570
I2C_T::I2CADM3
__IO uint32_t I2CADM3
Definition: Mini51Series.h:2421
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: Mini51Series.h:1125
I2C_T::I2CON
__IO uint32_t I2CON
Definition: Mini51Series.h:2409
ADC_T::ADTDCR
__IO uint32_t ADTDCR
Definition: Mini51Series.h:482
INT_T::NMICON
__IO uint32_t NMICON
Definition: Mini51Series.h:2716
GCR_T::IRCTRIMIER
__IO uint32_t IRCTRIMIER
Definition: Mini51Series.h:1525
INT_T::MCUIRQ
__IO uint32_t MCUIRQ
Definition: Mini51Series.h:2717
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: Mini51Series.h:846
PWM_T::PPR
__IO uint32_t PPR
Definition: Mini51Series.h:3555
ADC_T::ADSR
__IO uint32_t ADSR
Definition: Mini51Series.h:478
INT_T::SRC3
__I uint32_t SRC3
Definition: Mini51Series.h:2683
SPI_T::TX
__O uint32_t TX
Definition: Mini51Series.h:4483
GCR_T::RSTSRC
__IO uint32_t RSTSRC
Definition: Mini51Series.h:1505
I2C_T::I2CADM0
__IO uint32_t I2CADM0
Definition: Mini51Series.h:2418
GCR_T::P2_MFP
__IO uint32_t P2_MFP
Definition: Mini51Series.h:1517
PWM_T::PDZIR
__IO uint32_t PDZIR
Definition: Mini51Series.h:3567
INT_T::SRC9
__I uint32_t SRC9
Definition: Mini51Series.h:2689
PWM_T::TRGCON0
__IO uint32_t TRGCON0
Definition: Mini51Series.h:3568
UART_T::IRCR
__IO uint32_t IRCR
Definition: Mini51Series.h:5333
GCR_T::P1_MFP
__IO uint32_t P1_MFP
Definition: Mini51Series.h:1516
PWM_T::PCR
__IO uint32_t PCR
Definition: Mini51Series.h:3557
UART_T::ALT_CSR
__IO uint32_t ALT_CSR
Definition: Mini51Series.h:5334
INT_T::SRC5
__I uint32_t SRC5
Definition: Mini51Series.h:2685
PWM_T::POE
__IO uint32_t POE
Definition: Mini51Series.h:3565
PWM_T::INTACCUCTL
__IO uint32_t INTACCUCTL
Definition: Mini51Series.h:3575
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: Mini51Series.h:851
I2C_T::I2CDAT
__IO uint32_t I2CDAT
Definition: Mini51Series.h:2411
I2C_T::I2CADM2
__IO uint32_t I2CADM2
Definition: Mini51Series.h:2420
UART_T::ISR
__IO uint32_t ISR
Definition: Mini51Series.h:5330
I2C_T::I2CADDR3
__IO uint32_t I2CADDR3
Definition: Mini51Series.h:2417
GCR_T::IRCTRIMISR
__IO uint32_t IRCTRIMISR
Definition: Mini51Series.h:1526
TIMER_T::TEXISR
__IO uint32_t TEXISR
Definition: Mini51Series.h:4825
TIMER_T::TISR
__IO uint32_t TISR
Definition: Mini51Series.h:4821
GCR_T::P4_MFP
__IO uint32_t P4_MFP
Definition: Mini51Series.h:1519
UART_T::IER
__IO uint32_t IER
Definition: Mini51Series.h:5324
FMC_T::DFBADR
__I uint32_t DFBADR
Definition: Mini51Series.h:1128
I2C_T::I2CADM1
__IO uint32_t I2CADM1
Definition: Mini51Series.h:2419
GPIO_T::OFFD
__IO uint32_t OFFD
Definition: Mini51Series.h:2075
INT_T::SRC1
__I uint32_t SRC1
Definition: Mini51Series.h:2681
INT_T::SRC12
__I uint32_t SRC12
Definition: Mini51Series.h:2693
INT_T::SRC28
__I uint32_t SRC28
Definition: Mini51Series.h:2711
I2C_T::I2CADDR1
__IO uint32_t I2CADDR1
Definition: Mini51Series.h:2415
ADC_T::ADCHER
__IO uint32_t ADCHER
Definition: Mini51Series.h:476
FMC_T::ISPADR
__IO uint32_t ISPADR
Definition: Mini51Series.h:1124
UART_T::MCR
__IO uint32_t MCR
Definition: Mini51Series.h:5327
CLK_T::FRQDIV
__IO uint32_t FRQDIV
Definition: Mini51Series.h:855
PWM_T::PHCHGNXT
__IO uint32_t PHCHGNXT
Definition: Mini51Series.h:3573
INT_T::SRC6
__I uint32_t SRC6
Definition: Mini51Series.h:2686
TIMER_T::TDR
__I uint32_t TDR
Definition: Mini51Series.h:4822
GCR_T::P0_MFP
__IO uint32_t P0_MFP
Definition: Mini51Series.h:1515
PWM_T::TRGCON1
__IO uint32_t TRGCON1
Definition: Mini51Series.h:3569
CLK_T::PWRCON
__IO uint32_t PWRCON
Definition: Mini51Series.h:844
GCR_T::PDID
__I uint32_t PDID
Definition: Mini51Series.h:1504
i2c.h
Mini51 series I2C driver header file.
pwm.h
Mini51 series PWM driver header file.
spi.h
Mini51 series SPI driver header file.
ACMP_T
Definition: Mini51Series.h:157
ADC_T
Definition: Mini51Series.h:290
CLK_T
Definition: Mini51Series.h:608
FMC_T
Definition: Mini51Series.h:1018
GCR_T
Definition: Mini51Series.h:1200
GPIO_DBNCECON_T
GPIO debounce register map.
Definition: Mini51Series.h:2089
GPIO_T
Definition: Mini51Series.h:1796
I2C_T
Definition: Mini51Series.h:2203
INT_T
Definition: Mini51Series.h:2525
PWM_T
Definition: Mini51Series.h:2752
SPI_T
Definition: Mini51Series.h:4204
TIMER_T
Definition: Mini51Series.h:4662
UART_T
Definition: Mini51Series.h:4931
WDT_T
Definition: Mini51Series.h:5565
sys.h
Mini51 series SYS driver header file.
system_Mini51Series.h
Mini51 series system clock definition file.
timer.h
Mini51 series TIMER driver header file.
uart.h
Mini51 series UART driver header file.
wdt.h
Mini51 series WDT driver header file.