CMSIS-Driver: Driver_NAND.h File Reference

| CMSIS-Driver Version 2.04 Peripheral Interface for Middleware and Application Code

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Data Structures | Macros | Typedefs
Driver_NAND.h File Reference

## Data Structures
struct | ARM_NAND_ECC_INFO
| NAND ECC (Error Correction Code) Information. More...
struct | ARM_NAND_STATUS
| NAND Status. More...
struct | ARM_NAND_CAPABILITIES
| NAND Driver Capabilities. More...
struct | ARM_DRIVER_NAND
| Access structure of the NAND Driver. More...

## Macros
#define | ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */
#define | ARM_NAND_POWER_VCC_Pos 0
#define | ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos)
#define | ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos)
| VCC Power off.
#define | ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos)
| VCC = 3.3V.
#define | ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos)
| VCC = 1.8V.
#define | ARM_NAND_POWER_VCCQ_Pos 3
#define | ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
#define | ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos)
| VCCQ I/O Power off.
#define | ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos)
| VCCQ = 3.3V.
#define | ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos)
| VCCQ = 1.8V.
#define | ARM_NAND_POWER_VPP_OFF (1UL << 6)
| VPP off.
#define | ARM_NAND_POWER_VPP_ON (1Ul << 7)
| VPP on.
#define | ARM_NAND_BUS_MODE (0x01)
| Set Bus Mode as specified with arg.
#define | ARM_NAND_BUS_DATA_WIDTH (0x02)
| Set Bus Data Width as specified with arg.
#define | ARM_NAND_DRIVER_STRENGTH (0x03)
| Set Driver Strength as specified with arg.
#define | ARM_NAND_DEVICE_READY_EVENT (0x04)
| Generate ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled.
#define | ARM_NAND_DRIVER_READY_EVENT (0x05)
| Generate ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled.
#define | ARM_NAND_BUS_INTERFACE_Pos 4
#define | ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
#define | ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)
| Data Interface: SDR (Single Data Rate) - Traditional interface (default)
#define | ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)
| Data Interface: NV-DDR (Double Data Rate)
#define | ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)
| Data Interface: NV-DDR2 (Double Data Rate)
#define | ARM_NAND_BUS_TIMING_MODE_Pos 0
#define | ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
#define | ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 0 (default)
#define | ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 1.
#define | ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 2.
#define | ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 3.
#define | ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 4 (SDR EDO capable)
#define | ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 5 (SDR EDO capable)
#define | ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 6 (NV-DDR2 only)
#define | ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)
| Timing Mode 7 (NV-DDR2 only)
#define | ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8
#define | ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
#define | ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
| DDR2 Data Output Warm-up cycles: 0 (default)
#define | ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
| DDR2 Data Output Warm-up cycles: 1.
#define | ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
| DDR2 Data Output Warm-up cycles: 2.
#define | ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
| DDR2 Data Output Warm-up cycles: 4.
#define | ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12
#define | ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
#define | ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
| DDR2 Data Input Warm-up cycles: 0 (default)
#define | ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
| DDR2 Data Input Warm-up cycles: 1.
#define | ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
| DDR2 Data Input Warm-up cycles: 2.
#define | ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
| DDR2 Data Input Warm-up cycles: 4.
#define | ARM_NAND_BUS_DDR2_VEN (1UL << 16)
| DDR2 Enable external VREFQ as reference.
#define | ARM_NAND_BUS_DDR2_CMPD (1UL << 17)
| DDR2 Enable complementary DQS (DQS_c) signal.
#define | ARM_NAND_BUS_DDR2_CMPR (1UL << 18)
| DDR2 Enable complementary RE_n (RE_c) signal.
#define | ARM_NAND_BUS_DATA_WIDTH_8 (0x00)
| Bus Data Width: 8 bit (default)
#define | ARM_NAND_BUS_DATA_WIDTH_16 (0x01)
| Bus Data Width: 16 bit.
#define | ARM_NAND_DRIVER_STRENGTH_18 (0x00)
| Driver Strength 2.0x = 18 Ohms.
#define | ARM_NAND_DRIVER_STRENGTH_25 (0x01)
| Driver Strength 1.4x = 25 Ohms.
#define | ARM_NAND_DRIVER_STRENGTH_35 (0x02)
| Driver Strength 1.0x = 35 Ohms (default)
#define | ARM_NAND_DRIVER_STRENGTH_50 (0x03)
| Driver Strength 0.7x = 50 Ohms.
#define | ARM_NAND_ECC_INDEX_Pos 0
#define | ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
#define | ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk)
| Select ECC.
#define | ARM_NAND_ECC0 (1UL << 8)
| Use ECC0 of selected ECC.
#define | ARM_NAND_ECC1 (1UL << 9)
| Use ECC1 of selected ECC.
#define | ARM_NAND_DRIVER_DONE_EVENT (1UL << 16)
| Generate ARM_NAND_EVENT_DRIVER_DONE.
#define | ARM_NAND_CODE_SEND_CMD1 (1UL << 17)
| Send Command 1.
#define | ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18)
| Send Column Address 1.
#define | ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19)
| Send Column Address 2.
#define | ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20)
| Send Row Address 1.
#define | ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21)
| Send Row Address 2.
#define | ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22)
| Send Row Address 3.
#define | ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23)
| Auto-increment Row Address.
#define | ARM_NAND_CODE_WRITE_DATA (1UL << 24)
| Write Data.
#define | ARM_NAND_CODE_SEND_CMD2 (1UL << 25)
| Send Command 2.
#define | ARM_NAND_CODE_WAIT_BUSY (1UL << 26)
| Wait while R/Bn busy.
#define | ARM_NAND_CODE_READ_DATA (1UL << 27)
| Read Data.
#define | ARM_NAND_CODE_SEND_CMD3 (1UL << 28)
| Send Command 3.
#define | ARM_NAND_CODE_READ_STATUS (1UL << 29)
| Read Status byte and check FAIL bit (bit 0)
#define | ARM_NAND_CODE_CMD1_Pos 0
#define | ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
#define | ARM_NAND_CODE_CMD2_Pos 8
#define | ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
#define | ARM_NAND_CODE_CMD3_Pos 16
#define | ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
#define | ARM_NAND_CODE_ADDR_COL1_Pos 0
#define | ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
#define | ARM_NAND_CODE_ADDR_COL2_Pos 8
#define | ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
#define | ARM_NAND_CODE_ADDR_ROW1_Pos 0
#define | ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
#define | ARM_NAND_CODE_ADDR_ROW2_Pos 8
#define | ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
#define | ARM_NAND_CODE_ADDR_ROW3_Pos 16
#define | ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
#define | ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1)
| ECC generation/correction failed.
#define | ARM_NAND_EVENT_DEVICE_READY (1UL << 0)
| Device Ready: R/Bn rising edge.
#define | ARM_NAND_EVENT_DRIVER_READY (1UL << 1)
| Driver Ready.
#define | ARM_NAND_EVENT_DRIVER_DONE (1UL << 2)
| Driver operation done.
#define | ARM_NAND_EVENT_ECC_ERROR (1UL << 3)
| ECC could not correct data.

## Typedefs
typedef void(* | ARM_NAND_SignalEvent_t )(uint32_t dev_num, uint32_t event)
| Pointer to ARM_NAND_SignalEvent : Signal NAND Event.

## Macro Definition Documentation

#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */

#define ARM_NAND_POWER_VCC_Pos 0

#define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos)

#define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos)

VCC Power off.

#define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos)

VCC = 3.3V.

#define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos)

VCC = 1.8V.

#define ARM_NAND_POWER_VCCQ_Pos 3

#define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos)

#define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos)

VCCQ I/O Power off.

#define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos)

VCCQ = 3.3V.

#define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos)

VCCQ = 1.8V.

#define ARM_NAND_POWER_VPP_OFF (1UL << 6)

VPP off.

#define ARM_NAND_POWER_VPP_ON (1Ul << 7)

VPP on.

#define ARM_NAND_BUS_INTERFACE_Pos 4

#define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)

#define ARM_NAND_BUS_TIMING_MODE_Pos 0

#define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)

#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8

#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)

#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12

#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)

#define ARM_NAND_ECC_INDEX_Pos 0

#define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos)

#define ARM_NAND_CODE_CMD1_Pos 0

#define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos)

#define ARM_NAND_CODE_CMD2_Pos 8

#define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos)

#define ARM_NAND_CODE_CMD3_Pos 16

#define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos)

#define ARM_NAND_CODE_ADDR_COL1_Pos 0

#define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)

#define ARM_NAND_CODE_ADDR_COL2_Pos 8

#define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)

#define ARM_NAND_CODE_ADDR_ROW1_Pos 0

#define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)

#define ARM_NAND_CODE_ADDR_ROW2_Pos 8

#define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)

#define ARM_NAND_CODE_ADDR_ROW3_Pos 16

#define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)