| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
TIMER_T Struct Reference

`#include <Mini51Series.h>`

## Data Fields
__IO uint32_t | TCSR
__IO uint32_t | TCMPR
__IO uint32_t | TISR
__I uint32_t | TDR
__I uint32_t | TCAP
__IO uint32_t | TEXCON
__IO uint32_t | TEXISR

## Detailed Description

    @addtogroup TMR Timer Controller(TMR)
    Memory Mapped Structure for TMR Controller

Definition at line 8097 of file Mini51Series.h.

## Field Documentation

## ◆ TCAP

TIMER_T::TCAP

TCAP

Offset: 0x10 Timer Capture Data Register

Bits | Field | Descriptions
[23:0] | TCAP | Timer Capture Data Register When TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately.

Definition at line 8460 of file Mini51Series.h.

## ◆ TCMPR

TIMER_T::TCMPR

TCMPR

Offset: 0x04 Timer Compare Register

Bits | Field | Descriptions
[23:0] | TCMP | Timer Compared Value TCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1. Time-out period = (Period of Timer clock source) * (8-bit PRESCALE + 1) * (24-bit TCMP). Note1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.

Definition at line 8457 of file Mini51Series.h.

## ◆ TCSR

TIMER_T::TCSR

TCSR

Offset: 0x00 Timer Control and Status Register

Bits | Field | Descriptions
[7:0] | PRESCALE | Prescale Counter Timer input clock source is divided by (PRESCALE+1) before it is fed to the Timer up counter. If this field is 0 (PRESCALE = 0), then there is no scaling.
[16] | TDR_EN | Data Load Enable Control When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 0 = Timer Data Register update Disabled. 1 = Timer Data Register update Enabled while Timer counter is active.
[17] | PERIODIC_SEL | Periodic Mode Behavior Selection 0 = In One-shot or Periodic mode, when write new TCMP, timer counter will reset. 1 = In One-shot or Periodic mode, when write new TCMP if new TCMP > TDR(current counter) , timer counter keep counting and will not reset. If new TCMP <= TDR(current counter) , timer counter will reset.
[18] | TOUT_PIN | Toggle Out Pin Selection When Timer is set to toggle mode, 0 = Time0/1 toggle output pin is T0/T1 pin. 1 = Time0/1 toggle output pin is T0EX/T1EX pin.
[19] | CAP_SRC | Capture Pin Source Selection 0 = Capture Function source is from TxEX pin. 1 = Capture Function source is from ACMPx output signal.
[23] | WAKE_EN | Wake-up Enable Control When WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set, the timer controller will generator a wake-up trigger event to CPU. 0 = Wake-up trigger event Disabled. 1 = Wake-up trigger event Enabled.
[24] | CTB | Counter Mode Enable Control This bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description. 0 = External event counter mode Disabled. 1 = External event counter mode Enabled.
[25] | CACT | Timer Active Status (Read Only) This bit indicates the 24-bit up counter status. 0 = 24-bit up counter is not active. 1 = 24-bit up counter is active.
[26] | CRST | Timer Reset 0 = No effect. 1 = Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1.
[28:27] | MODE | Timer Operating Mode 00 = The timer is operating in the One-shot mode. The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware. 01 = The timer is operating in Periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). 10 = The timer is operating in Toggle mode. The interrupt signal is generated periodically (if IE is enabled). The associated signal (tout) is changing back and forth with 50% duty cycle. 11 = The timer is operating in Continuous Counting mode. The associated interrupt signal is generated when TDR = TCMPR (if IE is enabled). However, the 24-bit up-timer counts continuously. Please refer to 6.12.5.2 for detailed description about Continuous Counting mode operation.
[29] | IE | Interrupt Enable Control 0 = Timer Interrupt function Disabled. 1 = Timer Interrupt function Enabled. If this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
[30] | CEN | Timer Enable Control 0 = Stops/Suspends counting. 1 = Starts counting. Note1: In stop status, and then set CEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (MODE (TCSRx[28:27]) = 00) when the timer interrupt flag (TIF) is generated.
[31] | DBGACK_TMR | ICE Debug Mode Acknowledge Disable Control (Write Protect) 0 = ICE debug mode acknowledgement effects TIMER counting. Timer counter will be held while CPU is held by ICE. 1 = ICE debug mode acknowledgement Disabled. Timer counter will keep going no matter CPU is held by ICE or not.

Definition at line 8456 of file Mini51Series.h.

## ◆ TDR

TIMER_T::TDR

TDR

Offset: 0x0C Timer Data Register

Bits | Field | Descriptions
[23:0] | TDR | Timer Data Register If TDR_EN (TCSRx[16]) is set to 1, TDR register value will be updated continuously to monitor 24-bit up counter value.

Definition at line 8459 of file Mini51Series.h.

## ◆ TEXCON

TIMER_T::TEXCON

TEXCON

Offset: 0x14 Timer External Control Register

Bits | Field | Descriptions
[0] | TX_PHASE | Timer External Count Pin Phase Detect Selection This bit indicates the detection phase of Tx (x = 0~1) pin. 0 = A falling edge of Tx (x = 0~1) pin will be counted. 1 = A rising edge of Tx (x = 0~1) pin will be counted.
[2:1] | TEX_EDGE | Timer External Pin Edge Detection 00 = A 1 to 0 transition on TxEX (x = 0~1) will be detected. 01 = A 0 to 1 transition on TxEX (x = 0~1) will be detected. 10 = Either 1 to 0 or 0 to 1 transition on TxEX (x = 0~1) will be detected. 11 = Reserved.
[3] | TEXEN | Timer External Pin Function Enable Control This bit enables the RSTCAPSEL function on the TxEX (x = 0~1) pin. 0 = RSTCAPSEL function of TxEX (x = 0~1) pin will be ignored. 1 = RSTCAPSEL function of TxEX (x = 0~1) pin is active.
[4] | RSTCAPSEL | Timer External Reset Counter / Timer External Capture Mode Selection 0 = Transition on TxEX (x = 0~1) pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1. 1 = Transition on TxEX (x = 0~1) pin is using to reset the 24-bit up counter.
[5] | TEXIEN | Timer External Capture Interrupt Enable Control 0 = TxEX (x = 0~1) pin detection Interrupt Disabled. 1 = TxEX (x = 0~1) pin detection Interrupt Enabled. If TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1.
[6] | TEXDB | Timer External Capture Input Pin De-bounce Enable Control 0 = TxEX (x = 0~1) pin de-bounce Disabled. 1 = TxEX (x = 0~1) pin de-bounce Enabled. If this bit is enabled, the edge detection of TxEX (x = 0~1) pin is detected with de-bounce circuit.
[7] | TCDB | Timer External Counter Input Pin De-bounce Enable Control 0 = Tx (x = 0~1) pin de-bounce Disabled. 1 = Tx (x = 0~1) pin de-bounce Enabled. If this bit is enabled, the edge detection of Tx (x = 0~1) pin is detected with de-bounce circuit.
[8] | CAP_MODE | Capture Mode Selection 0 = Timer counter reset function or free-counting mode of timer capture function. 1 = Trigger-counting mode of timer capture function.

Definition at line 8461 of file Mini51Series.h.

## ◆ TEXISR

TIMER_T::TEXISR

TEXISR

Offset: 0x18 Timer External Interrupt Status Register

Bits | Field | Descriptions
[0] | TEXIF | Timer External Interrupt Flag This bit indicates the external capture interrupt flag status When TEXEN enabled, TxEX (x = 0, 1) pin selected as external capture function, and a transition on TxEX (x = 0, 1) pin matched the TEX_EDGE setting, this flag will set to 1 by hardware. 0 = TxEX (x = 0, 1) pin interrupt did not occur. 1 = TxEX (x = 0, 1) pin interrupt occurred. Note: This bit is cleared by writing 1 to it

Definition at line 8462 of file Mini51Series.h.

## ◆ TISR

TIMER_T::TISR

TISR

Offset: 0x08 Timer Interrupt Status Register

Bits | Field | Descriptions
[0] | TIF | Timer Interrupt Flag This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value. 0 = No effect. 1 = TDR value matches the TCMP value. Note: This bit is cleared by writing 1 to it.
[1] | TWF | Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of Time. 0 = Timer does not cause chip wake-up. 1 = Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated. Note: This bit is cleared by writing 1 to it.

Definition at line 8458 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h