| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
ADC_T Struct Reference
MINI51 Definitions

`#include <Mini51Series.h>`

## Data Fields
__I uint32_t | ADDR
__IO uint32_t | ADCR
__IO uint32_t | ADCHER
__IO uint32_t | ADCMPR [2]
__IO uint32_t | ADSR
__IO uint32_t | ADTDCR
__IO uint32_t | ADSAMP

## Detailed Description

    @addtogroup ADC Analog to Digital Converter(ADC)
    Memory Mapped Structure for ADC Controller

Definition at line 376 of file Mini51Series.h.

## Field Documentation

## ◆ ADCHER

ADC_T::ADCHER

ADCHER

Offset: 0x24 ADC Channel Enable Control Register

Bits | Field | Descriptions
[0] | CHEN0 | Analog Input Channel 0 Enable Control 0 = Channel 0 Disabled. 1 = Channel 0 Enabled. Note: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
[1] | CHEN1 | Analog Input Channel 1 Enable Control 0 = Channel 1 Disabled. 1 = Channel 1 Enabled.
[2] | CHEN2 | Analog Input Channel 2 Enable Control 0 = Channel 2 Disabled. 1 = Channel 2 Enabled.
[3] | CHEN3 | Analog Input Channel 3 Enable Control 0 = Channel 3 Disabled. 1 = Channel 3 Enabled.
[4] | CHEN4 | Analog Input Channel 4 Enable Control 0 = Channel 4 Disabled. 1 = Channel 4 Enabled.
[5] | CHEN5 | Analog Input Channel 5 Enable Control 0 = Channel 5 Disabled. 1 = Channel 5 Enabled.
[6] | CHEN6 | Analog Input Channel 6 Enable Control 0 = Channel 6 Disabled. 1 = Channel 6 Enabled.
[7] | CHEN7 | Analog Input Channel 7 Enable Control 0 = Channel 7 Disabled. 1 = Channel 7 Enabled.
[8] | PRESEL | Analog Input Channel 7 Selection 0 = External analog input. 1 = Internal band-gap voltage (VBG). Note: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.

Definition at line 795 of file Mini51Series.h.

## ◆ ADCMPR

ADC_T::ADCMPR

ADCMPR

Offset: 0x28 ~ 0x2C ADC Compare Register

Bits | Field | Descriptions
[0] | CMPEN | Compare Enable Control Set 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register. 0 = Compare function Disabled. 1 = Compare function Enabled.
[1] | CMPIE | Compare Interrupt Enable Control If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. 0 = Compare function interrupt Disabled. 1 = Compare function interrupt Enabled.
[2] | CMPCOND | Compare Condition 0 = Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPD (ADCMPRx[25:16]), the internal match counter will increase one. 1 = Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPD (ADCMPRx[25:16]), the internal match counter will increase one. Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
[5:3] | CMPCH | Compare Channel Selection 000 = Channel 0 conversion result is selected to be compared. 001 = Channel 1 conversion result is selected to be compared. 010 = Channel 2 conversion result is selected to be compared. 011 = Channel 3 conversion result is selected to be compared. 100 = Channel 4 conversion result is selected to be compared. 101 = Channel 5 conversion result is selected to be compared. 110 = Channel 6 conversion result is selected to be compared. 111 = Channel 7 conversion result is selected to be compared.
[11:8] | CMPMATCNT | Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
[25:16] | CMPD | Comparison Data The 10-bit data is used to compare with conversion result of specified channel.

Definition at line 796 of file Mini51Series.h.

## ◆ ADCR

ADC_T::ADCR

ADCR

Offset: 0x20 ADC Control Register

Bits | Field | Descriptions
[0] | ADEN | A/D Converter Enable Control 0 = A/D Converter Disabled. 1 = A/D Converter Enabled. Note: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
[1] | ADIE | A/D Interrupt Enable Control A/D conversion end interrupt request is generated if ADIE bit is set to 1. 0 = A/D interrupt function Disabled. 1 = A/D interrupt function Enabled.
[5:4] | TRGS | Hardware Trigger Source 00 = A/D conversion is started by external STADC pin. 11 = A/D conversion is started by PWM trigger. Others = Reserved. Note: Software should disable TRGEN and ADST before change TRGS.
[6] | TRGCOND | External Trigger Condition This bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger. 0 = Falling edge. 1 = Raising edge.
[8] | TRGEN | External Trigger Enable Control Enable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source. 0= External trigger Disabled. 1= External trigger Enabled.
[11] | ADST | A/D Conversion Start ADST bit can be set to 1 from three sources: software or PWM trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically after conversion complete. 0 = Conversion stopped and A/D converter entered idle state. 1 = Conversion start.

Definition at line 794 of file Mini51Series.h.

## ◆ ADDR

ADC_T::ADDR

ADDR

Offset: 0x00 ADC Data Register

Bits | Field | Descriptions
[9:0] | RSLT | A/D Conversion Result This field contains conversion result of ADC.
[16] | OVERRUN | Over Run Flag 0 = Data in RSLT (ADDR[9:0])is recent conversion result. 1 = Data in RSLT (ADDR[9:0])overwrote. If converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read.
[17] | VALID | Valid Flag 0 = Data in RSLT (ADDR[9:0]) bits not valid. 1 = Data in RSLT (ADDR[9:0]) bits valid. This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read.

Definition at line 790 of file Mini51Series.h.

## ◆ ADSAMP

ADC_T::ADSAMP

ADSAMP

Offset: 0x48 ADC Sampling Time Counter Register

Bits | Field | Descriptions
[3:0] | ADSAMPCNT | ADC Sampling Counter If the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clock. The additional clock number will be inserted to lengthen the sampling clock. 0000 = 0 additional ADC sample clock. 0001 = 1 additional ADC sample clock. 0010 = 2 additional ADC sample clock. 0011 = 4 additional ADC sample clock. 0100 = 8 additional ADC sample clock. 0101 = 16 additional ADC sample clock. 0110 = 32 additional ADC sample clock. 0111 = 64 additional ADC sample clock. 1000 = 128 additional ADC sample clock. 1001 = 256 additional ADC sample clock. 1010 = 512 additional ADC sample clock. 1011 = 1024 additional ADC sample clock. 1100 = 1024 additional ADC sample clock. 1101 = 1024 additional ADC sample clock. 1110 = 1024 additional ADC sample clock. 1111 = 1024 additional ADC sample clock.

Definition at line 802 of file Mini51Series.h.

## ◆ ADSR

ADC_T::ADSR

ADSR

Offset: 0x30 ADC Status Register

Bits | Field | Descriptions
[0] | ADF | A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to 1 When A/D conversion ends. Software can write 1 to clear this bit to 0.
[1] | CMPF0 | Compare Flag 0 When the selected channel A/D conversion result meets the setting condition in ADCMPR0, this bit is set to 1. Software can write 1 to clear this bit to 0. 0 = Conversion result in ADDR does not meet the ADCMPR0 setting. 1 = Conversion result in ADDR meets the ADCMPR0 setting.
[2] | CMPF1 | Compare Flag 1 When the selected channel A/D conversion result meets the setting condition in ADCMPR1, this bit is set to 1. Software can write 1 to clear this bit to 0. 0 = Conversion result in ADDR does not meet the ADCMPR1 setting. 1 = Conversion result in ADDR meets the ADCMPR1 setting.
[3] | BUSY | BUSY/IDLE (Read Only) This bit is mirror of as ADST bit in ADCR 0 = A/D converter is in idle state. 1 = A/D converter is busy at conversion.
[6:4] | CHANNEL | Current Conversion Channel (Read Only) This filed reflects the current conversion channel when BUSY=1. When BUSY=0, it shows the number of the next converted channel.
[8] | VALID | Data Valid Flag (Read Only) It is a mirror of VALID (ADDR[17]) bit in ADDR register.
[16] | OVERRUN | Overrun Flag (Read Only) It is a mirror to OVERRUN (ADSR[16]) bit in ADDR register.

Definition at line 797 of file Mini51Series.h.

## ◆ ADTDCR

ADC_T::ADTDCR

ADTDCR

Offset: 0x44 ADC Trigger Delay Control Register

Bits | Field | Descriptions
[7:0] | PTDT | PWM Trigger Delay Timer Set this field will delay ADC start conversion time after PWM trigger. PWM trigger delay time is (4 * PTDT) * system clock.

Definition at line 801 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h