| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
SPI_T Struct Reference

`#include <Mini51Series.h>`

## Data Fields
__IO uint32_t | CNTRL
__IO uint32_t | DIVIDER
__IO uint32_t | SSR
__I uint32_t | RX
__O uint32_t | TX
__IO uint32_t | CNTRL2
__IO uint32_t | FIFO_CTL
__IO uint32_t | STATUS

## Detailed Description

    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
    Memory Mapped Structure for SPI Controller

Definition at line 7300 of file Mini51Series.h.

## Field Documentation

## ◆ CNTRL

SPI_T::CNTRL

CNTRL

Offset: 0x00 SPI Control and Status Register

Bits | Field | Descriptions
[0] | GO_BUSY | SPI Transfer Control Bit And Busy Status If FIFO mode is enabled, this bit will be controlled by hardware and is Read only. If FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. 0 = Writing 0 to this bit to stop data transfer if SPI is transferring. 1 = In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master. Note 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the GO_BUSY bit. Note 2: In SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the GO_BUSY bit will not be cleared to 0 when slave select signal goes to inactive state.
[1] | RX_NEG | Receive On Negative Edge 0 = The received data input signal latched on the Rising edge of SPICLK. 1 = The received data input signal latched on the Falling edge of SPICLK.
[2] | TX_NEG | Transmit On Negative Edge 0 = The transmitted data output signal is driven on the Rising edge of SPICLK. 1 = The transmitted data output signal is driven on the Falling edge of SPICLK.
[7:3] | TX_BIT_LEN | Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits. TX_BIT_LEN = 0x08 ... 8 bits. TX_BIT_LEN = 0x09 ... 9 bits. ..... TX_BIT_LEN = 0x1F ... 31 bits. TX_BIT_LEN = 0x00 ... 32 bits.
[10] | LSB | LSB First 0 = The MSB is transmitted/received first. 1 = The LSB is transmitted/received first.
[11] | CLKP | Clock Polarity 0 = SPICLK idle low. 1 = SPICLK idle high.
[15:12] | SP_CYCLE | Suspend Interval (Master Only) The four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation: (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle Example: SP_CYCLE = 0x0 ... 0.5 SPICLK clock cycle. SP_CYCLE = 0x1 ... 1.5 SPICLK clock cycle. ..... SP_CYCLE = 0xE ... 14.5 SPICLK clock cycle. SP_CYCLE = 0xF ... 15.5 SPICLK clock cycle.
[16] | IF | Unit-transfer Interrupt Flag 0 = The transfer does not finish yet. 1 = The SPI controller has finished one unit transfer. Note 1: This bit will be cleared by writing 1 to itself. Note 2: It's a mutual mirror bit of SPI_STATUS[16].
[17] | IE | Unit-transfer Interrupt Enable Control 0 = SPI unit-transfer interrupt Disabled. 1 = SPI unit-transfer interrupt Enabled.
[18] | SLAVE | Slave Mode Control 0 = Master mode. 1 = Slave mode.
[19] | REORDER | Byte Reorder Function 0 = Byte reorder function Disabled. 1 = Byte reorder function Enabled. Note: This setting is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
[21] | FIFO | FIFO Mode Enable Control 0 = FIFO Mode Disabled. 1 = FIFO Mode Enabled. Note 1: Before enabling FIFO mode, the other related settings should be set in advance. Note 2: In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 4-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the GO_BUSY bit will back to 0.
[24] | RX_EMPTY | Receive FIFO Buffer Empty Indicator (Read Only) 0 = The receive FIFO buffer is not empty. 1 = The receive FIFO buffer is empty. Note: It's a mutual mirror bit of SPI_CNTRL[24].
[25] | RX_FULL | Receive FIFO Buffer Full Indicator (Read Only) 0 = The receive FIFO buffer is not full. 1 = The receive FIFO buffer is full. Note: It's a mutual mirror bit of SPI_STATUS[25]
[26] | TX_EMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) 0 = The transmit FIFO buffer is not empty. 1 = The transmit FIFO buffer is empty. Note: It's a mutual mirror bit of SPI_STAUTS[26].
[27] | TX_FULL | Transmit FIFO Buffer Full Indicator (Read Only) 0 =The transmit FIFO buffer is not full. 1 =The transmit FIFO buffer is full. Note: It's a mutual mirror bit of SPI_STATUS[27].

Definition at line 7909 of file Mini51Series.h.

## ◆ CNTRL2

SPI_T::CNTRL2

CNTRL2

Offset: 0x3C SPI Control and Status Register 2

Bits | Field | Descriptions
[8] | NOSLVSEL | Slave 3-wire Mode Enable Control (Slave Only) The SPI controller work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI 0 = The controller is 4-wire bi-direction interface. 1 = The controller is 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1. Note: In Slave 3-wire mode, the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1.
[9] | SLV_ABORT | Slave 3-wire Mode Abort Control Bit (Slave Only) In normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN. If the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. 0 = No force the transfer done when the NOSLVSEL bit is set to 1. 1 = Force the transfer done when the NOSLVSEL bit is set to 1. Note: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
[10] | SSTA_INTEN | Slave 3-wire Mode Start Interrupt Enable Control (Slave Only) It is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV_ABORT bit to force the transfer done. 0 = Transaction start interrupt Disabled. 1 = Transaction start interrupt Enabled. Note: It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared to 0.
[11] | SLV_START_INTSTS | Slave 3-wire Mode Start Interrupt Status (Slave Only) This bit dedicates if a transaction has started in slave 3-wire mode. 0 = Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1. 1 = The transfer has started in slave 3-wire mode. Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit. Note 2: It is a mutual mirror bit of SPI_STATUS[11].
[16] | SS_INT_OPT | Slave Select Inactive Interrupt Option (Slave Only) 0 = As the slave select signal goes to inactive level, the IF bit will NOT be set to 1. 1 = As the slave select signal goes to inactive level, the IF bit will be set to 1. Note: This setting is only available if the SPI controller is configured as level trigger in slave device.
[31] | BCn | Clock Configuration Backward Compatible Option 0 = The clock configuration is backward compatible. 1 = The clock configuration is not backward compatible. Note: Refer to the description of SPI_DIVIDER register for details.

Definition at line 7923 of file Mini51Series.h.

## ◆ DIVIDER

SPI_T::DIVIDER

DIVIDER

Offset: 0x04 SPI Clock Divider Register

Bits | Field | Descriptions
[7:0] | DIVIDER | Clock Divider Bits (Master Only) The value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation: If the bit of BCn, SPI_CNTRL2[31], is set to 0. else if BCn is set to 1, where is the SPI peripheral clock source which is defined in the CLKSEL1 register.

Definition at line 7910 of file Mini51Series.h.

## ◆ FIFO_CTL

SPI_T::FIFO_CTL

FIFO_CTL

Offset: 0x40 SPI FIFO Control Register

Bits | Field | Descriptions
[0] | RX_CLR | Clear Receive FIFO Buffer 0 = No effect. 1 = Clear receive FIFO buffer. Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared.
[1] | TX_CLR | Clear Transmit FIFO Buffer 0 = No effect. 1 = Clear transmit FIFO buffer. Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared.
[2] | RX_INTEN | Receive Threshold Interrupt Enable Control 0 = Receive threshold interrupt Disabled. 1 = Receive threshold interrupt Enabled.
[3] | TX_INTEN | Transmit Threshold Interrupt Enable Control 0 = Transmit threshold interrupt Disabled. 1 = Transmit threshold interrupt Enabled.
[6] | RXOV_INTEN | Receive FIFO Overrun Interrupt Enable Control 0 = Receive FIFO overrun interrupt Disabled. 1 = Receive FIFO overrun interrupt Enabled.
[21] | TIMEOUT_INTEN | Receive FIFO Time-out Interrupt Enable Control 0 = Time-out interrupt Disabled. 1 = Time-out interrupt Enabled.
[25:24] | RX_THRESHOLD | Received FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
[29:28] | TX_THRESHOLD | Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.

Definition at line 7924 of file Mini51Series.h.

## ◆ RX

SPI_T::RX

RX

Offset: 0x10 SPI Data Receive Register

Bits | Field | Descriptions
[31:0] | RX | Data Receive Bits (Read Only) The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08, bit RX [7:0] holds the received data. The values of the other bits are unknown.

Definition at line 7915 of file Mini51Series.h.

## ◆ SSR

SPI_T::SSR

SSR

Offset: 0x08 SPI Slave Select Register

Bits | Field | Descriptions
[0] | SSR | Slave Select Control Bit (Master Only) If AUTOSS bit is 0, 0 = Set the SPISS line to inactive state. 1 = Set the proper SPISS line to active state. If AUTOSS bit is 1, 0 = Keep the SPISS line at inactive state. 1 = Select the SPISS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPISS is specified in SS_LVL bit.
[2] | SS_LVL | Slave Select Active Level (Slave Only) It defines the active status of slave select signal (SPISS). If SS_LTRIG bit is 1: 0 = The slave select signal SPISS is active at Low-level. 1 = The slave select signal SPISS is active at High-level. If SS_LTRIG bit is 0: 0 = The slave select signal SPISS is active at Falling-edge. 1 = The slave select signal SPISS is active at Rising-edge.
[3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) 0 = SPISS pin signal will be asserted/de-asserted by setting /clearing SSR bit. 1 = SPISS pin signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished.
[4] | SS_LTRIG | Slave Select Level Trigger Enable Bit (Slave Only) 0 = The input slave select signal is edge-trigger. 1 = The input slave select signal is level-trigger.
[5] | LTRIG_FLAG | Level Trigger Flag (Read Only, Slave Only) When the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not. 0 = The transaction number or the transferred bit length of one transaction does not meet the specified requirements. 1 = The transaction number and the transferred bit length met the specified requirements which defined in TX_BIT_LEN.

Definition at line 7911 of file Mini51Series.h.

## ◆ STATUS

SPI_T::STATUS

STATUS

Offset: 0x44 SPI Status Register

Bits | Field | Descriptions
[0] | RX_INTSTS | Receive FIFO Threshold Interrupt Status (Read Only) 0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD. 1 = The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD. Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt request.
[2] | RX_OVERRUN | Receive FIFO Overrun Status When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 0 = No overrun in receive FIFO. 1 = Overrun in receive FIFO. Note: This bit will be cleared by writing 1 to itself.
[4] | TX_INTSTS | Transmit FIFO Threshold Interrupt Status (Read Only) 0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD. 1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD. Note: If TX_INTEN = 1 and TX_INTSTS = 1, the SPI controller will generate a SPI interrupt request.
[11] | SLV_START_INTSTS | Slave Start Interrupt Status (Slave Only) It is used to dedicate that the transfer has started in slave 3-wire mode. 0 = Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1. 1 = The transfer has started in slave 3-wire mode. Note 1: It will be cleared as transfer done or by writing one to this bit. Note 2: It's a mutual mirror bit of SPI_CNTRL2[11].
[15:12] | RX_FIFO_COUNT | Receive FIFO Data Count (Read Only) Indicates the valid data count of receive FIFO buffer.
[16] | IF | SPI Unit-transfer Interrupt Flag 0 = The transfer does not finish yet. 1 = The SPI controller has finished one unit transfer. Note 1: This bit will be cleared by writing 1 to itself. Note 2: It's a mutual mirror bit of SPI_CNTRL[16].
[20] | TIMEOUT | Time-out Interrupt Flag 0 = No receive FIFO time-out event. 1 = The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically. Note: This bit will be cleared by writing 1 to itself.
[24] | RX_EMPTY | Receive FIFO Buffer Empty Indicator (Read Only) 0 = The receive FIFO buffer is not empty. 1 = The receive FIFO buffer is empty. Note: It's a mutual mirror bit of SPI_CNTRL[24].
[25] | RX_FULL | Receive FIFO Buffer Full Indicator (Read Only) 0 = The receive FIFO buffer is not full. 1 = The receive FIFO buffer is full. Note: It's a mutual mirror bit of SPI_CNTRL[25].
[26] | TX_EMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) 0 = The transmit FIFO buffer is not empty. 1 = The transmit FIFO buffer is empty. Note: It's a mutual mirror bit of SPI_CNTRL[26].
[27] | TX_FULL | Transmit FIFO Buffer Full Indicator (Read Only) 0 = The transmit FIFO buffer is not full. 1 = The transmit FIFO buffer is full. Note: It's a mutual mirror bit of SPI_CNTRL[27].
[31:28] | TX_FIFO_COUNT | Transmit FIFO Data Count (Read Only) Indicates the valid data count of transmit FIFO buffer.

Definition at line 7925 of file Mini51Series.h.

## ◆ TX

SPI_T::TX

TX

Offset: 0x20 SPI Data Transmit Register

Bits | Field | Descriptions
[31:0] | TX | Data Transmit Bits (Write Only) The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if TX_BIT_LEN is set to 0x08, the bit TX [7:0] will be transmitted in next transfer.

Definition at line 7919 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h