| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Mini51Series.h
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1 /**************************************************************************/
52 #ifndef __MINI51SERIES_H__
53 #define __MINI51SERIES_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
69 /******************************************************************************/
70 /* Processor and Core Peripherals */
71 /******************************************************************************/
80 typedef enum IRQn
81 {
82 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
83
84 NonMaskableInt_IRQn = -14,
85 HardFault_IRQn = -13,
86 SVCall_IRQn = -5,
87 PendSV_IRQn = -2,
88 SysTick_IRQn = -1,
90 /****** Mini51 specific Interrupt Numbers ***********************************************/
91
92 BOD_IRQn = 0,
93 WDT_IRQn = 1,
94 EINT0_IRQn = 2,
95 EINT1_IRQn = 3,
96 GPIO01_IRQn = 4,
97 GPIO234_IRQn = 5,
98 PWM_IRQn = 6,
99 FB_IRQn = 7,
100 TMR0_IRQn = 8,
101 TMR1_IRQn = 9,
102 UART_IRQn = 12,
103 SPI_IRQn = 14,
104 GPIO5_IRQn = 16,
105 HIRC_IRQn = 17,
106 I2C_IRQn = 18,
107 ACMP_IRQn = 25,
108 PDWU_IRQn = 28,
109 ADC_IRQn = 29
111 } IRQn_Type;
112
113
114 /*
115 * ==========================================================================
116 * ----------- Processor and Core Peripheral Section ------------------------
117 * ==========================================================================
118 */
119
120
121 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
122 #define __CM0_REV 0x0201
123 #define __NVIC_PRIO_BITS 2
124 #define __Vendor_SysTickConfig 0
125 #define __MPU_PRESENT 0
126 #define __FPU_PRESENT 0
128 /* end of group MINI51_CMSIS */
129
130
131 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
132 #include "system_Mini51Series.h" /* Mini51 Series System include file */
133 #include <stdint.h>
134
135 /******************************************************************************/
136 /* Device Specific Peripheral registers structures */
137 /******************************************************************************/
143 #if defined ( __CC_ARM )
144 #pragma anon_unions
145 #endif
146
147
148
149 /*---------------------- Analog Comparator Controller -------------------------*/
156 typedef struct
157 {
158
313 __IO uint32_t CMPCR[2]; /* Offset: 0x00 ~0x04 Analog Comparator 0 & 1Control Register */
314 __IO uint32_t CMPSR; /* Offset: 0x08 Analog Comparator 0/1 Status Register */
315 __IO uint32_t CMPRVCR; /* Offset: 0x0C Analog Comparator Reference Voltage Control Register */
316
317 } ACMP_T;
318
319
320
326 #define ACMP_CMPCR_ACMPEN_Pos (0)
327 #define ACMP_CMPCR_ACMPEN_Msk (0x1ul << ACMP_CMPCR_ACMPEN_Pos)
329 #define ACMP_CMPCR_ACMPIE_Pos (1)
330 #define ACMP_CMPCR_ACMPIE_Msk (0x1ul << ACMP_CMPCR_ACMPIE_Pos)
332 #define ACMP_CMPCR_HYSEN_Pos (2)
333 #define ACMP_CMPCR_HYSEN_Msk (0x1ul << ACMP_CMPCR_HYSEN_Pos)
335 #define ACMP_CMPCR_NEGSEL_Pos (4)
336 #define ACMP_CMPCR_NEGSEL_Msk (0x1ul << ACMP_CMPCR_NEGSEL_Pos)
338 #define ACMP_CMPCR_RISING_Pos (8)
339 #define ACMP_CMPCR_RISING_Msk (0x1ul << ACMP_CMPCR_RISING_Pos)
341 #define ACMP_CMPCR_FALLING_Pos (9)
342 #define ACMP_CMPCR_FALLING_Msk (0x1ul << ACMP_CMPCR_FALLING_Pos)
344 #define ACMP_CMPCR_CPPSEL_Pos (29)
345 #define ACMP_CMPCR_CPPSEL_Msk (0x3ul << ACMP_CMPCR_CPPSEL_Pos)
347 #define ACMP_CMPSR_ACMPF0_Pos (0)
348 #define ACMP_CMPSR_ACMPF0_Msk (0x1ul << ACMP_CMPSR_ACMPF0_Pos)
350 #define ACMP_CMPSR_ACMPF1_Pos (1)
351 #define ACMP_CMPSR_ACMPF1_Msk (0x1ul << ACMP_CMPSR_ACMPF1_Pos)
353 #define ACMP_CMPSR_ACMPCO0_Pos (2)
354 #define ACMP_CMPSR_ACMPCO0_Msk (0x1ul << ACMP_CMPSR_ACMPCO0_Pos)
356 #define ACMP_CMPSR_ACMPCO1_Pos (3)
357 #define ACMP_CMPSR_ACMPCO1_Msk (0x1ul << ACMP_CMPSR_ACMPCO1_Pos)
359 #define ACMP_CMPRVCR_CRVS_Pos (0)
360 #define ACMP_CMPRVCR_CRVS_Msk (0xful << ACMP_CMPRVCR_CRVS_Pos)
362 #define ACMP_CMPRVCR_OUT_SEL_Pos (7)
363 #define ACMP_CMPRVCR_OUT_SEL_Msk (0x1ul << ACMP_CMPRVCR_OUT_SEL_Pos) /* ACMP_CONST */
366 /* end of ACMP register group */
367
368
369 /*---------------------- Analog to Digital Converter -------------------------*/
376 typedef struct
377 {
790 __I uint32_t ADDR; /* Offset: 0x00 ADC Data Register */
792 __I uint32_t RESERVE0[7];
794 __IO uint32_t ADCR; /* Offset: 0x20 ADC Control Register */
795 __IO uint32_t ADCHER; /* Offset: 0x24 ADC Channel Enable Control Register */
796 __IO uint32_t ADCMPR[2]; /* Offset: 0x28, 0x2C A/D Compare Register 0 & 1 */
797 __IO uint32_t ADSR; /* Offset: 0x30 ADC Status Register */
799 __I uint32_t RESERVE1[4];
801 __IO uint32_t ADTDCR; /* Offset: 0x44 ADC Trigger Delay Control Register */
802 __IO uint32_t ADSAMP; /* Offset: 0x48 ADC Sampling Time Counter Register */
803
804 } ADC_T;
805
806
807
813 #define ADC_ADDR_RSLT_Pos (0)
814 #define ADC_ADDR_RSLT_Msk (0x3fful << ADC_ADDR_RSLT_Pos)
816 #define ADC_ADDR_OVERRUN_Pos (16)
817 #define ADC_ADDR_OVERRUN_Msk (0x1ul << ADC_ADDR_OVERRUN_Pos)
819 #define ADC_ADDR_VALID_Pos (17)
820 #define ADC_ADDR_VALID_Msk (0x1ul << ADC_ADDR_VALID_Pos)
822 #define ADC_ADCR_ADEN_Pos (0)
823 #define ADC_ADCR_ADEN_Msk (0x1ul << ADC_ADCR_ADEN_Pos)
825 #define ADC_ADCR_ADIE_Pos (1)
826 #define ADC_ADCR_ADIE_Msk (0x1ul << ADC_ADCR_ADIE_Pos)
828 #define ADC_ADCR_TRGS_Pos (4)
829 #define ADC_ADCR_TRGS_Msk (0x3ul << ADC_ADCR_TRGS_Pos)
831 #define ADC_ADCR_TRGCOND_Pos (6)
832 #define ADC_ADCR_TRGCOND_Msk (0x1ul << ADC_ADCR_TRGCOND_Pos)
834 #define ADC_ADCR_TRGEN_Pos (8)
835 #define ADC_ADCR_TRGEN_Msk (0x1ul << ADC_ADCR_TRGEN_Pos)
837 #define ADC_ADCR_ADST_Pos (11)
838 #define ADC_ADCR_ADST_Msk (0x1ul << ADC_ADCR_ADST_Pos)
840 #define ADC_ADCHER_CHEN_Pos (0)
841 #define ADC_ADCHER_CHEN_Msk (0xfful << ADC_ADCHER_CHEN_Pos)
843 #define ADC_ADCHER_CHEN0_Pos (0)
844 #define ADC_ADCHER_CHEN0_Msk (0x1ul << ADC_ADCHER_CHEN0_Pos)
846 #define ADC_ADCHER_CHEN1_Pos (1)
847 #define ADC_ADCHER_CHEN1_Msk (0x1ul << ADC_ADCHER_CHEN1_Pos)
849 #define ADC_ADCHER_CHEN2_Pos (2)
850 #define ADC_ADCHER_CHEN2_Msk (0x1ul << ADC_ADCHER_CHEN2_Pos)
852 #define ADC_ADCHER_CHEN3_Pos (3)
853 #define ADC_ADCHER_CHEN3_Msk (0x1ul << ADC_ADCHER_CHEN3_Pos)
855 #define ADC_ADCHER_CHEN4_Pos (4)
856 #define ADC_ADCHER_CHEN4_Msk (0x1ul << ADC_ADCHER_CHEN4_Pos)
858 #define ADC_ADCHER_CHEN5_Pos (5)
859 #define ADC_ADCHER_CHEN5_Msk (0x1ul << ADC_ADCHER_CHEN5_Pos)
861 #define ADC_ADCHER_CHEN6_Pos (6)
862 #define ADC_ADCHER_CHEN6_Msk (0x1ul << ADC_ADCHER_CHEN6_Pos)
864 #define ADC_ADCHER_CHEN7_Pos (7)
865 #define ADC_ADCHER_CHEN7_Msk (0x1ul << ADC_ADCHER_CHEN7_Pos)
867 #define ADC_ADCHER_PRESEL_Pos (8)
868 #define ADC_ADCHER_PRESEL_Msk (0x1ul << ADC_ADCHER_PRESEL_Pos)
870 #define ADC_ADCMPR_CMPEN_Pos (0)
871 #define ADC_ADCMPR_CMPEN_Msk (0x1ul << ADC_ADCMPR_CMPEN_Pos)
873 #define ADC_ADCMPR_CMPIE_Pos (1)
874 #define ADC_ADCMPR_CMPIE_Msk (0x1ul << ADC_ADCMPR_CMPIE_Pos)
876 #define ADC_ADCMPR_CMPCOND_Pos (2)
877 #define ADC_ADCMPR_CMPCOND_Msk (0x1ul << ADC_ADCMPR_CMPCOND_Pos)
879 #define ADC_ADCMPR_CMPCH_Pos (3)
880 #define ADC_ADCMPR_CMPCH_Msk (0x7ul << ADC_ADCMPR_CMPCH_Pos)
882 #define ADC_ADCMPR_CMPMATCNT_Pos (8)
883 #define ADC_ADCMPR_CMPMATCNT_Msk (0xful << ADC_ADCMPR_CMPMATCNT_Pos)
885 #define ADC_ADCMPR_CMPD_Pos (16)
886 #define ADC_ADCMPR_CMPD_Msk (0x3fful << ADC_ADCMPR_CMPD_Pos)
888 #define ADC_ADSR_ADF_Pos (0)
889 #define ADC_ADSR_ADF_Msk (0x1ul << ADC_ADSR_ADF_Pos)
891 #define ADC_ADSR_CMPF0_Pos (1)
892 #define ADC_ADSR_CMPF0_Msk (0x1ul << ADC_ADSR_CMPF0_Pos)
894 #define ADC_ADSR_CMPF1_Pos (2)
895 #define ADC_ADSR_CMPF1_Msk (0x1ul << ADC_ADSR_CMPF1_Pos)
897 #define ADC_ADSR_BUSY_Pos (3)
898 #define ADC_ADSR_BUSY_Msk (0x1ul << ADC_ADSR_BUSY_Pos)
900 #define ADC_ADSR_CHANNEL_Pos (4)
901 #define ADC_ADSR_CHANNEL_Msk (0x7ul << ADC_ADSR_CHANNEL_Pos)
903 #define ADC_ADSR_VALID_Pos (8)
904 #define ADC_ADSR_VALID_Msk (0x1ul << ADC_ADSR_VALID_Pos)
906 #define ADC_ADSR_OVERRUN_Pos (16)
907 #define ADC_ADSR_OVERRUN_Msk (0x1ul << ADC_ADSR_OVERRUN_Pos)
909 #define ADC_ADTDCR_PTDT_Pos (0)
910 #define ADC_ADTDCR_PTDT_Msk (0xfful << ADC_ADTDCR_PTDT_Pos)
912 #define ADC_ADSAMP_SAMPCNT_Pos (0)
913 #define ADC_ADSAMP_SAMPCNT_Msk (0xful << ADC_ADSAMP_SAMPCNT_Pos) /* ADC_CONST */
916 /* end of ADC register group */
917
918
919 /*---------------------- System Clock Controller -------------------------*/
926 typedef struct
927 {
928
1462 __IO uint32_t PWRCON; /* Offset: 0x00 System Power-down Control Register */
1463 __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
1464 __IO uint32_t APBCLK; /* Offset: 0x08 APB Devices Clock Enable Control Register */
1465 __IO uint32_t CLKSTATUS; /* Offset: 0x0C Clock Status Monitor Register */
1466 __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
1467 __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
1468 __IO uint32_t CLKDIV; /* Offset: 0x18 Clock Divider Number Register */
1469 __IO uint32_t CLKSEL2; /* Offset: 0x1C Clock Source Select Control Register 2 */
1471 __I uint32_t RESERVE0[1];
1473 __IO uint32_t FRQDIV; /* Offset: 0x24 Frequency Divider Control Register */
1474
1475 } CLK_T;
1476
1477
1478
1484 #define CLK_PWRCON_XTLCLK_EN_Pos (0)
1485 #define CLK_PWRCON_XTLCLK_EN_Msk (0x3ul << CLK_PWRCON_XTLCLK_EN_Pos)
1487 #define CLK_PWRCON_OSC22M_EN_Pos (2)
1488 #define CLK_PWRCON_OSC22M_EN_Msk (0x1ul << CLK_PWRCON_OSC22M_EN_Pos)
1489 #define CLK_PWRCON_IRC22M_EN_Pos (2)
1490 #define CLK_PWRCON_IRC22M_EN_Msk (0x1ul << CLK_PWRCON_IRC22M_EN_Pos)
1491 #define CLK_PWRCON_HIRC_EN_Pos (2)
1492 #define CLK_PWRCON_HIRC_EN_Msk (0x1ul << CLK_PWRCON_HIRC_EN_Pos)
1494 #define CLK_PWRCON_OSC10K_EN_Pos (3)
1495 #define CLK_PWRCON_OSC10K_EN_Msk (0x1ul << CLK_PWRCON_OSC10K_EN_Pos)
1496 #define CLK_PWRCON_IRC10K_EN_Pos (3)
1497 #define CLK_PWRCON_IRC10K_EN_Msk (0x1ul << CLK_PWRCON_IRC10K_EN_Pos)
1498 #define CLK_PWRCON_LIRC_EN_Pos (3)
1499 #define CLK_PWRCON_LIRC_EN_Msk (0x1ul << CLK_PWRCON_LIRC_EN_Pos)
1501 #define CLK_PWRCON_WU_DLY_Pos (4)
1502 #define CLK_PWRCON_WU_DLY_Msk (0x1ul << CLK_PWRCON_WU_DLY_Pos)
1504 #define CLK_PWRCON_WINT_EN_Pos (5)
1505 #define CLK_PWRCON_WINT_EN_Msk (0x1ul << CLK_PWRCON_WINT_EN_Pos)
1507 #define CLK_PWRCON_PD_WU_STS_Pos (6)
1508 #define CLK_PWRCON_PD_WU_STS_Msk (0x1ul << CLK_PWRCON_PD_WU_STS_Pos)
1510 #define CLK_PWRCON_PWR_DOWN_EN_Pos (7)
1511 #define CLK_PWRCON_PWR_DOWN_EN_Msk (0x1ul << CLK_PWRCON_PWR_DOWN_EN_Pos)
1513 #define CLK_PWRCON_PD_32K_Pos (9)
1514 #define CLK_PWRCON_PD_32K_Msk (0x1ul << CLK_PWRCON_PD_32K_Pos)
1516 #define CLK_AHBCLK_ISP_EN_Pos (2)
1517 #define CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos)
1519 #define CLK_APBCLK_WDT_EN_Pos (0)
1520 #define CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos)
1522 #define CLK_APBCLK_TMR0_EN_Pos (2)
1523 #define CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos)
1525 #define CLK_APBCLK_TMR1_EN_Pos (3)
1526 #define CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos)
1528 #define CLK_APBCLK_FDIV_EN_Pos (6)
1529 #define CLK_APBCLK_FDIV_EN_Msk (0x1ul << CLK_APBCLK_FDIV_EN_Pos)
1531 #define CLK_APBCLK_I2C_EN_Pos (8)
1532 #define CLK_APBCLK_I2C_EN_Msk (0x1ul << CLK_APBCLK_I2C_EN_Pos)
1534 #define CLK_APBCLK_SPI_EN_Pos (12)
1535 #define CLK_APBCLK_SPI_EN_Msk (0x1ul << CLK_APBCLK_SPI_EN_Pos)
1537 #define CLK_APBCLK_UART_EN_Pos (16)
1538 #define CLK_APBCLK_UART_EN_Msk (0x1ul << CLK_APBCLK_UART_EN_Pos)
1540 #define CLK_APBCLK_PWM01_EN_Pos (20)
1541 #define CLK_APBCLK_PWM01_EN_Msk (0x1ul << CLK_APBCLK_PWM01_EN_Pos)
1543 #define CLK_APBCLK_PWM23_EN_Pos (21)
1544 #define CLK_APBCLK_PWM23_EN_Msk (0x1ul << CLK_APBCLK_PWM23_EN_Pos)
1546 #define CLK_APBCLK_PWM45_EN_Pos (22)
1547 #define CLK_APBCLK_PWM45_EN_Msk (0x1ul << CLK_APBCLK_PWM45_EN_Pos)
1549 #define CLK_APBCLK_ADC_EN_Pos (28)
1550 #define CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos)
1552 #define CLK_APBCLK_CMP_EN_Pos (30)
1553 #define CLK_APBCLK_CMP_EN_Msk (0x1ul << CLK_APBCLK_CMP_EN_Pos)
1555 #define CLK_CLKSTATUS_XTL_STB_Pos (0)
1556 #define CLK_CLKSTATUS_XTL_STB_Msk (0x1ul << CLK_CLKSTATUS_XTL_STB_Pos)
1557 #define CLK_CLKSTATUS_HXT_STB_Pos (0)
1558 #define CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos)
1559 #define CLK_CLKSTATUS_LXT_STB_Pos (0)
1560 #define CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos)
1562 #define CLK_CLKSTATUS_OSC10K_STB_Pos (3)
1563 #define CLK_CLKSTATUS_OSC10K_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC10K_STB_Pos)
1564 #define CLK_CLKSTATUS_IRC10K_STB_Pos (3)
1565 #define CLK_CLKSTATUS_IRC10K_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC10K_STB_Pos)
1566 #define CLK_CLKSTATUS_LIRC_STB_Pos (3)
1567 #define CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos)
1569 #define CLK_CLKSTATUS_OSC22M_STB_Pos (4)
1570 #define CLK_CLKSTATUS_OSC22M_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC22M_STB_Pos)
1571 #define CLK_CLKSTATUS_IRC22M_STB_Pos (4)
1572 #define CLK_CLKSTATUS_IRC22M_STB_Msk (0x1ul << CLK_CLKSTATUS_OSC22M_STB_Pos)
1573 #define CLK_CLKSTATUS_HIRC_STB_Pos (4)
1574 #define CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos)
1576 #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7)
1577 #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos)
1579 #define CLK_CLKSEL0_HCLK_S_Pos (0)
1580 #define CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos)
1582 #define CLK_CLKSEL0_STCLK_S_Pos (3)
1583 #define CLK_CLKSEL0_STCLK_S_Msk (0x7ul << CLK_CLKSEL0_STCLK_S_Pos)
1585 #define CLK_CLKSEL1_WDT_S_Pos (0)
1586 #define CLK_CLKSEL1_WDT_S_Msk (0x3ul << CLK_CLKSEL1_WDT_S_Pos)
1588 #define CLK_CLKSEL1_ADC_S_Pos (2)
1589 #define CLK_CLKSEL1_ADC_S_Msk (0x3ul << CLK_CLKSEL1_ADC_S_Pos)
1591 #define CLK_CLKSEL1_SPI_S_Pos (4)
1592 #define CLK_CLKSEL1_SPI_S_Msk (0x1ul << CLK_CLKSEL1_SPI_S_Pos)
1594 #define CLK_CLKSEL1_TMR0_S_Pos (8)
1595 #define CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos)
1597 #define CLK_CLKSEL1_TMR1_S_Pos (12)
1598 #define CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos)
1600 #define CLK_CLKSEL1_UART_S_Pos (24)
1601 #define CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos)
1603 #define CLK_CLKDIV_HCLK_N_Pos (0)
1604 #define CLK_CLKDIV_HCLK_N_Msk (0xful << CLK_CLKDIV_HCLK_N_Pos)
1606 #define CLK_CLKDIV_UART_N_Pos (8)
1607 #define CLK_CLKDIV_UART_N_Msk (0xful << CLK_CLKDIV_UART_N_Pos)
1609 #define CLK_CLKDIV_ADC_N_Pos (16)
1610 #define CLK_CLKDIV_ADC_N_Msk (0xfful << CLK_CLKDIV_ADC_N_Pos)
1612 #define CLK_CLKSEL2_FRQDIV_S_Pos (2)
1613 #define CLK_CLKSEL2_FRQDIV_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV_S_Pos)
1615 #define CLK_FRQDIV_FSEL_Pos (0)
1616 #define CLK_FRQDIV_FSEL_Msk (0xful << CLK_FRQDIV_FSEL_Pos)
1618 #define CLK_FRQDIV_DIVIDER_EN_Pos (4)
1619 #define CLK_FRQDIV_DIVIDER_EN_Msk (0x1ul << CLK_FRQDIV_DIVIDER_EN_Pos)
1621 #define CLK_FRQDIV_DIVIDER1_Pos (5)
1622 #define CLK_FRQDIV_DIVIDER1_Msk (0x1ul << CLK_FRQDIV_DIVIDER1_Pos) /* CLK_CONST */
1625 /* end of CLK register group */
1626
1627
1628 /*---------------------- Flash Memory Controller -------------------------*/
1635 typedef struct
1636 {
1637
1878 __IO uint32_t ISPCON; /* Offset: 0x00 ISP Control Register */
1879 __IO uint32_t ISPADR; /* Offset: 0x04 ISP Address Register */
1880 __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
1881 __IO uint32_t ISPCMD; /* Offset: 0x0C ISP Command Register */
1882 __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Register */
1883 __I uint32_t DFBADR; /* Offset: 0x14 Data Flash Start Address */
1885 __I uint32_t RESERVE0[10];
1887 __I uint32_t ISPSTA; /* Offset: 0x40 ISP Status Register */
1888
1889 } FMC_T;
1890
1891
1892
1898 #define FMC_ISPCON_ISPEN_Pos (0)
1899 #define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos)
1901 #define FMC_ISPCON_BS_Pos (1)
1902 #define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos)
1904 #define FMC_ISPCON_APUEN_Pos (3)
1905 #define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos)
1907 #define FMC_ISPCON_CFGUEN_Pos (4)
1908 #define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos)
1910 #define FMC_ISPCON_LDUEN_Pos (5)
1911 #define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos)
1913 #define FMC_ISPCON_ISPFF_Pos (6)
1914 #define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos)
1916 #define FMC_ISPADR_ISPADR_Pos (0)
1917 #define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos)
1919 #define FMC_ISPDAT_ISPDAT_Pos (0)
1920 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
1922 #define FMC_ISPCMD_ISPCMD_Pos (0)
1923 #define FMC_ISPCMD_ISPCMD_Msk (0x3ful << FMC_ISPCMD_ISPCMD_Pos)
1925 #define FMC_ISPTRG_ISPGO_Pos (0)
1926 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
1928 #define FMC_DFBADR_DFBA_Pos (0)
1929 #define FMC_DFBADR_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
1931 #define FMC_ISPSTA_ISPGO_Pos (0)
1932 #define FMC_ISPSTA_ISPGO_Msk (0x1ul << FMC_ISPSTA_ISPGO_Pos)
1934 #define FMC_ISPSTA_CBS_Pos (1)
1935 #define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos)
1937 #define FMC_ISPSTA_ISPFF_Pos (6)
1938 #define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos)
1940 #define FMC_ISPSTA_VECMAP_Pos (9)
1941 #define FMC_ISPSTA_VECMAP_Msk (0xffful << FMC_ISPSTA_VECMAP_Pos) /* FMC_CONST */
1944 /* end of FMC register group */
1945
1946
1947 /*---------------------- System Global Control Registers -------------------------*/
1954 typedef struct
1955 {
1956
2680 __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
2681 __IO uint32_t RSTSRC; /* Offset: 0x04 System Reset Source Register */
2682 __IO uint32_t IPRSTC1; /* Offset: 0x08 Peripheral Reset Control Resister 1 */
2683 __IO uint32_t IPRSTC2; /* Offset: 0x0C Peripheral Reset Control Resister 2 */
2685 __I uint32_t RESERVE0[2];
2687 __IO uint32_t BODCTL; /* Offset: 0x18 Brown-out Detector Control Register */
2689 __I uint32_t RESERVE1[5];
2691 __IO uint32_t P0_MFP; /* Offset: 0x30 P0 Multiple Function and Input Type Control Register */
2692 __IO uint32_t P1_MFP; /* Offset: 0x34 P1 Multiple Function and Input Type Control Register */
2693 __IO uint32_t P2_MFP; /* Offset: 0x38 P2 Multiple Function and Input Type Control Register */
2694 __IO uint32_t P3_MFP; /* Offset: 0x3C P3 Multiple Function and Input Type Control Register */
2695 __IO uint32_t P4_MFP; /* Offset: 0x40 P4 Multiple Function and Input Type Control Register */
2696 __IO uint32_t P5_MFP; /* Offset: 0x44 P5 Multiple Function and Input Type Control Register */
2698 __I uint32_t RESERVE2[14];
2700 __IO uint32_t IRCTRIMCTL; /* Offset: 0x80 HIRC Trim Control Register */
2701 __IO uint32_t IRCTRIMIER; /* Offset: 0x84 HIRC Trim Interrupt Enable Control Register */
2702 __IO uint32_t IRCTRIMISR; /* Offset: 0x88 HIRC Trim Interrupt Status Register */
2704 __IO uint32_t RESERVE3[29];
2706 __IO uint32_t RegLockAddr; /* Offset: 0x100 Register Write-Protection Control Register */
2707
2708 } GCR_T;
2709
2710
2711
2717 #define SYS_PDID_PDID_Pos (0)
2718 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
2720 #define SYS_RSTSRC_RSTS_POR_Pos (0)
2721 #define SYS_RSTSRC_RSTS_POR_Msk (0x1ul << SYS_RSTSRC_RSTS_POR_Pos)
2723 #define SYS_RSTSRC_RSTS_RESET_Pos (1)
2724 #define SYS_RSTSRC_RSTS_RESET_Msk (0x1ul << SYS_RSTSRC_RSTS_RESET_Pos)
2726 #define SYS_RSTSRC_RSTS_WDT_Pos (2)
2727 #define SYS_RSTSRC_RSTS_WDT_Msk (0x1ul << SYS_RSTSRC_RSTS_WDT_Pos)
2729 #define SYS_RSTSRC_RSTS_BOD_Pos (4)
2730 #define SYS_RSTSRC_RSTS_BOD_Msk (0x1ul << SYS_RSTSRC_RSTS_BOD_Pos)
2732 #define SYS_RSTSRC_RSTS_MCU_Pos (5)
2733 #define SYS_RSTSRC_RSTS_MCU_Msk (0x1ul << SYS_RSTSRC_RSTS_MCU_Pos)
2735 #define SYS_RSTSRC_RSTS_CPU_Pos (7)
2736 #define SYS_RSTSRC_RSTS_CPU_Msk (0x1ul << SYS_RSTSRC_RSTS_CPU_Pos)
2738 #define SYS_IPRSTC1_CHIP_RST_Pos (0)
2739 #define SYS_IPRSTC1_CHIP_RST_Msk (0x1ul << SYS_IPRSTC1_CHIP_RST_Pos)
2741 #define SYS_IPRSTC1_CPU_RST_Pos (1)
2742 #define SYS_IPRSTC1_CPU_RST_Msk (0x1ul << SYS_IPRSTC1_CPU_RST_Pos)
2744 #define SYS_IPRSTC2_GPIO_RST_Pos (1)
2745 #define SYS_IPRSTC2_GPIO_RST_Msk (0x1ul << SYS_IPRSTC2_GPIO_RST_Pos)
2747 #define SYS_IPRSTC2_TMR0_RST_Pos (2)
2748 #define SYS_IPRSTC2_TMR0_RST_Msk (0x1ul << SYS_IPRSTC2_TMR0_RST_Pos)
2750 #define SYS_IPRSTC2_TMR1_RST_Pos (3)
2751 #define SYS_IPRSTC2_TMR1_RST_Msk (0x1ul << SYS_IPRSTC2_TMR1_RST_Pos)
2753 #define SYS_IPRSTC2_I2C_RST_Pos (8)
2754 #define SYS_IPRSTC2_I2C_RST_Msk (0x1ul << SYS_IPRSTC2_I2C_RST_Pos)
2756 #define SYS_IPRSTC2_SPI_RST_Pos (12)
2757 #define SYS_IPRSTC2_SPI_RST_Msk (0x1ul << SYS_IPRSTC2_SPI_RST_Pos)
2759 #define SYS_IPRSTC2_UART_RST_Pos (16)
2760 #define SYS_IPRSTC2_UART_RST_Msk (0x1ul << SYS_IPRSTC2_UART_RST_Pos)
2762 #define SYS_IPRSTC2_PWM_RST_Pos (20)
2763 #define SYS_IPRSTC2_PWM_RST_Msk (0x1ul << SYS_IPRSTC2_PWM_RST_Pos)
2765 #define SYS_IPRSTC2_ACMP_RST_Pos (22)
2766 #define SYS_IPRSTC2_ACMP_RST_Msk (0x1ul << SYS_IPRSTC2_ACMP_RST_Pos)
2768 #define SYS_IPRSTC2_ADC_RST_Pos (28)
2769 #define SYS_IPRSTC2_ADC_RST_Msk (0x1ul << SYS_IPRSTC2_ADC_RST_Pos)
2771 #define SYS_BODCR_BOD_VL_EXT_Pos (0)
2772 #define SYS_BODCR_BOD_VL_EXT_Msk (0x1ul << SYS_BODCR_BOD_VL_EXT_Pos)
2774 #define SYS_BODCR_BOD_VL_Pos (1)
2775 #define SYS_BODCR_BOD_VL_Msk (0x3ul << SYS_BODCR_BOD_VL_Pos)
2777 #define SYS_BODCR_BOD_RSTEN_Pos (3)
2778 #define SYS_BODCR_BOD_RSTEN_Msk (0x1ul << SYS_BODCR_BOD_RSTEN_Pos)
2780 #define SYS_BODCR_BOD_INTF_Pos (4)
2781 #define SYS_BODCR_BOD_INTF_Msk (0x1ul << SYS_BODCR_BOD_INTF_Pos)
2783 #define SYS_BODCR_BOD_LPM_Pos (5)
2784 #define SYS_BODCR_BOD_LPM_Msk (0x1ul << SYS_BODCR_BOD_LPM_Pos)
2786 #define SYS_BODCR_BOD_OUT_Pos (6)
2787 #define SYS_BODCR_BOD_OUT_Msk (0x1ul << SYS_BODCR_BOD_OUT_Pos)
2789 #define SYS_P0_MFP_P0_MFP_Pos (0)
2790 #define SYS_P0_MFP_P0_MFP_Msk (0xfful << SYS_P0_MFP_P0_MFP_Pos)
2792 #define SYS_P0_MFP_P0_ALT_Pos (8)
2793 #define SYS_P0_MFP_P0_ALT_Msk (0xfful << SYS_P0_MFP_P0_ALT_Pos)
2795 #define SYS_P0_MFP_P0_ALT0_Pos (8)
2796 #define SYS_P0_MFP_P0_ALT0_Msk (0x1ul << SYS_P0_MFP_P0_ALT0_Pos)
2798 #define SYS_P0_MFP_P0_ALT1_Pos (9)
2799 #define SYS_P0_MFP_P0_ALT1_Msk (0x1ul << SYS_P0_MFP_P0_ALT1_Pos)
2801 #define SYS_P0_MFP_P0_ALT4_Pos (12)
2802 #define SYS_P0_MFP_P0_ALT4_Msk (0x1ul << SYS_P0_MFP_P0_ALT4_Pos)
2804 #define SYS_P0_MFP_P0_ALT5_Pos (13)
2805 #define SYS_P0_MFP_P0_ALT5_Msk (0x1ul << SYS_P0_MFP_P0_ALT5_Pos)
2807 #define SYS_P0_MFP_P0_ALT6_Pos (14)
2808 #define SYS_P0_MFP_P0_ALT6_Msk (0x1ul << SYS_P0_MFP_P0_ALT6_Pos)
2810 #define SYS_P0_MFP_P0_ALT7_Pos (15)
2811 #define SYS_P0_MFP_P0_ALT7_Msk (0x1ul << SYS_P0_MFP_P0_ALT7_Pos)
2813 #define SYS_P0_MFP_P0_TYPE_Pos (16)
2814 #define SYS_P0_MFP_P0_TYPE_Msk (0xfful << SYS_P0_MFP_P0_TYPE_Pos)
2816 #define SYS_P1_MFP_P1_MFP_Pos (0)
2817 #define SYS_P1_MFP_P1_MFP_Msk (0xfful << SYS_P1_MFP_P1_MFP_Pos)
2819 #define SYS_P1_MFP_P1_ALT_Pos (8)
2820 #define SYS_P1_MFP_P1_ALT_Msk (0xfful << SYS_P1_MFP_P1_ALT_Pos)
2822 #define SYS_P1_MFP_P1_ALT0_Pos (8)
2823 #define SYS_P1_MFP_P1_ALT0_Msk (0x1ul << SYS_P1_MFP_P1_ALT0_Pos)
2825 #define SYS_P1_MFP_P1_ALT2_Pos (10)
2826 #define SYS_P1_MFP_P1_ALT2_Msk (0x1ul << SYS_P1_MFP_P1_ALT2_Pos)
2828 #define SYS_P1_MFP_P1_ALT3_Pos (11)
2829 #define SYS_P1_MFP_P1_ALT3_Msk (0x1ul << SYS_P1_MFP_P1_ALT3_Pos)
2831 #define SYS_P1_MFP_P1_ALT4_Pos (12)
2832 #define SYS_P1_MFP_P1_ALT4_Msk (0x1ul << SYS_P1_MFP_P1_ALT4_Pos)
2834 #define SYS_P1_MFP_P1_ALT5_Pos (13)
2835 #define SYS_P1_MFP_P1_ALT5_Msk (0x1ul << SYS_P1_MFP_P1_ALT5_Pos)
2837 #define SYS_P1_MFP_P1_TYPE_Pos (16)
2838 #define SYS_P1_MFP_P1_TYPE_Msk (0xfful << SYS_P1_MFP_P1_TYPE_Pos)
2840 #define SYS_P2_MFP_P2_MFP_Pos (0)
2841 #define SYS_P2_MFP_P2_MFP_Msk (0xfful << SYS_P2_MFP_P2_MFP_Pos)
2843 #define SYS_P2_MFP_P2_ALT_Pos (8)
2844 #define SYS_P2_MFP_P2_ALT_Msk (0xfful << SYS_P2_MFP_P2_ALT_Pos)
2846 #define SYS_P2_MFP_P2_ALT2_Pos (10)
2847 #define SYS_P2_MFP_P2_ALT2_Msk (0x1ul << SYS_P2_MFP_P2_ALT2_Pos)
2849 #define SYS_P2_MFP_P2_ALT3_Pos (11)
2850 #define SYS_P2_MFP_P2_ALT3_Msk (0x1ul << SYS_P2_MFP_P2_ALT3_Pos)
2852 #define SYS_P2_MFP_P2_ALT4_Pos (12)
2853 #define SYS_P2_MFP_P2_ALT4_Msk (0x1ul << SYS_P2_MFP_P2_ALT4_Pos)
2855 #define SYS_P2_MFP_P2_ALT5_Pos (13)
2856 #define SYS_P2_MFP_P2_ALT5_Msk (0x1ul << SYS_P2_MFP_P2_ALT5_Pos)
2858 #define SYS_P2_MFP_P2_ALT6_Pos (14)
2859 #define SYS_P2_MFP_P2_ALT6_Msk (0x1ul << SYS_P2_MFP_P2_ALT6_Pos)
2861 #define SYS_P2_MFP_P2_TYPE_Pos (16)
2862 #define SYS_P2_MFP_P2_TYPE_Msk (0xfful << SYS_P2_MFP_P2_TYPE_Pos)
2864 #define SYS_P3_MFP_P3_MFP_Pos (0)
2865 #define SYS_P3_MFP_P3_MFP_Msk (0xfful << SYS_P3_MFP_P3_MFP_Pos)
2867 #define SYS_P3_MFP_P3_ALT_Pos (8)
2868 #define SYS_P3_MFP_P3_ALT_Msk (0xfful << SYS_P3_MFP_P3_ALT_Pos)
2870 #define SYS_P3_MFP_P3_ALT0_Pos (8)
2871 #define SYS_P3_MFP_P3_ALT0_Msk (0x1ul << SYS_P3_MFP_P3_ALT0_Pos)
2873 #define SYS_P3_MFP_P3_ALT1_Pos (9)
2874 #define SYS_P3_MFP_P3_ALT1_Msk (0x1ul << SYS_P3_MFP_P3_ALT1_Pos)
2876 #define SYS_P3_MFP_P3_ALT2_Pos (10)
2877 #define SYS_P3_MFP_P3_ALT2_Msk (0x1ul << SYS_P3_MFP_P3_ALT2_Pos)
2879 #define SYS_P3_MFP_P3_ALT4_Pos (12)
2880 #define SYS_P3_MFP_P3_ALT4_Msk (0x1ul << SYS_P3_MFP_P3_ALT4_Pos)
2882 #define SYS_P3_MFP_P3_ALT5_Pos (13)
2883 #define SYS_P3_MFP_P3_ALT5_Msk (0x1ul << SYS_P3_MFP_P3_ALT5_Pos)
2885 #define SYS_P3_MFP_P3_ALT6_Pos (14)
2886 #define SYS_P3_MFP_P3_ALT6_Msk (0x1ul << SYS_P3_MFP_P3_ALT6_Pos)
2888 #define SYS_P3_MFP_P3_TYPE_Pos (16)
2889 #define SYS_P3_MFP_P3_TYPE_Msk (0xfful << SYS_P3_MFP_P3_TYPE_Pos)
2891 #define SYS_P3_MFP_P32CPP1_Pos (24)
2892 #define SYS_P3_MFP_P32CPP1_Msk (0x1ul << SYS_P3_MFP_P32CPP1_Pos)
2894 #define SYS_P4_MFP_P4_MFP_Pos (0)
2895 #define SYS_P4_MFP_P4_MFP_Msk (0xfful << SYS_P4_MFP_P4_MFP_Pos)
2897 #define SYS_P4_MFP_P4_ALT_Pos (8)
2898 #define SYS_P4_MFP_P4_ALT_Msk (0xfful << SYS_P4_MFP_P4_ALT_Pos)
2900 #define SYS_P4_MFP_P4_ALT6_Pos (14)
2901 #define SYS_P4_MFP_P4_ALT6_Msk (0x1ul << SYS_P4_MFP_P4_ALT6_Pos)
2903 #define SYS_P4_MFP_P4_ALT7_Pos (15)
2904 #define SYS_P4_MFP_P4_ALT7_Msk (0x1ul << SYS_P4_MFP_P4_ALT7_Pos)
2906 #define SYS_P4_MFP_P4_TYPE_Pos (16)
2907 #define SYS_P4_MFP_P4_TYPE_Msk (0xfful << SYS_P4_MFP_P4_TYPE_Pos)
2909 #define SYS_P5_MFP_P5_MFP_Pos (0)
2910 #define SYS_P5_MFP_P5_MFP_Msk (0xfful << SYS_P5_MFP_P5_MFP_Pos)
2912 #define SYS_P5_MFP_P5_ALT_Pos (8)
2913 #define SYS_P5_MFP_P5_ALT_Msk (0xFFul << SYS_P5_MFP_P5_ALT_Pos)
2915 #define SYS_P5_MFP_P5_ALT0_Pos (8)
2916 #define SYS_P5_MFP_P5_ALT0_Msk (0x1ul << SYS_P5_MFP_P5_ALT0_Pos)
2918 #define SYS_P5_MFP_P5_ALT1_Pos (9)
2919 #define SYS_P5_MFP_P5_ALT1_Msk (0x1ul << SYS_P5_MFP_P5_ALT1_Pos)
2921 #define SYS_P5_MFP_P5_ALT2_Pos (10)
2922 #define SYS_P5_MFP_P5_ALT2_Msk (0x1ul << SYS_P5_MFP_P5_ALT2_Pos)
2924 #define SYS_P5_MFP_P5_ALT3_Pos (11)
2925 #define SYS_P5_MFP_P5_ALT3_Msk (0x1ul << SYS_P5_MFP_P5_ALT3_Pos)
2927 #define SYS_P5_MFP_P5_ALT4_Pos (12)
2928 #define SYS_P5_MFP_P5_ALT4_Msk (0x1ul << SYS_P5_MFP_P5_ALT4_Pos)
2930 #define SYS_P5_MFP_P5_ALT5_Pos (13)
2931 #define SYS_P5_MFP_P5_ALT5_Msk (0x1ul << SYS_P5_MFP_P5_ALT5_Pos)
2933 #define SYS_P5_MFP_P5_TYPE_Pos (16)
2934 #define SYS_P5_MFP_P5_TYPE_Msk (0xfful << SYS_P5_MFP_P5_TYPE_Pos)
2936 #define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0)
2937 #define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x1ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos)
2939 #define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4)
2940 #define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos)
2942 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1)
2943 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos)
2945 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2)
2946 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos)
2948 #define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0)
2949 #define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos)
2951 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1)
2952 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos)
2954 #define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2)
2955 #define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos)
2957 #define SYS_RegLockAddr_RegUnLock_Pos 0
2958 #define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) /* GCR_CONST */
2961 /* end of GCR register group */
2962
2963
2964 /*---------------------- General Purpose Input/Output Controller -------------------------*/
2971 typedef struct
2972 {
2973
3569 __IO uint32_t PMD; /* Offset: 0x00 Px I/O Mode Control */
3570 __IO uint32_t OFFD; /* Offset: 0x04 Px Digital Input Path Disable Control */
3571 __IO uint32_t DOUT; /* Offset: 0x08 Px Data Output Value */
3572 __IO uint32_t DMASK; /* Offset: 0x0C Px Data Output Write Mask */
3573 __I uint32_t PIN; /* Offset: 0x10 Px Pin Value */
3574 __IO uint32_t DBEN; /* Offset: 0x14 Px De-bounce Enable Control */
3575 __IO uint32_t IMD; /* Offset: 0x18 Px Interrupt Mode Control */
3576 __IO uint32_t IEN; /* Offset: 0x1C Px Interrupt Enable Control */
3577 __IO uint32_t ISRC; /* Offset: 0x20 Px Interrupt Source Flag */
3578 } GPIO_T;
3579
3583 typedef struct
3584 {
3652 __IO uint32_t DBNCECON; /* Offset: 0x00 Interrupt De-bounce Control */
3653 } GPIO_DBNCECON_T;
3654
3655
3656
3662 #define GPIO_PMD_PMD0_Pos (0)
3663 #define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos)
3665 #define GPIO_PMD_PMD1_Pos (2)
3666 #define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos)
3668 #define GPIO_PMD_PMD2_Pos (4)
3669 #define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos)
3671 #define GPIO_PMD_PMD3_Pos (6)
3672 #define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos)
3674 #define GPIO_PMD_PMD4_Pos (8)
3675 #define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos)
3677 #define GPIO_PMD_PMD5_Pos (10)
3678 #define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos)
3680 #define GPIO_PMD_PMD6_Pos (12)
3681 #define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos)
3683 #define GPIO_PMD_PMD7_Pos (14)
3684 #define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos)
3686 #define GPIO_OFFD_OFFD_Pos (16)
3687 #define GPIO_OFFD_OFFD_Msk (0xfful << GPIO_OFFD_OFFD_Pos)
3689 #define GPIO_DOUT_DOUT_Pos (0)
3690 #define GPIO_DOUT_DOUT_Msk (0xfful << GPIO_DOUT_DOUT_Pos)
3692 #define GPIO_DMASK_DMASK_Pos (0)
3693 #define GPIO_DMASK_DMASK_Msk (0xfful << GPIO_DMASK_DMASK_Pos)
3695 #define GPIO_PIN_PIN_Pos (0)
3696 #define GPIO_PIN_PIN_Msk (0xfful << GPIO_PIN_PIN_Pos)
3698 #define GPIO_DBEN_DBEN_Pos (0)
3699 #define GPIO_DBEN_DBEN_Msk (0xfful << GPIO_DBEN_DBEN_Pos)
3701 #define GPIO_IMD_IMD_Pos (0)
3702 #define GPIO_IMD_IMD_Msk (0xfful << GPIO_IMD_IMD_Pos)
3704 #define GPIO_IEN_IF_EN_Pos (0)
3705 #define GPIO_IEN_IF_EN_Msk (0x1ul << GPIO_IEN_IF_EN_Pos)
3707 #define GPIO_IEN_IR_EN_Pos (16)
3708 #define GPIO_IEN_IR_EN_Msk (0xfful << GPIO_IEN_IR_EN_Pos)
3710 #define GPIO_ISRC_ISRC_Pos (0)
3711 #define GPIO_ISRC_ISRC_Msk (0xfful << GPIO_ISRC_ISRC_Pos)
3713 #define GPIO_DBNCECON_DBCLKSEL_Pos (0)
3714 #define GPIO_DBNCECON_DBCLKSEL_Msk (0xful << GPIO_DBNCECON_DBCLKSEL_Pos)
3716 #define GPIO_DBNCECON_DBCLKSRC_Pos (4)
3717 #define GPIO_DBNCECON_DBCLKSRC_Msk (0x1ul << GPIO_DBNCECON_DBCLKSRC_Pos)
3719 #define GPIO_DBNCECON_ICLK_ON_Pos (5)
3720 #define GPIO_DBNCECON_ICLK_ON_Msk (0x1ul << GPIO_DBNCECON_ICLK_ON_Pos) /* GP_CONST */
3723 /* end of GP register group */
3724
3725
3726 /*---------------------- Inter-IC Bus Controller -------------------------*/
3733 typedef struct
3734 {
3735
4221 __IO uint32_t I2CON; /* Offset: 0x00 I2C Control Register */
4222 __IO uint32_t I2CADDR0; /* Offset: 0x04 I2C Slave Address Register 0 */
4223 __IO uint32_t I2CDAT; /* Offset: 0x08 I2C DATA Register */
4224 __I uint32_t I2CSTATUS; /* Offset: 0x0C I2C Status Register */
4225 __IO uint32_t I2CLK; /* Offset: 0x10 I2C Clock Divided Register */
4226 __IO uint32_t I2CTOC; /* Offset: 0x14 I2C Time-Out Counter Register */
4227 __IO uint32_t I2CADDR1; /* Offset: 0x18 I2C Slave Address Register 1 */
4228 __IO uint32_t I2CADDR2; /* Offset: 0x1C I2C Slave Address Register 2 */
4229 __IO uint32_t I2CADDR3; /* Offset: 0x20 I2C Slave Address Register 3 */
4230 __IO uint32_t I2CADM0; /* Offset: 0x24 I2C Slave Address Mask Register 0 */
4231 __IO uint32_t I2CADM1; /* Offset: 0x28 I2C Slave Address Mask Register 1 */
4232 __IO uint32_t I2CADM2; /* Offset: 0x2C I2C Slave Address Mask Register 2 */
4233 __IO uint32_t I2CADM3; /* Offset: 0x30 I2C Slave Address Mask Register 3 */
4235 __I uint32_t RESERVE0[2];
4237 __IO uint32_t I2CON2; /* Offset: 0x3C I2C Control Register 2 */
4238 __IO uint32_t I2CSTATUS2; /* Offset: 0x40 I2C Status Register 2 */
4239
4240 } I2C_T;
4241
4242
4243
4249 #define I2C_I2CON_AA_Pos (2)
4250 #define I2C_I2CON_AA_Msk (0x1ul << I2C_I2CON_AA_Pos)
4252 #define I2C_I2CON_SI_Pos (3)
4253 #define I2C_I2CON_SI_Msk (0x1ul << I2C_I2CON_SI_Pos)
4255 #define I2C_I2CON_STO_Pos (4)
4256 #define I2C_I2CON_STO_Msk (0x1ul << I2C_I2CON_STO_Pos)
4258 #define I2C_I2CON_STA_Pos (5)
4259 #define I2C_I2CON_STA_Msk (0x1ul << I2C_I2CON_STA_Pos)
4261 #define I2C_I2CON_ENSI_Pos (6)
4262 #define I2C_I2CON_ENSI_Msk (0x1ul << I2C_I2CON_ENSI_Pos)
4264 #define I2C_I2CON_EI_Pos (7)
4265 #define I2C_I2CON_EI_Msk (0x1ul << I2C_I2CON_EI_Pos)
4267 #define I2C_I2CADDR_GC_Pos (0)
4268 #define I2C_I2CADDR_GC_Msk (0x1ul << I2C_I2CADDR_GC_Pos)
4270 #define I2C_I2CADDR_I2CADDR_Pos (1)
4271 #define I2C_I2CADDR_I2CADDR_Msk (0x7ful << I2C_I2CADDR_I2CADDR_Pos)
4273 #define I2C_I2CDAT_I2CDAT_Pos (0)
4274 #define I2C_I2CDAT_I2CDAT_Msk (0xfful << I2C_I2CDAT_I2CDAT_Pos)
4276 #define I2C_I2CSTATUS_I2CSTATUS_Pos (0)
4277 #define I2C_I2CSTATUS_I2CSTATUS_Msk (0xfful << I2C_I2CSTATUS_I2CSTATUS_Pos)
4279 #define I2C_I2CLK_I2CLK_Pos (0)
4280 #define I2C_I2CLK_I2CLK_Msk (0xfful << I2C_I2CLK_I2CLK_Pos)
4282 #define I2C_I2CTOC_TIF_Pos (0)
4283 #define I2C_I2CTOC_TIF_Msk (0x1ul << I2C_I2CTOC_TIF_Pos)
4285 #define I2C_I2CTOC_DIV4_Pos (1)
4286 #define I2C_I2CTOC_DIV4_Msk (0x1ul << I2C_I2CTOC_DIV4_Pos)
4288 #define I2C_I2CTOC_ENTI_Pos (2)
4289 #define I2C_I2CTOC_ENTI_Msk (0x1ul << I2C_I2CTOC_ENTI_Pos)
4291 #define I2C_I2CADM_I2CADM_Pos (1)
4292 #define I2C_I2CADM_I2CADM_Msk (0x7ful << I2C_I2CADM_I2CADM_Pos)
4294 #define I2C_I2CON2_WKUPEN_Pos (0)
4295 #define I2C_I2CON2_WKUPEN_Msk (0x1ul << I2C_I2CON2_WKUPEN_Pos)
4297 #define I2C_I2CON2_TWOFF_EN_Pos (1)
4298 #define I2C_I2CON2_TWOFF_EN_Msk (0x1ul << I2C_I2CON2_TWOFF_EN_Pos)
4300 #define I2C_I2CON2_NOSTRETCH_Pos (2)
4301 #define I2C_I2CON2_NOSTRETCH_Msk (0x1ul << I2C_I2CON2_NOSTRETCH_Pos)
4303 #define I2C_I2CON2_OVER_INTEN_Pos (3)
4304 #define I2C_I2CON2_OVER_INTEN_Msk (0x1ul << I2C_I2CON2_OVER_INTEN_Pos)
4306 #define I2C_I2CON2_UNDER_INTEN_Pos (4)
4307 #define I2C_I2CON2_UNDER_INTEN_Msk (0x1ul << I2C_I2CON2_UNDER_INTEN_Pos)
4309 #define I2C_I2CSTATUS2_WAKEUP_Pos (0)
4310 #define I2C_I2CSTATUS2_WAKEUP_Msk (0x1ul << I2C_I2CSTATUS2_WAKEUP_Pos)
4312 #define I2C_I2CSTATUS2_FULL_Pos (1)
4313 #define I2C_I2CSTATUS2_FULL_Msk (0x1ul << I2C_I2CSTATUS2_FULL_Pos)
4315 #define I2C_I2CSTATUS2_EMPTY_Pos (2)
4316 #define I2C_I2CSTATUS2_EMPTY_Msk (0x1ul << I2C_I2CSTATUS2_EMPTY_Pos)
4318 #define I2C_I2CSTATUS2_OVERUN_Pos (3)
4319 #define I2C_I2CSTATUS2_OVERUN_Msk (0x1ul << I2C_I2CSTATUS2_OVERUN_Pos)
4321 #define I2C_I2CSTATUS2_UNDERUN_Pos (4)
4322 #define I2C_I2CSTATUS2_UNDERUN_Msk (0x1ul << I2C_I2CSTATUS2_UNDERUN_Pos) /* I2C_CONST */
4325 /* end of I2C register group */
4326
4327
4328 /*---------------------- INT Controller -------------------------*/
4336 typedef struct
4337 {
4338
4723 __I uint32_t SRC0; /* Offset: 0x00 IRQ0 (BOD) Interrupt Source Identity */
4724 __I uint32_t SRC1; /* Offset: 0x04 IRQ1 (WDT) Interrupt Source Identity */
4725 __I uint32_t SRC2; /* Offset: 0x08 IRQ2 (EINT0) Interrupt Source Identity */
4726 __I uint32_t SRC3; /* Offset: 0x0C IRQ3 (EINT1) Interrupt Source Identity */
4727 __I uint32_t SRC4; /* Offset: 0x10 IRQ4 (GP0/1) Interrupt Source Identity */
4728 __I uint32_t SRC5; /* Offset: 0x14 IRQ5 (GP2/3/4) Interrupt Source Identity */
4729 __I uint32_t SRC6; /* Offset: 0x18 IRQ6 (PWM) Interrupt Source Identity */
4730 __I uint32_t SRC7; /* Offset: 0x1C IRQ7 (BRAKE) Interrupt Source Identity */
4731 __I uint32_t SRC8; /* Offset: 0x20 IRQ8 (TMR0) Interrupt Source Identity */
4732 __I uint32_t SRC9; /* Offset: 0x24 IRQ9 (TMR1) Interrupt Source Identity */
4734 __I uint32_t RESERVED0[2];
4736 __I uint32_t SRC12; /* Offset: 0x30 IRQ12 (UART) Interrupt Source Identity */
4738 __I uint32_t RESERVED1;
4740 __I uint32_t SRC14; /* Offset: 0x38 IRQ14 (SPI) Interrupt Source Identity */
4742 __I uint32_t RESERVED2;
4744 __I uint32_t SRC16; /* Offset: 0x40 IRQ16 (GP5) Interrupt Source Identity */
4745 __I uint32_t SRC17; /* Offset: 0x44 IRQ17 (HIRC trim) Interrupt Source Identity */
4746 __I uint32_t SRC18; /* Offset: 0x48 IRQ18 (I2C) Interrupt Source Identity */
4748 __I uint32_t RESERVED3[6];
4750 __I uint32_t SRC25; /* Offset: 0x64 IRQ25 (ACMP) Interrupt Source Identity */
4752 __I uint32_t RESERVED4[2];
4754 __I uint32_t SRC28; /* Offset: 0x70 IRQ28 (PWRWU) Interrupt Source Identity */
4755 __I uint32_t SRC29; /* Offset: 0x74 IRQ29 (ADC) Interrupt Source Identity */
4757 __I uint32_t RESERVED5[2];
4759 __IO uint32_t NMICON; /* Offset: 0x80 NMI Source Interrupt Select Control Register */
4760 __IO uint32_t MCUIRQ; /* Offset: 0x84 MCU IRQ Number Identity Register */
4761
4762 } INT_T;
4763
4764
4765
4771 #define INT_SRC_INT_SRC_Pos (0)
4772 #define INT_SRC_INT_SRC_Msk (0x7ul << INT_SRC_INT_SRC_Pos)
4774 #define INT_CON_NMI_SEL_Pos (0)
4775 #define INT_CON_NMI_SEL_Msk (0x1ful << INT_CON_NMI_SEL_Pos)
4777 #define INT_CON_NMI_SEL_EN_Pos (8)
4778 #define INT_CON_NMI_SEL_EN_Msk (0x1ul << INT_CON_NMI_SEL_EN_Pos)
4780 #define INT_IRQ_MCU_IRQ_Pos (0)
4781 #define INT_IRQ_MCU_IRQ_Msk (0xfffffffful << INT_IRQ_MCU_IRQ_Pos) /* INT_CONST */
4784 /* end of INT register group */
4785
4786
4787 /*---------------------- Pulse Width Modulation Controller -------------------------*/
4794 typedef struct
4795 {
4796
6652 __IO uint32_t PPR; /* Offset: 0x00 PWM Pre-scale Register */
6653 __IO uint32_t CSR; /* Offset: 0x04 PWM Clock Select Register */
6654 __IO uint32_t PCR; /* Offset: 0x08 PWM Control Register */
6655 __IO uint32_t CNR[6]; /* Offset: 0x000C ~ 0x0020 PWM Counter Register 0 ~ 5 */
6656 __IO uint32_t CMR[6]; /* Offset: 0x0024 ~ 0x0038 PWM Comparator Register 0 ~ 5 */
6658 __I uint32_t RESERVE0[6];
6660 __IO uint32_t PIER; /* Offset: 0x54 PWM Interrupt Enable Control Register */
6661 __IO uint32_t PIIR; /* Offset: 0x58 PWM Interrupt Indication Register */
6662 __IO uint32_t POE; /* Offset: 0x5C PWM Output Enable for Channel 0~5 */
6663 __IO uint32_t PFBCON; /* Offset: 0x60 PWM Fault Brake Control Register */
6664 __IO uint32_t PDZIR; /* Offset: 0x64 PWM Dead-zone Interval Register */
6665 __IO uint32_t TRGCON0; /* Offset: 0x68 PWM Trigger Control Register 0 */
6666 __IO uint32_t TRGCON1; /* Offset: 0x6C PWM Trigger Control Register 1 */
6667 __IO uint32_t TRGSTS0; /* Offset: 0x70 PWM Trigger Status Register 0 */
6668 __IO uint32_t TRGSTS1; /* Offset: 0x74 PWM Trigger Status Register 1 */
6669 __IO uint32_t PHCHG; /* Offset: 0x78 Phase Change Register */
6670 __IO uint32_t PHCHGNXT; /* Offset: 0x7C Next Phase Change Register */
6671 __IO uint32_t PHCHGMASK; /* Offset: 0x80 Phase Change MASK Register */
6672 __IO uint32_t INTACCUCTL; /* Offset: 0x84 Period Interrupt Accumulation Control Register */
6673
6674 } PWM_T;
6675
6676
6677
6683 #define PWM_PPR_CP01_Pos (0)
6684 #define PWM_PPR_CP01_Msk (0xfful << PWM_PPR_CP01_Pos)
6686 #define PWM_PPR_CP23_Pos (8)
6687 #define PWM_PPR_CP23_Msk (0xfful << PWM_PPR_CP23_Pos)
6689 #define PWM_PPR_CP45_Pos (16)
6690 #define PWM_PPR_CP45_Msk (0xfful << PWM_PPR_CP45_Pos)
6692 #define PWM_CSR_CSR0_Pos (0)
6693 #define PWM_CSR_CSR0_Msk (0x7ul << PWM_CSR_CSR0_Pos)
6695 #define PWM_CSR_CSR1_Pos (4)
6696 #define PWM_CSR_CSR1_Msk (0x7ul << PWM_CSR_CSR1_Pos)
6698 #define PWM_CSR_CSR2_Pos (8)
6699 #define PWM_CSR_CSR2_Msk (0x7ul << PWM_CSR_CSR2_Pos)
6701 #define PWM_CSR_CSR3_Pos (12)
6702 #define PWM_CSR_CSR3_Msk (0x7ul << PWM_CSR_CSR3_Pos)
6704 #define PWM_CSR_CSR4_Pos (16)
6705 #define PWM_CSR_CSR4_Msk (0x7ul << PWM_CSR_CSR4_Pos)
6707 #define PWM_CSR_CSR5_Pos (20)
6708 #define PWM_CSR_CSR5_Msk (0x7ul << PWM_CSR_CSR5_Pos)
6710 #define PWM_PCR_CH0EN_Pos (0)
6711 #define PWM_PCR_CH0EN_Msk (0x1ul << PWM_PCR_CH0EN_Pos)
6713 #define PWM_PCR_DB_MOD_Pos (1)
6714 #define PWM_PCR_DB_MOD_Msk (0x1ul << PWM_PCR_DB_MOD_Pos)
6716 #define PWM_PCR_CH0INV_Pos (2)
6717 #define PWM_PCR_CH0INV_Msk (0x1ul << PWM_PCR_CH0INV_Pos)
6719 #define PWM_PCR_CH0MOD_Pos (3)
6720 #define PWM_PCR_CH0MOD_Msk (0x1ul << PWM_PCR_CH0MOD_Pos)
6722 #define PWM_PCR_CH1EN_Pos (4)
6723 #define PWM_PCR_CH1EN_Msk (0x1ul << PWM_PCR_CH1EN_Pos)
6725 #define PWM_PCR_CH1INV_Pos (6)
6726 #define PWM_PCR_CH1INV_Msk (0x1ul << PWM_PCR_CH1INV_Pos)
6728 #define PWM_PCR_CH1MOD_Pos (7)
6729 #define PWM_PCR_CH1MOD_Msk (0x1ul << PWM_PCR_CH1MOD_Pos)
6731 #define PWM_PCR_CH2EN_Pos (8)
6732 #define PWM_PCR_CH2EN_Msk (0x1ul << PWM_PCR_CH2EN_Pos)
6734 #define PWM_PCR_CH2INV_Pos (10)
6735 #define PWM_PCR_CH2INV_Msk (0x1ul << PWM_PCR_CH2INV_Pos)
6737 #define PWM_PCR_CH2MOD_Pos (11)
6738 #define PWM_PCR_CH2MOD_Msk (0x1ul << PWM_PCR_CH2MOD_Pos)
6740 #define PWM_PCR_CH3EN_Pos (12)
6741 #define PWM_PCR_CH3EN_Msk (0x1ul << PWM_PCR_CH3EN_Pos)
6743 #define PWM_PCR_CH3INV_Pos (14)
6744 #define PWM_PCR_CH3INV_Msk (0x1ul << PWM_PCR_CH3INV_Pos)
6746 #define PWM_PCR_CH3MOD_Pos (15)
6747 #define PWM_PCR_CH3MOD_Msk (0x1ul << PWM_PCR_CH3MOD_Pos)
6749 #define PWM_PCR_CH4EN_Pos (16)
6750 #define PWM_PCR_CH4EN_Msk (0x1ul << PWM_PCR_CH4EN_Pos)
6752 #define PWM_PCR_CH4INV_Pos (18)
6753 #define PWM_PCR_CH4INV_Msk (0x1ul << PWM_PCR_CH4INV_Pos)
6755 #define PWM_PCR_CH4MOD_Pos (19)
6756 #define PWM_PCR_CH4MOD_Msk (0x1ul << PWM_PCR_CH4MOD_Pos)
6758 #define PWM_PCR_CH5EN_Pos (20)
6759 #define PWM_PCR_CH5EN_Msk (0x1ul << PWM_PCR_CH5EN_Pos)
6761 #define PWM_PCR_CH5INV_Pos (22)
6762 #define PWM_PCR_CH5INV_Msk (0x1ul << PWM_PCR_CH5INV_Pos)
6764 #define PWM_PCR_CH5MOD_Pos (23)
6765 #define PWM_PCR_CH5MOD_Msk (0x1ul << PWM_PCR_CH5MOD_Pos)
6767 #define PWM_PCR_DZEN01_Pos (24)
6768 #define PWM_PCR_DZEN01_Msk (0x1ul << PWM_PCR_DZEN01_Pos)
6770 #define PWM_PCR_DZEN23_Pos (25)
6771 #define PWM_PCR_DZEN23_Msk (0x1ul << PWM_PCR_DZEN23_Pos)
6773 #define PWM_PCR_DZEN45_Pos (26)
6774 #define PWM_PCR_DZEN45_Msk (0x1ul << PWM_PCR_DZEN45_Pos)
6776 #define PWM_PCR_CLRPWM_Pos (27)
6777 #define PWM_PCR_CLRPWM_Msk (0x1ul << PWM_PCR_CLRPWM_Pos)
6779 #define PWM_PCR_PWMMOD_Pos (28)
6780 #define PWM_PCR_PWMMOD_Msk (0x3ul << PWM_PCR_PWMMOD_Pos)
6782 #define PWM_PCR_GRP_Pos (30)
6783 #define PWM_PCR_GRP_Msk (0x1ul << PWM_PCR_GRP_Pos)
6785 #define PWM_PCR_PWMTYPE_Pos (31)
6786 #define PWM_PCR_PWMTYPE_Msk (0x1ul << PWM_PCR_PWMTYPE_Pos)
6788 #define PWM_CNR_CNR_Pos 0
6789 #define PWM_CNR_CNR_Msk (0xfffful << PWM_CNR_CNR_Pos)
6791 #define PWM_CMR_CMR_Pos 0
6792 #define PWM_CMR_CMR_Msk (0xfffful << PWM_CMR_CMR_Pos)
6794 #define PWM_PIER_PWMPIE0_Pos (0)
6795 #define PWM_PIER_PWMPIE0_Msk (0x1ul << PWM_PIER_PWMPIE0_Pos)
6797 #define PWM_PIER_PWMPIE1_Pos (1)
6798 #define PWM_PIER_PWMPIE1_Msk (0x1ul << PWM_PIER_PWMPIE1_Pos)
6800 #define PWM_PIER_PWMPIE2_Pos (2)
6801 #define PWM_PIER_PWMPIE2_Msk (0x1ul << PWM_PIER_PWMPIE2_Pos)
6803 #define PWM_PIER_PWMPIE3_Pos (3)
6804 #define PWM_PIER_PWMPIE3_Msk (0x1ul << PWM_PIER_PWMPIE3_Pos)
6806 #define PWM_PIER_PWMPIE4_Pos (4)
6807 #define PWM_PIER_PWMPIE4_Msk (0x1ul << PWM_PIER_PWMPIE4_Pos)
6809 #define PWM_PIER_PWMPIE5_Pos (5)
6810 #define PWM_PIER_PWMPIE5_Msk (0x1ul << PWM_PIER_PWMPIE5_Pos)
6812 #define PWM_PIER_PWMDIE0_Pos (8)
6813 #define PWM_PIER_PWMDIE0_Msk (0x1ul << PWM_PIER_PWMDIE0_Pos)
6815 #define PWM_PIER_PWMDIE1_Pos (9)
6816 #define PWM_PIER_PWMDIE1_Msk (0x1ul << PWM_PIER_PWMDIE1_Pos)
6818 #define PWM_PIER_PWMDIE2_Pos (10)
6819 #define PWM_PIER_PWMDIE2_Msk (0x1ul << PWM_PIER_PWMDIE2_Pos)
6821 #define PWM_PIER_PWMDIE3_Pos (11)
6822 #define PWM_PIER_PWMDIE3_Msk (0x1ul << PWM_PIER_PWMDIE3_Pos)
6824 #define PWM_PIER_PWMDIE4_Pos (12)
6825 #define PWM_PIER_PWMDIE4_Msk (0x1ul << PWM_PIER_PWMDIE4_Pos)
6827 #define PWM_PIER_PWMDIE5_Pos (13)
6828 #define PWM_PIER_PWMDIE5_Msk (0x1ul << PWM_PIER_PWMDIE5_Pos)
6830 #define PWM_PIER_BRKIE_Pos (16)
6831 #define PWM_PIER_BRKIE_Msk (0x1ul << PWM_PIER_BRKIE_Pos)
6833 #define PWM_PIER_INT_TYPE_Pos (17)
6834 #define PWM_PIER_INT_TYPE_Msk (0x1ul << PWM_PIER_INT_TYPE_Pos)
6836 #define PWM_PIIR_PWMPIF0_Pos (0)
6837 #define PWM_PIIR_PWMPIF0_Msk (0x1ul << PWM_PIIR_PWMPIF0_Pos)
6839 #define PWM_PIIR_PWMPIF1_Pos (1)
6840 #define PWM_PIIR_PWMPIF1_Msk (0x1ul << PWM_PIIR_PWMPIF1_Pos)
6842 #define PWM_PIIR_PWMPIF2_Pos (2)
6843 #define PWM_PIIR_PWMPIF2_Msk (0x1ul << PWM_PIIR_PWMPIF2_Pos)
6845 #define PWM_PIIR_PWMPIF3_Pos (3)
6846 #define PWM_PIIR_PWMPIF3_Msk (0x1ul << PWM_PIIR_PWMPIF3_Pos)
6848 #define PWM_PIIR_PWMPIF4_Pos (4)
6849 #define PWM_PIIR_PWMPIF4_Msk (0x1ul << PWM_PIIR_PWMPIF4_Pos)
6851 #define PWM_PIIR_PWMPIF5_Pos (5)
6852 #define PWM_PIIR_PWMPIF5_Msk (0x1ul << PWM_PIIR_PWMPIF5_Pos)
6854 #define PWM_PIIR_PWMDIF0_Pos (8)
6855 #define PWM_PIIR_PWMDIF0_Msk (0x1ul << PWM_PIIR_PWMDIF0_Pos)
6857 #define PWM_PIIR_PWMDIF1_Pos (9)
6858 #define PWM_PIIR_PWMDIF1_Msk (0x1ul << PWM_PIIR_PWMDIF1_Pos)
6860 #define PWM_PIIR_PWMDIF2_Pos (10)
6861 #define PWM_PIIR_PWMDIF2_Msk (0x1ul << PWM_PIIR_PWMDIF2_Pos)
6863 #define PWM_PIIR_PWMDIF3_Pos (11)
6864 #define PWM_PIIR_PWMDIF3_Msk (0x1ul << PWM_PIIR_PWMDIF3_Pos)
6866 #define PWM_PIIR_PWMDIF4_Pos (12)
6867 #define PWM_PIIR_PWMDIF4_Msk (0x1ul << PWM_PIIR_PWMDIF4_Pos)
6869 #define PWM_PIIR_PWMDIF5_Pos (13)
6870 #define PWM_PIIR_PWMDIF5_Msk (0x1ul << PWM_PIIR_PWMDIF5_Pos)
6872 #define PWM_PIIR_BKF0_Pos (16)
6873 #define PWM_PIIR_BKF0_Msk (0x1ul << PWM_PIIR_BKF0_Pos)
6875 #define PWM_PIIR_BKF1_Pos (17)
6876 #define PWM_PIIR_BKF1_Msk (0x1ul << PWM_PIIR_BKF1_Pos)
6878 #define PWM_POE_PWM0_Pos (0)
6879 #define PWM_POE_PWM0_Msk (0x1ul << PWM_POE_PWM0_Pos)
6881 #define PWM_POE_PWM1_Pos (1)
6882 #define PWM_POE_PWM1_Msk (0x1ul << PWM_POE_PWM1_Pos)
6884 #define PWM_POE_PWM2_Pos (2)
6885 #define PWM_POE_PWM2_Msk (0x1ul << PWM_POE_PWM2_Pos)
6887 #define PWM_POE_PWM3_Pos (3)
6888 #define PWM_POE_PWM3_Msk (0x1ul << PWM_POE_PWM3_Pos)
6890 #define PWM_POE_PWM4_Pos (4)
6891 #define PWM_POE_PWM4_Msk (0x1ul << PWM_POE_PWM4_Pos)
6893 #define PWM_POE_PWM5_Pos (5)
6894 #define PWM_POE_PWM5_Msk (0x1ul << PWM_POE_PWM5_Pos)
6896 #define PWM_PFBCON_BKEN0_Pos (0)
6897 #define PWM_PFBCON_BKEN0_Msk (0x1ul << PWM_PFBCON_BKEN0_Pos)
6899 #define PWM_PFBCON_BKEN1_Pos (1)
6900 #define PWM_PFBCON_BKEN1_Msk (0x1ul << PWM_PFBCON_BKEN1_Pos)
6902 #define PWM_PFBCON_CPO0BKEN_Pos (2)
6903 #define PWM_PFBCON_CPO0BKEN_Msk (0x1ul << PWM_PFBCON_CPO0BKEN_Pos)
6905 #define PWM_PFBCON_CPO1BKEN_Pos (3)
6906 #define PWM_PFBCON_CPO1BKEN_Msk (0x1ul << PWM_PFBCON_CPO1BKEN_Pos)
6908 #define PWM_PFBCON_BKF_Pos (7)
6909 #define PWM_PFBCON_BKF_Msk (0x1ul << PWM_PFBCON_BKF_Pos)
6911 #define PWM_PFBCON_PWMBKO0_Pos (24)
6912 #define PWM_PFBCON_PWMBKO0_Msk (0x1ul << PWM_PFBCON_PWMBKO0_Pos)
6914 #define PWM_PFBCON_PWMBKO1_Pos (25)
6915 #define PWM_PFBCON_PWMBKO1_Msk (0x1ul << PWM_PFBCON_PWMBKO1_Pos)
6917 #define PWM_PFBCON_PWMBKO2_Pos (26)
6918 #define PWM_PFBCON_PWMBKO2_Msk (0x1ul << PWM_PFBCON_PWMBKO2_Pos)
6920 #define PWM_PFBCON_PWMBKO3_Pos (27)
6921 #define PWM_PFBCON_PWMBKO3_Msk (0x1ul << PWM_PFBCON_PWMBKO3_Pos)
6923 #define PWM_PFBCON_PWMBKO4_Pos (28)
6924 #define PWM_PFBCON_PWMBKO4_Msk (0x1ul << PWM_PFBCON_PWMBKO4_Pos)
6926 #define PWM_PFBCON_PWMBKO5_Pos (29)
6927 #define PWM_PFBCON_PWMBKO5_Msk (0x1ul << PWM_PFBCON_PWMBKO5_Pos)
6929 #define PWM_PFBCON_D6BKO6_Pos (30)
6930 #define PWM_PFBCON_D6BKO6_Msk (0x1ul << PWM_PFBCON_D6BKO6_Pos)
6932 #define PWM_PFBCON_D7BKO7_Pos (31)
6933 #define PWM_PFBCON_D7BKO7_Msk (0x1ul << PWM_PFBCON_D7BKO7_Pos)
6935 #define PWM_DZIR_DZI01_Pos (0)
6936 #define PWM_DZIR_DZI01_Msk (0xfful << PWM_DZIR_DZI01_Pos)
6938 #define PWM_DZIR_DZI23_Pos (8)
6939 #define PWM_DZIR_DZI23_Msk (0xfful << PWM_DZIR_DZI23_Pos)
6941 #define PWM_DZIR_DZI45_Pos (16)
6942 #define PWM_DZIR_DZI45_Msk (0xfful << PWM_DZIR_DZI45_Pos)
6944 #define PWM_TRGCON0_CM0TRGREN_Pos (0)
6945 #define PWM_TRGCON0_CM0TRGREN_Msk (0x1ul << PWM_TRGCON0_CM0TRGREN_Pos)
6947 #define PWM_TRGCON0_CNT0TRGEN_Pos (1)
6948 #define PWM_TRGCON0_CNT0TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT0TRGEN_Pos)
6950 #define PWM_TRGCON0_CM0TRGFEN_Pos (2)
6951 #define PWM_TRGCON0_CM0TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM0TRGFEN_Pos)
6953 #define PWM_TRGCON0_P0TRGEN_Pos (3)
6954 #define PWM_TRGCON0_P0TRGEN_Msk (0x1ul << PWM_TRGCON0_P0TRGEN_Pos)
6956 #define PWM_TRGCON0_CM1TRGREN_Pos (8)
6957 #define PWM_TRGCON0_CM1TRGREN_Msk (0x1ul << PWM_TRGCON0_CM1TRGREN_Pos)
6959 #define PWM_TRGCON0_CNT1TRGEN_Pos (9)
6960 #define PWM_TRGCON0_CNT1TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT1TRGEN_Pos)
6962 #define PWM_TRGCON0_CM1TRGFEN_Pos (10)
6963 #define PWM_TRGCON0_CM1TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM1TRGFEN_Pos)
6965 #define PWM_TRGCON0_P1TRGEN_Pos (11)
6966 #define PWM_TRGCON0_P1TRGEN_Msk (0x1ul << PWM_TRGCON0_P1TRGEN_Pos)
6968 #define PWM_TRGCON0_CM2TRGREN_Pos (16)
6969 #define PWM_TRGCON0_CM2TRGREN_Msk (0x1ul << PWM_TRGCON0_CM2TRGREN_Pos)
6971 #define PWM_TRGCON0_CNT2TRGEN_Pos (17)
6972 #define PWM_TRGCON0_CNT2TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT2TRGEN_Pos)
6974 #define PWM_TRGCON0_CM2TRGFEN_Pos (18)
6975 #define PWM_TRGCON0_CM2TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM2TRGFEN_Pos)
6977 #define PWM_TRGCON0_P2TRGEN_Pos (19)
6978 #define PWM_TRGCON0_P2TRGEN_Msk (0x1ul << PWM_TRGCON0_P2TRGEN_Pos)
6980 #define PWM_TRGCON0_CM3TRGREN_Pos (24)
6981 #define PWM_TRGCON0_CM3TRGREN_Msk (0x1ul << PWM_TRGCON0_CM3TRGREN_Pos)
6983 #define PWM_TRGCON0_CNT3TRGEN_Pos (25)
6984 #define PWM_TRGCON0_CNT3TRGEN_Msk (0x1ul << PWM_TRGCON0_CNT3TRGEN_Pos)
6986 #define PWM_TRGCON0_CM3TRGFEN_Pos (26)
6987 #define PWM_TRGCON0_CM3TRGFEN_Msk (0x1ul << PWM_TRGCON0_CM3TRGFEN_Pos)
6989 #define PWM_TRGCON0_P3TRGEN_Pos (27)
6990 #define PWM_TRGCON0_P3TRGEN_Msk (0x1ul << PWM_TRGCON0_P3TRGEN_Pos)
6992 #define PWM_TRGCON1_CM4TRGREN_Pos (0)
6993 #define PWM_TRGCON1_CM4TRGREN_Msk (0x1ul << PWM_TRGCON1_CM4TRGREN_Pos)
6995 #define PWM_TRGCON1_CNT4TRGEN_Pos (1)
6996 #define PWM_TRGCON1_CNT4TRGEN_Msk (0x1ul << PWM_TRGCON1_CNT4TRGEN_Pos)
6998 #define PWM_TRGCON1_CM4TRGFEN_Pos (2)
6999 #define PWM_TRGCON1_CM4TRGFEN_Msk (0x1ul << PWM_TRGCON1_CM4TRGFEN_Pos)
7001 #define PWM_TRGCON1_P4TRGEN_Pos (3)
7002 #define PWM_TRGCON1_P4TRGEN_Msk (0x1ul << PWM_TRGCON1_P4TRGEN_Pos)
7004 #define PWM_TRGCON1_CM5TRGREN_Pos (8)
7005 #define PWM_TRGCON1_CM5TRGREN_Msk (0x1ul << PWM_TRGCON1_CM5TRGREN_Pos)
7007 #define PWM_TRGCON1_CNT5TRGEN_Pos (9)
7008 #define PWM_TRGCON1_CNT5TRGEN_Msk (0x1ul << PWM_TRGCON1_CNT5TRGEN_Pos)
7010 #define PWM_TRGCON1_CM5TRGFEN_Pos (10)
7011 #define PWM_TRGCON1_CM5TRGFEN_Msk (0x1ul << PWM_TRGCON1_CM5TRGFEN_Pos)
7013 #define PWM_TRGCON1_P5TRGEN_Pos (11)
7014 #define PWM_TRGCON1_P5TRGEN_Msk (0x1ul << PWM_TRGCON1_P5TRGEN_Pos)
7016 #define PWM_TRGSTS0_CMR0FLAG_R_Pos (0)
7017 #define PWM_TRGSTS0_CMR0FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR0FLAG_R_Pos)
7019 #define PWM_TRGSTS0_CNT0FLAG_Pos (1)
7020 #define PWM_TRGSTS0_CNT0FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT0FLAG_Pos)
7022 #define PWM_TRGSTS0_CMR0FLAG_F_Pos (2)
7023 #define PWM_TRGSTS0_CMR0FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR0FLAG_F_Pos)
7025 #define PWM_TRGSTS0_PERID0FLAG_Pos (3)
7026 #define PWM_TRGSTS0_PERID0FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID0FLAG_Pos)
7028 #define PWM_TRGSTS0_CMR1FLAG_R_Pos (8)
7029 #define PWM_TRGSTS0_CMR1FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR1FLAG_R_Pos)
7031 #define PWM_TRGSTS0_CNT1FLAG_Pos (9)
7032 #define PWM_TRGSTS0_CNT1FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT1FLAG_Pos)
7034 #define PWM_TRGSTS0_CMR1FLAG_F_Pos (10)
7035 #define PWM_TRGSTS0_CMR1FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR1FLAG_F_Pos)
7037 #define PWM_TRGSTS0_PERID1FLAG_Pos (11)
7038 #define PWM_TRGSTS0_PERID1FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID1FLAG_Pos)
7040 #define PWM_TRGSTS0_CMR2FLAG_R_Pos (16)
7041 #define PWM_TRGSTS0_CMR2FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR2FLAG_R_Pos)
7043 #define PWM_TRGSTS0_CNT2FLAG_Pos (17)
7044 #define PWM_TRGSTS0_CNT2FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT2FLAG_Pos)
7046 #define PWM_TRGSTS0_CMR2FLAG_F_Pos (18)
7047 #define PWM_TRGSTS0_CMR2FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR2FLAG_F_Pos)
7049 #define PWM_TRGSTS0_PERID2FLAG_Pos (19)
7050 #define PWM_TRGSTS0_PERID2FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID2FLAG_Pos)
7052 #define PWM_TRGSTS0_CMR3FLAG_R_Pos (24)
7053 #define PWM_TRGSTS0_CMR3FLAG_R_Msk (0x1ul << PWM_TRGSTS0_CMR3FLAG_R_Pos)
7055 #define PWM_TRGSTS0_CNT3FLAG_Pos (25)
7056 #define PWM_TRGSTS0_CNT3FLAG_Msk (0x1ul << PWM_TRGSTS0_CNT3FLAG_Pos)
7058 #define PWM_TRGSTS0_CMR3FLAG_F_Pos (26)
7059 #define PWM_TRGSTS0_CMR3FLAG_F_Msk (0x1ul << PWM_TRGSTS0_CMR3FLAG_F_Pos)
7061 #define PWM_TRGSTS0_PERID3FLAG_Pos (27)
7062 #define PWM_TRGSTS0_PERID3FLAG_Msk (0x1ul << PWM_TRGSTS0_PERID3FLAG_Pos)
7064 #define PWM_TRGSTS1_CMR4FLAG_R_Pos (0)
7065 #define PWM_TRGSTS1_CMR4FLAG_R_Msk (0x1ul << PWM_TRGSTS1_CMR4FLAG_R_Pos)
7067 #define PWM_TRGSTS1_CNT4FLAG_Pos (1)
7068 #define PWM_TRGSTS1_CNT4FLAG_Msk (0x1ul << PWM_TRGSTS1_CNT4FLAG_Pos)
7070 #define PWM_TRGSTS1_CMR4FLAG_F_Pos (2)
7071 #define PWM_TRGSTS1_CMR4FLAG_F_Msk (0x1ul << PWM_TRGSTS1_CMR4FLAG_F_Pos)
7073 #define PWM_TRGSTS1_PERID4FLAG_Pos (3)
7074 #define PWM_TRGSTS1_PERID4FLAG_Msk (0x1ul << PWM_TRGSTS1_PERID4FLAG_Pos)
7076 #define PWM_TRGSTS1_CMR5FLAG_R_Pos (8)
7077 #define PWM_TRGSTS1_CMR5FLAG_R_Msk (0x1ul << PWM_TRGSTS1_CMR5FLAG_R_Pos)
7079 #define PWM_TRGSTS1_CNT5FLAG_Pos (9)
7080 #define PWM_TRGSTS1_CNT5FLAG_Msk (0x1ul << PWM_TRGSTS1_CNT5FLAG_Pos)
7082 #define PWM_TRGSTS1_CMR5FLAG_F_Pos (10)
7083 #define PWM_TRGSTS1_CMR5FLAG_F_Msk (0x1ul << PWM_TRGSTS1_CMR5FLAG_F_Pos)
7085 #define PWM_TRGSTS1_PERID5FLAG_Pos (11)
7086 #define PWM_TRGSTS1_PERID5FLAG_Msk (0x1ul << PWM_TRGSTS1_PERID5FLAG_Pos)
7088 #define PWM_PHCHG_D0_Pos (0)
7089 #define PWM_PHCHG_D0_Msk (0x1ul << PWM_PHCHG_D0_Pos)
7091 #define PWM_PHCHG_D1_Pos (1)
7092 #define PWM_PHCHG_D1_Msk (0x1ul << PWM_PHCHG_D1_Pos)
7094 #define PWM_PHCHG_D2_Pos (2)
7095 #define PWM_PHCHG_D2_Msk (0x1ul << PWM_PHCHG_D2_Pos)
7097 #define PWM_PHCHG_D3_Pos (3)
7098 #define PWM_PHCHG_D3_Msk (0x1ul << PWM_PHCHG_D3_Pos)
7100 #define PWM_PHCHG_D4_Pos (4)
7101 #define PWM_PHCHG_D4_Msk (0x1ul << PWM_PHCHG_D4_Pos)
7103 #define PWM_PHCHG_D5_Pos (5)
7104 #define PWM_PHCHG_D5_Msk (0x1ul << PWM_PHCHG_D5_Pos)
7106 #define PWM_PHCHG_D6_Pos (6)
7107 #define PWM_PHCHG_D6_Msk (0x1ul << PWM_PHCHG_D6_Pos)
7109 #define PWM_PHCHG_D7_Pos (7)
7110 #define PWM_PHCHG_D7_Msk (0x1ul << PWM_PHCHG_D7_Pos)
7112 #define PWM_PHCHG_PWM0_Pos (8)
7113 #define PWM_PHCHG_PWM0_Msk (0x1ul << PWM_PHCHG_PWM0_Pos)
7115 #define PWM_PHCHG_PWM1_Pos (9)
7116 #define PWM_PHCHG_PWM1_Msk (0x1ul << PWM_PHCHG_PWM1_Pos)
7118 #define PWM_PHCHG_PWM2_Pos (10)
7119 #define PWM_PHCHG_PWM2_Msk (0x1ul << PWM_PHCHG_PWM2_Pos)
7121 #define PWM_PHCHG_PWM3_Pos (11)
7122 #define PWM_PHCHG_PWM3_Msk (0x1ul << PWM_PHCHG_PWM3_Pos)
7124 #define PWM_PHCHG_PWM4_Pos (12)
7125 #define PWM_PHCHG_PWM4_Msk (0x1ul << PWM_PHCHG_PWM4_Pos)
7127 #define PWM_PHCHG_PWM5_Pos (13)
7128 #define PWM_PHCHG_PWM5_Msk (0x1ul << PWM_PHCHG_PWM5_Pos)
7130 #define PWM_PHCHG_ACCNT0_Pos (14)
7131 #define PWM_PHCHG_ACCNT0_Msk (0x1ul << PWM_PHCHG_ACCNT0_Pos)
7133 #define PWM_PHCHG_ACCNT1_Pos (15)
7134 #define PWM_PHCHG_ACCNT1_Msk (0x1ul << PWM_PHCHG_ACCNT1_Pos)
7136 #define PWM_PHCHG_CH01TOFF1_Pos (16)
7137 #define PWM_PHCHG_CH01TOFF1_Msk (0x1ul << PWM_PHCHG_CH01TOFF1_Pos)
7139 #define PWM_PHCHG_CH11TOFF1_Pos (17)
7140 #define PWM_PHCHG_CH11TOFF1_Msk (0x1ul << PWM_PHCHG_CH11TOFF1_Pos)
7142 #define PWM_PHCHG_CH21TOFF1_Pos (18)
7143 #define PWM_PHCHG_CH21TOFF1_Msk (0x1ul << PWM_PHCHG_CH21TOFF1_Pos)
7145 #define PWM_PHCHG_CH31TOFF1_Pos (19)
7146 #define PWM_PHCHG_CH31TOFF1_Msk (0x1ul << PWM_PHCHG_CH31TOFF1_Pos)
7148 #define PWM_PHCHG_CMP1SEL_Pos (20)
7149 #define PWM_PHCHG_CMP1SEL_Msk (0x3ul << PWM_PHCHG_CMP1SEL_Pos)
7151 #define PWM_PHCHG_T1_Pos (22)
7152 #define PWM_PHCHG_T1_Msk (0x1ul << PWM_PHCHG_T1_Pos)
7154 #define PWM_PHCHG_CE1_Pos (23)
7155 #define PWM_PHCHG_CE1_Msk (0x1ul << PWM_PHCHG_CE1_Pos)
7157 #define PWM_PHCHG_CH01TOFF0_Pos (24)
7158 #define PWM_PHCHG_CH01TOFF0_Msk (0x1ul << PWM_PHCHG_CH01TOFF0_Pos)
7160 #define PWM_PHCHG_CH11TOFF0_Pos (25)
7161 #define PWM_PHCHG_CH11TOFF0_Msk (0x1ul << PWM_PHCHG_CH11TOFF0_Pos)
7163 #define PWM_PHCHG_CH21TOFF0_Pos (26)
7164 #define PWM_PHCHG_CH21TOFF0_Msk (0x1ul << PWM_PHCHG_CH21TOFF0_Pos)
7166 #define PWM_PHCHG_CH31TOFF0_Pos (27)
7167 #define PWM_PHCHG_CH31TOFF0_Msk (0x1ul << PWM_PHCHG_CH31TOFF0_Pos)
7169 #define PWM_PHCHG_CMP0SEL_Pos (28)
7170 #define PWM_PHCHG_CMP0SEL_Msk (0x3ul << PWM_PHCHG_CMP0SEL_Pos)
7172 #define PWM_PHCHG_T0_Pos (30)
7173 #define PWM_PHCHG_T0_Msk (0x1ul << PWM_PHCHG_T0_Pos)
7175 #define PWM_PHCHG_CE0_Pos (31)
7176 #define PWM_PHCHG_CE0_Msk (0x1ul << PWM_PHCHG_CE0_Pos)
7178 #define PWM_PHCHGNXT_D0_Pos (0)
7179 #define PWM_PHCHGNXT_D0_Msk (0x1ul << PWM_PHCHGNXT_D0_Pos)
7181 #define PWM_PHCHGNXT_D1_Pos (1)
7182 #define PWM_PHCHGNXT_D1_Msk (0x1ul << PWM_PHCHGNXT_D1_Pos)
7184 #define PWM_PHCHGNXT_D2_Pos (2)
7185 #define PWM_PHCHGNXT_D2_Msk (0x1ul << PWM_PHCHGNXT_D2_Pos)
7187 #define PWM_PHCHGNXT_D3_Pos (3)
7188 #define PWM_PHCHGNXT_D3_Msk (0x1ul << PWM_PHCHGNXT_D3_Pos)
7190 #define PWM_PHCHGNXT_D4_Pos (4)
7191 #define PWM_PHCHGNXT_D4_Msk (0x1ul << PWM_PHCHGNXT_D4_Pos)
7193 #define PWM_PHCHGNXT_D5_Pos (5)
7194 #define PWM_PHCHGNXT_D5_Msk (0x1ul << PWM_PHCHGNXT_D5_Pos)
7196 #define PWM_PHCHGNXT_D6_Pos (6)
7197 #define PWM_PHCHGNXT_D6_Msk (0x1ul << PWM_PHCHGNXT_D6_Pos)
7199 #define PWM_PHCHGNXT_D7_Pos (7)
7200 #define PWM_PHCHGNXT_D7_Msk (0x1ul << PWM_PHCHGNXT_D7_Pos)
7202 #define PWM_PHCHGNXT_PWM0_Pos (8)
7203 #define PWM_PHCHGNXT_PWM0_Msk (0x1ul << PWM_PHCHGNXT_PWM0_Pos)
7205 #define PWM_PHCHGNXT_PWM1_Pos (9)
7206 #define PWM_PHCHGNXT_PWM1_Msk (0x1ul << PWM_PHCHGNXT_PWM1_Pos)
7208 #define PWM_PHCHGNXT_PWM2_Pos (10)
7209 #define PWM_PHCHGNXT_PWM2_Msk (0x1ul << PWM_PHCHGNXT_PWM2_Pos)
7211 #define PWM_PHCHGNXT_PWM3_Pos (11)
7212 #define PWM_PHCHGNXT_PWM3_Msk (0x1ul << PWM_PHCHGNXT_PWM3_Pos)
7214 #define PWM_PHCHGNXT_PWM4_Pos (12)
7215 #define PWM_PHCHGNXT_PWM4_Msk (0x1ul << PWM_PHCHGNXT_PWM4_Pos)
7217 #define PWM_PHCHGNXT_PWM5_Pos (13)
7218 #define PWM_PHCHGNXT_PWM5_Msk (0x1ul << PWM_PHCHGNXT_PWM5_Pos)
7220 #define PWM_PHCHGNXT_ACCNT0_Pos (14)
7221 #define PWM_PHCHGNXT_ACCNT0_Msk (0x1ul << PWM_PHCHGNXT_ACCNT0_Pos)
7223 #define PWM_PHCHGNXT_ACCNT1_Pos (15)
7224 #define PWM_PHCHGNXT_ACCNT1_Msk (0x1ul << PWM_PHCHGNXT_ACCNT1_Pos)
7226 #define PWM_PHCHGNXT_CH01TOFF1_Pos (16)
7227 #define PWM_PHCHGNXT_CH01TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH01TOFF1_Pos)
7229 #define PWM_PHCHGNXT_CH11TOFF1_Pos (17)
7230 #define PWM_PHCHGNXT_CH11TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH11TOFF1_Pos)
7232 #define PWM_PHCHGNXT_CH21TOFF1_Pos (18)
7233 #define PWM_PHCHGNXT_CH21TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH21TOFF1_Pos)
7235 #define PWM_PHCHGNXT_CH31TOFF1_Pos (19)
7236 #define PWM_PHCHGNXT_CH31TOFF1_Msk (0x1ul << PWM_PHCHGNXT_CH31TOFF1_Pos)
7238 #define PWM_PHCHGNXT_CMP1SEL_Pos (20)
7239 #define PWM_PHCHGNXT_CMP1SEL_Msk (0x3ul << PWM_PHCHGNXT_CMP1SEL_Pos)
7241 #define PWM_PHCHGNXT_T1_Pos (22)
7242 #define PWM_PHCHGNXT_T1_Msk (0x1ul << PWM_PHCHGNXT_T1_Pos)
7244 #define PWM_PHCHGNXT_CE1_Pos (23)
7245 #define PWM_PHCHGNXT_CE1_Msk (0x1ul << PWM_PHCHGNXT_CE1_Pos)
7247 #define PWM_PHCHGNXT_CH01TOFF0_Pos (24)
7248 #define PWM_PHCHGNXT_CH01TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH01TOFF0_Pos)
7250 #define PWM_PHCHGNXT_CH11TOFF0_Pos (25)
7251 #define PWM_PHCHGNXT_CH11TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH11TOFF0_Pos)
7253 #define PWM_PHCHGNXT_CH21TOFF0_Pos (26)
7254 #define PWM_PHCHGNXT_CH21TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH21TOFF0_Pos)
7256 #define PWM_PHCHGNXT_CH31TOFF0_Pos (27)
7257 #define PWM_PHCHGNXT_CH31TOFF0_Msk (0x1ul << PWM_PHCHGNXT_CH31TOFF0_Pos)
7259 #define PWM_PHCHGNXT_CMP0SEL_Pos (28)
7260 #define PWM_PHCHGNXT_CMP0SEL_Msk (0x3ul << PWM_PHCHGNXT_CMP0SEL_Pos)
7262 #define PWM_PHCHGNXT_T0_Pos (30)
7263 #define PWM_PHCHGNXT_T0_Msk (0x1ul << PWM_PHCHGNXT_T0_Pos)
7265 #define PWM_PHCHGNXT_CE0_Pos (31)
7266 #define PWM_PHCHGNXT_CE0_Msk (0x1ul << PWM_PHCHGNXT_CE0_Pos)
7268 #define PWM_PHCHGMASK_MASK6_Pos (6)
7269 #define PWM_PHCHGMASK_MASK6_Msk (0x1ul << PWM_PHCHGMASK_MASK6_Pos)
7271 #define PWM_PHCHGMASK_MASK7_Pos (7)
7272 #define PWM_PHCHGMASK_MASK7_Msk (0x1ul << PWM_PHCHGMASK_MASK7_Pos)
7274 #define PWM_PHCHGMASK_CMPMASK_Pos (8)
7275 #define PWM_PHCHGMASK_CMPMASK_Msk (0x3ul << PWM_PHCHGMASK_CMPMASK_Pos)
7277 #define PWM_PHCHGMASK_CMPMASK0_Pos (8)
7278 #define PWM_PHCHGMASK_CMPMASK0_Msk (0x1ul << PWM_PHCHGMASK_CMPMASK0_Pos)
7280 #define PWM_PHCHGMASK_CMPMASK1_Pos (9)
7281 #define PWM_PHCHGMASK_CMPMASK1_Msk (0x1ul << PWM_PHCHGMASK_CMPMASK1_Pos)
7283 #define PWM_INTACCUCTL_INTACCUEN0_Pos (0)
7284 #define PWM_INTACCUCTL_INTACCUEN0_Msk (0x1ul << PWM_INTACCUCTL_INTACCUEN0_Pos)
7286 #define PWM_INTACCUCTL_PERIODCNT_Pos (4)
7287 #define PWM_INTACCUCTL_PERIODCNT_Msk (0xful << PWM_INTACCUCTL_PERIODCNT_Pos) /* PWM_CONST */
7290 /* end of PWM register group */
7291
7292
7293 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
7300 typedef struct
7301 {
7302
7909 __IO uint32_t CNTRL; /* Offset: 0x00 SPI Control and Status Register */
7910 __IO uint32_t DIVIDER; /* Offset: 0x04 SPI Clock Divider Register */
7911 __IO uint32_t SSR; /* Offset: 0x08 SPI Slave Select Register */
7913 __I uint32_t RESERVE0[1];
7915 __I uint32_t RX; /* Offset: 0x10 SPI Data Receive Register */
7917 __I uint32_t RESERVE1[3];
7919 __O uint32_t TX; /* Offset: 0x20 SPI Data Transmit Register */
7921 __I uint32_t RESERVE2[6];
7923 __IO uint32_t CNTRL2; /* Offset: 0x3C SPI Control and Status Register 2 */
7924 __IO uint32_t FIFO_CTL; /* Offset: 0x40 SPI FIFO Control Register */
7925 __IO uint32_t STATUS; /* Offset: 0x44 SPI Status Register */
7926
7927 } SPI_T;
7928
7929
7930
7936 #define SPI_CNTRL_GO_BUSY_Pos (0)
7937 #define SPI_CNTRL_GO_BUSY_Msk (0x1ul << SPI_CNTRL_GO_BUSY_Pos)
7939 #define SPI_CNTRL_RX_NEG_Pos (1)
7940 #define SPI_CNTRL_RX_NEG_Msk (0x1ul << SPI_CNTRL_RX_NEG_Pos)
7942 #define SPI_CNTRL_TX_NEG_Pos (2)
7943 #define SPI_CNTRL_TX_NEG_Msk (0x1ul << SPI_CNTRL_TX_NEG_Pos)
7945 #define SPI_CNTRL_TX_BIT_LEN_Pos (3)
7946 #define SPI_CNTRL_TX_BIT_LEN_Msk (0x1ful << SPI_CNTRL_TX_BIT_LEN_Pos)
7948 #define SPI_CNTRL_LSB_Pos (10)
7949 #define SPI_CNTRL_LSB_Msk (0x1ul << SPI_CNTRL_LSB_Pos)
7951 #define SPI_CNTRL_CLKP_Pos (11)
7952 #define SPI_CNTRL_CLKP_Msk (0x1ul << SPI_CNTRL_CLKP_Pos)
7954 #define SPI_CNTRL_SP_CYCLE_Pos (12)
7955 #define SPI_CNTRL_SP_CYCLE_Msk (0xful << SPI_CNTRL_SP_CYCLE_Pos)
7957 #define SPI_CNTRL_IF_Pos (16)
7958 #define SPI_CNTRL_IF_Msk (0x1ul << SPI_CNTRL_IF_Pos)
7960 #define SPI_CNTRL_IE_Pos (17)
7961 #define SPI_CNTRL_IE_Msk (0x1ul << SPI_CNTRL_IE_Pos)
7963 #define SPI_CNTRL_SLAVE_Pos (18)
7964 #define SPI_CNTRL_SLAVE_Msk (0x1ul << SPI_CNTRL_SLAVE_Pos)
7966 #define SPI_CNTRL_REORDER_Pos (19)
7967 #define SPI_CNTRL_REORDER_Msk (0x1ul << SPI_CNTRL_REORDER_Pos)
7969 #define SPI_CNTRL_FIFO_Pos (21)
7970 #define SPI_CNTRL_FIFO_Msk (0x1ul << SPI_CNTRL_FIFO_Pos)
7972 #define SPI_CNTRL_RX_EMPTY_Pos (24)
7973 #define SPI_CNTRL_RX_EMPTY_Msk (0x1ul << SPI_CNTRL_RX_EMPTY_Pos)
7975 #define SPI_CNTRL_RX_FULL_Pos (25)
7976 #define SPI_CNTRL_RX_FULL_Msk (0x1ul << SPI_CNTRL_RX_FULL_Pos)
7978 #define SPI_CNTRL_TX_EMPTY_Pos (26)
7979 #define SPI_CNTRL_TX_EMPTY_Msk (0x1ul << SPI_CNTRL_TX_EMPTY_Pos)
7981 #define SPI_CNTRL_TX_FULL_Pos (27)
7982 #define SPI_CNTRL_TX_FULL_Msk (0x1ul << SPI_CNTRL_TX_FULL_Pos)
7984 #define SPI_DIVIDER_DIVIDER_Pos (0)
7985 #define SPI_DIVIDER_DIVIDER_Msk (0xfful << SPI_DIVIDER_DIVIDER_Pos)
7987 #define SPI_SSR_SSR_Pos (0)
7988 #define SPI_SSR_SSR_Msk (0x1ul << SPI_SSR_SSR_Pos)
7990 #define SPI_SSR_SS_LVL_Pos (2)
7991 #define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos)
7993 #define SPI_SSR_AUTOSS_Pos (3)
7994 #define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos)
7996 #define SPI_SSR_SS_LTRIG_Pos (4)
7997 #define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos)
7999 #define SPI_SSR_LTRIG_FLAG_Pos (5)
8000 #define SPI_SSR_LTRIG_FLAG_Msk (0x1ul << SPI_SSR_LTRIG_FLAG_Pos)
8002 #define SPI_RX_RX_Pos (0)
8003 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos)
8005 #define SPI_TX_TX_Pos (0)
8006 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos)
8008 #define SPI_CNTRL2_NOSLVSEL_Pos (8)
8009 #define SPI_CNTRL2_NOSLVSEL_Msk (0x1ul << SPI_CNTRL2_NOSLVSEL_Pos)
8011 #define SPI_CNTRL2_SLV_ABORT_Pos (9)
8012 #define SPI_CNTRL2_SLV_ABORT_Msk (0x1ul << SPI_CNTRL2_SLV_ABORT_Pos)
8014 #define SPI_CNTRL2_SSTA_INTEN_Pos (10)
8015 #define SPI_CNTRL2_SSTA_INTEN_Msk (0x1ul << SPI_CNTRL2_SSTA_INTEN_Pos)
8017 #define SPI_CNTRL2_SLV_START_INTSTS_Pos (11)
8018 #define SPI_CNTRL2_SLV_START_INTSTS_Msk (0x1ul << SPI_CNTRL2_SLV_START_INTSTS_Pos)
8020 #define SPI_CNTRL2_SS_INT_OPT_Pos (16)
8021 #define SPI_CNTRL2_SS_INT_OPT_Msk (0x1ul << SPI_CNTRL2_SS_INT_OPT_Pos)
8023 #define SPI_CNTRL2_BCn_Pos (31)
8024 #define SPI_CNTRL2_BCn_Msk (0x1ul << SPI_CNTRL2_BCn_Pos)
8026 #define SPI_FIFO_CTL_RX_CLR_Pos (0)
8027 #define SPI_FIFO_CTL_RX_CLR_Msk (0x1ul << SPI_FIFO_CTL_RX_CLR_Pos)
8029 #define SPI_FIFO_CTL_TX_CLR_Pos (1)
8030 #define SPI_FIFO_CTL_TX_CLR_Msk (0x1ul << SPI_FIFO_CTL_TX_CLR_Pos)
8032 #define SPI_FIFO_CTL_RX_INTEN_Pos (2)
8033 #define SPI_FIFO_CTL_RX_INTEN_Msk (0x1ul << SPI_FIFO_CTL_RX_INTEN_Pos)
8035 #define SPI_FIFO_CTL_TX_INTEN_Pos (3)
8036 #define SPI_FIFO_CTL_TX_INTEN_Msk (0x1ul << SPI_FIFO_CTL_TX_INTEN_Pos)
8038 #define SPI_FIFO_CTL_RXOV_INTEN_Pos (6)
8039 #define SPI_FIFO_CTL_RXOV_INTEN_Msk (0x1ul << SPI_FIFO_CTL_RXOV_INTEN_Pos)
8041 #define SPI_FIFO_CTL_TIMEOUT_INTEN_Pos (21)
8042 #define SPI_FIFO_CTL_TIMEOUT_INTEN_Msk (0x1ul << SPI_FIFO_CTL_TIMEOUT_INTEN_Pos)
8044 #define SPI_FIFO_CTL_RX_THRESHOLD_Pos (24)
8045 #define SPI_FIFO_CTL_RX_THRESHOLD_Msk (0x3ul << SPI_FIFO_CTL_RX_THRESHOLD_Pos)
8047 #define SPI_FIFO_CTL_TX_THRESHOLD_Pos (28)
8048 #define SPI_FIFO_CTL_TX_THRESHOLD_Msk (0x3ul << SPI_FIFO_CTL_TX_THRESHOLD_Pos)
8050 #define SPI_STATUS_RX_INTSTS_Pos (0)
8051 #define SPI_STATUS_RX_INTSTS_Msk (0x1ul << SPI_STATUS_RX_INTSTS_Pos)
8053 #define SPI_STATUS_RX_OVERRUN_Pos (2)
8054 #define SPI_STATUS_RX_OVERRUN_Msk (0x1ul << SPI_STATUS_RX_OVERRUN_Pos)
8056 #define SPI_STATUS_TX_INTSTS_Pos (4)
8057 #define SPI_STATUS_TX_INTSTS_Msk (0x1ul << SPI_STATUS_TX_INTSTS_Pos)
8059 #define SPI_STATUS_SLV_START_INTSTS_Pos (11)
8060 #define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos)
8062 #define SPI_STATUS_RX_FIFO_COUNT_Pos (12)
8063 #define SPI_STATUS_RX_FIFO_COUNT_Msk (0xful << SPI_STATUS_RX_FIFO_COUNT_Pos)
8065 #define SPI_STATUS_IF_Pos (16)
8066 #define SPI_STATUS_IF_Msk (0x1ul << SPI_STATUS_IF_Pos)
8068 #define SPI_STATUS_TIMEOUT_Pos (20)
8069 #define SPI_STATUS_TIMEOUT_Msk (0x1ul << SPI_STATUS_TIMEOUT_Pos)
8071 #define SPI_STATUS_RX_EMPTY_Pos (24)
8072 #define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos)
8074 #define SPI_STATUS_RX_FULL_Pos (25)
8075 #define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos)
8077 #define SPI_STATUS_TX_EMPTY_Pos (26)
8078 #define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos)
8080 #define SPI_STATUS_TX_FULL_Pos (27)
8081 #define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos)
8083 #define SPI_STATUS_TX_FIFO_COUNT_Pos (28)
8084 #define SPI_STATUS_TX_FIFO_COUNT_Msk (0xful << SPI_STATUS_TX_FIFO_COUNT_Pos) /* SPI_CONST */
8087 /* end of SPI register group */
8088
8089
8090 /*---------------------- Timer Controller -------------------------*/
8097 typedef struct
8098 {
8099
8456 __IO uint32_t TCSR; /* Offset: 0x00 Timer Control and Status Register */
8457 __IO uint32_t TCMPR; /* Offset: 0x04 Timer Compare Register */
8458 __IO uint32_t TISR; /* Offset: 0x08 Timer Interrupt Status Register */
8459 __I uint32_t TDR; /* Offset: 0x0C Timer Data Register */
8460 __I uint32_t TCAP; /* Offset: 0x10 Timer Capture Data Register */
8461 __IO uint32_t TEXCON; /* Offset: 0x14 Timer External Control Register */
8462 __IO uint32_t TEXISR; /* Offset: 0x18 Timer External Interrupt Status Register */
8463 } TIMER_T;
8464
8465
8466
8472 #define TIMER_TCSR_PRESCALE_Pos (0)
8473 #define TIMER_TCSR_PRESCALE_Msk (0xfful << TIMER_TCSR_PRESCALE_Pos)
8475 #define TIMER_TCSR_TDR_EN_Pos (16)
8476 #define TIMER_TCSR_TDR_EN_Msk (0x1ul << TIMER_TCSR_TDR_EN_Pos)
8478 #define TIMER_TCSR_PERIODIC_SEL_Pos (17)
8479 #define TIMER_TCSR_PERIODIC_SEL_Msk (0x1ul << TIMER_TCSR_PERIODIC_SEL_Pos)
8481 #define TIMER_TCSR_TOGGLE_PIN_Pos (18)
8482 #define TIMER_TCSR_TOGGLE_PIN_Msk (0x1ul << TIMER_TCSR_TOGGLE_PIN_Pos)
8484 #define TIMER_TCSR_TOUT_PIN_Pos (18)
8485 #define TIMER_TCSR_TOUT_PIN_Msk (0x1ul << TIMER_TCSR_TOUT_PIN_Pos)
8487 #define TIMER_TCSR_CAP_SRC_Pos (19)
8488 #define TIMER_TCSR_CAP_SRC_Msk (0x1ul << TIMER_TCSR_CAP_SRC_Pos)
8490 #define TIMER_TCSR_WAKE_EN_Pos (23)
8491 #define TIMER_TCSR_WAKE_EN_Msk (0x1ul << TIMER_TCSR_WAKE_EN_Pos)
8493 #define TIMER_TCSR_CTB_Pos (24)
8494 #define TIMER_TCSR_CTB_Msk (0x1ul << TIMER_TCSR_CTB_Pos)
8496 #define TIMER_TCSR_CACT_Pos (25)
8497 #define TIMER_TCSR_CACT_Msk (0x1ul << TIMER_TCSR_CACT_Pos)
8499 #define TIMER_TCSR_CRST_Pos (26)
8500 #define TIMER_TCSR_CRST_Msk (0x1ul << TIMER_TCSR_CRST_Pos)
8502 #define TIMER_TCSR_MODE_Pos (27)
8503 #define TIMER_TCSR_MODE_Msk (0x3ul << TIMER_TCSR_MODE_Pos)
8505 #define TIMER_TCSR_IE_Pos (29)
8506 #define TIMER_TCSR_IE_Msk (0x1ul << TIMER_TCSR_IE_Pos)
8508 #define TIMER_TCSR_CEN_Pos (30)
8509 #define TIMER_TCSR_CEN_Msk (0x1ul << TIMER_TCSR_CEN_Pos)
8511 #define TIMER_TCSR_DBGACK_TMR_Pos (31)
8512 #define TIMER_TCSR_DBGACK_TMR_Msk (0x1ul << TIMER_TCSR_DBGACK_TMR_Pos)
8514 #define TIMER_TCMP_TCMP_Pos (0)
8515 #define TIMER_TCMP_TCMP_Msk (0xfffffful << TIMER_TCMP_TCMP_Pos)
8517 #define TIMER_TISR_TIF_Pos (0)
8518 #define TIMER_TISR_TIF_Msk (0x1ul << TIMER_TISR_TIF_Pos)
8520 #define TIMER_TISR_TWF_Pos (1)
8521 #define TIMER_TISR_TWF_Msk (0x1ul << TIMER_TISR_TWF_Pos)
8523 #define TIMER_TDR_TDR_Pos (0)
8524 #define TIMER_TDR_TDR_Msk (0xfffffful << TIMER_TDR_TDR_Pos)
8526 #define TIMER_TCAP_TCAP_Pos (0)
8527 #define TIMER_TCAP_TCAP_Msk (0xfffffful << TIMER_TCAP_TCAP_Pos)
8529 #define TIMER_TEXCON_TX_PHASE_Pos (0)
8530 #define TIMER_TEXCON_TX_PHASE_Msk (0x1ul << TIMER_TEXCON_TX_PHASE_Pos)
8532 #define TIMER_TEXCON_TEX_EDGE_Pos (1)
8533 #define TIMER_TEXCON_TEX_EDGE_Msk (0x3ul << TIMER_TEXCON_TEX_EDGE_Pos)
8535 #define TIMER_TEXCON_TEXEN_Pos (3)
8536 #define TIMER_TEXCON_TEXEN_Msk (0x1ul << TIMER_TEXCON_TEXEN_Pos)
8538 #define TIMER_TEXCON_RSTCAPSEL_Pos (4)
8539 #define TIMER_TEXCON_RSTCAPSEL_Msk (0x1ul << TIMER_TEXCON_RSTCAPSEL_Pos)
8541 #define TIMER_TEXCON_TEXIEN_Pos (5)
8542 #define TIMER_TEXCON_TEXIEN_Msk (0x1ul << TIMER_TEXCON_TEXIEN_Pos)
8544 #define TIMER_TEXCON_TEXDB_Pos (6)
8545 #define TIMER_TEXCON_TEXDB_Msk (0x1ul << TIMER_TEXCON_TEXDB_Pos)
8547 #define TIMER_TEXCON_TCDB_Pos (7)
8548 #define TIMER_TEXCON_TCDB_Msk (0x1ul << TIMER_TEXCON_TCDB_Pos)
8550 #define TIMER_TEXCON_CAP_MODE_Pos (8)
8551 #define TIMER_TEXCON_CAP_MODE_Msk (0x1ul << TIMER_TEXCON_CAP_MODE_Pos)
8553 #define TIMER_TEXISR_TEXIF_Pos (0)
8554 #define TIMER_TEXISR_TEXIF_Msk (0x1ul << TIMER_TEXISR_TEXIF_Pos) /* TMR_CONST */
8557 /* end of TMR register group */
8558
8559
8560 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
8567 typedef struct
8568 {
8569
9451 union
9452 {
9453 __I uint32_t RBR; /* Offset: 0x00 UART Receive Buffer Register */
9454 __O uint32_t THR; /* Offset: 0x00 UART Transmit Holding Register */
9455 };
9456 __IO uint32_t IER; /* Offset: 0x04 UART Interrupt Enable Control Register */
9457 __IO uint32_t FCR; /* Offset: 0x08 UART FIFO Control Register */
9458 __IO uint32_t LCR; /* Offset: 0x0C UART Line Control Register */
9459 __IO uint32_t MCR; /* Offset: 0x10 UART Modem Control Register */
9460 __IO uint32_t MSR; /* Offset: 0x14 UART Modem Status Register */
9461 __IO uint32_t FSR; /* Offset: 0x18 UART FIFO Status Register */
9462 __IO uint32_t ISR; /* Offset: 0x1C UART Interrupt Status Register */
9463 __IO uint32_t TOR; /* Offset: 0x20 UART Time-out Register */
9464 __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
9465 __IO uint32_t IRCR; /* Offset: 0x28 UART IrDA Control Register */
9466 __IO uint32_t ALT_CSR; /* Offset: 0x2C UART Alternate Control/Status Register */
9467 __IO uint32_t FUN_SEL; /* Offset: 0x30 UART Function Select Register */
9468
9469 } UART_T;
9470
9471
9472
9478 #define UART_RBR_RBR_Pos (0)
9479 #define UART_RBR_RBR_Msk (0xfful << UART_RBR_RBR_Pos)
9481 #define UART_THR_THR_Pos (0)
9482 #define UART_THR_THR_Msk (0xfful << UART_THR_THR_Pos)
9484 #define UART_IER_RDA_IEN_Pos (0)
9485 #define UART_IER_RDA_IEN_Msk (0x1ul << UART_IER_RDA_IEN_Pos)
9487 #define UART_IER_THRE_IEN_Pos (1)
9488 #define UART_IER_THRE_IEN_Msk (0x1ul << UART_IER_THRE_IEN_Pos)
9490 #define UART_IER_RLS_IEN_Pos (2)
9491 #define UART_IER_RLS_IEN_Msk (0x1ul << UART_IER_RLS_IEN_Pos)
9493 #define UART_IER_MODEM_IEN_Pos (3)
9494 #define UART_IER_MODEM_IEN_Msk (0x1ul << UART_IER_MODEM_IEN_Pos)
9496 #define UART_IER_RTO_IEN_Pos (4)
9497 #define UART_IER_RTO_IEN_Msk (0x1ul << UART_IER_RTO_IEN_Pos)
9499 #define UART_IER_BUF_ERR_IEN_Pos (5)
9500 #define UART_IER_BUF_ERR_IEN_Msk (0x1ul << UART_IER_BUF_ERR_IEN_Pos)
9502 #define UART_IER_WAKE_EN_Pos (6)
9503 #define UART_IER_WAKE_EN_Msk (0x1ul << UART_IER_WAKE_EN_Pos)
9505 #define UART_IER_TIME_OUT_EN_Pos (11)
9506 #define UART_IER_TIME_OUT_EN_Msk (0x1ul << UART_IER_TIME_OUT_EN_Pos)
9508 #define UART_IER_AUTO_RTS_EN_Pos (12)
9509 #define UART_IER_AUTO_RTS_EN_Msk (0x1ul << UART_IER_AUTO_RTS_EN_Pos)
9511 #define UART_IER_AUTO_CTS_EN_Pos (13)
9512 #define UART_IER_AUTO_CTS_EN_Msk (0x1ul << UART_IER_AUTO_CTS_EN_Pos)
9514 #define UART_FCR_RFR_Pos (1)
9515 #define UART_FCR_RFR_Msk (0x1ul << UART_FCR_RFR_Pos)
9517 #define UART_FCR_TFR_Pos (2)
9518 #define UART_FCR_TFR_Msk (0x1ul << UART_FCR_TFR_Pos)
9520 #define UART_FCR_RFITL_Pos (4)
9521 #define UART_FCR_RFITL_Msk (0xful << UART_FCR_RFITL_Pos)
9523 #define UART_FCR_RX_DIS_Pos (8)
9524 #define UART_FCR_RX_DIS_Msk (0x1ul << UART_FCR_RX_DIS_Pos)
9526 #define UART_FCR_RTS_TRI_LEV_Pos (16)
9527 #define UART_FCR_RTS_TRI_LEV_Msk (0xful << UART_FCR_RTS_TRI_LEV_Pos)
9529 #define UART_LCR_WLS_Pos (0)
9530 #define UART_LCR_WLS_Msk (0x3ul << UART_LCR_WLS_Pos)
9532 #define UART_LCR_NSB_Pos (2)
9533 #define UART_LCR_NSB_Msk (0x1ul << UART_LCR_NSB_Pos)
9535 #define UART_LCR_PBE_Pos (3)
9536 #define UART_LCR_PBE_Msk (0x1ul << UART_LCR_PBE_Pos)
9538 #define UART_LCR_EPE_Pos (4)
9539 #define UART_LCR_EPE_Msk (0x1ul << UART_LCR_EPE_Pos)
9541 #define UART_LCR_SPE_Pos (5)
9542 #define UART_LCR_SPE_Msk (0x1ul << UART_LCR_SPE_Pos)
9544 #define UART_LCR_BCB_Pos (6)
9545 #define UART_LCR_BCB_Msk (0x1ul << UART_LCR_BCB_Pos)
9547 #define UART_MCR_RTS_Pos (1)
9548 #define UART_MCR_RTS_Msk (0x1ul << UART_MCR_RTS_Pos)
9550 #define UART_MCR_LEV_RTS_Pos (9)
9551 #define UART_MCR_LEV_RTS_Msk (0x1ul << UART_MCR_LEV_RTS_Pos)
9553 #define UART_MCR_RTS_ST_Pos (13)
9554 #define UART_MCR_RTS_ST_Msk (0x1ul << UART_MCR_RTS_ST_Pos)
9556 #define UART_MSR_DCTSF_Pos (0)
9557 #define UART_MSR_DCTSF_Msk (0x1ul << UART_MSR_DCTSF_Pos)
9559 #define UART_MSR_CTS_ST_Pos (4)
9560 #define UART_MSR_CTS_ST_Msk (0x1ul << UART_MSR_CTS_ST_Pos)
9562 #define UART_MSR_LEV_CTS_Pos (8)
9563 #define UART_MSR_LEV_CTS_Msk (0x1ul << UART_MSR_LEV_CTS_Pos)
9565 #define UART_FSR_RX_OVER_IF_Pos (0)
9566 #define UART_FSR_RX_OVER_IF_Msk (0x1ul << UART_FSR_RX_OVER_IF_Pos)
9568 #define UART_FSR_RS485_ADD_DETF_Pos (3)
9569 #define UART_FSR_RS485_ADD_DETF_Msk (0x1ul << UART_FSR_RS485_ADD_DETF_Pos)
9571 #define UART_FSR_PEF_Pos (4)
9572 #define UART_FSR_PEF_Msk (0x1ul << UART_FSR_PEF_Pos)
9574 #define UART_FSR_FEF_Pos (5)
9575 #define UART_FSR_FEF_Msk (0x1ul << UART_FSR_FEF_Pos)
9577 #define UART_FSR_BIF_Pos (6)
9578 #define UART_FSR_BIF_Msk (0x1ul << UART_FSR_BIF_Pos)
9580 #define UART_FSR_RX_POINTER_Pos (8)
9581 #define UART_FSR_RX_POINTER_Msk (0x3ful << UART_FSR_RX_POINTER_Pos)
9583 #define UART_FSR_RX_EMPTY_Pos (14)
9584 #define UART_FSR_RX_EMPTY_Msk (0x1ul << UART_FSR_RX_EMPTY_Pos)
9586 #define UART_FSR_RX_FULL_Pos (15)
9587 #define UART_FSR_RX_FULL_Msk (0x1ul << UART_FSR_RX_FULL_Pos)
9589 #define UART_FSR_TX_POINTER_Pos (16)
9590 #define UART_FSR_TX_POINTER_Msk (0x3ful << UART_FSR_TX_POINTER_Pos)
9592 #define UART_FSR_TX_EMPTY_Pos (22)
9593 #define UART_FSR_TX_EMPTY_Msk (0x1ul << UART_FSR_TX_EMPTY_Pos)
9595 #define UART_FSR_TX_FULL_Pos (23)
9596 #define UART_FSR_TX_FULL_Msk (0x1ul << UART_FSR_TX_FULL_Pos)
9598 #define UART_FSR_TX_OVER_IF_Pos (24)
9599 #define UART_FSR_TX_OVER_IF_Msk (0x1ul << UART_FSR_TX_OVER_IF_Pos)
9601 #define UART_FSR_TE_FLAG_Pos (28)
9602 #define UART_FSR_TE_FLAG_Msk (0x1ul << UART_FSR_TE_FLAG_Pos)
9604 #define UART_ISR_RDA_IF_Pos (0)
9605 #define UART_ISR_RDA_IF_Msk (0x1ul << UART_ISR_RDA_IF_Pos)
9607 #define UART_ISR_THRE_IF_Pos (1)
9608 #define UART_ISR_THRE_IF_Msk (0x1ul << UART_ISR_THRE_IF_Pos)
9610 #define UART_ISR_RLS_IF_Pos (2)
9611 #define UART_ISR_RLS_IF_Msk (0x1ul << UART_ISR_RLS_IF_Pos)
9613 #define UART_ISR_MODEM_IF_Pos (3)
9614 #define UART_ISR_MODEM_IF_Msk (0x1ul << UART_ISR_MODEM_IF_Pos)
9616 #define UART_ISR_TOUT_IF_Pos (4)
9617 #define UART_ISR_TOUT_IF_Msk (0x1ul << UART_ISR_TOUT_IF_Pos)
9619 #define UART_ISR_BUF_ERR_IF_Pos (5)
9620 #define UART_ISR_BUF_ERR_IF_Msk (0x1ul << UART_ISR_BUF_ERR_IF_Pos)
9622 #define UART_ISR_RDA_INT_Pos (8)
9623 #define UART_ISR_RDA_INT_Msk (0x1ul << UART_ISR_RDA_INT_Pos)
9625 #define UART_ISR_THRE_INT_Pos (9)
9626 #define UART_ISR_THRE_INT_Msk (0x1ul << UART_ISR_THRE_INT_Pos)
9628 #define UART_ISR_RLS_INT_Pos (10)
9629 #define UART_ISR_RLS_INT_Msk (0x1ul << UART_ISR_RLS_INT_Pos)
9631 #define UART_ISR_MODEM_INT_Pos (11)
9632 #define UART_ISR_MODEM_INT_Msk (0x1ul << UART_ISR_MODEM_INT_Pos)
9634 #define UART_ISR_TOUT_INT_Pos (12)
9635 #define UART_ISR_TOUT_INT_Msk (0x1ul << UART_ISR_TOUT_INT_Pos)
9637 #define UART_ISR_BUF_ERR_INT_Pos (13)
9638 #define UART_ISR_BUF_ERR_INT_Msk (0x1ul << UART_ISR_BUF_ERR_INT_Pos)
9640 #define UART_TOR_TOIC_Pos (0)
9641 #define UART_TOR_TOIC_Msk (0xfful << UART_TOR_TOIC_Pos)
9643 #define UART_TOR_DLY_Pos (8)
9644 #define UART_TOR_DLY_Msk (0xfful << UART_TOR_DLY_Pos)
9646 #define UART_BAUD_BRD_Pos (0)
9647 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
9649 #define UART_BAUD_DIVIDER_X_Pos (24)
9650 #define UART_BAUD_DIVIDER_X_Msk (0xful << UART_BAUD_DIVIDER_X_Pos)
9652 #define UART_BAUD_DIV_X_ONE_Pos (28)
9653 #define UART_BAUD_DIV_X_ONE_Msk (0x1ul << UART_BAUD_DIV_X_ONE_Pos)
9655 #define UART_BAUD_DIV_X_EN_Pos (29)
9656 #define UART_BAUD_DIV_X_EN_Msk (0x1ul << UART_BAUD_DIV_X_EN_Pos)
9658 #define UART_IRCR_TX_SELECT_Pos (1)
9659 #define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos)
9661 #define UART_IRCR_INV_TX_Pos (5)
9662 #define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos)
9664 #define UART_IRCR_INV_RX_Pos (6)
9665 #define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos)
9667 #define UART_ALT_CSR_RS485_NMM_Pos (8)
9668 #define UART_ALT_CSR_RS485_NMM_Msk (0x1ul << UART_ALT_CSR_RS485_NMM_Pos)
9670 #define UART_ALT_CSR_RS485_AAD_Pos (9)
9671 #define UART_ALT_CSR_RS485_AAD_Msk (0x1ul << UART_ALT_CSR_RS485_AAD_Pos)
9673 #define UART_ALT_CSR_RS485_AUD_Pos (10)
9674 #define UART_ALT_CSR_RS485_AUD_Msk (0x1ul << UART_ALT_CSR_RS485_AUD_Pos)
9676 #define UART_ALT_CSR_RS485_ADD_EN_Pos (15)
9677 #define UART_ALT_CSR_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CSR_RS485_ADD_EN_Pos)
9679 #define UART_ALT_CSR_ADDR_MATCH_Pos (24)
9680 #define UART_ALT_CSR_ADDR_MATCH_Msk (0xfful << UART_ALT_CSR_ADDR_MATCH_Pos)
9682 #define UART_FUN_SEL_FUN_SEL_Pos (0)
9683 #define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /* UART_CONST */
9686 /* end of UART register group */
9687
9688
9689 /*---------------------- Watch Dog Timer Controller -------------------------*/
9696 typedef struct
9697 {
9698
9826 __IO uint32_t WTCR; /* Offset: 0x00 Watchdog Timer Control Register */
9827
9828 } WDT_T;
9829
9830
9831
9837 #define WDT_WTCR_WTR_Pos (0)
9838 #define WDT_WTCR_WTR_Msk (0x1ul << WDT_WTCR_WTR_Pos)
9840 #define WDT_WTCR_WTRE_Pos (1)
9841 #define WDT_WTCR_WTRE_Msk (0x1ul << WDT_WTCR_WTRE_Pos)
9843 #define WDT_WTCR_WTRF_Pos (2)
9844 #define WDT_WTCR_WTRF_Msk (0x1ul << WDT_WTCR_WTRF_Pos)
9846 #define WDT_WTCR_WTIF_Pos (3)
9847 #define WDT_WTCR_WTIF_Msk (0x1ul << WDT_WTCR_WTIF_Pos)
9849 #define WDT_WTCR_WTWKE_Pos (4)
9850 #define WDT_WTCR_WTWKE_Msk (0x1ul << WDT_WTCR_WTWKE_Pos)
9852 #define WDT_WTCR_WTWKF_Pos (5)
9853 #define WDT_WTCR_WTWKF_Msk (0x1ul << WDT_WTCR_WTWKF_Pos)
9855 #define WDT_WTCR_WTIE_Pos (6)
9856 #define WDT_WTCR_WTIE_Msk (0x1ul << WDT_WTCR_WTIE_Pos)
9858 #define WDT_WTCR_WTE_Pos (7)
9859 #define WDT_WTCR_WTE_Msk (0x1ul << WDT_WTCR_WTE_Pos)
9861 #define WDT_WTCR_WTIS_Pos (8)
9862 #define WDT_WTCR_WTIS_Msk (0x7ul << WDT_WTCR_WTIS_Pos)
9864 #define WDT_WTCR_DBGACK_WDT_Pos (31)
9865 #define WDT_WTCR_DBGACK_WDT_Msk (0x1ul << WDT_WTCR_DBGACK_WDT_Pos) /* WDT_CONST */
9868 /* end of WDT register group */
9869
9870
9871 #if defined ( __CC_ARM )
9872 #pragma no_anon_unions
9873 #endif
9874
9879 /* Peripheral and SRAM base address */
9880 #define FLASH_BASE ((uint32_t)0x00000000)
9881 #define SRAM_BASE ((uint32_t)0x20000000)
9882 #define APB1PERIPH_BASE ((uint32_t)0x40000000)
9883 #define APB2PERIPH_BASE ((uint32_t)0x40100000)
9884 #define AHBPERIPH_BASE ((uint32_t)0x50000000)
9885
9886 /* Peripheral memory map */
9887 #define WDT_BASE (APB1PERIPH_BASE + 0x04000)
9888 #define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
9889 #define TIMER1_BASE (APB1PERIPH_BASE + 0x10020)
9890 #define I2C_BASE (APB1PERIPH_BASE + 0x20000)
9891 #define SPI_BASE (APB1PERIPH_BASE + 0x30000)
9892 #define PWM_BASE (APB1PERIPH_BASE + 0x40000)
9893 #define UART_BASE (APB1PERIPH_BASE + 0x50000)
9894 #define ACMP_BASE (APB1PERIPH_BASE + 0xD0000)
9895 #define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
9896
9897 #define GCR_BASE (AHBPERIPH_BASE + 0x00000)
9898 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
9899 #define INT_BASE (AHBPERIPH_BASE + 0x00300)
9900 #define P0_BASE (AHBPERIPH_BASE + 0x04000)
9901 #define P1_BASE (AHBPERIPH_BASE + 0x04040)
9902 #define P2_BASE (AHBPERIPH_BASE + 0x04080)
9903 #define P3_BASE (AHBPERIPH_BASE + 0x040C0)
9904 #define P4_BASE (AHBPERIPH_BASE + 0x04100)
9905 #define P5_BASE (AHBPERIPH_BASE + 0x04140)
9906 #define GPIO_DBNCECON_BASE (AHBPERIPH_BASE + 0x04180)
9907 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
9908 #define GPIOBIT0_BASE (AHBPERIPH_BASE + 0x04200)
9909 #define GPIOBIT1_BASE (AHBPERIPH_BASE + 0x04220)
9910 #define GPIOBIT2_BASE (AHBPERIPH_BASE + 0x04240)
9911 #define GPIOBIT3_BASE (AHBPERIPH_BASE + 0x04260)
9912 #define GPIOBIT4_BASE (AHBPERIPH_BASE + 0x04280)
9913 #define GPIOBIT5_BASE (AHBPERIPH_BASE + 0x042A0)
9914 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
9915
9916 /* end of group MINI51_PERIPHERAL_MEM_MAP */
9917
9918
9923 #define WDT ((WDT_T *) WDT_BASE)
9924 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
9925 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
9926 #define I2C ((I2C_T *) I2C_BASE)
9927 #define I2C0 ((I2C_T *) I2C_BASE)
9928 #define SPI ((SPI_T *) SPI_BASE)
9929 #define SPI0 ((SPI_T *) SPI_BASE)
9930 #define PWM ((PWM_T *) PWM_BASE)
9931 #define UART ((UART_T *) UART_BASE)
9932 #define UART0 ((UART_T *) UART_BASE)
9933 #define ADC ((ADC_T *) ADC_BASE)
9934 #define ACMP ((ACMP_T *) ACMP_BASE)
9935
9936 #define SYS ((GCR_T *) GCR_BASE)
9937 #define CLK ((CLK_T *) CLK_BASE)
9938 #define INT ((INT_T *) INT_BASE)
9939 #define P0 ((GPIO_T *) P0_BASE)
9940 #define P1 ((GPIO_T *) P1_BASE)
9941 #define P2 ((GPIO_T *) P2_BASE)
9942 #define P3 ((GPIO_T *) P3_BASE)
9943 #define P4 ((GPIO_T *) P4_BASE)
9944 #define P5 ((GPIO_T *) P5_BASE)
9945 #define GPIO ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE)
9946 #define FMC ((FMC_T *) FMC_BASE)
9947
9948 /* end of group MINI51_PERIPHERAL_DECLARATION */ /* end of group MINI51_Peripherals */
9950
9956 typedef volatile unsigned char vu8;
9957 typedef volatile unsigned short vu16;
9958 typedef volatile unsigned long vu32;
9959
9965 #define M8(addr) (*((vu8 *) (addr)))
9966
9973 #define M16(addr) (*((vu16 *) (addr)))
9974
9981 #define M32(addr) (*((vu32 *) (addr)))
9982
9990 #define outpw(port,value) *((volatile unsigned int *)(port)) = value
9991
9998 #define inpw(port) (*((volatile unsigned int *)(port)))
9999
10007 #define outps(port,value) *((volatile unsigned short *)(port)) = value
10008
10015 #define inps(port) (*((volatile unsigned short *)(port)))
10016
10023 #define outpb(port,value) *((volatile unsigned char *)(port)) = value
10024
10030 #define inpb(port) (*((volatile unsigned char *)(port)))
10031
10039 #define outp32(port,value) *((volatile unsigned int *)(port)) = value
10040
10047 #define inp32(port) (*((volatile unsigned int *)(port)))
10048
10056 #define outp16(port,value) *((volatile unsigned short *)(port)) = value
10057
10064 #define inp16(port) (*((volatile unsigned short *)(port)))
10065
10072 #define outp8(port,value) *((volatile unsigned char *)(port)) = value
10073
10079 #define inp8(port) (*((volatile unsigned char *)(port)))
10080
10081 /* end of group MINI51_IO_ROUTINE */
10083
10084 /******************************************************************************/
10085 /* Legacy Constants */
10086 /******************************************************************************/
10092 #ifndef NULL
10093 #define NULL (0)
10094 #endif
10095
10096 #define TRUE (1)
10097 #define FALSE (0)
10098
10099 #define ENABLE (1)
10100 #define DISABLE (0)
10101
10102 /* Define one bit mask */
10103 #define BIT0 (0x00000001)
10104 #define BIT1 (0x00000002)
10105 #define BIT2 (0x00000004)
10106 #define BIT3 (0x00000008)
10107 #define BIT4 (0x00000010)
10108 #define BIT5 (0x00000020)
10109 #define BIT6 (0x00000040)
10110 #define BIT7 (0x00000080)
10111 #define BIT8 (0x00000100)
10112 #define BIT9 (0x00000200)
10113 #define BIT10 (0x00000400)
10114 #define BIT11 (0x00000800)
10115 #define BIT12 (0x00001000)
10116 #define BIT13 (0x00002000)
10117 #define BIT14 (0x00004000)
10118 #define BIT15 (0x00008000)
10119 #define BIT16 (0x00010000)
10120 #define BIT17 (0x00020000)
10121 #define BIT18 (0x00040000)
10122 #define BIT19 (0x00080000)
10123 #define BIT20 (0x00100000)
10124 #define BIT21 (0x00200000)
10125 #define BIT22 (0x00400000)
10126 #define BIT23 (0x00800000)
10127 #define BIT24 (0x01000000)
10128 #define BIT25 (0x02000000)
10129 #define BIT26 (0x04000000)
10130 #define BIT27 (0x08000000)
10131 #define BIT28 (0x10000000)
10132 #define BIT29 (0x20000000)
10133 #define BIT30 (0x40000000)
10134 #define BIT31 (0x80000000)
10135
10136 /* Byte Mask Definitions */
10137 #define BYTE0_Msk (0x000000FF)
10138 #define BYTE1_Msk (0x0000FF00)
10139 #define BYTE2_Msk (0x00FF0000)
10140 #define BYTE3_Msk (0xFF000000)
10141
10142 #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
10143 #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
10144 #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
10145 #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
10147 /* end of group MINI51_legacy_Constants */
10148 /* end of group MINI51_Definitions */
10150
10151 #ifdef __cplusplus
10152 }
10153 #endif
10154
10155
10156 /******************************************************************************/
10157 /* Peripheral header files */
10158 /******************************************************************************/
10159 #include "sys.h"
10160 #include "clk.h"
10161 #include "acmp.h"
10162 #include "adc.h"
10163 #include "fmc.h"
10164 #include "gpio.h"
10165 #include "i2c.h"
10166 #include "pwm.h"
10167 #include "spi.h"
10168 #include "timer.h"
10169 #include "uart.h"
10170 #include "wdt.h"
10171
10172 #endif // __MINI51SERIES_H__
10173
PWM_T::TRGCON1
__IO uint32_t TRGCON1
Definition: Mini51Series.h:6666
ADC_T::ADSR
__IO uint32_t ADSR
Definition: Mini51Series.h:797
SPI_T::TX
__O uint32_t TX
Definition: Mini51Series.h:7919
GCR_T::IRCTRIMIER
__IO uint32_t IRCTRIMIER
Definition: Mini51Series.h:2701
UART_T::FCR
__IO uint32_t FCR
Definition: Mini51Series.h:9457
FMC_T::ISPCON
__IO uint32_t ISPCON
Definition: Mini51Series.h:1878
uart.h
Mini51 series UART driver header file.
GPIO_T
Definition: Mini51Series.h:2971
CLK_T::CLKSTATUS
__IO uint32_t CLKSTATUS
Definition: Mini51Series.h:1465
UART_T::IER
__IO uint32_t IER
Definition: Mini51Series.h:9456
GCR_T
Definition: Mini51Series.h:1954
pwm.h
Mini51 series PWM driver header file.
I2C_T::I2CDAT
__IO uint32_t I2CDAT
Definition: Mini51Series.h:4223
SPI_T::DIVIDER
__IO uint32_t DIVIDER
Definition: Mini51Series.h:7910
UART_IRQn
Definition: Mini51Series.h:102
acmp.h
Mini51 series Analog Comparator(ACMP) driver header file.
PWM_T::TRGSTS1
__IO uint32_t TRGSTS1
Definition: Mini51Series.h:6668
INT_T::SRC16
__I uint32_t SRC16
Definition: Mini51Series.h:4744
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Mini51Series.h:9956
UART_T::FUN_SEL
__IO uint32_t FUN_SEL
Definition: Mini51Series.h:9467
EINT0_IRQn
Definition: Mini51Series.h:94
GCR_T::BODCTL
__IO uint32_t BODCTL
Definition: Mini51Series.h:2687
INT_T::SRC17
__I uint32_t SRC17
Definition: Mini51Series.h:4745
TIMER_T::TEXCON
__IO uint32_t TEXCON
Definition: Mini51Series.h:8461
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: Mini51Series.h:1882
gpio.h
Mini51 series GPIO driver header file.
SPI_T::RX
__I uint32_t RX
Definition: Mini51Series.h:7915
GCR_T::P1_MFP
__IO uint32_t P1_MFP
Definition: Mini51Series.h:2692
I2C_T
Definition: Mini51Series.h:3733
ADC_T::ADDR
__I uint32_t ADDR
Definition: Mini51Series.h:790
INT_T::SRC1
__I uint32_t SRC1
Definition: Mini51Series.h:4724
PWM_IRQn
Definition: Mini51Series.h:98
INT_T
Definition: Mini51Series.h:4336
I2C_T::I2CADM2
__IO uint32_t I2CADM2
Definition: Mini51Series.h:4232
PWM_T::TRGCON0
__IO uint32_t TRGCON0
Definition: Mini51Series.h:6665
I2C_T::I2CADM3
__IO uint32_t I2CADM3
Definition: Mini51Series.h:4233
UART_T::ISR
__IO uint32_t ISR
Definition: Mini51Series.h:9462
PWM_T::PIIR
__IO uint32_t PIIR
Definition: Mini51Series.h:6661
GCR_T::P2_MFP
__IO uint32_t P2_MFP
Definition: Mini51Series.h:2693
sys.h
Mini51 series SYS driver header file.
GPIO_T::ISRC
__IO uint32_t ISRC
Definition: Mini51Series.h:3577
PWM_T::INTACCUCTL
__IO uint32_t INTACCUCTL
Definition: Mini51Series.h:6672
CLK_T
Definition: Mini51Series.h:926
I2C_T::I2CON2
__IO uint32_t I2CON2
Definition: Mini51Series.h:4237
UART_T::LCR
__IO uint32_t LCR
Definition: Mini51Series.h:9458
INT_T::NMICON
__IO uint32_t NMICON
Definition: Mini51Series.h:4759
PWM_T::PPR
__IO uint32_t PPR
Definition: Mini51Series.h:6652
SPI_T::CNTRL
__IO uint32_t CNTRL
Definition: Mini51Series.h:7909
GCR_T::IPRSTC2
__IO uint32_t IPRSTC2
Definition: Mini51Series.h:2683
system_Mini51Series.h
Mini51 series system clock definition file.
timer.h
Mini51 series TIMER driver header file.
adc.h
Mini51 series ADC driver header file.
CLK_T::PWRCON
__IO uint32_t PWRCON
Definition: Mini51Series.h:1462
SPI_T
Definition: Mini51Series.h:7300
wdt.h
Mini51 series WDT driver header file.
INT_T::SRC4
__I uint32_t SRC4
Definition: Mini51Series.h:4727
GPIO_T::IMD
__IO uint32_t IMD
Definition: Mini51Series.h:3575
I2C_T::I2CADDR3
__IO uint32_t I2CADDR3
Definition: Mini51Series.h:4229
spi.h
Mini51 series SPI driver header file.
PWM_T::PHCHGMASK
__IO uint32_t PHCHGMASK
Definition: Mini51Series.h:6671
FB_IRQn
Definition: Mini51Series.h:99
SPI_T::CNTRL2
__IO uint32_t CNTRL2
Definition: Mini51Series.h:7923
SPI_IRQn
Definition: Mini51Series.h:103
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: Mini51Series.h:1880
INT_T::SRC29
__I uint32_t SRC29
Definition: Mini51Series.h:4755
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: Mini51Series.h:1466
GPIO_DBNCECON_T
GPIO debounce register map.
Definition: Mini51Series.h:3583
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: Mini51Series.h:1467
IRQn
IRQn
Definition: Mini51Series.h:80
WDT_T
Definition: Mini51Series.h:9696
UART_T::ALT_CSR
__IO uint32_t ALT_CSR
Definition: Mini51Series.h:9466
TMR0_IRQn
Definition: Mini51Series.h:100
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: Mini51Series.h:1469
GCR_T::IRCTRIMISR
__IO uint32_t IRCTRIMISR
Definition: Mini51Series.h:2702
INT_T::SRC5
__I uint32_t SRC5
Definition: Mini51Series.h:4728
PWM_T::PFBCON
__IO uint32_t PFBCON
Definition: Mini51Series.h:6663
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Mini51Series.h:9957
INT_T::SRC12
__I uint32_t SRC12
Definition: Mini51Series.h:4736
UART_T::BAUD
__IO uint32_t BAUD
Definition: Mini51Series.h:9464
ACMP_T
Definition: Mini51Series.h:156
UART_T::MCR
__IO uint32_t MCR
Definition: Mini51Series.h:9459
INT_T::SRC6
__I uint32_t SRC6
Definition: Mini51Series.h:4729
I2C_T::I2CSTATUS2
__IO uint32_t I2CSTATUS2
Definition: Mini51Series.h:4238
fmc.h
MINI51 series FMC driver header file.
EINT1_IRQn
Definition: Mini51Series.h:95
GCR_T::IRCTRIMCTL
__IO uint32_t IRCTRIMCTL
Definition: Mini51Series.h:2700
INT_T::MCUIRQ
__IO uint32_t MCUIRQ
Definition: Mini51Series.h:4760
ADC_IRQn
Definition: Mini51Series.h:109
SysTick_IRQn
Definition: Mini51Series.h:88
INT_T::SRC25
__I uint32_t SRC25
Definition: Mini51Series.h:4750
PendSV_IRQn
Definition: Mini51Series.h:87
ACMP_T::CMPSR
__IO uint32_t CMPSR
Definition: Mini51Series.h:314
TIMER_T::TCAP
__I uint32_t TCAP
Definition: Mini51Series.h:8460
clk.h
Mini51 series CLK driver header file.
GCR_T::IPRSTC1
__IO uint32_t IPRSTC1
Definition: Mini51Series.h:2682
PWM_T::PHCHGNXT
__IO uint32_t PHCHGNXT
Definition: Mini51Series.h:6670
I2C_T::I2CTOC
__IO uint32_t I2CTOC
Definition: Mini51Series.h:4226
PWM_T::PCR
__IO uint32_t PCR
Definition: Mini51Series.h:6654
INT_T::SRC7
__I uint32_t SRC7
Definition: Mini51Series.h:4730
INT_T::SRC2
__I uint32_t SRC2
Definition: Mini51Series.h:4725
CLK_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Mini51Series.h:1468
TIMER_T::TEXISR
__IO uint32_t TEXISR
Definition: Mini51Series.h:8462
TIMER_T::TDR
__I uint32_t TDR
Definition: Mini51Series.h:8459
I2C_T::I2CADDR1
__IO uint32_t I2CADDR1
Definition: Mini51Series.h:4227
I2C_T::I2CLK
__IO uint32_t I2CLK
Definition: Mini51Series.h:4225
GCR_T::RegLockAddr
__IO uint32_t RegLockAddr
Definition: Mini51Series.h:2706
UART_T::MSR
__IO uint32_t MSR
Definition: Mini51Series.h:9460
UART_T::FSR
__IO uint32_t FSR
Definition: Mini51Series.h:9461
UART_T::THR
__O uint32_t THR
Definition: Mini51Series.h:9454
INT_T::SRC0
__I uint32_t SRC0
Definition: Mini51Series.h:4723
WDT_IRQn
Definition: Mini51Series.h:93
HardFault_IRQn
Definition: Mini51Series.h:85
GPIO01_IRQn
Definition: Mini51Series.h:96
GPIO_T::PMD
__IO uint32_t PMD
Definition: Mini51Series.h:3569
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: Mini51Series.h:1881
ADC_T
Definition: Mini51Series.h:376
PWM_T::POE
__IO uint32_t POE
Definition: Mini51Series.h:6662
TIMER_T::TCMPR
__IO uint32_t TCMPR
Definition: Mini51Series.h:8457
ADC_T::ADTDCR
__IO uint32_t ADTDCR
Definition: Mini51Series.h:801
I2C_T::I2CSTATUS
__I uint32_t I2CSTATUS
Definition: Mini51Series.h:4224
UART_T::IRCR
__IO uint32_t IRCR
Definition: Mini51Series.h:9465
ACMP_IRQn
Definition: Mini51Series.h:107
I2C_T::I2CADDR2
__IO uint32_t I2CADDR2
Definition: Mini51Series.h:4228
CLK_T::FRQDIV
__IO uint32_t FRQDIV
Definition: Mini51Series.h:1473
PWM_T::CSR
__IO uint32_t CSR
Definition: Mini51Series.h:6653
I2C_IRQn
Definition: Mini51Series.h:106
FMC_T::DFBADR
__I uint32_t DFBADR
Definition: Mini51Series.h:1883
ADC_T::ADCR
__IO uint32_t ADCR
Definition: Mini51Series.h:794
FMC_T
Definition: Mini51Series.h:1635
GCR_T::P5_MFP
__IO uint32_t P5_MFP
Definition: Mini51Series.h:2696
TIMER_T::TISR
__IO uint32_t TISR
Definition: Mini51Series.h:8458
INT_T::SRC9
__I uint32_t SRC9
Definition: Mini51Series.h:4732
GCR_T::PDID
__I uint32_t PDID
Definition: Mini51Series.h:2680
TIMER_T
Definition: Mini51Series.h:8097
TIMER_T::TCSR
__IO uint32_t TCSR
Definition: Mini51Series.h:8456
ADC_T::ADCHER
__IO uint32_t ADCHER
Definition: Mini51Series.h:795
IRQn_Type
enum IRQn IRQn_Type
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: Mini51Series.h:3574
GCR_T::P3_MFP
__IO uint32_t P3_MFP
Definition: Mini51Series.h:2694
ACMP_T::CMPRVCR
__IO uint32_t CMPRVCR
Definition: Mini51Series.h:315
GCR_T::P4_MFP
__IO uint32_t P4_MFP
Definition: Mini51Series.h:2695
INT_T::SRC8
__I uint32_t SRC8
Definition: Mini51Series.h:4731
UART_T::RBR
__I uint32_t RBR
Definition: Mini51Series.h:9453
WDT_T::WTCR
__IO uint32_t WTCR
Definition: Mini51Series.h:9826
PWM_T::PHCHG
__IO uint32_t PHCHG
Definition: Mini51Series.h:6669
SPI_T::FIFO_CTL
__IO uint32_t FIFO_CTL
Definition: Mini51Series.h:7924
PWM_T::PDZIR
__IO uint32_t PDZIR
Definition: Mini51Series.h:6664
FMC_T::ISPADR
__IO uint32_t ISPADR
Definition: Mini51Series.h:1879
GPIO_T::OFFD
__IO uint32_t OFFD
Definition: Mini51Series.h:3570
UART_T
Definition: Mini51Series.h:8567
SVCall_IRQn
Definition: Mini51Series.h:86
SPI_T::SSR
__IO uint32_t SSR
Definition: Mini51Series.h:7911
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: Mini51Series.h:1463
I2C_T::I2CON
__IO uint32_t I2CON
Definition: Mini51Series.h:4221
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: Mini51Series.h:3571
FMC_T::ISPSTA
__I uint32_t ISPSTA
Definition: Mini51Series.h:1887
INT_T::SRC18
__I uint32_t SRC18
Definition: Mini51Series.h:4746
GPIO5_IRQn
Definition: Mini51Series.h:104
PDWU_IRQn
Definition: Mini51Series.h:108
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Mini51Series.h:7925
I2C_T::I2CADDR0
__IO uint32_t I2CADDR0
Definition: Mini51Series.h:4222
BOD_IRQn
Definition: Mini51Series.h:92
GPIO_T::IEN
__IO uint32_t IEN
Definition: Mini51Series.h:3576
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: Mini51Series.h:1464
NonMaskableInt_IRQn
Definition: Mini51Series.h:84
PWM_T::TRGSTS0
__IO uint32_t TRGSTS0
Definition: Mini51Series.h:6667
TMR1_IRQn
Definition: Mini51Series.h:101
GCR_T::P0_MFP
__IO uint32_t P0_MFP
Definition: Mini51Series.h:2691
INT_T::SRC3
__I uint32_t SRC3
Definition: Mini51Series.h:4726
GPIO_T::DMASK
__IO uint32_t DMASK
Definition: Mini51Series.h:3572
GPIO_T::PIN
__I uint32_t PIN
Definition: Mini51Series.h:3573
I2C_T::I2CADM1
__IO uint32_t I2CADM1
Definition: Mini51Series.h:4231
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Mini51Series.h:9958
INT_T::SRC28
__I uint32_t SRC28
Definition: Mini51Series.h:4754
GPIO234_IRQn
Definition: Mini51Series.h:97
GPIO_DBNCECON_T::DBNCECON
__IO uint32_t DBNCECON
Definition: Mini51Series.h:3652
UART_T::TOR
__IO uint32_t TOR
Definition: Mini51Series.h:9463
I2C_T::I2CADM0
__IO uint32_t I2CADM0
Definition: Mini51Series.h:4230
INT_T::SRC14
__I uint32_t SRC14
Definition: Mini51Series.h:4740
ADC_T::ADSAMP
__IO uint32_t ADSAMP
Definition: Mini51Series.h:802
PWM_T::PIER
__IO uint32_t PIER
Definition: Mini51Series.h:6660
HIRC_IRQn
Definition: Mini51Series.h:105
GCR_T::RSTSRC
__IO uint32_t RSTSRC
Definition: Mini51Series.h:2681
i2c.h
Mini51 series I2C driver header file.
PWM_T
Definition: Mini51Series.h:4794