| Mini51 BSP V3.02.002 The Board Support Package for Mini51 Series

Data Fields
GCR_T Struct Reference

`#include <Mini51Series.h>`

## Data Fields
__I uint32_t | PDID
__IO uint32_t | RSTSRC
__IO uint32_t | IPRSTC1
__IO uint32_t | IPRSTC2
__IO uint32_t | BODCTL
__IO uint32_t | P0_MFP
__IO uint32_t | P1_MFP
__IO uint32_t | P2_MFP
__IO uint32_t | P3_MFP
__IO uint32_t | P4_MFP
__IO uint32_t | P5_MFP
__IO uint32_t | IRCTRIMCTL
__IO uint32_t | IRCTRIMIER
__IO uint32_t | IRCTRIMISR
__IO uint32_t | RegLockAddr

## Detailed Description

    @addtogroup GCR System Global Control Registers(GCR)
    Memory Mapped Structure for GCR Controller

Definition at line 1954 of file Mini51Series.h.

## Field Documentation

## ◆ BODCTL

GCR_T::BODCTL

BODCTL

Offset: 0x18 Brown-out Detector Control Register

Bits | Field | Descriptions
[0] | BOD_VL_EXT | Brown-out Detector Selection Extension (Initiated & Write-protected Bit) The default value is set by flash controller user configuration CBOVEXT bit (config0 [23]). If config0 bit[23] is set to 1, default value of BOD_VL_EXT is 0. If config0 bit[23] is set to 0, default value of BOD_VL_EXT is 1. 0 = Brown-out detector threshold voltage is selected by the table defined in BOD_VL. 1 = Brown-out detector threshold voltage is selected by the table defined below. 11 = 4.4V 10 = 3.7V 01 = 2.7V 00 = 2.2V
[2:1] | BOD_VL | Brown-out Detector Threshold Voltage Selection (Initiated & Write-protected Bit) The default value is set by flash controller user configuration CBOV bit (config0 [22:21]). BOD_VL[1] BOD_VL[0] Brown-out voltage 11 = Disable 10 = 3.7V 01 = 2.7V 00 = Reserved
[3] | BOD_RSTEN | Brown-out Reset Enable Control (Initiated And Write-protected Bit) 0 = Brown-out "INTERRUPT" function Enabled; when the Brown-out Detector function is enable and the detected voltage is lower than the threshold, then assert a signal to interrupt the Cortex-M0 CPU. 1 = Brown-out "RESET" function Enabled; when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip. The default value is set by flash controller user configuration register config0 bit[20]. When the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is required.
[4] | BOD_INTF | Brown-out Detector Interrupt Flag 0 = Brown-out Detector does not detect any voltage dropped at AVDD down through or up through the voltage of BOD_VL setting. 1 = When Brown-out Detector detects the AVDD is dropped through the voltage of BOD_VL setting or the AVDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled.
[5] | BOD_LPM | Brown-out Detector Low Power Mode (Write Protect) 0 = BOD operate in normal mode (default). 1 = Enable the BOD low power mode. The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1uA but slow the BOD response.
[6] | BOD_OUT | Brown-out Detector Output State 0 = Brown-out Detector status output is 0, the detected voltage is higher than BOD_VL setting. 1 = Brown-out Detector status output is 1, the detected voltage is lower than BOD_VL setting.

Definition at line 2687 of file Mini51Series.h.

## ◆ IPRSTC1

GCR_T::IPRSTC1

IPRSTC1

Offset: 0x08 Peripheral Reset Control Resister 1

Bits | Field | Descriptions
[0] | CHIP_RST | CHIP One-shot Reset (Write Protect) Setting this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is the same as the POR reset, and all the chip module is reset and the chip settings from flash are also reloaded. 0 = Chip normal operation. 1 = CHIP one-shot reset. Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.
[1] | CPU_RST | CPU Kernel Reset Setting this bit will reset the CPU kernel, and this bit will automatically return to 0 after the 2 clock cycles. 0 = CPU normal operation. 1 = Reset CPU Kernel. Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.

Definition at line 2682 of file Mini51Series.h.

## ◆ IPRSTC2

GCR_T::IPRSTC2

IPRSTC2

Offset: 0x0C Peripheral Reset Control Resister 2

Bits | Field | Descriptions
[1] | GPIO_RST | GPIO (P0~P5) Controller Reset 0 = GPIO module normal operation. 1 = GPIO module reset.
[2] | TMR0_RST | Timer0 Controller Reset 0 = Timer0 module normal operation. 1 = Timer0 module reset.
[3] | TMR1_RST | Timer1 Controller Reset 0 = Timer1 module normal operation. 1 = Timer1 module reset.
[8] | I2C_RST | I2C Controller Reset 0 = I2C module normal operation. 1 = I2C module reset.
[12] | SPI_RST | SPI Controller Reset 0 = SPI module normal operation. 1 = SPI module reset.
[16] | UART_RST | UART Controller Reset 0 = UART module normal operation. 1 = UART module reset.
[20] | PWM_RST | PWM Controller Reset 0 = PWM module normal operation. 1 = PWM module reset.
[22] | ACMP_RST | ACMP Controller Reset 0 = ACMP module normal operation. 1 = ACMP module reset.
[28] | ADC_RST | ADC Controller Reset 0 = ADC module normal operation. 1 = ADC module reset.

Definition at line 2683 of file Mini51Series.h.

## ◆ IRCTRIMCTL

GCR_T::IRCTRIMCTL

IRCTRIMCTL

Offset: 0x80 HIRC Trim Control Register

Bits | Field | Descriptions
[0] | TRIM_SEL | Trim Frequency Selection This bit is to enable the HIRC auto trim. When setting this bit to 1, the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock. During auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically. 0 = HIRC auto trim function Disabled. 1 = HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz.
[5:4] | TRIM_LOOP | Trim Calculation Loop This field defines that trim value calculation is based on how many LXT clocks in. For example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clock. 00 = Trim value calculation is based on average difference in 4 LXT clocks. 01 = Trim value calculation is based on average difference in 8 LXT clocks. 10 = Trim value calculation is based on average difference in 16 LXT clocks. 11 = Trim value calculation is based on average difference in 32 LXT clocks.

Definition at line 2700 of file Mini51Series.h.

## ◆ IRCTRIMIER

GCR_T::IRCTRIMIER

IRCTRIMIER

Offset: 0x84 HIRC Trim Interrupt Enable Control Register

Bits | Field | Descriptions
[1] | TRIM_FAIL_IEN | Trim Failure Interrupt Enable Control This bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by TRIM_SEL. If this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count is reached. 0 = TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU. 1 = TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU.
[2] | 32K_ERR_IEN | LXT Clock Error Interrupt Enable Control This bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation. If this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate. 0 = 32K_ERR_INT status Disabled to trigger an interrupt to CPU. 1 = 32K_ERR_INT status Enabled to trigger an interrupt to CPU.

Definition at line 2701 of file Mini51Series.h.

## ◆ IRCTRIMISR

GCR_T::IRCTRIMISR

IRCTRIMISR

Offset: 0x88 HIRC Trim Interrupt Status Register

Bits | Field | Descriptions
[0] | FREQ_LOCK | HIRC Frequency Lock Status This bit indicates the HIRC frequency locked in 22.1184 MHz. This is a read only status bit and doesn't trigger any interrupt.
[1] | TRIM_FAIL_INT | Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically. If this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Software can write 1 to clear this bit to 0. 0 = Trim value update limitation count is not reached. 1 = Trim value update limitation count is reached and HIRC frequency is still not locked.
[2] | 32K_ERR_INT | LXT Clock Error Interrupt Status This bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically. If this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to 0. 0 = LXT clock frequency is accuracy. 1 = LXT clock frequency is inaccuracy.

Definition at line 2702 of file Mini51Series.h.

## ◆ P0_MFP

GCR_T::P0_MFP

P0_MFP

Offset: 0x30 P0 Multiple Function and Input Type Control Register

Bits | Field | Descriptions
[7:0] | P0_MFP | P0 Multiple Function Selection
[8] | P0_ALT0 | P0.0 Alternate Function Selection
[9] | P0_ALT1 | P0.1 Alternate Function Selection
[12] | P0_ALT4 | P0.4 Alternate Function Selection
[13] | P0_ALT5 | P0.5 Alternate Function Selection
[14] | P0_ALT6 | P0.6 Alternate Function Selection
[15] | P0_ALT7 | P0.7 Alternate Function Selection
[23:16] | P0_TYPE | P0[7:0] TTL Or Schmitt Trigger Function Enable Control 0 = P0[7:0]Select I/O input as TTL function. 1 = P0[7:0] Select I/O input as Schmitt Trigger function .

Definition at line 2691 of file Mini51Series.h.

## ◆ P1_MFP

GCR_T::P1_MFP

P1_MFP

Offset: 0x34 P1 Multiple Function and Input Type Control Register

Bits | Field | Descriptions
[7:0] | P1_MFP | P1 Multiple Function Selection
[8] | P1_ALT0 | P1.0 Alternate Function Selection
[10] | P1_ALT2 | P1.2 Alternate Function Selection
[11] | P1_ALT3 | P1.3 Alternate Function Selection
[12] | P1_ALT4 | P1.4 Alternate Function Selection
[13] | P1_ALT5 | P1.5 Alternate Function Selection
[23:16] | P1_TYPE | P1[7:0] TTL Or Schmitt Trigger Function Enable Control 0 = P1[7:0]Select I/O input as TTL function. 1 = P1[7:0] Select I/O input as Schmitt Trigger function .

Definition at line 2692 of file Mini51Series.h.

## ◆ P2_MFP

GCR_T::P2_MFP

P2_MFP

Offset: 0x38 P2 Multiple Function and Input Type Control Register

Bits | Field | Descriptions
[7:0] | P2_MFP | P2 Multiple Function Selection
[10] | P2_ALT2 | P2.2 Alternate Function Selection
[11] | P2_ALT3 | P2.3 Alternate Function Selection
[12] | P2_ALT4 | P2.4 Alternate Function Selection
[13] | P2_ALT5 | P2.5 Alternate Function Selection
[14] | P2_ALT6 | P2.6 Alternate Function Selection
[23:16] | P2_TYPE | P2[7:0] TTL Or Schmitt Trigger Function Enable Control 0 = P2[7:0]Select I/O input as TTL function. 1 = P2[7:0] Select I/O input as Schmitt Trigger function .

Definition at line 2693 of file Mini51Series.h.

## ◆ P3_MFP

GCR_T::P3_MFP

P3_MFP

Offset: 0x3C P3 Multiple Function and Input Type Control Register

Bits | Field | Descriptions
[7:0] | P3_MFP | P3 Multiple Function Selection
[8] | P3_ALT0 | P3.0 Alternate Function Selection
[9] | P3_ALT1 | P3.1 Alternate Function Selection
[10] | P3_ALT2 | P3.2 Alternate Function Selection
[12] | P3_ALT4 | P3.4 Alternate Function Selection
[13] | P3_ALT5 | P3.5 Alternate Function Selection
[14] | P3_ALT6 | P3.6 Alternate Function Selection
[23:16] | P3_TYPE | P3[7:0] TTL Or Schmitt Trigger Function Enable Control 0 = P3[7:0]Select I/O input as TTL function. 1 = P3[7:0] Select I/O input as Schmitt Trigger function .
[24] | P32CPP1 | P3.2 Alternate Function Selection Extension

Definition at line 2694 of file Mini51Series.h.

## ◆ P4_MFP

GCR_T::P4_MFP

P4_MFP

Offset: 0x40 P4 Multiple Function and Input Type Control Register

Bits | Field | Descriptions
[7:0] | P4_MFP | P4 Multiple Function Selection
[14] | P4_ALT6 | P4.6 Alternate Function Selection
[15] | P4_ALT7 | P4.7 Alternate Function Selection
[23:16] | P4_TYPE | P4[7:0] TTL Or Schmitt Trigger Function Enable Control 0 = P4[7:0]Select I/O input as TTL function. 1 = P4[7:0] Select I/O input as Schmitt Trigger function .

Definition at line 2695 of file Mini51Series.h.

## ◆ P5_MFP

GCR_T::P5_MFP

P5_MFP

Offset: 0x44 P5 Multiple Function and Input Type Control Register

Bits | Field | Descriptions
[7:0] | P5_MFP | P5 Multiple Function Selection
[8] | P5_ALT0 | P5.0 Alternate Function Selection
[9] | P5_ALT1 | P5.1 Alternate Function Selection
[10] | P5_ALT2 | P5.2 Alternate Function Selection
[11] | P5_ALT3 | P5.3 Alternate Function Selection
[12] | P5_ALT4 | P5.4 Alternate Function Selection
[13] | P5_ALT5 | P5.5 Alternate Function Selection
[23:16] | P5_TYPE | P5[7:0] TTL Or Schmitt Trigger Function Enable Control 0 = P5[7:0]Select I/O input as TTL function. 1 = P5[7:0] Select I/O input as Schmitt Trigger function .

Definition at line 2696 of file Mini51Series.h.

## ◆ PDID

GCR_T::PDID

PDID

Offset: 0x00 Part Device Identification Number Register

Bits | Field | Descriptions
[31:0] | PDID | Product Device Identification Number This register reflects the device part number code. Software can read this register to identify which device is used. For example, the MINI51LDE PDID code is "0x20205100".

Definition at line 2680 of file Mini51Series.h.

## ◆ RegLockAddr

GCR_T::RegLockAddr

RegLockAddr

Offset: 0x100 Register Write-Protection Control Register

Bits | Field | Descriptions
[0] | RegUnLock | Register Write-protection Disable Index (Read Only) 0 = Write-protection Enabled for writing protected registers. Any write to the protected register is ignored. 1 = Write-protection Disabled for writing protected registers. The Protected registers are: IPRSTC1 (0x5000_0008) BODCTL (0x5000_0018) PWRCON (0x5000_0200), bit[6] is not protected for power wake-up interrupt clear APBCLK (0x5000_0208), bit[0] watchdog clock enable only CLKSEL0 (0x5000_0210) CLKSEL1 (0x5000_0214), bit[1:0] Watchdog clock source select only NMI_SEL (0x5000_0380), bit[8] NMI interrupt enable only ISPCON (0x5000_C000) ISPTRG (0x5000_C010) WTCR (0x4000_4000) Note: The bits which are write-protected will be noted as" (Write Protect)" beside the description.
[7:0] | REGWRPROT | Register Write-protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.

Definition at line 2706 of file Mini51Series.h.

## ◆ RSTSRC

GCR_T::RSTSRC

RSTSRC

Offset: 0x04 System Reset Source Register

Bits | Field | Descriptions
[0] | RSTS_POR | Power-on Reset Flag The RSTS_POR flag is set by the "reset signal", which is from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]), to indicate the previous reset source. 0 = No reset from POR or CHIP_RST. 1 = Power-on-Reset (POR) or CHIP_RST had issued the reset signal to reset the system. Note: Software can write 1 to clear this bit to 0.
[1] | RSTS_RESET | Reset Pin Reset Flag The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. 0 = No reset from pin /RESET pin. 1 = The /RESET pin had issued the reset signal to reset the system. Note: Software can write 1 to clear this bit to 0.
[2] | RSTS_WDT | Watchdog Reset Flag The RSTS_WDT flag is set by the "reset signal" from the Watchdog timer to indicate the previous reset source. 0 = No reset from Watchdog timer. 1 = The Watchdog timer had issued the reset signal to reset the system. Note: Software can write 1 to clear this bit to 0.
[4] | RSTS_BOD | Brown-out Detector Reset Flag The RSTS_BOD flag is set by the "reset signal" from the Brown-out Detector to indicate the previous reset source. 0 = No reset from BOD. 1 = The BOD had issued the reset signal to reset the system. Note: Software can write 1 to clear this bit to 0.
[5] | RSTS_MCU | MCU Reset Flag The RSTS_MCU flag is set by the "reset signal" from the Cortex-M0 core to indicate the previous reset source. 0 = No reset from Cortex-M0. 1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C in system control registers of Cortex-M0 core. Note: Software can write 1 to clear this bit to 0.
[7] | RSTS_CPU | CPU Reset Flag The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC). 0 = No reset from CPU. 1 = Cortex-M0 core and FMC are reset by software setting CPU_RST to 1. Note: Software can write 1 to clear this bit to 0.

Definition at line 2681 of file Mini51Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Mini51Series/Include/Mini51Series.h