| CMSIS-Core (Cortex-M) CMSIS-Core support for Cortex-M processor-based devices |

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Macros
PMU Events for Cortex-M55
PMU Functions for Armv8.1-M

IDs for additional events defined for Cortex-M55. More...

## Macros
#define | ARMCM55_PMU_AXI_READ_ACCESS 0xC303
| Any beat access to M-AXI read interface.
#define | ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302
| Any beat access to M-AXI write interface.
#define | ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400
| Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress.
#define | ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401
| Denial of Service timeout has fired three times and blocked the LSU to force forward progress.
#define | ARMCM55_PMU_ECC_ERR 0xC000
| Any ECC error.
#define | ARMCM55_PMU_ECC_ERR_DCACHE 0xC010
| Any ECC error in the data cache.
#define | ARMCM55_PMU_ECC_ERR_DTCM 0xC020
| Any ECC error in the DTCM.
#define | ARMCM55_PMU_ECC_ERR_FATAL 0xC001
| Any fatal ECC error.
#define | ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012
| Any fatal ECC error in the data cache.
#define | ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022
| Any fatal ECC error in the DTCM.
#define | ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013
| Any fatal ECC error in the instruction cache.
#define | ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023
| Any fatal ECC error in the ITCM.
#define | ARMCM55_PMU_ECC_ERR_ICACHE 0xC011
| Any ECC error in the instruction cache.
#define | ARMCM55_PMU_ECC_ERR_ITCM 0xC021
| Any ECC error in the ITCM.
#define | ARMCM55_PMU_NWAMODE 0xC201
| Write-allocate store is not allocated into the data cache due to no-write-allocate mode.
#define | ARMCM55_PMU_NWAMODE_ENTER 0xC200
| No write-allocate mode entry.
#define | ARMCM55_PMU_PAHB_ACCESS 0xC301
| Read or write access on the P-AHB interface.
#define | ARMCM55_PMU_PF_CANCEL 0xC101
| A prefetcher stops prefetching.
#define | ARMCM55_PMU_PF_DROP_LINEFILL 0xC102
| A linefill triggered by a prefetcher has been dropped because of lack of buffering.
#define | ARMCM55_PMU_PF_LINEFILL 0xC100
| A prefetcher starts a line-fill.
#define | ARMCM55_PMU_SAHB_ACCESS 0xC300
| Read or write access on the S-AHB interface to the TCM.
#define | ARMCM55_PMU_SAHB_ACCESS 0xC300
| Read or write access on the S-AHB interface to the TCM.

## Description

IDs for additional events defined for Cortex-M55.

These events are available on a Cortex-M55 device including a PMU.

## Macro Definition Documentation

## ◆ ARMCM55_PMU_AXI_READ_ACCESS

#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303

Any beat access to M-AXI read interface.

## ◆ ARMCM55_PMU_AXI_WRITE_ACCESS

#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302

Any beat access to M-AXI write interface.

## ◆ ARMCM55_PMU_DOSTIMEOUT_DOUBLE

#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400

Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress.

## ◆ ARMCM55_PMU_DOSTIMEOUT_TRIPLE

#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401

Denial of Service timeout has fired three times and blocked the LSU to force forward progress.

## ◆ ARMCM55_PMU_ECC_ERR

#define ARMCM55_PMU_ECC_ERR 0xC000

Any ECC error.

## ◆ ARMCM55_PMU_ECC_ERR_DCACHE

#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010

Any ECC error in the data cache.

## ◆ ARMCM55_PMU_ECC_ERR_DTCM

#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020

Any ECC error in the DTCM.

## ◆ ARMCM55_PMU_ECC_ERR_FATAL

#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001

Any fatal ECC error.

## ◆ ARMCM55_PMU_ECC_ERR_FATAL_DCACHE

#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012

Any fatal ECC error in the data cache.

## ◆ ARMCM55_PMU_ECC_ERR_FATAL_DTCM

#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022

Any fatal ECC error in the DTCM.

## ◆ ARMCM55_PMU_ECC_ERR_FATAL_ICACHE

#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013

Any fatal ECC error in the instruction cache.

## ◆ ARMCM55_PMU_ECC_ERR_FATAL_ITCM

#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023

Any fatal ECC error in the ITCM.

## ◆ ARMCM55_PMU_ECC_ERR_ICACHE

#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011

Any ECC error in the instruction cache.

## ◆ ARMCM55_PMU_ECC_ERR_ITCM

#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021

Any ECC error in the ITCM.

## ◆ ARMCM55_PMU_NWAMODE

#define ARMCM55_PMU_NWAMODE 0xC201

Write-allocate store is not allocated into the data cache due to no-write-allocate mode.

## ◆ ARMCM55_PMU_NWAMODE_ENTER

#define ARMCM55_PMU_NWAMODE_ENTER 0xC200

No write-allocate mode entry.

## ◆ ARMCM55_PMU_PAHB_ACCESS

#define ARMCM55_PMU_PAHB_ACCESS 0xC301

Read or write access on the P-AHB interface.

## ◆ ARMCM55_PMU_PF_CANCEL

#define ARMCM55_PMU_PF_CANCEL 0xC101

A prefetcher stops prefetching.

## ◆ ARMCM55_PMU_PF_DROP_LINEFILL

#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102

A linefill triggered by a prefetcher has been dropped because of lack of buffering.

## ◆ ARMCM55_PMU_PF_LINEFILL

#define ARMCM55_PMU_PF_LINEFILL 0xC100

A prefetcher starts a line-fill.

## ◆ ARMCM55_PMU_SAHB_ACCESS [1/2]

#define ARMCM55_PMU_SAHB_ACCESS 0xC300

Read or write access on the S-AHB interface to the TCM.

## ◆ ARMCM55_PMU_SAHB_ACCESS [2/2]

#define ARMCM55_PMU_SAHB_ACCESS 0xC300

Read or write access on the S-AHB interface to the TCM.