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CMSIS-Core (Cortex-A)
Version 1.0.0
CMSIS-Core support for Cortex-A processor-based devices
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Physical Timer Control register.
Data Fields | |
| struct { | |
| uint32_t ENABLE:1 | |
| bit: 0 Enables the timer. More... | |
| uint32_t IMASK:1 | |
| bit: 1 Timer output signal mask bit. More... | |
| uint32_t ISTATUS:1 | |
| bit: 2 The status of the timer. More... | |
| uint32_t _reserved0:29 | |
| bit: 3..31 Reserved More... | |
| } | b |
| Structure used for bit access. More... | |
| uint32_t | w |
| Type used for word access. More... | |
| struct { | |
| uint32_t ENABLE:1 | |
| bit: 0 Enables the timer. More... | |
| uint32_t IMASK:1 | |
| bit: 1 Timer output signal mask bit. More... | |
| uint32_t ISTATUS:1 | |
| bit: 2 The status of the timer. More... | |
| } | b |
| Structure used for bit access. More... | |
| uint32_t CNTP_CTL_Type::_reserved0 |
| struct { ... } CNTP_CTL_Type::b |
| struct { ... } CNTP_CTL_Type::b |
| uint32_t CNTP_CTL_Type::ENABLE |
Enables the timer.
Permitted values are:
| uint32_t CNTP_CTL_Type::IMASK |
Timer output signal mask bit.
Permitted values are:
| uint32_t CNTP_CTL_Type::ISTATUS |
The status of the timer.
This bit indicates whether the timer condition is asserted:
| uint32_t CNTP_CTL_Type::w |