The SCTLR provides the top level control of the system, including its memory system.
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In a VMSAv7 implementation, the SCTLR bit assignments are:
| Bits | Name | Function |
| [31] | - | Reserved. |
| [30] | TE | Thumb Exception enable. |
| [29] | AFE | Access flag enable bit. |
| [28] | TRE | TEX remap enable bit. |
| [27:26] | - | Reserved. |
| [25] | EE | Exception Endianness bit. |
| [24:21] | - | Reserved. |
| [20] | UWXN | Unprivileged write permission implies PL1 Execute Never (XN). |
| [19] | WXN | Write permission implies Execute Never (XN). |
| [18:14] | - | Reserved. |
| [13] | V | Vectors bit. |
| [12] | I | Instruction cache enable bit. |
| [11] | Z | Branch prediction enable bit. |
| [10] | SW | SWP and SWPB enable bit. |
| [9:3] | - | Reserved. |
| [2] | C | Cache enable bit. |
| [1] | A | Alignment bit. |
| [0] | M | Address translation enable bit. |
Consider using __get_SCTLR and __set_SCTLR for accessing this register.