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CMSIS-Core (Cortex-A)
Version 1.0.0
CMSIS-Core support for Cortex-A processor-based devices
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TTBRn holds the base address of translation table n, and information about the memory it occupies. More...
Functions | |
| __STATIC_INLINE uint32_t | __get_TTBR0 () |
| Get TTBR0 (Translation Table Base Register 0) More... | |
| __STATIC_INLINE void | __set_TTBR0 (uint32_t ttbr0) |
| Set TTBR0 Translation Table Base Register 0. More... | |
32-bit TTBR format
| Bits | Name | Function |
|---|---|---|
| [31:x] | BADDR | Translation table base address, bits[31:x]. |
| [x-1:7] | - | Reserved. |
| [6] | IRGN[0] | Inner region bit 0. |
| [5] | NOS | Not Outer Shareable bit. |
| [4:3] | RGN | Region bits. |
| [2] | - | Reserved. |
| [1] | S | Shareable bit. |
| [0] | C/IRGN[1] | Cacheable bit. / Inner region bit 1. |
x=14-N. x=14.64-bit TTBR format
| Bits | Name | Function |
|---|---|---|
| [63:56] | - | Reserved. |
| [55:48] | ASID | An ASID for the translation table base address. |
| [47:40] | - | Reserved. |
| [39:x] | BADDR | Translation table base address, bits[39:x]. |
| [x-1:0] | - | Reserved. |
x=14-TnSZ.Consider using __get_TTBR0 and __set_TTBR0 for accessing TTBR0 register.
| __STATIC_INLINE uint32_t __get_TTBR0 | ( | ) |
This function returns the value of the Translation Table Base Register 0.
| __STATIC_INLINE void __set_TTBR0 | ( | uint32_t | ttbr0 | ) |
| [in] | ttbr0 | Translation Table Base Register 0 value to set |
This function assigns the given value to the Translation Table Base Register 0.