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CMSIS-Core (Cortex-A)
Version 1.0.0
CMSIS-Core support for Cortex-A processor-based devices
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Interrupt Controller API header file. More...
Macros | |
| #define | IRQHANDLER_T |
| #define | IRQN_ID_T |
| #define | IRQ_MODE_TRIG_Pos (0U) |
| #define | IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) |
| #define | IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: level triggered interrupt. More... | |
| #define | IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: low level triggered interrupt. More... | |
| #define | IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: high level triggered interrupt. More... | |
| #define | IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: edge triggered interrupt. More... | |
| #define | IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: rising edge triggered interrupt. More... | |
| #define | IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: falling edge triggered interrupt. More... | |
| #define | IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) |
| Trigger: rising and falling edge triggered interrupt. More... | |
| #define | IRQ_MODE_TYPE_Pos (3U) |
| #define | IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) |
| #define | IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) |
| Type: interrupt source triggers CPU IRQ line. More... | |
| #define | IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) |
| Type: interrupt source triggers CPU FIQ line. More... | |
| #define | IRQ_MODE_DOMAIN_Pos (4U) |
| #define | IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) |
| #define | IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) |
| Domain: interrupt is targeting non-secure domain. More... | |
| #define | IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) |
| Domain: interrupt is targeting secure domain. More... | |
| #define | IRQ_MODE_CPU_Pos (5U) |
| #define | IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) |
| #define | IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets all CPUs. More... | |
| #define | IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 0. More... | |
| #define | IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 1. More... | |
| #define | IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 2. More... | |
| #define | IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 3. More... | |
| #define | IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 4. More... | |
| #define | IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 5. More... | |
| #define | IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 6. More... | |
| #define | IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) |
| CPU: interrupt targets CPU 7. More... | |
| #define | IRQ_MODE_ERROR (0x80000000UL) |
| Bit indicating mode value error. More... | |
| #define | IRQ_PRIORITY_Msk (0x0000FFFFUL) |
| Interrupt priority value bit-mask. More... | |
| #define | IRQ_PRIORITY_ERROR (0x80000000UL) |
| Bit indicating priority value error. More... | |
Typedefs | |
| typedef void(* | IRQHandler_t )(void) |
| Interrupt handler data type. More... | |
| typedef int32_t | IRQn_ID_t |
| Interrupt ID number data type. More... | |
Functions | |
| int32_t | IRQ_Initialize (void) |
| Initialize interrupt controller. More... | |
| int32_t | IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) |
| Register interrupt handler. More... | |
| IRQHandler_t | IRQ_GetHandler (IRQn_ID_t irqn) |
| Get the registered interrupt handler. More... | |
| int32_t | IRQ_Enable (IRQn_ID_t irqn) |
| Enable interrupt. More... | |
| int32_t | IRQ_Disable (IRQn_ID_t irqn) |
| Disable interrupt. More... | |
| uint32_t | IRQ_GetEnableState (IRQn_ID_t irqn) |
| Get interrupt enable state. More... | |
| int32_t | IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) |
| Configure interrupt request mode. More... | |
| uint32_t | IRQ_GetMode (IRQn_ID_t irqn) |
| Get interrupt mode configuration. More... | |
| IRQn_ID_t | IRQ_GetActiveIRQ (void) |
| Get ID number of current interrupt request (IRQ). More... | |
| IRQn_ID_t | IRQ_GetActiveFIQ (void) |
| Get ID number of current fast interrupt request (FIQ). More... | |
| int32_t | IRQ_EndOfInterrupt (IRQn_ID_t irqn) |
| Signal end of interrupt processing. More... | |
| int32_t | IRQ_SetPending (IRQn_ID_t irqn) |
| Set interrupt pending flag. More... | |
| uint32_t | IRQ_GetPending (IRQn_ID_t irqn) |
| Get interrupt pending flag. More... | |
| int32_t | IRQ_ClearPending (IRQn_ID_t irqn) |
| Clear interrupt pending flag. More... | |
| int32_t | IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) |
| Set interrupt priority value. More... | |
| uint32_t | IRQ_GetPriority (IRQn_ID_t irqn) |
| Get interrupt priority. More... | |
| int32_t | IRQ_SetPriorityMask (uint32_t priority) |
| Set priority masking threshold. More... | |
| uint32_t | IRQ_GetPriorityMask (void) |
| Get priority masking threshold. More... | |
| int32_t | IRQ_SetPriorityGroupBits (uint32_t bits) |
| Set priority grouping field split point. More... | |
| uint32_t | IRQ_GetPriorityGroupBits (void) |
| Get priority grouping field split point. More... | |
| #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) |
| #define IRQ_MODE_CPU_Pos (5U) |
| #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) |
| #define IRQ_MODE_DOMAIN_Pos (4U) |
| #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) |
| #define IRQ_MODE_TRIG_Pos (0U) |
| #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) |
| #define IRQ_MODE_TYPE_Pos (3U) |
| #define IRQHANDLER_T |
| #define IRQN_ID_T |
| typedef void(* IRQHandler_t)(void) |
| typedef int32_t IRQn_ID_t |