CMSIS-Core (Cortex-A)  Version 1.0.0
CMSIS-Core support for Cortex-A processor-based devices
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Intrinsic Functions

Functions that generate specific Cortex-A CPU Instructions. More...

Macros

#define __NOP   __nop
 No Operation. More...
 
#define __WFI   __wfi
 Wait For Interrupt. More...
 
#define __WFE   __wfe
 Wait For Event. More...
 
#define __SEV   __sev
 Send Event. More...
 
#define __ISB()
 Instruction Synchronization Barrier. More...
 
#define __DSB()
 Data Synchronization Barrier. More...
 
#define __DMB()
 Data Memory Barrier. More...
 
#define __REV   __rev
 Reverse byte order (32 bit) More...
 
#define __ROR   __ror
 Reverse byte order (16 bit) More...
 
#define __BKPT(value)   __breakpoint(value)
 Breakpoint. More...
 
#define __CLZ   __clz
 Count leading zeros. More...
 

Functions

_STATIC_INLINE __ASM uint32_t __REV16 (uint32_t value)
 
fn __STATIC_INLINE __ASM int32_t __REVSH (int32_t value)
 

Description

Macro Definition Documentation

#define __BKPT (   value)    __breakpoint(value)

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Parameters
[in]valueis ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
#define __CLZ   __clz

Counts the number of leading zeros of a data value.

Parameters
[in]valueValue to count the leading zeros
Returns
number of leading zeros in value
#define __DMB ( )

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

#define __DSB ( )

Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

#define __ISB ( )

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

#define __NOP   __nop

No Operation does nothing. This instruction can be used for code alignment purposes.

#define __REV   __rev

Reverses the byte order in integer value.

Parameters
[in]valueValue to reverse
Returns
Reversed value
#define __ROR   __ror

Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

Parameters
[in]valueValue to reverse
Returns
Reversed value Reverse byte order in signed short value
Parameters
[in]valueValue to reverse
Returns
Reversed value Rotate Right in unsigned value (32 bit)
Parameters
[in]op1Value to rotate
[in]op2Number of Bits to rotate
Returns
Rotated value
#define __SEV   __sev

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

#define __WFE   __wfe

Wait For Event is a hint instruction that permits the processor to enter

#define __WFI   __wfi

Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

Function Documentation

_STATIC_INLINE __ASM uint32_t __REV16 ( uint32_t  value)

Reverses the byte order in two unsigned short values.

fn __STATIC_INLINE __ASM int32_t __REVSH ( int32_t  value)

Reverses the byte order in a signed short value with sign extension to integer.