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CMSIS-Core (Cortex-A)
Version 1.0.0
CMSIS-Core support for Cortex-A processor-based devices
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Bit position and mask macros. More...
Macros | |
| #define | CPACR_ASEDIS_Pos 31U |
| CPACR: ASEDIS Position. More... | |
| #define | CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) |
| CPACR: ASEDIS Mask. More... | |
| #define | CPACR_D32DIS_Pos 30U |
| CPACR: D32DIS Position. More... | |
| #define | CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) |
| CPACR: D32DIS Mask. More... | |
| #define | CPACR_TRCDIS_Pos 28U |
| CPACR: D32DIS Position. More... | |
| #define | CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) |
| CPACR: D32DIS Mask. More... | |
| #define | CPACR_CP_Pos_(n) (n*2U) |
| CPACR: CPn Position. More... | |
| #define | CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) |
| CPACR: CPn Mask. More... | |
| #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) |
| #define CPACR_ASEDIS_Pos 31U |
| #define CPACR_CP_Msk_ | ( | n | ) | (3UL << CPACR_CP_Pos_(n)) |
| #define CPACR_CP_Pos_ | ( | n | ) | (n*2U) |
| #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) |
| #define CPACR_D32DIS_Pos 30U |
| #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) |
| #define CPACR_TRCDIS_Pos 28U |