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CMSIS-Core (Cortex-A)
Version 1.0.0
CMSIS-Core support for Cortex-A processor-based devices
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| Functions for system and clock setup available in system_device.c | |
| Functions to access the Cortex-A core registers | |
| The ACTLR provides IMPLEMENTATION DEFINED configuration and control options | |
| Bit position and mask macros | |
| This section describes the cache and branch predictor maintenance operations | |
| Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13] | |
| Bit position and mask macros | |
| The CPACR controls access to coprocessors CP0 to CP13 | |
| Bit position and mask macros | |
| Valid values for CPACR CP field | |
| The Current Program Status Register (CPSR) holds processor status and control information | |
| Bit position and mask macros | |
| Valid values for CPSR M field | |
| The DFSR holds status information about the last data fault | |
| Bit position and mask macros | |
| DACR defines the access permission for each of the sixteen memory domains | |
| Bit position and mask macros | |
| Valid values for DACR Dn field | |
| Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded | |
| Provides floating-point system status information and control | |
| Bit position and mask macros | |
| The IFSR holds status information about the last instruction fault | |
| Bit position and mask macros | |
| The ISR shows whether an IRQ, FIQ, or external abort is pending | |
| Bit position and mask macros | |
| In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions | |
| The control register for the physical timer | |
| Holds the timer value for the PL1 physical timer | |
| The processor uses SP as a pointer to the active stack | |
| The SCTLR provides the top level control of the system, including its memory system | |
| Bit position and mask macros | |
| This section describes the TLB operations that are implemented on all ARMv7-A implementations | |
| TTBRn holds the base address of translation table n, and information about the memory it occupies | |
| When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode | |
| Naming conventions and optional features for accessing peripherals | |
| Version symbols for CMSIS release specific C/C++ source code | |
| The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC) | |
| L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache | |
| L2C-310 Cache Controller gives access to functions for level 2 cache maintenance. Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual | |
| Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices. Reference: Cortex-A7 MPCore Technical Reference Manual | |
| Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices. References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual | |
| MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map. Reference: Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition | |
| Defines and structures that relate to the Memory Management Unit | |
| FPU Functions enable the use of Floating Point instructions and extensions. Reference: Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition | |
| Compiler agnostic #define symbols for generic C/C++ source code | |
| Functions that generate specific Cortex-A CPU Instructions | |
| Generic functions to access the Interrupt Controller | |
| Configure interrupt line mode | |
| Definitions used by interrupt priority functions |