CMSIS-Core (Cortex-A)  Version 1.0.0
CMSIS-Core support for Cortex-A processor-based devices
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
PL1 Physical Timer Control register (CNTP_CTL)

The control register for the physical timer. More...

Functions

__STATIC_INLINE void __set_CNTP_CTL (uint32_t value)
 Set CNTP_CTL (PL1 Physical Timer Control Register) More...
 
__STATIC_INLINE uint32_t __get_CNTP_CTL ()
 Get CNTP_CTL register. More...
 

Description

Bits Name Function
[31:3] - Reserved.
[2] ISTATUS The status of the timer.
[1] IMASK Timer output signal mask bit.
[0] ENABLE Enables the timer.

Consider __get_CNTP_CTL and __set_CNTP_CTL to access this register.

Consider using Generic Physical Timer Functions for controlling the PL1 Timer instead.

Function Documentation

__STATIC_INLINE uint32_t __get_CNTP_CTL ( )
Returns
CNTP_CTL Register value

This function returns the value of the PL1 Physical Timer Control Register. (CNTP_CTL).

__STATIC_INLINE void __set_CNTP_CTL ( uint32_t  value)
Parameters
[in]valueCNTP_CTL Register value to set

This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).