| CMSIS-Core (Cortex-A) CMSIS-Core support for Cortex-A processor-based devices |

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Macros | Typedefs | Functions
irq_ctrl.h File Reference

## Macros
#define | IRQHANDLER_T
#define | IRQN_ID_T
#define | IRQ_MODE_TRIG_Pos (0U)
#define | IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
#define | IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: level triggered interrupt.
#define | IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: low level triggered interrupt.
#define | IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: high level triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: edge triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: rising edge triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: falling edge triggered interrupt.
#define | IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
| Trigger: rising and falling edge triggered interrupt.
#define | IRQ_MODE_TYPE_Pos (3U)
#define | IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
#define | IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos)
| Type: interrupt source triggers CPU IRQ line.
#define | IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos)
| Type: interrupt source triggers CPU FIQ line.
#define | IRQ_MODE_DOMAIN_Pos (4U)
#define | IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
#define | IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos)
| Domain: interrupt is targeting non-secure domain.
#define | IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos)
| Domain: interrupt is targeting secure domain.
#define | IRQ_MODE_CPU_Pos (5U)
#define | IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
#define | IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets all CPUs.
#define | IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 0.
#define | IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 1.
#define | IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 2.
#define | IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 3.
#define | IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 4.
#define | IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 5.
#define | IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 6.
#define | IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos)
| CPU: interrupt targets CPU 7.
#define | IRQ_MODE_MODEL_Pos (13U)
#define | IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos)
#define | IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos)
| Corresponding interrupt is handled using the N-N model.
#define | IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos)
| Corresponding interrupt is handled using the 1-N model.
#define | IRQ_MODE_ERROR (0x80000000UL)
| Bit indicating mode value error.
#define | IRQ_PRIORITY_Msk (0x0000FFFFUL)
| Interrupt priority value bit-mask.
#define | IRQ_PRIORITY_ERROR (0x80000000UL)
| Bit indicating priority value error.

## Typedefs
typedef void(* | IRQHandler_t) (void)
| Interrupt handler data type.
typedef int32_t | IRQn_ID_t
| Interrupt ID number data type.

## Functions
int32_t | IRQ_Initialize (void)
| Initialize interrupt controller.
int32_t | IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler)
| Register interrupt handler.
IRQHandler_t | IRQ_GetHandler (IRQn_ID_t irqn)
| Get the registered interrupt handler.
int32_t | IRQ_Enable (IRQn_ID_t irqn)
| Enable interrupt.
int32_t | IRQ_Disable (IRQn_ID_t irqn)
| Disable interrupt.
uint32_t | IRQ_GetEnableState (IRQn_ID_t irqn)
| Get interrupt enable state.
int32_t | IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode)
| Configure interrupt request mode.
uint32_t | IRQ_GetMode (IRQn_ID_t irqn)
| Get interrupt mode configuration.
IRQn_ID_t | IRQ_GetActiveIRQ (void)
| Get ID number of current interrupt request (IRQ).
IRQn_ID_t | IRQ_GetActiveFIQ (void)
| Get ID number of current fast interrupt request (FIQ).
int32_t | IRQ_EndOfInterrupt (IRQn_ID_t irqn)
| Signal end of interrupt processing.
int32_t | IRQ_SetPending (IRQn_ID_t irqn)
| Set interrupt pending flag.
uint32_t | IRQ_GetPending (IRQn_ID_t irqn)
| Get interrupt pending flag.
int32_t | IRQ_ClearPending (IRQn_ID_t irqn)
| Clear interrupt pending flag.
int32_t | IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority)
| Set interrupt priority value.
uint32_t | IRQ_GetPriority (IRQn_ID_t irqn)
| Get interrupt priority.
int32_t | IRQ_SetPriorityMask (uint32_t priority)
| Set priority masking threshold.
uint32_t | IRQ_GetPriorityMask (void)
| Get priority masking threshold.
int32_t | IRQ_SetPriorityGroupBits (uint32_t bits)
| Set priority grouping field split point.
uint32_t | IRQ_GetPriorityGroupBits (void)
| Get priority grouping field split point.

## Macro Definition Documentation

## ◆ IRQ_MODE_CPU_Msk

#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)

## ◆ IRQ_MODE_CPU_Pos

#define IRQ_MODE_CPU_Pos (5U)

## ◆ IRQ_MODE_DOMAIN_Msk

#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)

## ◆ IRQ_MODE_DOMAIN_Pos

#define IRQ_MODE_DOMAIN_Pos (4U)

## ◆ IRQ_MODE_MODEL_1N

#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos)

Corresponding interrupt is handled using the 1-N model.

## ◆ IRQ_MODE_MODEL_Msk

#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos)

## ◆ IRQ_MODE_MODEL_NN

#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos)

Corresponding interrupt is handled using the N-N model.

## ◆ IRQ_MODE_MODEL_Pos

#define IRQ_MODE_MODEL_Pos (13U)

## ◆ IRQ_MODE_TRIG_Msk

#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)

## ◆ IRQ_MODE_TRIG_Pos

#define IRQ_MODE_TRIG_Pos (0U)

## ◆ IRQ_MODE_TYPE_Msk

#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)

## ◆ IRQ_MODE_TYPE_Pos

#define IRQ_MODE_TYPE_Pos (3U)

## ◆ IRQHANDLER_T

#define IRQHANDLER_T

## ◆ IRQN_ID_T

#define IRQN_ID_T

## Typedef Documentation

## ◆ IRQHandler_t

typedef void(* IRQHandler_t) (void)

Interrupt handler data type.

## ◆ IRQn_ID_t

typedef int32_t IRQn_ID_t

Interrupt ID number data type.