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M480 BSP
V3.05.001
The Board Support Package for M480 Series
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SPI register definition header file. More...
Go to the source code of this file.
Data Structures | |
| struct | SPI_T |
Macros | |
| #define | SPI_CTL_SPIEN_Pos (0) |
| #define | SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) |
| #define | SPI_CTL_RXNEG_Pos (1) |
| #define | SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) |
| #define | SPI_CTL_TXNEG_Pos (2) |
| #define | SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) |
| #define | SPI_CTL_CLKPOL_Pos (3) |
| #define | SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) |
| #define | SPI_CTL_SUSPITV_Pos (4) |
| #define | SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) |
| #define | SPI_CTL_DWIDTH_Pos (8) |
| #define | SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) |
| #define | SPI_CTL_LSB_Pos (13) |
| #define | SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
| #define | SPI_CTL_HALFDPX_Pos (14) |
| #define | SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) |
| #define | SPI_CTL_RXONLY_Pos (15) |
| #define | SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) |
| #define | SPI_CTL_UNITIEN_Pos (17) |
| #define | SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) |
| #define | SPI_CTL_SLAVE_Pos (18) |
| #define | SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
| #define | SPI_CTL_REORDER_Pos (19) |
| #define | SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) |
| #define | SPI_CTL_DATDIR_Pos (20) |
| #define | SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) |
| #define | SPI_CLKDIV_DIVIDER_Pos (0) |
| #define | SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) |
| #define | SPI_SSCTL_SS_Pos (0) |
| #define | SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) |
| #define | SPI_SSCTL_SSACTPOL_Pos (2) |
| #define | SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) |
| #define | SPI_SSCTL_AUTOSS_Pos (3) |
| #define | SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) |
| #define | SPI_SSCTL_SLVBEIEN_Pos (8) |
| #define | SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) |
| #define | SPI_SSCTL_SLVURIEN_Pos (9) |
| #define | SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) |
| #define | SPI_SSCTL_SSACTIEN_Pos (12) |
| #define | SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) |
| #define | SPI_SSCTL_SSINAIEN_Pos (13) |
| #define | SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) |
| #define | SPI_SSCTL_SLVTOCNT_Pos (16) |
| #define | SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) |
| #define | SPI_PDMACTL_TXPDMAEN_Pos (0) |
| #define | SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) |
| #define | SPI_PDMACTL_RXPDMAEN_Pos (1) |
| #define | SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) |
| #define | SPI_PDMACTL_PDMARST_Pos (2) |
| #define | SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) |
| #define | SPI_FIFOCTL_RXRST_Pos (0) |
| #define | SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) |
| #define | SPI_FIFOCTL_TXRST_Pos (1) |
| #define | SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) |
| #define | SPI_FIFOCTL_RXTHIEN_Pos (2) |
| #define | SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) |
| #define | SPI_FIFOCTL_TXTHIEN_Pos (3) |
| #define | SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) |
| #define | SPI_FIFOCTL_RXTOIEN_Pos (4) |
| #define | SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) |
| #define | SPI_FIFOCTL_RXOVIEN_Pos (5) |
| #define | SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) |
| #define | SPI_FIFOCTL_TXUFPOL_Pos (6) |
| #define | SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) |
| #define | SPI_FIFOCTL_TXUFIEN_Pos (7) |
| #define | SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) |
| #define | SPI_FIFOCTL_RXFBCLR_Pos (8) |
| #define | SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) |
| #define | SPI_FIFOCTL_TXFBCLR_Pos (9) |
| #define | SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) |
| #define | SPI_FIFOCTL_RXTH_Pos (24) |
| #define | SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) |
| #define | SPI_FIFOCTL_TXTH_Pos (28) |
| #define | SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) |
| #define | SPI_STATUS_BUSY_Pos (0) |
| #define | SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) |
| #define | SPI_STATUS_UNITIF_Pos (1) |
| #define | SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) |
| #define | SPI_STATUS_SSACTIF_Pos (2) |
| #define | SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) |
| #define | SPI_STATUS_SSINAIF_Pos (3) |
| #define | SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) |
| #define | SPI_STATUS_SSLINE_Pos (4) |
| #define | SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) |
| #define | SPI_STATUS_SLVBEIF_Pos (6) |
| #define | SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) |
| #define | SPI_STATUS_SLVURIF_Pos (7) |
| #define | SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) |
| #define | SPI_STATUS_RXEMPTY_Pos (8) |
| #define | SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) |
| #define | SPI_STATUS_RXFULL_Pos (9) |
| #define | SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) |
| #define | SPI_STATUS_RXTHIF_Pos (10) |
| #define | SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) |
| #define | SPI_STATUS_RXOVIF_Pos (11) |
| #define | SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) |
| #define | SPI_STATUS_RXTOIF_Pos (12) |
| #define | SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) |
| #define | SPI_STATUS_SPIENSTS_Pos (15) |
| #define | SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) |
| #define | SPI_STATUS_TXEMPTY_Pos (16) |
| #define | SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) |
| #define | SPI_STATUS_TXFULL_Pos (17) |
| #define | SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) |
| #define | SPI_STATUS_TXTHIF_Pos (18) |
| #define | SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) |
| #define | SPI_STATUS_TXUFIF_Pos (19) |
| #define | SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) |
| #define | SPI_STATUS_TXRXRST_Pos (23) |
| #define | SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) |
| #define | SPI_STATUS_RXCNT_Pos (24) |
| #define | SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) |
| #define | SPI_STATUS_TXCNT_Pos (28) |
| #define | SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) |
| #define | SPI_TX_TX_Pos (0) |
| #define | SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) |
| #define | SPI_RX_RX_Pos (0) |
| #define | SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) |
| #define | SPI_I2SCTL_I2SEN_Pos (0) |
| #define | SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) |
| #define | SPI_I2SCTL_TXEN_Pos (1) |
| #define | SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) |
| #define | SPI_I2SCTL_RXEN_Pos (2) |
| #define | SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) |
| #define | SPI_I2SCTL_MUTE_Pos (3) |
| #define | SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) |
| #define | SPI_I2SCTL_WDWIDTH_Pos (4) |
| #define | SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) |
| #define | SPI_I2SCTL_MONO_Pos (6) |
| #define | SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) |
| #define | SPI_I2SCTL_ORDER_Pos (7) |
| #define | SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) |
| #define | SPI_I2SCTL_SLAVE_Pos (8) |
| #define | SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) |
| #define | SPI_I2SCTL_MCLKEN_Pos (15) |
| #define | SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) |
| #define | SPI_I2SCTL_RZCEN_Pos (16) |
| #define | SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) |
| #define | SPI_I2SCTL_LZCEN_Pos (17) |
| #define | SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) |
| #define | SPI_I2SCTL_RXLCH_Pos (23) |
| #define | SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) |
| #define | SPI_I2SCTL_RZCIEN_Pos (24) |
| #define | SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) |
| #define | SPI_I2SCTL_LZCIEN_Pos (25) |
| #define | SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) |
| #define | SPI_I2SCTL_FORMAT_Pos (28) |
| #define | SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) |
| #define | SPI_I2SCLK_MCLKDIV_Pos (0) |
| #define | SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) |
| #define | SPI_I2SCLK_BCLKDIV_Pos (8) |
| #define | SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) |
| #define | SPI_I2SSTS_RIGHT_Pos (4) |
| #define | SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) |
| #define | SPI_I2SSTS_RXEMPTY_Pos (8) |
| #define | SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) |
| #define | SPI_I2SSTS_RXFULL_Pos (9) |
| #define | SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) |
| #define | SPI_I2SSTS_RXTHIF_Pos (10) |
| #define | SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) |
| #define | SPI_I2SSTS_RXOVIF_Pos (11) |
| #define | SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) |
| #define | SPI_I2SSTS_RXTOIF_Pos (12) |
| #define | SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) |
| #define | SPI_I2SSTS_I2SENSTS_Pos (15) |
| #define | SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) |
| #define | SPI_I2SSTS_TXEMPTY_Pos (16) |
| #define | SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) |
| #define | SPI_I2SSTS_TXFULL_Pos (17) |
| #define | SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) |
| #define | SPI_I2SSTS_TXTHIF_Pos (18) |
| #define | SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) |
| #define | SPI_I2SSTS_TXUFIF_Pos (19) |
| #define | SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) |
| #define | SPI_I2SSTS_RZCIF_Pos (20) |
| #define | SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) |
| #define | SPI_I2SSTS_LZCIF_Pos (21) |
| #define | SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) |
| #define | SPI_I2SSTS_TXRXRST_Pos (23) |
| #define | SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) |
| #define | SPI_I2SSTS_RXCNT_Pos (24) |
| #define | SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) |
| #define | SPI_I2SSTS_TXCNT_Pos (28) |
| #define | SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) |
SPI register definition header file.
Definition in file spi_reg.h.
1.8.15