spi.h

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/**************************************************************************/
#ifndef __SPI_H__
#define __SPI_H__

#ifdef __cplusplus
extern "C"
{
#endif


#define SPI_MODE_0        (SPI_CTL_TXNEG_Msk)                             
#define SPI_MODE_1        (SPI_CTL_RXNEG_Msk)                             
#define SPI_MODE_2        (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)        
#define SPI_MODE_3        (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)        
#define SPI_SLAVE         (SPI_CTL_SLAVE_Msk)                             
#define SPI_MASTER        (0x0U)                                          
#define SPI_SS                (SPI_SSCTL_SS_Msk)                          
#define SPI_SS_ACTIVE_HIGH    (SPI_SSCTL_SSACTPOL_Msk)                    
#define SPI_SS_ACTIVE_LOW     (0x0U)                                      
/* SPI Interrupt Mask */
#define SPI_UNIT_INT_MASK                (0x001U)                          
#define SPI_SSACT_INT_MASK               (0x002U)                          
#define SPI_SSINACT_INT_MASK             (0x004U)                          
#define SPI_SLVUR_INT_MASK               (0x008U)                          
#define SPI_SLVBE_INT_MASK               (0x010U)                          
#define SPI_TXUF_INT_MASK                (0x040U)                          
#define SPI_FIFO_TXTH_INT_MASK           (0x080U)                          
#define SPI_FIFO_RXTH_INT_MASK           (0x100U)                          
#define SPI_FIFO_RXOV_INT_MASK           (0x200U)                          
#define SPI_FIFO_RXTO_INT_MASK           (0x400U)                          
/* SPI Status Mask */
#define SPI_BUSY_MASK                    (0x01U)                           
#define SPI_RX_EMPTY_MASK                (0x02U)                           
#define SPI_RX_FULL_MASK                 (0x04U)                           
#define SPI_TX_EMPTY_MASK                (0x08U)                           
#define SPI_TX_FULL_MASK                 (0x10U)                           
#define SPI_TXRX_RESET_MASK              (0x20U)                           
#define SPI_SPIEN_STS_MASK               (0x40U)                           
#define SPI_SSLINE_STS_MASK              (0x80U)                           
/* I2S Data Width */
#define SPII2S_DATABIT_8           (0U << SPI_I2SCTL_WDWIDTH_Pos)      
#define SPII2S_DATABIT_16          (1U << SPI_I2SCTL_WDWIDTH_Pos)      
#define SPII2S_DATABIT_24          (2U << SPI_I2SCTL_WDWIDTH_Pos)      
#define SPII2S_DATABIT_32          (3U << SPI_I2SCTL_WDWIDTH_Pos)      
/* I2S Audio Format */
#define SPII2S_MONO                SPI_I2SCTL_MONO_Msk                
#define SPII2S_STEREO              (0U)                               
/* I2S Data Format */
#define SPII2S_FORMAT_I2S          (0U<<SPI_I2SCTL_FORMAT_Pos)         
#define SPII2S_FORMAT_MSB          (1U<<SPI_I2SCTL_FORMAT_Pos)         
#define SPII2S_FORMAT_PCMA         (2U<<SPI_I2SCTL_FORMAT_Pos)         
#define SPII2S_FORMAT_PCMB         (3U<<SPI_I2SCTL_FORMAT_Pos)         
/* I2S Operation mode */
#define SPII2S_MODE_SLAVE          SPI_I2SCTL_SLAVE_Msk               
#define SPII2S_MODE_MASTER         (0U)                               
/* I2S Record Channel */
#define SPII2S_MONO_RIGHT          (0U)                               
#define SPII2S_MONO_LEFT           SPI_I2SCTL_RXLCH_Msk               
/* I2S Channel */
#define SPII2S_RIGHT               (0U)                               
#define SPII2S_LEFT                (1U)                               
/* I2S Interrupt Mask */
#define SPII2S_FIFO_TXTH_INT_MASK           (0x01U)                          
#define SPII2S_FIFO_RXTH_INT_MASK           (0x02U)                          
#define SPII2S_FIFO_RXOV_INT_MASK           (0x04U)                          
#define SPII2S_FIFO_RXTO_INT_MASK           (0x08U)                          
#define SPII2S_TXUF_INT_MASK                (0x10U)                          
#define SPII2S_RIGHT_ZC_INT_MASK            (0x20U)                          
#define SPII2S_LEFT_ZC_INT_MASK             (0x40U)                          
 /* end of group SPI_EXPORTED_CONSTANTS */


#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi)   ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)

#define SPI_TRIGGER_RX_PDMA(spi)   ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)

#define SPI_TRIGGER_TX_PDMA(spi)   ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)

#define SPI_TRIGGER_TX_RX_PDMA(spi)   ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk))

#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )

#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )

#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )

#define SPI_GET_RX_FIFO_COUNT(spi)   (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)

#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)

#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)

#define SPI_GET_TX_FIFO_FULL_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)

#define SPI_READ_RX(spi)   ((spi)->RX)

#define SPI_WRITE_TX(spi, u32TxData)   ((spi)->TX = (u32TxData))

#define SPI_SET_SS_HIGH(spi)   ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))

#define SPI_SET_SS_LOW(spi)   ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)

#define SPI_ENABLE_BYTE_REORDER(spi)   ((spi)->CTL |=  SPI_CTL_REORDER_Msk)

#define SPI_DISABLE_BYTE_REORDER(spi)   ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)

#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle)   ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))

#define SPI_SET_LSB_FIRST(spi)   ((spi)->CTL |= SPI_CTL_LSB_Msk)

#define SPI_SET_MSB_FIRST(spi)   ((spi)->CTL &= ~SPI_CTL_LSB_Msk)

#define SPI_SET_DATA_WIDTH(spi, u32Width)   ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))

#define SPI_IS_BUSY(spi)   ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )

#define SPI_ENABLE(spi)   ((spi)->CTL |= SPI_CTL_SPIEN_Msk)

#define SPI_DISABLE(spi)   ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)

/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);

__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
{
    if(u32ChMask == SPII2S_RIGHT)
    {
        i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
    }
    else
    {
        i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
    }
}

__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
{
    if(u32ChMask == SPII2S_RIGHT)
    {
        i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
    }
    else
    {
        i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
    }
}

#define SPII2S_ENABLE_TXDMA(i2s)  ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )

#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )

#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )

#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )

#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )

#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )

#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )

#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )

#define SPII2S_ENABLE_TX_MUTE(i2s)  ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )

#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )

#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )

#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )

__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
{
    u32Ch == SPII2S_MONO_LEFT ?
    (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
    (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
}

#define SPII2S_WRITE_TX_FIFO(i2s, u32Data)  ( (i2s)->TX = (u32Data) )

#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )

#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )

#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )

#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos  )

#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )



/* Function prototype declaration */
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void SPI_Close(SPI_T *spi);
void SPI_ClearRxFIFO(SPI_T *spi);
void SPI_ClearTxFIFO(SPI_T *spi);
void SPI_DisableAutoSS(SPI_T *spi);
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
uint32_t SPI_GetBusClock(SPI_T *spi);
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);

uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
void SPII2S_Close(SPI_T *i2s);
void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
void SPII2S_DisableMCLK(SPI_T *i2s);
void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);

 /* end of group SPI_EXPORTED_FUNCTIONS */
 /* end of group SPI_Driver */
 /* end of group Standard_Driver */

#ifdef __cplusplus
}
#endif

#endif

/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/