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M480 BSP
V3.05.001
The Board Support Package for M480 Series
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QEI register definition header file. More...
Go to the source code of this file.
Data Structures | |
| struct | QEI_T |
Macros | |
| #define | QEI_CNT_CNT_Pos (0) |
| #define | QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) |
| #define | QEI_CNTHOLD_CNTHOLD_Pos (0) |
| #define | QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) |
| #define | QEI_CNTLATCH_CNTLATCH_Pos (0) |
| #define | QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) |
| #define | QEI_CNTCMP_CNTCMP_Pos (0) |
| #define | QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) |
| #define | QEI_CNTMAX_CNTMAX_Pos (0) |
| #define | QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) |
| #define | QEI_CTL_NFCLKSEL_Pos (0) |
| #define | QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) |
| #define | QEI_CTL_NFDIS_Pos (3) |
| #define | QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) |
| #define | QEI_CTL_CHAEN_Pos (4) |
| #define | QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) |
| #define | QEI_CTL_CHBEN_Pos (5) |
| #define | QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) |
| #define | QEI_CTL_IDXEN_Pos (6) |
| #define | QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) |
| #define | QEI_CTL_MODE_Pos (8) |
| #define | QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) |
| #define | QEI_CTL_CHAINV_Pos (12) |
| #define | QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) |
| #define | QEI_CTL_CHBINV_Pos (13) |
| #define | QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) |
| #define | QEI_CTL_IDXINV_Pos (14) |
| #define | QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) |
| #define | QEI_CTL_OVUNIEN_Pos (16) |
| #define | QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) |
| #define | QEI_CTL_DIRIEN_Pos (17) |
| #define | QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) |
| #define | QEI_CTL_CMPIEN_Pos (18) |
| #define | QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) |
| #define | QEI_CTL_IDXIEN_Pos (19) |
| #define | QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) |
| #define | QEI_CTL_HOLDTMR0_Pos (20) |
| #define | QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) |
| #define | QEI_CTL_HOLDTMR1_Pos (21) |
| #define | QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) |
| #define | QEI_CTL_HOLDTMR2_Pos (22) |
| #define | QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) |
| #define | QEI_CTL_HOLDTMR3_Pos (23) |
| #define | QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) |
| #define | QEI_CTL_HOLDCNT_Pos (24) |
| #define | QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) |
| #define | QEI_CTL_IDXLATEN_Pos (25) |
| #define | QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) |
| #define | QEI_CTL_IDXRLDEN_Pos (27) |
| #define | QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) |
| #define | QEI_CTL_CMPEN_Pos (28) |
| #define | QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) |
| #define | QEI_CTL_QEIEN_Pos (29) |
| #define | QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) |
| #define | QEI_STATUS_IDXF_Pos (0) |
| #define | QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) |
| #define | QEI_STATUS_CMPF_Pos (1) |
| #define | QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) |
| #define | QEI_STATUS_OVUNF_Pos (2) |
| #define | QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) |
| #define | QEI_STATUS_DIRCHGF_Pos (3) |
| #define | QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) |
| #define | QEI_STATUS_DIRF_Pos (8) |
| #define | QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) |
QEI register definition header file.
Definition in file qei_reg.h.
1.8.15