M480 BSP  V3.05.001
The Board Support Package for M480 Series
pdma.c
Go to the documentation of this file.
1 /**************************************************************************/
9 #include "NuMicro.h"
10 
11 
12 static uint8_t u32ChSelect[PDMA_CH_MAX];
13 
38 void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask)
39 {
40  uint32_t i;
41 
42  for (i=0UL; i<PDMA_CH_MAX; i++)
43  {
44  if((1 << i) & u32Mask)
45  {
46  pdma->DSCT[i].CTL = 0UL;
47  u32ChSelect[i] = PDMA_MEM;
48  }
49  }
50 
51  pdma->CHCTL |= u32Mask;
52 }
53 
63 void PDMA_Close(PDMA_T * pdma)
64 {
65  pdma->CHCTL = 0UL;
66 }
67 
83 void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
84 {
86  pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
87 }
88 
102 void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
103 {
104  pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
105  pdma->STRIDE[u32Ch].ASOCR =((u32DestLen-1)<<16) | (u32SrcLen-1);
106  pdma->STRIDE[u32Ch].STCR = u32TransCount-1;
107 }
108 
122 void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount)
123 {
124  pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
125  pdma->REPEAT[u32Ch].AICTL =((u32DestInterval)<<16) | (u32SrcInterval);
126  pdma->REPEAT[u32Ch].RCNT = u32RepeatCount;
127 }
128 
147 void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
148 {
149  pdma->DSCT[u32Ch].SA = u32SrcAddr;
150  pdma->DSCT[u32Ch].DA = u32DstAddr;
152  pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
153 }
154 
235 void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
236 {
237  u32ChSelect[u32Ch] = u32Peripheral;
238  switch(u32Ch)
239  {
240  case 0ul:
241  pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
242  break;
243  case 1ul:
244  pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
245  break;
246  case 2ul:
247  pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
248  break;
249  case 3ul:
250  pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
251  break;
252  case 4ul:
253  pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
254  break;
255  case 5ul:
256  pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
257  break;
258  case 6ul:
259  pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
260  break;
261  case 7ul:
262  pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
263  break;
264  case 8ul:
265  pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
266  break;
267  case 9ul:
268  pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
269  break;
270  case 10ul:
271  pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
272  break;
273  case 11ul:
274  pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
275  break;
276  case 12ul:
277  pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral;
278  break;
279  case 13ul:
281  break;
282  case 14ul:
284  break;
285  case 15ul:
287  break;
288  default:
289  break;
290  }
291 
292  if(u32ScatterEn)
293  {
294  pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
295  pdma->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
296  }
297  else
298  {
299  pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
300  }
301 }
302 
325 void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
326 {
328  pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
329 }
330 
342 void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask)
343 {
344  pdma->TOUTEN |= u32Mask;
345 }
346 
358 void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask)
359 {
360  pdma->TOUTEN &= ~u32Mask;
361 }
362 
376 void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
377 {
378  switch(u32Ch)
379  {
380  case 0ul:
381  pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
382  break;
383  case 1ul:
384  pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
385  break;
386  default:
387  break;
388  }
389 
390  if (u32OnOff)
391  pdma->TOUTEN |= (1 << u32Ch);
392  else
393  pdma->TOUTEN &= ~(1 << u32Ch);
394 }
395 
406 void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch)
407 {
408  if(u32ChSelect[u32Ch] == PDMA_MEM)
409  {
410  pdma->SWREQ = (1ul << u32Ch);
411  }
412  else {}
413 }
414 
429 void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask)
430 {
431  switch(u32Mask)
432  {
433  case PDMA_INT_TRANS_DONE:
434  pdma->INTEN |= (1ul << u32Ch);
435  break;
436  case PDMA_INT_TEMPTY:
437  pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
438  break;
439  case PDMA_INT_TIMEOUT:
440  pdma->TOUTIEN |= (1ul << u32Ch);
441  break;
442 
443  default:
444  break;
445  }
446 }
447 
462 void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask)
463 {
464  switch(u32Mask)
465  {
466  case PDMA_INT_TRANS_DONE:
467  pdma->INTEN &= ~(1ul << u32Ch);
468  break;
469  case PDMA_INT_TEMPTY:
470  pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
471  break;
472  case PDMA_INT_TIMEOUT:
473  pdma->TOUTIEN &= ~(1ul << u32Ch);
474  break;
475 
476  default:
477  break;
478  }
479 }
480  /* end of group PDMA_EXPORTED_FUNCTIONS */
482  /* end of group PDMA_Driver */
484  /* end of group Standard_Driver */
486 
487 /*** (C) COPYRIGHT 2014~2016 Nuvoton Technology Corp. ***/
__IO uint32_t DA
Definition: pdma_reg.h:231
#define PDMA_DSCT_CTL_DAINC_Msk
Definition: pdma_reg.h:1275
#define PDMA_DSCT_CTL_TXWIDTH_Msk
Definition: pdma_reg.h:1278
__IO uint32_t NEXT
Definition: pdma_reg.h:232
#define PDMA_REQSEL4_7_REQSRC6_Pos
Definition: pdma_reg.h:1484
#define PDMA_REQSEL4_7_REQSRC5_Msk
Definition: pdma_reg.h:1482
__IO uint32_t CTL
Definition: pdma_reg.h:229
#define PDMA_REQSEL8_11_REQSRC9_Msk
Definition: pdma_reg.h:1494
#define PDMA_MEM
Definition: pdma.h:77
__IO uint32_t CHCTL
Definition: pdma_reg.h:1216
REPEAT_T REPEAT[2]
Definition: pdma_reg.h:1251
__IO uint32_t AICTL
Definition: pdma_reg.h:332
__IO uint32_t TOUTEN
Definition: pdma_reg.h:1229
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
Definition: pdma.c:235
#define PDMA_DSCT_CTL_SAINC_Msk
Definition: pdma_reg.h:1272
#define PDMA_INT_TEMPTY
Definition: pdma.h:150
__IO uint32_t STCR
Definition: pdma_reg.h:282
#define PDMA_DSCT_CTL_OPMODE_Msk
Definition: pdma_reg.h:1260
#define PDMA_TOC0_1_TOC1_Msk
Definition: pdma_reg.h:1461
#define PDMA_REQSEL4_7_REQSRC7_Msk
Definition: pdma_reg.h:1488
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
Definition: pdma.c:147
static uint8_t u32ChSelect[PDMA_CH_MAX]
Definition: pdma.c:12
__IO uint32_t REQSEL8_11
Definition: pdma_reg.h:1242
NuMicro peripheral access layer header file.
#define PDMA_REQSEL12_15_REQSRC12_Msk
Definition: pdma_reg.h:1503
#define PDMA_REQSEL12_15_REQSRC14_Pos
Definition: pdma_reg.h:1508
#define PDMA_OP_BASIC
Definition: pdma.h:35
#define PDMA_REQSEL0_3_REQSRC1_Msk
Definition: pdma_reg.h:1470
#define PDMA_REQSEL4_7_REQSRC6_Msk
Definition: pdma_reg.h:1485
__IO uint32_t TOC0_1
Definition: pdma_reg.h:1232
#define PDMA_OP_SCATTER
Definition: pdma.h:36
#define PDMA_REQSEL8_11_REQSRC11_Msk
Definition: pdma_reg.h:1500
#define PDMA_REQSEL12_15_REQSRC15_Msk
Definition: pdma_reg.h:1512
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
Definition: pdma.c:462
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)
Disable timeout function.
Definition: pdma.c:358
__IO uint32_t REQSEL0_3
Definition: pdma_reg.h:1240
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)
Trigger PDMA.
Definition: pdma.c:406
#define PDMA_REQSEL0_3_REQSRC2_Msk
Definition: pdma_reg.h:1473
#define PDMA_REQSEL8_11_REQSRC9_Pos
Definition: pdma_reg.h:1493
#define PDMA_REQSEL8_11_REQSRC8_Msk
Definition: pdma_reg.h:1491
#define PDMA_REQSEL0_3_REQSRC3_Pos
Definition: pdma_reg.h:1475
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
Definition: pdma.c:83
#define PDMA_REQSEL4_7_REQSRC4_Msk
Definition: pdma_reg.h:1479
__IO uint32_t INTEN
Definition: pdma_reg.h:1222
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask)
Enable timeout function.
Definition: pdma.c:342
#define PDMA_REQSEL0_3_REQSRC2_Pos
Definition: pdma_reg.h:1472
__IO uint32_t TOUTIEN
Definition: pdma_reg.h:1230
__O uint32_t SWREQ
Definition: pdma_reg.h:1218
#define PDMA_DSCT_CTL_TXCNT_Msk
Definition: pdma_reg.h:1287
#define PDMA_INT_TRANS_DONE
Definition: pdma.h:149
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
Set PDMA Burst Type and Size.
Definition: pdma.c:325
void PDMA_Close(PDMA_T *pdma)
PDMA Close.
Definition: pdma.c:63
#define PDMA
Definition: M480.h:387
__IO uint32_t RCNT
Definition: pdma_reg.h:333
#define PDMA_DSCT_CTL_TXTYPE_Msk
Definition: pdma_reg.h:1263
#define PDMA_REQSEL12_15_REQSRC13_Msk
Definition: pdma_reg.h:1506
#define PDMA_DSCT_CTL_BURSIZE_Msk
Definition: pdma_reg.h:1266
__IO uint32_t SA
Definition: pdma_reg.h:230
#define PDMA_REQSEL8_11_REQSRC10_Pos
Definition: pdma_reg.h:1496
#define PDMA_REQSEL12_15_REQSRC13_Pos
Definition: pdma_reg.h:1505
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)
PDMA Open.
Definition: pdma.c:38
#define PDMA_REQSEL12_15_REQSRC15_Pos
Definition: pdma_reg.h:1511
void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
Set PDMA Stride Mode.
Definition: pdma.c:102
#define PDMA_REQSEL0_3_REQSRC3_Msk
Definition: pdma_reg.h:1476
#define PDMA_REQSEL4_7_REQSRC7_Pos
Definition: pdma_reg.h:1487
#define PDMA_REQSEL0_3_REQSRC1_Pos
Definition: pdma_reg.h:1469
__IO uint32_t REQSEL12_15
Definition: pdma_reg.h:1243
#define PDMA_REQSEL4_7_REQSRC5_Pos
Definition: pdma_reg.h:1481
#define PDMA_REQSEL8_11_REQSRC11_Pos
Definition: pdma_reg.h:1499
#define PDMA_REQSEL8_11_REQSRC10_Msk
Definition: pdma_reg.h:1497
#define PDMA_DSCT_CTL_TXCNT_Pos
Definition: pdma_reg.h:1286
void PDMA_SetRepeat(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount)
Set PDMA Repeat.
Definition: pdma.c:122
#define PDMA_CH_MAX
Definition: pdma.h:29
DSCT_T DSCT[16]
Definition: pdma_reg.h:1211
#define PDMA_INT_TIMEOUT
Definition: pdma.h:151
__IO uint32_t ASOCR
Definition: pdma_reg.h:283
STRIDE_T STRIDE[6]
Definition: pdma_reg.h:1247
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
Definition: pdma.c:429
__IO uint32_t REQSEL4_7
Definition: pdma_reg.h:1241
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout Count.
Definition: pdma.c:376
#define PDMA_TOC0_1_TOC1_Pos
Definition: pdma_reg.h:1460
#define PDMA_TOC0_1_TOC0_Msk
Definition: pdma_reg.h:1458
#define PDMA_DSCT_CTL_STRIDEEN_Msk
Definition: pdma_reg.h:1284
#define PDMA_DSCT_CTL_TBINTDIS_Msk
Definition: pdma_reg.h:1269
#define PDMA_REQSEL12_15_REQSRC14_Msk
Definition: pdma_reg.h:1509
#define PDMA_REQSEL0_3_REQSRC0_Msk
Definition: pdma_reg.h:1467