i2s.h

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/****************************************************************************/
#ifndef __I2S_H__
#define __I2S_H__

#ifdef __cplusplus
extern "C"
{
#endif

#define I2S_DATABIT_8           (0U << I2S_CTL0_DATWIDTH_Pos)       
#define I2S_DATABIT_16          (1U << I2S_CTL0_DATWIDTH_Pos)       
#define I2S_DATABIT_24          (2U << I2S_CTL0_DATWIDTH_Pos)       
#define I2S_DATABIT_32          (3U << I2S_CTL0_DATWIDTH_Pos)       
/* Audio Format */
#define I2S_ENABLE_MONO         I2S_CTL0_MONO_Msk                   
#define I2S_DISABLE_MONO        (0U)                                
/* I2S Data Format */
#define I2S_FORMAT_I2S          (0U << I2S_CTL0_FORMAT_Pos)         
#define I2S_FORMAT_I2S_MSB      (1U << I2S_CTL0_FORMAT_Pos)         
#define I2S_FORMAT_I2S_LSB      (2U << I2S_CTL0_FORMAT_Pos)         
#define I2S_FORMAT_PCM          (4U << I2S_CTL0_FORMAT_Pos)         
#define I2S_FORMAT_PCM_MSB      (5U << I2S_CTL0_FORMAT_Pos)         
#define I2S_FORMAT_PCM_LSB      (6U << I2S_CTL0_FORMAT_Pos)         
/* I2S Data Format */
#define I2S_ORDER_AT_MSB        (0U)                                
#define I2S_ORDER_AT_LSB        I2S_CTL0_ORDER_Msk                  
/* I2S TDM Channel Number */
#define I2S_TDM_2CH            0U                                   
#define I2S_TDM_4CH            1U                                   
#define I2S_TDM_6CH            2U                                   
#define I2S_TDM_8CH            3U                                   
/* I2S TDM Channel Width */
#define I2S_TDM_WIDTH_8BIT      0U                                  
#define I2S_TDM_WIDTH_16BIT     1U                                  
#define I2S_TDM_WIDTH_24BIT     2U                                  
#define I2S_TDM_WIDTH_32BIT     3U                                  
/* I2S TDM Sync Width */
#define I2S_TDM_SYNC_ONE_BCLK       0U                              
#define I2S_TDM_SYNC_ONE_CHANNEL    1U                              
/* I2S Operation mode */
#define I2S_MODE_SLAVE          I2S_CTL0_SLAVE_Msk                  
#define I2S_MODE_MASTER         (0u)                                
/* I2S FIFO Threshold */
#define I2S_FIFO_TX_LEVEL_WORD_0    (0U)                             
#define I2S_FIFO_TX_LEVEL_WORD_1    (1U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_2    (2U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_3    (3U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_4    (4U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_5    (5U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_6    (6U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_7    (7U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_8    (8U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_9    (9U << I2S_CTL1_TXTH_Pos)        
#define I2S_FIFO_TX_LEVEL_WORD_10   (10U << I2S_CTL1_TXTH_Pos)       
#define I2S_FIFO_TX_LEVEL_WORD_11   (11U << I2S_CTL1_TXTH_Pos)       
#define I2S_FIFO_TX_LEVEL_WORD_12   (12U << I2S_CTL1_TXTH_Pos)       
#define I2S_FIFO_TX_LEVEL_WORD_13   (13U << I2S_CTL1_TXTH_Pos)       
#define I2S_FIFO_TX_LEVEL_WORD_14   (14U << I2S_CTL1_TXTH_Pos)       
#define I2S_FIFO_TX_LEVEL_WORD_15   (15U << I2S_CTL1_TXTH_Pos)       
#define I2S_FIFO_RX_LEVEL_WORD_1    (0U)                             
#define I2S_FIFO_RX_LEVEL_WORD_2    (1U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_3    (2U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_4    (3U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_5    (4U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_6    (5U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_7    (6U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_8    (7U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_9    (8U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_10   (9U << I2S_CTL1_RXTH_Pos)        
#define I2S_FIFO_RX_LEVEL_WORD_11   (10U << I2S_CTL1_RXTH_Pos)       
#define I2S_FIFO_RX_LEVEL_WORD_12   (11U << I2S_CTL1_RXTH_Pos)       
#define I2S_FIFO_RX_LEVEL_WORD_13   (12U << I2S_CTL1_RXTH_Pos)       
#define I2S_FIFO_RX_LEVEL_WORD_14   (13U << I2S_CTL1_RXTH_Pos)       
#define I2S_FIFO_RX_LEVEL_WORD_15   (14U << I2S_CTL1_RXTH_Pos)       
#define I2S_FIFO_RX_LEVEL_WORD_16   (15U << I2S_CTL1_RXTH_Pos)       
/* I2S Record Channel */
#define I2S_MONO_RIGHT          (0U)                                  
#define I2S_MONO_LEFT           I2S_CTL0_RXLCH_Msk                    
/* I2S Channel */
#define I2S_RIGHT               (0U)                                  
#define I2S_LEFT                (1U)                                  
 /* end of group I2S_EXPORTED_CONSTANTS */

/*---------------------------------------------------------------------------------------------------------*/
/* inline functions                                                                                        */
/*---------------------------------------------------------------------------------------------------------*/
__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
{
    if((u32ChMask > 0U) && (u32ChMask < 9U))
    {
        i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U));
    }
}

__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
{
    if((u32ChMask > 0U) && (u32ChMask < 9U))
    {
        i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U));
    }
}

#define I2S_ENABLE_TXDMA(i2s)  ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )

#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )

#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )

#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )

#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )

#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )

#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )

#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )

#define I2S_ENABLE_TX_MUTE(i2s)  ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )

#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )

#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )

#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )

__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
{
    u32Ch == I2S_MONO_LEFT ?
    (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
    (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
}

#define I2S_WRITE_TX_FIFO(i2s, u32Data)  ( (i2s)->TXFIFO = (u32Data) )

#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )

#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )

#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )

#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )

#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )

#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )

#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )

void I2S_Close(I2S_T *i2s);
void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
void I2S_DisableMCLK(I2S_T *i2s);
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
 /* end of group I2S_EXPORTED_FUNCTIONS */

 /* end of group I2S_Driver */
 /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif

#endif

/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/