Macros
#define	EADC_CTL_DIFFEN_SINGLE_END

#define	EADC_CTL_DIFFEN_DIFFERENTIAL

#define	EADC_CTL_DMOF_STRAIGHT_BINARY

#define	EADC_CTL_DMOF_TWOS_COMPLEMENT

#define	EADC_SCTL_CHSEL(x)

#define	EADC_SCTL_TRGDLYDIV(x)

#define	EADC_SCTL_TRGDLYCNT(x)

#define	EADC_SOFTWARE_TRIGGER

#define	EADC_FALLING_EDGE_TRIGGER

#define	EADC_RISING_EDGE_TRIGGER

#define	EADC_FALLING_RISING_EDGE_TRIGGER

#define	EADC_ADINT0_TRIGGER

#define	EADC_ADINT1_TRIGGER

#define	EADC_TIMER0_TRIGGER

#define	EADC_TIMER1_TRIGGER

#define	EADC_TIMER2_TRIGGER

#define	EADC_TIMER3_TRIGGER

#define	EADC_EPWM0TG0_TRIGGER

#define	EADC_EPWM0TG1_TRIGGER

#define	EADC_EPWM0TG2_TRIGGER

#define	EADC_EPWM0TG3_TRIGGER

#define	EADC_EPWM0TG4_TRIGGER

#define	EADC_EPWM0TG5_TRIGGER

#define	EADC_EPWM1TG0_TRIGGER

#define	EADC_EPWM1TG1_TRIGGER

#define	EADC_EPWM1TG2_TRIGGER

#define	EADC_EPWM1TG3_TRIGGER

#define	EADC_EPWM1TG4_TRIGGER

#define	EADC_EPWM1TG5_TRIGGER

#define	EADC_BPWM0TG_TRIGGER

#define	EADC_BPWM1TG_TRIGGER

#define	EADC_SCTL_TRGDLYDIV_DIVIDER_1

#define	EADC_SCTL_TRGDLYDIV_DIVIDER_2

#define	EADC_SCTL_TRGDLYDIV_DIVIDER_4

#define	EADC_SCTL_TRGDLYDIV_DIVIDER_16

#define	EADC_CMP_CMPCOND_LESS_THAN

#define	EADC_CMP_CMPCOND_GREATER_OR_EQUAL

#define	EADC_CMP_CMPWEN_ENABLE

#define	EADC_CMP_CMPWEN_DISABLE

#define	EADC_CMP_ADCMPIE_ENABLE

#define	EADC_CMP_ADCMPIE_DISABLE

Detailed Description

Macro Definition Documentation

◆ EADC_ADINT0_TRIGGER

#define EADC_ADINT0_TRIGGER

ADC ADINT0 interrupt EOC pulse trigger

Definition at line 50 of file eadc.h.

◆ EADC_ADINT1_TRIGGER

#define EADC_ADINT1_TRIGGER

ADC ADINT1 interrupt EOC pulse trigger

Definition at line 51 of file eadc.h.

◆ EADC_BPWM0TG_TRIGGER

#define EADC_BPWM0TG_TRIGGER

BPWM0TG trigger

Definition at line 68 of file eadc.h.

◆ EADC_BPWM1TG_TRIGGER

#define EADC_BPWM1TG_TRIGGER

BPWM1TG trigger

Definition at line 69 of file eadc.h.

◆ EADC_CMP_ADCMPIE_DISABLE

#define EADC_CMP_ADCMPIE_DISABLE

A/D result compare interrupt disable

Definition at line 85 of file eadc.h.

◆ EADC_CMP_ADCMPIE_ENABLE

#define EADC_CMP_ADCMPIE_ENABLE

A/D result compare interrupt enable

Definition at line 84 of file eadc.h.

◆ EADC_CMP_CMPCOND_GREATER_OR_EQUAL

#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL

The compare condition is "greater than or equal to"

Definition at line 81 of file eadc.h.

◆ EADC_CMP_CMPCOND_LESS_THAN

#define EADC_CMP_CMPCOND_LESS_THAN

The compare condition is "less than"

Definition at line 80 of file eadc.h.

◆ EADC_CMP_CMPWEN_DISABLE

#define EADC_CMP_CMPWEN_DISABLE

Compare window mode disable

Definition at line 83 of file eadc.h.

◆ EADC_CMP_CMPWEN_ENABLE

#define EADC_CMP_CMPWEN_ENABLE

Compare window mode enable

Definition at line 82 of file eadc.h.

◆ EADC_CTL_DIFFEN_DIFFERENTIAL

#define EADC_CTL_DIFFEN_DIFFERENTIAL

Differential input mode

Definition at line 34 of file eadc.h.

◆ EADC_CTL_DIFFEN_SINGLE_END

#define EADC_CTL_DIFFEN_SINGLE_END

Single-end input mode

Definition at line 33 of file eadc.h.

◆ EADC_CTL_DMOF_STRAIGHT_BINARY

#define EADC_CTL_DMOF_STRAIGHT_BINARY

Select the straight binary format as the output format of the conversion result

Definition at line 36 of file eadc.h.

◆ EADC_CTL_DMOF_TWOS_COMPLEMENT

#define EADC_CTL_DMOF_TWOS_COMPLEMENT

Select the 2's complement format as the output format of the conversion result

Definition at line 37 of file eadc.h.

◆ EADC_EPWM0TG0_TRIGGER

#define EADC_EPWM0TG0_TRIGGER

EPWM0TG0 trigger

Definition at line 56 of file eadc.h.

◆ EADC_EPWM0TG1_TRIGGER

#define EADC_EPWM0TG1_TRIGGER

EPWM0TG1 trigger

Definition at line 57 of file eadc.h.

◆ EADC_EPWM0TG2_TRIGGER

#define EADC_EPWM0TG2_TRIGGER

EPWM0TG2 trigger

Definition at line 58 of file eadc.h.

◆ EADC_EPWM0TG3_TRIGGER

#define EADC_EPWM0TG3_TRIGGER

EPWM0TG3 trigger

Definition at line 59 of file eadc.h.

◆ EADC_EPWM0TG4_TRIGGER

#define EADC_EPWM0TG4_TRIGGER

EPWM0TG4 trigger

Definition at line 60 of file eadc.h.

◆ EADC_EPWM0TG5_TRIGGER

#define EADC_EPWM0TG5_TRIGGER

EPWM0TG5 trigger

Definition at line 61 of file eadc.h.

◆ EADC_EPWM1TG0_TRIGGER

#define EADC_EPWM1TG0_TRIGGER

EPWM1TG0 trigger

Definition at line 62 of file eadc.h.

◆ EADC_EPWM1TG1_TRIGGER

#define EADC_EPWM1TG1_TRIGGER

EPWM1TG1 trigger

Definition at line 63 of file eadc.h.

◆ EADC_EPWM1TG2_TRIGGER

#define EADC_EPWM1TG2_TRIGGER

EPWM1TG2 trigger

Definition at line 64 of file eadc.h.

◆ EADC_EPWM1TG3_TRIGGER

#define EADC_EPWM1TG3_TRIGGER

EPWM1TG3 trigger

Definition at line 65 of file eadc.h.

◆ EADC_EPWM1TG4_TRIGGER

#define EADC_EPWM1TG4_TRIGGER

EPWM1TG4 trigger

Definition at line 66 of file eadc.h.

◆ EADC_EPWM1TG5_TRIGGER

#define EADC_EPWM1TG5_TRIGGER

EPWM1TG5 trigger

Definition at line 67 of file eadc.h.

◆ EADC_FALLING_EDGE_TRIGGER

#define EADC_FALLING_EDGE_TRIGGER

STADC pin falling edge trigger

Definition at line 47 of file eadc.h.

◆ EADC_FALLING_RISING_EDGE_TRIGGER

#define EADC_FALLING_RISING_EDGE_TRIGGER

STADC pin both falling and rising edge trigger

Definition at line 49 of file eadc.h.

◆ EADC_RISING_EDGE_TRIGGER

#define EADC_RISING_EDGE_TRIGGER

STADC pin rising edge trigger

Definition at line 48 of file eadc.h.

◆ EADC_SCTL_CHSEL

#define EADC_SCTL_CHSEL ( x )

A/D sample module channel selection

Definition at line 42 of file eadc.h.

◆ EADC_SCTL_TRGDLYCNT

#define EADC_SCTL_TRGDLYCNT ( x )

A/D sample module start of conversion trigger delay time

Definition at line 44 of file eadc.h.

◆ EADC_SCTL_TRGDLYDIV

#define EADC_SCTL_TRGDLYDIV ( x )

A/D sample module start of conversion trigger delay clock divider selection

Definition at line 43 of file eadc.h.

◆ EADC_SCTL_TRGDLYDIV_DIVIDER_1

#define EADC_SCTL_TRGDLYDIV_DIVIDER_1

Trigger delay clock frequency is ADC_CLK/1

Definition at line 71 of file eadc.h.

◆ EADC_SCTL_TRGDLYDIV_DIVIDER_16

#define EADC_SCTL_TRGDLYDIV_DIVIDER_16

Trigger delay clock frequency is ADC_CLK/16

Definition at line 74 of file eadc.h.

◆ EADC_SCTL_TRGDLYDIV_DIVIDER_2

#define EADC_SCTL_TRGDLYDIV_DIVIDER_2

Trigger delay clock frequency is ADC_CLK/2

Definition at line 72 of file eadc.h.

◆ EADC_SCTL_TRGDLYDIV_DIVIDER_4

#define EADC_SCTL_TRGDLYDIV_DIVIDER_4

Trigger delay clock frequency is ADC_CLK/4

Definition at line 73 of file eadc.h.

◆ EADC_SOFTWARE_TRIGGER

#define EADC_SOFTWARE_TRIGGER

Software trigger

Definition at line 46 of file eadc.h.

◆ EADC_TIMER0_TRIGGER

#define EADC_TIMER0_TRIGGER

Timer0 overflow pulse trigger

Definition at line 52 of file eadc.h.

◆ EADC_TIMER1_TRIGGER

#define EADC_TIMER1_TRIGGER

Timer1 overflow pulse trigger

Definition at line 53 of file eadc.h.

◆ EADC_TIMER2_TRIGGER

#define EADC_TIMER2_TRIGGER

Timer2 overflow pulse trigger

Definition at line 54 of file eadc.h.

◆ EADC_TIMER3_TRIGGER

#define EADC_TIMER3_TRIGGER

Timer3 overflow pulse trigger

Definition at line 55 of file eadc.h.

Macros