Document/html/emac__reg_8h_source.html

 /**************************************************************************/
 #ifndef __EMAC_REG_H__
 #define __EMAC_REG_H__

 #if defined ( __CC_ARM   )
 #pragma anon_unions
 #endif

 typedef struct
 {

     __IO uint32_t CAMCTL;
     __IO uint32_t CAMEN;
     __IO uint32_t CAM0M;
     __IO uint32_t CAM0L;
     __IO uint32_t CAM1M;
     __IO uint32_t CAM1L;
     __IO uint32_t CAM2M;
     __IO uint32_t CAM2L;
     __IO uint32_t CAM3M;
     __IO uint32_t CAM3L;
     __IO uint32_t CAM4M;
     __IO uint32_t CAM4L;
     __IO uint32_t CAM5M;
     __IO uint32_t CAM5L;
     __IO uint32_t CAM6M;
     __IO uint32_t CAM6L;
     __IO uint32_t CAM7M;
     __IO uint32_t CAM7L;
     __IO uint32_t CAM8M;
     __IO uint32_t CAM8L;
     __IO uint32_t CAM9M;
     __IO uint32_t CAM9L;
     __IO uint32_t CAM10M;
     __IO uint32_t CAM10L;
     __IO uint32_t CAM11M;
     __IO uint32_t CAM11L;
     __IO uint32_t CAM12M;
     __IO uint32_t CAM12L;
     __IO uint32_t CAM13M;
     __IO uint32_t CAM13L;
     __IO uint32_t CAM14M;
     __IO uint32_t CAM14L;
     __IO uint32_t CAM15MSB;
     __IO uint32_t CAM15LSB;
     __IO uint32_t TXDSA;
     __IO uint32_t RXDSA;
     __IO uint32_t CTL;
     __IO uint32_t MIIMDAT;
     __IO uint32_t MIIMCTL;
     __IO uint32_t FIFOCTL;
     __O  uint32_t TXST;
     __O  uint32_t RXST;
     __IO uint32_t MRFL;
     __IO uint32_t INTEN;
     __IO uint32_t INTSTS;
     __IO uint32_t GENSTS;
     __IO uint32_t MPCNT;
     __I  uint32_t RPCNT;
     __I  uint32_t RESERVE0[2];
     __IO uint32_t FRSTS;
     __I  uint32_t CTXDSA;
     __I  uint32_t CTXBSA;
     __I  uint32_t CRXDSA;
     __I  uint32_t CRXBSA;
     __I  uint32_t RESERVE1[9];
     __IO uint32_t TSCTL;
     __I  uint32_t RESERVE2[3];
     __I  uint32_t TSSEC;
     __I  uint32_t TSSUBSEC;
     __IO uint32_t TSINC;
     __IO uint32_t TSADDEND;
     __IO uint32_t UPDSEC;
     __IO uint32_t UPDSUBSEC;
     __IO uint32_t ALMSEC;
     __IO uint32_t ALMSUBSEC;
 } EMAC_T;

 #define EMAC_CAMCTL_AUP_Pos              (0)
 #define EMAC_CAMCTL_AUP_Msk              (0x1ul << EMAC_CAMCTL_AUP_Pos)
 #define EMAC_CAMCTL_AMP_Pos              (1)
 #define EMAC_CAMCTL_AMP_Msk              (0x1ul << EMAC_CAMCTL_AMP_Pos)
 #define EMAC_CAMCTL_ABP_Pos              (2)
 #define EMAC_CAMCTL_ABP_Msk              (0x1ul << EMAC_CAMCTL_ABP_Pos)
 #define EMAC_CAMCTL_COMPEN_Pos           (3)
 #define EMAC_CAMCTL_COMPEN_Msk           (0x1ul << EMAC_CAMCTL_COMPEN_Pos)
 #define EMAC_CAMCTL_CMPEN_Pos            (4)
 #define EMAC_CAMCTL_CMPEN_Msk            (0x1ul << EMAC_CAMCTL_CMPEN_Pos)
 #define EMAC_CAMEN_CAMxEN_Pos            (0)
 #define EMAC_CAMEN_CAMxEN_Msk            (0x1ul << EMAC_CAMEN_CAMxEN_Pos)
 #define EMAC_CAM0M_MACADDR2_Pos          (0)
 #define EMAC_CAM0M_MACADDR2_Msk          (0xfful << EMAC_CAM0M_MACADDR2_Pos)
 #define EMAC_CAM0M_MACADDR3_Pos          (8)
 #define EMAC_CAM0M_MACADDR3_Msk          (0xfful << EMAC_CAM0M_MACADDR3_Pos)
 #define EMAC_CAM0M_MACADDR4_Pos          (16)
 #define EMAC_CAM0M_MACADDR4_Msk          (0xfful << EMAC_CAM0M_MACADDR4_Pos)
 #define EMAC_CAM0M_MACADDR5_Pos          (24)
 #define EMAC_CAM0M_MACADDR5_Msk          (0xfful << EMAC_CAM0M_MACADDR5_Pos)
 #define EMAC_CAM0L_MACADDR0_Pos          (16)
 #define EMAC_CAM0L_MACADDR0_Msk          (0xfful << EMAC_CAM0L_MACADDR0_Pos)
 #define EMAC_CAM0L_MACADDR1_Pos          (24)
 #define EMAC_CAM0L_MACADDR1_Msk          (0xfful << EMAC_CAM0L_MACADDR1_Pos)
 #define EMAC_CAM1M_MACADDR2_Pos          (0)
 #define EMAC_CAM1M_MACADDR2_Msk          (0xfful << EMAC_CAM1M_MACADDR2_Pos)
 #define EMAC_CAM1M_MACADDR3_Pos          (8)
 #define EMAC_CAM1M_MACADDR3_Msk          (0xfful << EMAC_CAM1M_MACADDR3_Pos)
 #define EMAC_CAM1M_MACADDR4_Pos          (16)
 #define EMAC_CAM1M_MACADDR4_Msk          (0xfful << EMAC_CAM1M_MACADDR4_Pos)
 #define EMAC_CAM1M_MACADDR5_Pos          (24)
 #define EMAC_CAM1M_MACADDR5_Msk          (0xfful << EMAC_CAM1M_MACADDR5_Pos)
 #define EMAC_CAM1L_MACADDR0_Pos          (16)
 #define EMAC_CAM1L_MACADDR0_Msk          (0xfful << EMAC_CAM1L_MACADDR0_Pos)
 #define EMAC_CAM1L_MACADDR1_Pos          (24)
 #define EMAC_CAM1L_MACADDR1_Msk          (0xfful << EMAC_CAM1L_MACADDR1_Pos)
 #define EMAC_CAM2M_MACADDR2_Pos          (0)
 #define EMAC_CAM2M_MACADDR2_Msk          (0xfful << EMAC_CAM2M_MACADDR2_Pos)
 #define EMAC_CAM2M_MACADDR3_Pos          (8)
 #define EMAC_CAM2M_MACADDR3_Msk          (0xfful << EMAC_CAM2M_MACADDR3_Pos)
 #define EMAC_CAM2M_MACADDR4_Pos          (16)
 #define EMAC_CAM2M_MACADDR4_Msk          (0xfful << EMAC_CAM2M_MACADDR4_Pos)
 #define EMAC_CAM2M_MACADDR5_Pos          (24)
 #define EMAC_CAM2M_MACADDR5_Msk          (0xfful << EMAC_CAM2M_MACADDR5_Pos)
 #define EMAC_CAM2L_MACADDR0_Pos          (16)
 #define EMAC_CAM2L_MACADDR0_Msk          (0xfful << EMAC_CAM2L_MACADDR0_Pos)
 #define EMAC_CAM2L_MACADDR1_Pos          (24)
 #define EMAC_CAM2L_MACADDR1_Msk          (0xfful << EMAC_CAM2L_MACADDR1_Pos)
 #define EMAC_CAM3M_MACADDR2_Pos          (0)
 #define EMAC_CAM3M_MACADDR2_Msk          (0xfful << EMAC_CAM3M_MACADDR2_Pos)
 #define EMAC_CAM3M_MACADDR3_Pos          (8)
 #define EMAC_CAM3M_MACADDR3_Msk          (0xfful << EMAC_CAM3M_MACADDR3_Pos)
 #define EMAC_CAM3M_MACADDR4_Pos          (16)
 #define EMAC_CAM3M_MACADDR4_Msk          (0xfful << EMAC_CAM3M_MACADDR4_Pos)
 #define EMAC_CAM3M_MACADDR5_Pos          (24)
 #define EMAC_CAM3M_MACADDR5_Msk          (0xfful << EMAC_CAM3M_MACADDR5_Pos)
 #define EMAC_CAM3L_MACADDR0_Pos          (16)
 #define EMAC_CAM3L_MACADDR0_Msk          (0xfful << EMAC_CAM3L_MACADDR0_Pos)
 #define EMAC_CAM3L_MACADDR1_Pos          (24)
 #define EMAC_CAM3L_MACADDR1_Msk          (0xfful << EMAC_CAM3L_MACADDR1_Pos)
 #define EMAC_CAM4M_MACADDR2_Pos          (0)
 #define EMAC_CAM4M_MACADDR2_Msk          (0xfful << EMAC_CAM4M_MACADDR2_Pos)
 #define EMAC_CAM4M_MACADDR3_Pos          (8)
 #define EMAC_CAM4M_MACADDR3_Msk          (0xfful << EMAC_CAM4M_MACADDR3_Pos)
 #define EMAC_CAM4M_MACADDR4_Pos          (16)
 #define EMAC_CAM4M_MACADDR4_Msk          (0xfful << EMAC_CAM4M_MACADDR4_Pos)
 #define EMAC_CAM4M_MACADDR5_Pos          (24)
 #define EMAC_CAM4M_MACADDR5_Msk          (0xfful << EMAC_CAM4M_MACADDR5_Pos)
 #define EMAC_CAM4L_MACADDR0_Pos          (16)
 #define EMAC_CAM4L_MACADDR0_Msk          (0xfful << EMAC_CAM4L_MACADDR0_Pos)
 #define EMAC_CAM4L_MACADDR1_Pos          (24)
 #define EMAC_CAM4L_MACADDR1_Msk          (0xfful << EMAC_CAM4L_MACADDR1_Pos)
 #define EMAC_CAM5M_MACADDR2_Pos          (0)
 #define EMAC_CAM5M_MACADDR2_Msk          (0xfful << EMAC_CAM5M_MACADDR2_Pos)
 #define EMAC_CAM5M_MACADDR3_Pos          (8)
 #define EMAC_CAM5M_MACADDR3_Msk          (0xfful << EMAC_CAM5M_MACADDR3_Pos)
 #define EMAC_CAM5M_MACADDR4_Pos          (16)
 #define EMAC_CAM5M_MACADDR4_Msk          (0xfful << EMAC_CAM5M_MACADDR4_Pos)
 #define EMAC_CAM5M_MACADDR5_Pos          (24)
 #define EMAC_CAM5M_MACADDR5_Msk          (0xfful << EMAC_CAM5M_MACADDR5_Pos)
 #define EMAC_CAM5L_MACADDR0_Pos          (16)
 #define EMAC_CAM5L_MACADDR0_Msk          (0xfful << EMAC_CAM5L_MACADDR0_Pos)
 #define EMAC_CAM5L_MACADDR1_Pos          (24)
 #define EMAC_CAM5L_MACADDR1_Msk          (0xfful << EMAC_CAM5L_MACADDR1_Pos)
 #define EMAC_CAM6M_MACADDR2_Pos          (0)
 #define EMAC_CAM6M_MACADDR2_Msk          (0xfful << EMAC_CAM6M_MACADDR2_Pos)
 #define EMAC_CAM6M_MACADDR3_Pos          (8)
 #define EMAC_CAM6M_MACADDR3_Msk          (0xfful << EMAC_CAM6M_MACADDR3_Pos)
 #define EMAC_CAM6M_MACADDR4_Pos          (16)
 #define EMAC_CAM6M_MACADDR4_Msk          (0xfful << EMAC_CAM6M_MACADDR4_Pos)
 #define EMAC_CAM6M_MACADDR5_Pos          (24)
 #define EMAC_CAM6M_MACADDR5_Msk          (0xfful << EMAC_CAM6M_MACADDR5_Pos)
 #define EMAC_CAM6L_MACADDR0_Pos          (16)
 #define EMAC_CAM6L_MACADDR0_Msk          (0xfful << EMAC_CAM6L_MACADDR0_Pos)
 #define EMAC_CAM6L_MACADDR1_Pos          (24)
 #define EMAC_CAM6L_MACADDR1_Msk          (0xfful << EMAC_CAM6L_MACADDR1_Pos)
 #define EMAC_CAM7M_MACADDR2_Pos          (0)
 #define EMAC_CAM7M_MACADDR2_Msk          (0xfful << EMAC_CAM7M_MACADDR2_Pos)
 #define EMAC_CAM7M_MACADDR3_Pos          (8)
 #define EMAC_CAM7M_MACADDR3_Msk          (0xfful << EMAC_CAM7M_MACADDR3_Pos)
 #define EMAC_CAM7M_MACADDR4_Pos          (16)
 #define EMAC_CAM7M_MACADDR4_Msk          (0xfful << EMAC_CAM7M_MACADDR4_Pos)
 #define EMAC_CAM7M_MACADDR5_Pos          (24)
 #define EMAC_CAM7M_MACADDR5_Msk          (0xfful << EMAC_CAM7M_MACADDR5_Pos)
 #define EMAC_CAM7L_MACADDR0_Pos          (16)
 #define EMAC_CAM7L_MACADDR0_Msk          (0xfful << EMAC_CAM7L_MACADDR0_Pos)
 #define EMAC_CAM7L_MACADDR1_Pos          (24)
 #define EMAC_CAM7L_MACADDR1_Msk          (0xfful << EMAC_CAM7L_MACADDR1_Pos)
 #define EMAC_CAM8M_MACADDR2_Pos          (0)
 #define EMAC_CAM8M_MACADDR2_Msk          (0xfful << EMAC_CAM8M_MACADDR2_Pos)
 #define EMAC_CAM8M_MACADDR3_Pos          (8)
 #define EMAC_CAM8M_MACADDR3_Msk          (0xfful << EMAC_CAM8M_MACADDR3_Pos)
 #define EMAC_CAM8M_MACADDR4_Pos          (16)
 #define EMAC_CAM8M_MACADDR4_Msk          (0xfful << EMAC_CAM8M_MACADDR4_Pos)
 #define EMAC_CAM8M_MACADDR5_Pos          (24)
 #define EMAC_CAM8M_MACADDR5_Msk          (0xfful << EMAC_CAM8M_MACADDR5_Pos)
 #define EMAC_CAM8L_MACADDR0_Pos          (16)
 #define EMAC_CAM8L_MACADDR0_Msk          (0xfful << EMAC_CAM8L_MACADDR0_Pos)
 #define EMAC_CAM8L_MACADDR1_Pos          (24)
 #define EMAC_CAM8L_MACADDR1_Msk          (0xfful << EMAC_CAM8L_MACADDR1_Pos)
 #define EMAC_CAM9M_MACADDR2_Pos          (0)
 #define EMAC_CAM9M_MACADDR2_Msk          (0xfful << EMAC_CAM9M_MACADDR2_Pos)
 #define EMAC_CAM9M_MACADDR3_Pos          (8)
 #define EMAC_CAM9M_MACADDR3_Msk          (0xfful << EMAC_CAM9M_MACADDR3_Pos)
 #define EMAC_CAM9M_MACADDR4_Pos          (16)
 #define EMAC_CAM9M_MACADDR4_Msk          (0xfful << EMAC_CAM9M_MACADDR4_Pos)
 #define EMAC_CAM9M_MACADDR5_Pos          (24)
 #define EMAC_CAM9M_MACADDR5_Msk          (0xfful << EMAC_CAM9M_MACADDR5_Pos)
 #define EMAC_CAM9L_MACADDR0_Pos          (16)
 #define EMAC_CAM9L_MACADDR0_Msk          (0xfful << EMAC_CAM9L_MACADDR0_Pos)
 #define EMAC_CAM9L_MACADDR1_Pos          (24)
 #define EMAC_CAM9L_MACADDR1_Msk          (0xfful << EMAC_CAM9L_MACADDR1_Pos)
 #define EMAC_CAM10M_MACADDR2_Pos         (0)
 #define EMAC_CAM10M_MACADDR2_Msk         (0xfful << EMAC_CAM10M_MACADDR2_Pos)
 #define EMAC_CAM10M_MACADDR3_Pos         (8)
 #define EMAC_CAM10M_MACADDR3_Msk         (0xfful << EMAC_CAM10M_MACADDR3_Pos)
 #define EMAC_CAM10M_MACADDR4_Pos         (16)
 #define EMAC_CAM10M_MACADDR4_Msk         (0xfful << EMAC_CAM10M_MACADDR4_Pos)
 #define EMAC_CAM10M_MACADDR5_Pos         (24)
 #define EMAC_CAM10M_MACADDR5_Msk         (0xfful << EMAC_CAM10M_MACADDR5_Pos)
 #define EMAC_CAM10L_MACADDR0_Pos         (16)
 #define EMAC_CAM10L_MACADDR0_Msk         (0xfful << EMAC_CAM10L_MACADDR0_Pos)
 #define EMAC_CAM10L_MACADDR1_Pos         (24)
 #define EMAC_CAM10L_MACADDR1_Msk         (0xfful << EMAC_CAM10L_MACADDR1_Pos)
 #define EMAC_CAM11M_MACADDR2_Pos         (0)
 #define EMAC_CAM11M_MACADDR2_Msk         (0xfful << EMAC_CAM11M_MACADDR2_Pos)
 #define EMAC_CAM11M_MACADDR3_Pos         (8)
 #define EMAC_CAM11M_MACADDR3_Msk         (0xfful << EMAC_CAM11M_MACADDR3_Pos)
 #define EMAC_CAM11M_MACADDR4_Pos         (16)
 #define EMAC_CAM11M_MACADDR4_Msk         (0xfful << EMAC_CAM11M_MACADDR4_Pos)
 #define EMAC_CAM11M_MACADDR5_Pos         (24)
 #define EMAC_CAM11M_MACADDR5_Msk         (0xfful << EMAC_CAM11M_MACADDR5_Pos)
 #define EMAC_CAM11L_MACADDR0_Pos         (16)
 #define EMAC_CAM11L_MACADDR0_Msk         (0xfful << EMAC_CAM11L_MACADDR0_Pos)
 #define EMAC_CAM11L_MACADDR1_Pos         (24)
 #define EMAC_CAM11L_MACADDR1_Msk         (0xfful << EMAC_CAM11L_MACADDR1_Pos)
 #define EMAC_CAM12M_MACADDR2_Pos         (0)
 #define EMAC_CAM12M_MACADDR2_Msk         (0xfful << EMAC_CAM12M_MACADDR2_Pos)
 #define EMAC_CAM12M_MACADDR3_Pos         (8)
 #define EMAC_CAM12M_MACADDR3_Msk         (0xfful << EMAC_CAM12M_MACADDR3_Pos)
 #define EMAC_CAM12M_MACADDR4_Pos         (16)
 #define EMAC_CAM12M_MACADDR4_Msk         (0xfful << EMAC_CAM12M_MACADDR4_Pos)
 #define EMAC_CAM12M_MACADDR5_Pos         (24)
 #define EMAC_CAM12M_MACADDR5_Msk         (0xfful << EMAC_CAM12M_MACADDR5_Pos)
 #define EMAC_CAM12L_MACADDR0_Pos         (16)
 #define EMAC_CAM12L_MACADDR0_Msk         (0xfful << EMAC_CAM12L_MACADDR0_Pos)
 #define EMAC_CAM12L_MACADDR1_Pos         (24)
 #define EMAC_CAM12L_MACADDR1_Msk         (0xfful << EMAC_CAM12L_MACADDR1_Pos)
 #define EMAC_CAM13M_MACADDR2_Pos         (0)
 #define EMAC_CAM13M_MACADDR2_Msk         (0xfful << EMAC_CAM13M_MACADDR2_Pos)
 #define EMAC_CAM13M_MACADDR3_Pos         (8)
 #define EMAC_CAM13M_MACADDR3_Msk         (0xfful << EMAC_CAM13M_MACADDR3_Pos)
 #define EMAC_CAM13M_MACADDR4_Pos         (16)
 #define EMAC_CAM13M_MACADDR4_Msk         (0xfful << EMAC_CAM13M_MACADDR4_Pos)
 #define EMAC_CAM13M_MACADDR5_Pos         (24)
 #define EMAC_CAM13M_MACADDR5_Msk         (0xfful << EMAC_CAM13M_MACADDR5_Pos)
 #define EMAC_CAM13L_MACADDR0_Pos         (16)
 #define EMAC_CAM13L_MACADDR0_Msk         (0xfful << EMAC_CAM13L_MACADDR0_Pos)
 #define EMAC_CAM13L_MACADDR1_Pos         (24)
 #define EMAC_CAM13L_MACADDR1_Msk         (0xfful << EMAC_CAM13L_MACADDR1_Pos)
 #define EMAC_CAM14M_MACADDR2_Pos         (0)
 #define EMAC_CAM14M_MACADDR2_Msk         (0xfful << EMAC_CAM14M_MACADDR2_Pos)
 #define EMAC_CAM14M_MACADDR3_Pos         (8)
 #define EMAC_CAM14M_MACADDR3_Msk         (0xfful << EMAC_CAM14M_MACADDR3_Pos)
 #define EMAC_CAM14M_MACADDR4_Pos         (16)
 #define EMAC_CAM14M_MACADDR4_Msk         (0xfful << EMAC_CAM14M_MACADDR4_Pos)
 #define EMAC_CAM14M_MACADDR5_Pos         (24)
 #define EMAC_CAM14M_MACADDR5_Msk         (0xfful << EMAC_CAM14M_MACADDR5_Pos)
 #define EMAC_CAM14L_MACADDR0_Pos         (16)
 #define EMAC_CAM14L_MACADDR0_Msk         (0xfful << EMAC_CAM14L_MACADDR0_Pos)
 #define EMAC_CAM14L_MACADDR1_Pos         (24)
 #define EMAC_CAM14L_MACADDR1_Msk         (0xfful << EMAC_CAM14L_MACADDR1_Pos)
 #define EMAC_CAM15MSB_OPCODE_Pos         (0)
 #define EMAC_CAM15MSB_OPCODE_Msk         (0xfffful << EMAC_CAM15MSB_OPCODE_Pos)
 #define EMAC_CAM15MSB_LENGTH_Pos         (16)
 #define EMAC_CAM15MSB_LENGTH_Msk         (0xfffful << EMAC_CAM15MSB_LENGTH_Pos)
 #define EMAC_CAM15LSB_OPERAND_Pos        (24)
 #define EMAC_CAM15LSB_OPERAND_Msk        (0xfful << EMAC_CAM15LSB_OPERAND_Pos)
 #define EMAC_TXDSA_TXDSA_Pos             (0)
 #define EMAC_TXDSA_TXDSA_Msk             (0xfffffffful << EMAC_TXDSA_TXDSA_Pos)
 #define EMAC_RXDSA_RXDSA_Pos             (0)
 #define EMAC_RXDSA_RXDSA_Msk             (0xfffffffful << EMAC_RXDSA_RXDSA_Pos)
 #define EMAC_CTL_RXON_Pos                (0)
 #define EMAC_CTL_RXON_Msk                (0x1ul << EMAC_CTL_RXON_Pos)
 #define EMAC_CTL_ALP_Pos                 (1)
 #define EMAC_CTL_ALP_Msk                 (0x1ul << EMAC_CTL_ALP_Pos)
 #define EMAC_CTL_ARP_Pos                 (2)
 #define EMAC_CTL_ARP_Msk                 (0x1ul << EMAC_CTL_ARP_Pos)
 #define EMAC_CTL_ACP_Pos                 (3)
 #define EMAC_CTL_ACP_Msk                 (0x1ul << EMAC_CTL_ACP_Pos)
 #define EMAC_CTL_AEP_Pos                 (4)
 #define EMAC_CTL_AEP_Msk                 (0x1ul << EMAC_CTL_AEP_Pos)
 #define EMAC_CTL_STRIPCRC_Pos            (5)
 #define EMAC_CTL_STRIPCRC_Msk            (0x1ul << EMAC_CTL_STRIPCRC_Pos)
 #define EMAC_CTL_WOLEN_Pos               (6)
 #define EMAC_CTL_WOLEN_Msk               (0x1ul << EMAC_CTL_WOLEN_Pos)
 #define EMAC_CTL_TXON_Pos                (8)
 #define EMAC_CTL_TXON_Msk                (0x1ul << EMAC_CTL_TXON_Pos)
 #define EMAC_CTL_NODEF_Pos               (9)
 #define EMAC_CTL_NODEF_Msk               (0x1ul << EMAC_CTL_NODEF_Pos)
 #define EMAC_CTL_SDPZ_Pos                (16)
 #define EMAC_CTL_SDPZ_Msk                (0x1ul << EMAC_CTL_SDPZ_Pos)
 #define EMAC_CTL_SQECHKEN_Pos            (17)
 #define EMAC_CTL_SQECHKEN_Msk            (0x1ul << EMAC_CTL_SQECHKEN_Pos)
 #define EMAC_CTL_FUDUP_Pos               (18)
 #define EMAC_CTL_FUDUP_Msk               (0x1ul << EMAC_CTL_FUDUP_Pos)
 #define EMAC_CTL_RMIIRXCTL_Pos           (19)
 #define EMAC_CTL_RMIIRXCTL_Msk           (0x1ul << EMAC_CTL_RMIIRXCTL_Pos)
 #define EMAC_CTL_OPMODE_Pos              (20)
 #define EMAC_CTL_OPMODE_Msk              (0x1ul << EMAC_CTL_OPMODE_Pos)
 #define EMAC_CTL_RMIIEN_Pos              (22)
 #define EMAC_CTL_RMIIEN_Msk              (0x1ul << EMAC_CTL_RMIIEN_Pos)
 #define EMAC_CTL_RST_Pos                 (24)
 #define EMAC_CTL_RST_Msk                 (0x1ul << EMAC_CTL_RST_Pos)
 #define EMAC_MIIMDAT_DATA_Pos            (0)
 #define EMAC_MIIMDAT_DATA_Msk            (0xfffful << EMAC_MIIMDAT_DATA_Pos)
 #define EMAC_MIIMCTL_PHYREG_Pos          (0)
 #define EMAC_MIIMCTL_PHYREG_Msk          (0x1ful << EMAC_MIIMCTL_PHYREG_Pos)
 #define EMAC_MIIMCTL_PHYADDR_Pos         (8)
 #define EMAC_MIIMCTL_PHYADDR_Msk         (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos)
 #define EMAC_MIIMCTL_WRITE_Pos           (16)
 #define EMAC_MIIMCTL_WRITE_Msk           (0x1ul << EMAC_MIIMCTL_WRITE_Pos)
 #define EMAC_MIIMCTL_BUSY_Pos            (17)
 #define EMAC_MIIMCTL_BUSY_Msk            (0x1ul << EMAC_MIIMCTL_BUSY_Pos)
 #define EMAC_MIIMCTL_PREAMSP_Pos         (18)
 #define EMAC_MIIMCTL_PREAMSP_Msk         (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos)
 #define EMAC_MIIMCTL_MDCON_Pos           (19)
 #define EMAC_MIIMCTL_MDCON_Msk           (0x1ul << EMAC_MIIMCTL_MDCON_Pos)
 #define EMAC_FIFOCTL_RXFIFOTH_Pos        (0)
 #define EMAC_FIFOCTL_RXFIFOTH_Msk        (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos)
 #define EMAC_FIFOCTL_TXFIFOTH_Pos        (8)
 #define EMAC_FIFOCTL_TXFIFOTH_Msk        (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos)
 #define EMAC_FIFOCTL_BURSTLEN_Pos        (20)
 #define EMAC_FIFOCTL_BURSTLEN_Msk        (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos)
 #define EMAC_TXST_TXST_Pos               (0)
 #define EMAC_TXST_TXST_Msk               (0xfffffffful << EMAC_TXST_TXST_Pos)
 #define EMAC_RXST_RXST_Pos               (0)
 #define EMAC_RXST_RXST_Msk               (0xfffffffful << EMAC_RXST_RXST_Pos)
 #define EMAC_MRFL_MRFL_Pos               (0)
 #define EMAC_MRFL_MRFL_Msk               (0xfffful << EMAC_MRFL_MRFL_Pos)
 #define EMAC_INTEN_RXIEN_Pos             (0)
 #define EMAC_INTEN_RXIEN_Msk             (0x1ul << EMAC_INTEN_RXIEN_Pos)
 #define EMAC_INTEN_CRCEIEN_Pos           (1)
 #define EMAC_INTEN_CRCEIEN_Msk           (0x1ul << EMAC_INTEN_CRCEIEN_Pos)
 #define EMAC_INTEN_RXOVIEN_Pos           (2)
 #define EMAC_INTEN_RXOVIEN_Msk           (0x1ul << EMAC_INTEN_RXOVIEN_Pos)
 #define EMAC_INTEN_LPIEN_Pos             (3)
 #define EMAC_INTEN_LPIEN_Msk             (0x1ul << EMAC_INTEN_LPIEN_Pos)
 #define EMAC_INTEN_RXGDIEN_Pos           (4)
 #define EMAC_INTEN_RXGDIEN_Msk           (0x1ul << EMAC_INTEN_RXGDIEN_Pos)
 #define EMAC_INTEN_ALIEIEN_Pos           (5)
 #define EMAC_INTEN_ALIEIEN_Msk           (0x1ul << EMAC_INTEN_ALIEIEN_Pos)
 #define EMAC_INTEN_RPIEN_Pos             (6)
 #define EMAC_INTEN_RPIEN_Msk             (0x1ul << EMAC_INTEN_RPIEN_Pos)
 #define EMAC_INTEN_MPCOVIEN_Pos          (7)
 #define EMAC_INTEN_MPCOVIEN_Msk          (0x1ul << EMAC_INTEN_MPCOVIEN_Pos)
 #define EMAC_INTEN_MFLEIEN_Pos           (8)
 #define EMAC_INTEN_MFLEIEN_Msk           (0x1ul << EMAC_INTEN_MFLEIEN_Pos)
 #define EMAC_INTEN_DENIEN_Pos            (9)
 #define EMAC_INTEN_DENIEN_Msk            (0x1ul << EMAC_INTEN_DENIEN_Pos)
 #define EMAC_INTEN_RDUIEN_Pos            (10)
 #define EMAC_INTEN_RDUIEN_Msk            (0x1ul << EMAC_INTEN_RDUIEN_Pos)
 #define EMAC_INTEN_RXBEIEN_Pos           (11)
 #define EMAC_INTEN_RXBEIEN_Msk           (0x1ul << EMAC_INTEN_RXBEIEN_Pos)
 #define EMAC_INTEN_CFRIEN_Pos            (14)
 #define EMAC_INTEN_CFRIEN_Msk            (0x1ul << EMAC_INTEN_CFRIEN_Pos)
 #define EMAC_INTEN_WOLIEN_Pos            (15)
 #define EMAC_INTEN_WOLIEN_Msk            (0x1ul << EMAC_INTEN_WOLIEN_Pos)
 #define EMAC_INTEN_TXIEN_Pos             (16)
 #define EMAC_INTEN_TXIEN_Msk             (0x1ul << EMAC_INTEN_TXIEN_Pos)
 #define EMAC_INTEN_TXUDIEN_Pos           (17)
 #define EMAC_INTEN_TXUDIEN_Msk           (0x1ul << EMAC_INTEN_TXUDIEN_Pos)
 #define EMAC_INTEN_TXCPIEN_Pos           (18)
 #define EMAC_INTEN_TXCPIEN_Msk           (0x1ul << EMAC_INTEN_TXCPIEN_Pos)
 #define EMAC_INTEN_EXDEFIEN_Pos          (19)
 #define EMAC_INTEN_EXDEFIEN_Msk          (0x1ul << EMAC_INTEN_EXDEFIEN_Pos)
 #define EMAC_INTEN_NCSIEN_Pos            (20)
 #define EMAC_INTEN_NCSIEN_Msk            (0x1ul << EMAC_INTEN_NCSIEN_Pos)
 #define EMAC_INTEN_TXABTIEN_Pos          (21)
 #define EMAC_INTEN_TXABTIEN_Msk          (0x1ul << EMAC_INTEN_TXABTIEN_Pos)
 #define EMAC_INTEN_LCIEN_Pos             (22)
 #define EMAC_INTEN_LCIEN_Msk             (0x1ul << EMAC_INTEN_LCIEN_Pos)
 #define EMAC_INTEN_TDUIEN_Pos            (23)
 #define EMAC_INTEN_TDUIEN_Msk            (0x1ul << EMAC_INTEN_TDUIEN_Pos)
 #define EMAC_INTEN_TXBEIEN_Pos           (24)
 #define EMAC_INTEN_TXBEIEN_Msk           (0x1ul << EMAC_INTEN_TXBEIEN_Pos)
 #define EMAC_INTEN_TSALMIEN_Pos          (28)
 #define EMAC_INTEN_TSALMIEN_Msk          (0x1ul << EMAC_INTEN_TSALMIEN_Pos)
 #define EMAC_INTSTS_RXIF_Pos             (0)
 #define EMAC_INTSTS_RXIF_Msk             (0x1ul << EMAC_INTSTS_RXIF_Pos)
 #define EMAC_INTSTS_CRCEIF_Pos           (1)
 #define EMAC_INTSTS_CRCEIF_Msk           (0x1ul << EMAC_INTSTS_CRCEIF_Pos)
 #define EMAC_INTSTS_RXOVIF_Pos           (2)
 #define EMAC_INTSTS_RXOVIF_Msk           (0x1ul << EMAC_INTSTS_RXOVIF_Pos)
 #define EMAC_INTSTS_LPIF_Pos             (3)
 #define EMAC_INTSTS_LPIF_Msk             (0x1ul << EMAC_INTSTS_LPIF_Pos)
 #define EMAC_INTSTS_RXGDIF_Pos           (4)
 #define EMAC_INTSTS_RXGDIF_Msk           (0x1ul << EMAC_INTSTS_RXGDIF_Pos)
 #define EMAC_INTSTS_ALIEIF_Pos           (5)
 #define EMAC_INTSTS_ALIEIF_Msk           (0x1ul << EMAC_INTSTS_ALIEIF_Pos)
 #define EMAC_INTSTS_RPIF_Pos             (6)
 #define EMAC_INTSTS_RPIF_Msk             (0x1ul << EMAC_INTSTS_RPIF_Pos)
 #define EMAC_INTSTS_MPCOVIF_Pos          (7)
 #define EMAC_INTSTS_MPCOVIF_Msk          (0x1ul << EMAC_INTSTS_MPCOVIF_Pos)
 #define EMAC_INTSTS_MFLEIF_Pos           (8)
 #define EMAC_INTSTS_MFLEIF_Msk           (0x1ul << EMAC_INTSTS_MFLEIF_Pos)
 #define EMAC_INTSTS_DENIF_Pos            (9)
 #define EMAC_INTSTS_DENIF_Msk            (0x1ul << EMAC_INTSTS_DENIF_Pos)
 #define EMAC_INTSTS_RDUIF_Pos            (10)
 #define EMAC_INTSTS_RDUIF_Msk            (0x1ul << EMAC_INTSTS_RDUIF_Pos)
 #define EMAC_INTSTS_RXBEIF_Pos           (11)
 #define EMAC_INTSTS_RXBEIF_Msk           (0x1ul << EMAC_INTSTS_RXBEIF_Pos)
 #define EMAC_INTSTS_CFRIF_Pos            (14)
 #define EMAC_INTSTS_CFRIF_Msk            (0x1ul << EMAC_INTSTS_CFRIF_Pos)
 #define EMAC_INTSTS_WOLIF_Pos            (15)
 #define EMAC_INTSTS_WOLIF_Msk            (0x1ul << EMAC_INTSTS_WOLIF_Pos)
 #define EMAC_INTSTS_TXIF_Pos             (16)
 #define EMAC_INTSTS_TXIF_Msk             (0x1ul << EMAC_INTSTS_TXIF_Pos)
 #define EMAC_INTSTS_TXUDIF_Pos           (17)
 #define EMAC_INTSTS_TXUDIF_Msk           (0x1ul << EMAC_INTSTS_TXUDIF_Pos)
 #define EMAC_INTSTS_TXCPIF_Pos           (18)
 #define EMAC_INTSTS_TXCPIF_Msk           (0x1ul << EMAC_INTSTS_TXCPIF_Pos)
 #define EMAC_INTSTS_EXDEFIF_Pos          (19)
 #define EMAC_INTSTS_EXDEFIF_Msk          (0x1ul << EMAC_INTSTS_EXDEFIF_Pos)
 #define EMAC_INTSTS_NCSIF_Pos            (20)
 #define EMAC_INTSTS_NCSIF_Msk            (0x1ul << EMAC_INTSTS_NCSIF_Pos)
 #define EMAC_INTSTS_TXABTIF_Pos          (21)
 #define EMAC_INTSTS_TXABTIF_Msk          (0x1ul << EMAC_INTSTS_TXABTIF_Pos)
 #define EMAC_INTSTS_LCIF_Pos             (22)
 #define EMAC_INTSTS_LCIF_Msk             (0x1ul << EMAC_INTSTS_LCIF_Pos)
 #define EMAC_INTSTS_TDUIF_Pos            (23)
 #define EMAC_INTSTS_TDUIF_Msk            (0x1ul << EMAC_INTSTS_TDUIF_Pos)
 #define EMAC_INTSTS_TXBEIF_Pos           (24)
 #define EMAC_INTSTS_TXBEIF_Msk           (0x1ul << EMAC_INTSTS_TXBEIF_Pos)
 #define EMAC_INTSTS_TSALMIF_Pos          (28)
 #define EMAC_INTSTS_TSALMIF_Msk          (0x1ul << EMAC_INTSTS_TSALMIF_Pos)
 #define EMAC_GENSTS_CFR_Pos              (0)
 #define EMAC_GENSTS_CFR_Msk              (0x1ul << EMAC_GENSTS_CFR_Pos)
 #define EMAC_GENSTS_RXHALT_Pos           (1)
 #define EMAC_GENSTS_RXHALT_Msk           (0x1ul << EMAC_GENSTS_RXHALT_Pos)
 #define EMAC_GENSTS_RXFFULL_Pos          (2)
 #define EMAC_GENSTS_RXFFULL_Msk          (0x1ul << EMAC_GENSTS_RXFFULL_Pos)
 #define EMAC_GENSTS_COLCNT_Pos           (4)
 #define EMAC_GENSTS_COLCNT_Msk           (0xful << EMAC_GENSTS_COLCNT_Pos)
 #define EMAC_GENSTS_DEF_Pos              (8)
 #define EMAC_GENSTS_DEF_Msk              (0x1ul << EMAC_GENSTS_DEF_Pos)
 #define EMAC_GENSTS_TXPAUSED_Pos         (9)
 #define EMAC_GENSTS_TXPAUSED_Msk         (0x1ul << EMAC_GENSTS_TXPAUSED_Pos)
 #define EMAC_GENSTS_SQE_Pos              (10)
 #define EMAC_GENSTS_SQE_Msk              (0x1ul << EMAC_GENSTS_SQE_Pos)
 #define EMAC_GENSTS_TXHALT_Pos           (11)
 #define EMAC_GENSTS_TXHALT_Msk           (0x1ul << EMAC_GENSTS_TXHALT_Pos)
 #define EMAC_GENSTS_RPSTS_Pos            (12)
 #define EMAC_GENSTS_RPSTS_Msk            (0x1ul << EMAC_GENSTS_RPSTS_Pos)
 #define EMAC_MPCNT_MPCNT_Pos             (0)
 #define EMAC_MPCNT_MPCNT_Msk             (0xfffful << EMAC_MPCNT_MPCNT_Pos)
 #define EMAC_RPCNT_RPCNT_Pos             (0)
 #define EMAC_RPCNT_RPCNT_Msk             (0xfffful << EMAC_RPCNT_RPCNT_Pos)
 #define EMAC_FRSTS_RXFLT_Pos             (0)
 #define EMAC_FRSTS_RXFLT_Msk             (0xfffful << EMAC_FRSTS_RXFLT_Pos)
 #define EMAC_CTXDSA_CTXDSA_Pos           (0)
 #define EMAC_CTXDSA_CTXDSA_Msk           (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos)
 #define EMAC_CTXBSA_CTXBSA_Pos           (0)
 #define EMAC_CTXBSA_CTXBSA_Msk           (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos)
 #define EMAC_CRXDSA_CRXDSA_Pos           (0)
 #define EMAC_CRXDSA_CRXDSA_Msk           (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos)
 #define EMAC_CRXBSA_CRXBSA_Pos           (0)
 #define EMAC_CRXBSA_CRXBSA_Msk           (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos)
 #define EMAC_TSCTL_TSEN_Pos              (0)
 #define EMAC_TSCTL_TSEN_Msk              (0x1ul << EMAC_TSCTL_TSEN_Pos)
 #define EMAC_TSCTL_TSIEN_Pos             (1)
 #define EMAC_TSCTL_TSIEN_Msk             (0x1ul << EMAC_TSCTL_TSIEN_Pos)
 #define EMAC_TSCTL_TSMODE_Pos            (2)
 #define EMAC_TSCTL_TSMODE_Msk            (0x1ul << EMAC_TSCTL_TSMODE_Pos)
 #define EMAC_TSCTL_TSUPDATE_Pos          (3)
 #define EMAC_TSCTL_TSUPDATE_Msk          (0x1ul << EMAC_TSCTL_TSUPDATE_Pos)
 #define EMAC_TSCTL_TSALMEN_Pos           (5)
 #define EMAC_TSCTL_TSALMEN_Msk           (0x1ul << EMAC_TSCTL_TSALMEN_Pos)
 #define EMAC_TSSEC_SEC_Pos               (0)
 #define EMAC_TSSEC_SEC_Msk               (0xfffffffful << EMAC_TSSEC_SEC_Pos)
 #define EMAC_TSSUBSEC_SUBSEC_Pos         (0)
 #define EMAC_TSSUBSEC_SUBSEC_Msk         (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos)
 #define EMAC_TSINC_CNTINC_Pos            (0)
 #define EMAC_TSINC_CNTINC_Msk            (0xfful << EMAC_TSINC_CNTINC_Pos)
 #define EMAC_TSADDEND_ADDEND_Pos         (0)
 #define EMAC_TSADDEND_ADDEND_Msk         (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos)
 #define EMAC_UPDSEC_SEC_Pos              (0)
 #define EMAC_UPDSEC_SEC_Msk              (0xfffffffful << EMAC_UPDSEC_SEC_Pos)
 #define EMAC_UPDSUBSEC_SUBSEC_Pos        (0)
 #define EMAC_UPDSUBSEC_SUBSEC_Msk        (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos)
 #define EMAC_ALMSEC_SEC_Pos              (0)
 #define EMAC_ALMSEC_SEC_Msk              (0xfffffffful << EMAC_ALMSEC_SEC_Pos)
 #define EMAC_ALMSUBSEC_SUBSEC_Pos        (0)
 #define EMAC_ALMSUBSEC_SUBSEC_Msk        (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos)        /* EMAC_CONST */
  /* end of EMAC register group */ /* end of REGISTER group */

 #if defined ( __CC_ARM   )
 #pragma no_anon_unions
 #endif

 #endif /* __EMAC_REG_H__ */
EMAC_T::CTL
__IO uint32_t CTL
Definition: emac_reg.h:3109

EMAC_T::CAM12M
__IO uint32_t CAM12M
Definition: emac_reg.h:3099

EMAC_T::CAM13M
__IO uint32_t CAM13M
Definition: emac_reg.h:3101

EMAC_T::CAM11L
__IO uint32_t CAM11L
Definition: emac_reg.h:3098

EMAC_T::CAMCTL
__IO uint32_t CAMCTL
Definition: emac_reg.h:3073

EMAC_T::CAM0L
__IO uint32_t CAM0L
Definition: emac_reg.h:3076

EMAC_T::CAM10M
__IO uint32_t CAM10M
Definition: emac_reg.h:3095

EMAC_T::CAM6L
__IO uint32_t CAM6L
Definition: emac_reg.h:3088

EMAC_T::MRFL
__IO uint32_t MRFL
Definition: emac_reg.h:3115

EMAC_T::CAM9M
__IO uint32_t CAM9M
Definition: emac_reg.h:3093

EMAC_T::CAM11M
__IO uint32_t CAM11M
Definition: emac_reg.h:3097

EMAC_T::INTSTS
__IO uint32_t INTSTS
Definition: emac_reg.h:3117

EMAC_T::CAM3M
__IO uint32_t CAM3M
Definition: emac_reg.h:3081

EMAC_T::CRXDSA
__I uint32_t CRXDSA
Definition: emac_reg.h:3127

EMAC_T::RPCNT
__I uint32_t RPCNT
Definition: emac_reg.h:3120

EMAC_T::CAM9L
__IO uint32_t CAM9L
Definition: emac_reg.h:3094

EMAC_T::CAM3L
__IO uint32_t CAM3L
Definition: emac_reg.h:3082

EMAC_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: emac_reg.h:3112

EMAC_T::ALMSEC
__IO uint32_t ALMSEC
Definition: emac_reg.h:3142

EMAC_T::CAM0M
__IO uint32_t CAM0M
Definition: emac_reg.h:3075

EMAC_T::ALMSUBSEC
__IO uint32_t ALMSUBSEC
Definition: emac_reg.h:3143

EMAC_T::MIIMCTL
__IO uint32_t MIIMCTL
Definition: emac_reg.h:3111

EMAC_T::CAM2M
__IO uint32_t CAM2M
Definition: emac_reg.h:3079

EMAC_T::TSADDEND
__IO uint32_t TSADDEND
Definition: emac_reg.h:3139

EMAC_T::RXDSA
__IO uint32_t RXDSA
Definition: emac_reg.h:3108

EMAC_T::CAM8M
__IO uint32_t CAM8M
Definition: emac_reg.h:3091

EMAC_T::CAM15LSB
__IO uint32_t CAM15LSB
Definition: emac_reg.h:3106

EMAC_T::CAM14M
__IO uint32_t CAM14M
Definition: emac_reg.h:3103

EMAC_T::CTXBSA
__I uint32_t CTXBSA
Definition: emac_reg.h:3126

EMAC_T::UPDSEC
__IO uint32_t UPDSEC
Definition: emac_reg.h:3140

EMAC_T::TSSUBSEC
__I uint32_t TSSUBSEC
Definition: emac_reg.h:3137

EMAC_T::RXST
__O uint32_t RXST
Definition: emac_reg.h:3114

EMAC_T::MPCNT
__IO uint32_t MPCNT
Definition: emac_reg.h:3119

EMAC_T::INTEN
__IO uint32_t INTEN
Definition: emac_reg.h:3116

EMAC_T::CAM12L
__IO uint32_t CAM12L
Definition: emac_reg.h:3100

EMAC_T::UPDSUBSEC
__IO uint32_t UPDSUBSEC
Definition: emac_reg.h:3141

EMAC_T::CAM8L
__IO uint32_t CAM8L
Definition: emac_reg.h:3092

EMAC_T::CAM4L
__IO uint32_t CAM4L
Definition: emac_reg.h:3084

EMAC_T::CAM4M
__IO uint32_t CAM4M
Definition: emac_reg.h:3083

EMAC_T::CAM2L
__IO uint32_t CAM2L
Definition: emac_reg.h:3080

EMAC_T::TXST
__O uint32_t TXST
Definition: emac_reg.h:3113

EMAC_T::CAM5M
__IO uint32_t CAM5M
Definition: emac_reg.h:3085

EMAC_T::CAM10L
__IO uint32_t CAM10L
Definition: emac_reg.h:3096

EMAC_T::CRXBSA
__I uint32_t CRXBSA
Definition: emac_reg.h:3128

EMAC_T::CAM13L
__IO uint32_t CAM13L
Definition: emac_reg.h:3102

EMAC_T::CAM14L
__IO uint32_t CAM14L
Definition: emac_reg.h:3104

EMAC_T::MIIMDAT
__IO uint32_t MIIMDAT
Definition: emac_reg.h:3110

EMAC_T::TSSEC
__I uint32_t TSSEC
Definition: emac_reg.h:3136

EMAC_T::CAM5L
__IO uint32_t CAM5L
Definition: emac_reg.h:3086

EMAC_T::TSINC
__IO uint32_t TSINC
Definition: emac_reg.h:3138

EMAC_T::TXDSA
__IO uint32_t TXDSA
Definition: emac_reg.h:3107

EMAC_T::FRSTS
__IO uint32_t FRSTS
Definition: emac_reg.h:3124

EMAC_T::GENSTS
__IO uint32_t GENSTS
Definition: emac_reg.h:3118

EMAC_T::CAM7M
__IO uint32_t CAM7M
Definition: emac_reg.h:3089

EMAC_T::CTXDSA
__I uint32_t CTXDSA
Definition: emac_reg.h:3125

EMAC_T::CAM7L
__IO uint32_t CAM7L
Definition: emac_reg.h:3090

EMAC_T::CAM1L
__IO uint32_t CAM1L
Definition: emac_reg.h:3078

EMAC_T::CAM15MSB
__IO uint32_t CAM15MSB
Definition: emac_reg.h:3105

EMAC_T::CAMEN
__IO uint32_t CAMEN
Definition: emac_reg.h:3074

EMAC_T::CAM6M
__IO uint32_t CAM6M
Definition: emac_reg.h:3087

EMAC_T
Definition: emac_reg.h:26

EMAC_T::TSCTL
__IO uint32_t TSCTL
Definition: emac_reg.h:3132

EMAC_T::CAM1M
__IO uint32_t CAM1M
Definition: emac_reg.h:3077