Document/html/bpwm__reg_8h_source.html

 /**************************************************************************/
 #ifndef __BPWM_REG_H__
 #define __BPWM_REG_H__

 #if defined ( __CC_ARM   )
 #pragma anon_unions
 #endif

 typedef struct
 {
     __IO uint32_t RCAPDAT;
     __IO uint32_t FCAPDAT;
 } BCAPDAT_T;

 typedef struct
 {


     __IO uint32_t CTL0;
     __IO uint32_t CTL1;
     __I  uint32_t RESERVE0[2];
     __IO uint32_t CLKSRC;
     __IO uint32_t CLKPSC;
     __I  uint32_t RESERVE1[2];
     __IO uint32_t CNTEN;
     __IO uint32_t CNTCLR;
     __I  uint32_t RESERVE2[2];
     __IO uint32_t PERIOD;
     __I  uint32_t RESERVE3[7];
     __IO uint32_t CMPDAT[6];
     __I  uint32_t RESERVE4[10];
     __I  uint32_t CNT;
     __I  uint32_t RESERVE5[7];
     __IO uint32_t WGCTL0;
     __IO uint32_t WGCTL1;
     __IO uint32_t MSKEN;
     __IO uint32_t MSK;
     __I  uint32_t RESERVE6[5];
     __IO uint32_t POLCTL;
     __IO uint32_t POEN;
     __I  uint32_t RESERVE7[1];
     __IO uint32_t INTEN;
     __I  uint32_t RESERVE8[1];
     __IO uint32_t INTSTS;
     __I  uint32_t RESERVE9[3];
     __IO uint32_t EADCTS0;
     __IO uint32_t EADCTS1;
     __I  uint32_t RESERVE10[4];
     __IO uint32_t SSCTL;
     __O  uint32_t SSTRG;
     __I  uint32_t RESERVE11[2];
     __IO uint32_t STATUS;
     __I  uint32_t RESERVE12[55];
     __IO uint32_t CAPINEN;
     __IO uint32_t CAPCTL;
     __I  uint32_t CAPSTS;
     BCAPDAT_T CAPDAT[6];
     __I  uint32_t RESERVE13[5];
     __IO uint32_t CAPIEN;
     __IO uint32_t CAPIF;
     __I  uint32_t RESERVE14[43];
     __I  uint32_t PBUF;
     __I  uint32_t RESERVE15[5];
     __I  uint32_t CMPBUF[6];
 } BPWM_T;

 #define BPWM_CTL0_CTRLD0_Pos             (0)
 #define BPWM_CTL0_CTRLD0_Msk             (0x1ul << BPWM_CTL0_CTRLD0_Pos)
 #define BPWM_CTL0_CTRLD1_Pos             (1)
 #define BPWM_CTL0_CTRLD1_Msk             (0x1ul << BPWM_CTL0_CTRLD1_Pos)
 #define BPWM_CTL0_CTRLD2_Pos             (2)
 #define BPWM_CTL0_CTRLD2_Msk             (0x1ul << BPWM_CTL0_CTRLD2_Pos)
 #define BPWM_CTL0_CTRLD3_Pos             (3)
 #define BPWM_CTL0_CTRLD3_Msk             (0x1ul << BPWM_CTL0_CTRLD3_Pos)
 #define BPWM_CTL0_CTRLD4_Pos             (4)
 #define BPWM_CTL0_CTRLD4_Msk             (0x1ul << BPWM_CTL0_CTRLD4_Pos)
 #define BPWM_CTL0_CTRLD5_Pos             (5)
 #define BPWM_CTL0_CTRLD5_Msk             (0x1ul << BPWM_CTL0_CTRLD5_Pos)
 #define BPWM_CTL0_IMMLDEN0_Pos           (16)
 #define BPWM_CTL0_IMMLDEN0_Msk           (0x1ul << BPWM_CTL0_IMMLDEN0_Pos)
 #define BPWM_CTL0_IMMLDEN1_Pos           (17)
 #define BPWM_CTL0_IMMLDEN1_Msk           (0x1ul << BPWM_CTL0_IMMLDEN1_Pos)
 #define BPWM_CTL0_IMMLDEN2_Pos           (18)
 #define BPWM_CTL0_IMMLDEN2_Msk           (0x1ul << BPWM_CTL0_IMMLDEN2_Pos)
 #define BPWM_CTL0_IMMLDEN3_Pos           (19)
 #define BPWM_CTL0_IMMLDEN3_Msk           (0x1ul << BPWM_CTL0_IMMLDEN3_Pos)
 #define BPWM_CTL0_IMMLDEN4_Pos           (20)
 #define BPWM_CTL0_IMMLDEN4_Msk           (0x1ul << BPWM_CTL0_IMMLDEN4_Pos)
 #define BPWM_CTL0_IMMLDEN5_Pos           (21)
 #define BPWM_CTL0_IMMLDEN5_Msk           (0x1ul << BPWM_CTL0_IMMLDEN5_Pos)
 #define BPWM_CTL0_DBGHALT_Pos            (30)
 #define BPWM_CTL0_DBGHALT_Msk            (0x1ul << BPWM_CTL0_DBGHALT_Pos)
 #define BPWM_CTL0_DBGTRIOFF_Pos          (31)
 #define BPWM_CTL0_DBGTRIOFF_Msk          (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos)
 #define BPWM_CTL1_CNTTYPE0_Pos           (0)
 #define BPWM_CTL1_CNTTYPE0_Msk           (0x3ul << BPWM_CTL1_CNTTYPE0_Pos)
 #define BPWM_CLKSRC_ECLKSRC0_Pos         (0)
 #define BPWM_CLKSRC_ECLKSRC0_Msk         (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos)
 #define BPWM_CLKPSC_CLKPSC_Pos           (0)
 #define BPWM_CLKPSC_CLKPSC_Msk           (0xffful << BPWM_CLKPSC_CLKPSC_Pos)
 #define BPWM_CNTEN_CNTEN0_Pos            (0)
 #define BPWM_CNTEN_CNTEN0_Msk            (0x1ul << BPWM_CNTEN_CNTEN0_Pos)
 #define BPWM_CNTCLR_CNTCLR0_Pos          (0)
 #define BPWM_CNTCLR_CNTCLR0_Msk          (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos)
 #define BPWM_PERIOD_PERIOD_Pos           (0)
 #define BPWM_PERIOD_PERIOD_Msk           (0xfffful << BPWM_PERIOD_PERIOD_Pos)
 #define BPWM_CMPDAT0_CMPDAT_Pos          (0)
 #define BPWM_CMPDAT0_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos)
 #define BPWM_CMPDAT1_CMPDAT_Pos          (0)
 #define BPWM_CMPDAT1_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos)
 #define BPWM_CMPDAT2_CMPDAT_Pos          (0)
 #define BPWM_CMPDAT2_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos)
 #define BPWM_CMPDAT3_CMPDAT_Pos          (0)
 #define BPWM_CMPDAT3_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos)
 #define BPWM_CMPDAT4_CMPDAT_Pos          (0)
 #define BPWM_CMPDAT4_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos)
 #define BPWM_CMPDAT5_CMPDAT_Pos          (0)
 #define BPWM_CMPDAT5_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos)
 #define BPWM_CNT_CNT_Pos                 (0)
 #define BPWM_CNT_CNT_Msk                 (0xfffful << BPWM_CNT_CNT_Pos)
 #define BPWM_CNT_DIRF_Pos                (16)
 #define BPWM_CNT_DIRF_Msk                (0x1ul << BPWM_CNT_DIRF_Pos)
 #define BPWM_WGCTL0_ZPCTL0_Pos           (0)
 #define BPWM_WGCTL0_ZPCTL0_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos)
 #define BPWM_WGCTL0_ZPCTL1_Pos           (2)
 #define BPWM_WGCTL0_ZPCTL1_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos)
 #define BPWM_WGCTL0_ZPCTL2_Pos           (4)
 #define BPWM_WGCTL0_ZPCTL2_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos)
 #define BPWM_WGCTL0_ZPCTL3_Pos           (6)
 #define BPWM_WGCTL0_ZPCTL3_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos)
 #define BPWM_WGCTL0_ZPCTL4_Pos           (8)
 #define BPWM_WGCTL0_ZPCTL4_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos)
 #define BPWM_WGCTL0_ZPCTL5_Pos           (10)
 #define BPWM_WGCTL0_ZPCTL5_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos)
 #define BPWM_WGCTL0_ZPCTLn_Pos           (0)
 #define BPWM_WGCTL0_ZPCTLn_Msk           (0xffful << BPWM_WGCTL0_ZPCTLn_Pos)
 #define BPWM_WGCTL0_PRDPCTL0_Pos         (16)
 #define BPWM_WGCTL0_PRDPCTL0_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos)
 #define BPWM_WGCTL0_PRDPCTL1_Pos         (18)
 #define BPWM_WGCTL0_PRDPCTL1_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos)
 #define BPWM_WGCTL0_PRDPCTL2_Pos         (20)
 #define BPWM_WGCTL0_PRDPCTL2_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos)
 #define BPWM_WGCTL0_PRDPCTL3_Pos         (22)
 #define BPWM_WGCTL0_PRDPCTL3_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos)
 #define BPWM_WGCTL0_PRDPCTL4_Pos         (24)
 #define BPWM_WGCTL0_PRDPCTL4_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos)
 #define BPWM_WGCTL0_PRDPCTL5_Pos         (26)
 #define BPWM_WGCTL0_PRDPCTL5_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos)
 #define BPWM_WGCTL0_PRDPCTLn_Pos         (16)
 #define BPWM_WGCTL0_PRDPCTLn_Msk         (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos)
 #define BPWM_WGCTL1_CMPUCTL0_Pos         (0)
 #define BPWM_WGCTL1_CMPUCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos)
 #define BPWM_WGCTL1_CMPUCTL1_Pos         (2)
 #define BPWM_WGCTL1_CMPUCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos)
 #define BPWM_WGCTL1_CMPUCTL2_Pos         (4)
 #define BPWM_WGCTL1_CMPUCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos)
 #define BPWM_WGCTL1_CMPUCTL3_Pos         (6)
 #define BPWM_WGCTL1_CMPUCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos)
 #define BPWM_WGCTL1_CMPUCTL4_Pos         (8)
 #define BPWM_WGCTL1_CMPUCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos)
 #define BPWM_WGCTL1_CMPUCTL5_Pos         (10)
 #define BPWM_WGCTL1_CMPUCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos)
 #define BPWM_WGCTL1_CMPUCTLn_Pos         (0)
 #define BPWM_WGCTL1_CMPUCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos)
 #define BPWM_WGCTL1_CMPDCTL0_Pos         (16)
 #define BPWM_WGCTL1_CMPDCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos)
 #define BPWM_WGCTL1_CMPDCTL1_Pos         (18)
 #define BPWM_WGCTL1_CMPDCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos)
 #define BPWM_WGCTL1_CMPDCTL2_Pos         (20)
 #define BPWM_WGCTL1_CMPDCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos)
 #define BPWM_WGCTL1_CMPDCTL3_Pos         (22)
 #define BPWM_WGCTL1_CMPDCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos)
 #define BPWM_WGCTL1_CMPDCTL4_Pos         (24)
 #define BPWM_WGCTL1_CMPDCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos)
 #define BPWM_WGCTL1_CMPDCTL5_Pos         (26)
 #define BPWM_WGCTL1_CMPDCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos)
 #define BPWM_WGCTL1_CMPDCTLn_Pos         (16)
 #define BPWM_WGCTL1_CMPDCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos)
 #define BPWM_MSKEN_MSKEN0_Pos            (0)
 #define BPWM_MSKEN_MSKEN0_Msk            (0x1ul << BPWM_MSKEN_MSKEN0_Pos)
 #define BPWM_MSKEN_MSKEN1_Pos            (1)
 #define BPWM_MSKEN_MSKEN1_Msk            (0x1ul << BPWM_MSKEN_MSKEN1_Pos)
 #define BPWM_MSKEN_MSKEN2_Pos            (2)
 #define BPWM_MSKEN_MSKEN2_Msk            (0x1ul << BPWM_MSKEN_MSKEN2_Pos)
 #define BPWM_MSKEN_MSKEN3_Pos            (3)
 #define BPWM_MSKEN_MSKEN3_Msk            (0x1ul << BPWM_MSKEN_MSKEN3_Pos)
 #define BPWM_MSKEN_MSKEN4_Pos            (4)
 #define BPWM_MSKEN_MSKEN4_Msk            (0x1ul << BPWM_MSKEN_MSKEN4_Pos)
 #define BPWM_MSKEN_MSKEN5_Pos            (5)
 #define BPWM_MSKEN_MSKEN5_Msk            (0x1ul << BPWM_MSKEN_MSKEN5_Pos)
 #define BPWM_MSKEN_MSKENn_Pos            (0)
 #define BPWM_MSKEN_MSKENn_Msk            (0x3ful << BPWM_MSKEN_MSKENn_Pos)
 #define BPWM_MSK_MSKDAT0_Pos             (0)
 #define BPWM_MSK_MSKDAT0_Msk             (0x1ul << BPWM_MSK_MSKDAT0_Pos)
 #define BPWM_MSK_MSKDAT1_Pos             (1)
 #define BPWM_MSK_MSKDAT1_Msk             (0x1ul << BPWM_MSK_MSKDAT1_Pos)
 #define BPWM_MSK_MSKDAT2_Pos             (2)
 #define BPWM_MSK_MSKDAT2_Msk             (0x1ul << BPWM_MSK_MSKDAT2_Pos)
 #define BPWM_MSK_MSKDAT3_Pos             (3)
 #define BPWM_MSK_MSKDAT3_Msk             (0x1ul << BPWM_MSK_MSKDAT3_Pos)
 #define BPWM_MSK_MSKDAT4_Pos             (4)
 #define BPWM_MSK_MSKDAT4_Msk             (0x1ul << BPWM_MSK_MSKDAT4_Pos)
 #define BPWM_MSK_MSKDAT5_Pos             (5)
 #define BPWM_MSK_MSKDAT5_Msk             (0x1ul << BPWM_MSK_MSKDAT5_Pos)
 #define BPWM_MSK_MSKDATn_Pos             (0)
 #define BPWM_MSK_MSKDATn_Msk             (0x3ful << BPWM_MSK_MSKDATn_Pos)
 #define BPWM_POLCTL_PINV0_Pos            (0)
 #define BPWM_POLCTL_PINV0_Msk            (0x1ul << BPWM_POLCTL_PINV0_Pos)
 #define BPWM_POLCTL_PINV1_Pos            (1)
 #define BPWM_POLCTL_PINV1_Msk            (0x1ul << BPWM_POLCTL_PINV1_Pos)
 #define BPWM_POLCTL_PINV2_Pos            (2)
 #define BPWM_POLCTL_PINV2_Msk            (0x1ul << BPWM_POLCTL_PINV2_Pos)
 #define BPWM_POLCTL_PINV3_Pos            (3)
 #define BPWM_POLCTL_PINV3_Msk            (0x1ul << BPWM_POLCTL_PINV3_Pos)
 #define BPWM_POLCTL_PINV4_Pos            (4)
 #define BPWM_POLCTL_PINV4_Msk            (0x1ul << BPWM_POLCTL_PINV4_Pos)
 #define BPWM_POLCTL_PINV5_Pos            (5)
 #define BPWM_POLCTL_PINV5_Msk            (0x1ul << BPWM_POLCTL_PINV5_Pos)
 #define BPWM_POLCTL_PINVn_Pos            (0)
 #define BPWM_POLCTL_PINVn_Msk            (0x3ful << BPWM_POLCTL_PINVn_Pos)
 #define BPWM_POEN_POEN0_Pos              (0)
 #define BPWM_POEN_POEN0_Msk              (0x1ul << BPWM_POEN_POEN0_Pos)
 #define BPWM_POEN_POEN1_Pos              (1)
 #define BPWM_POEN_POEN1_Msk              (0x1ul << BPWM_POEN_POEN1_Pos)
 #define BPWM_POEN_POEN2_Pos              (2)
 #define BPWM_POEN_POEN2_Msk              (0x1ul << BPWM_POEN_POEN2_Pos)
 #define BPWM_POEN_POEN3_Pos              (3)
 #define BPWM_POEN_POEN3_Msk              (0x1ul << BPWM_POEN_POEN3_Pos)
 #define BPWM_POEN_POEN4_Pos              (4)
 #define BPWM_POEN_POEN4_Msk              (0x1ul << BPWM_POEN_POEN4_Pos)
 #define BPWM_POEN_POEN5_Pos              (5)
 #define BPWM_POEN_POEN5_Msk              (0x1ul << BPWM_POEN_POEN5_Pos)
 #define BPWM_POEN_POENn_Pos              (0)
 #define BPWM_POEN_POENn_Msk              (0x3ful << BPWM_POEN_POENn_Pos)
 #define BPWM_INTEN_ZIEN0_Pos             (0)
 #define BPWM_INTEN_ZIEN0_Msk             (0x1ul << BPWM_INTEN_ZIEN0_Pos)
 #define BPWM_INTEN_PIEN0_Pos             (8)
 #define BPWM_INTEN_PIEN0_Msk             (0x1ul << BPWM_INTEN_PIEN0_Pos)
 #define BPWM_INTEN_CMPUIEN0_Pos          (16)
 #define BPWM_INTEN_CMPUIEN0_Msk          (0x1ul << BPWM_INTEN_CMPUIEN0_Pos)
 #define BPWM_INTEN_CMPUIEN1_Pos          (17)
 #define BPWM_INTEN_CMPUIEN1_Msk          (0x1ul << BPWM_INTEN_CMPUIEN1_Pos)
 #define BPWM_INTEN_CMPUIEN2_Pos          (18)
 #define BPWM_INTEN_CMPUIEN2_Msk          (0x1ul << BPWM_INTEN_CMPUIEN2_Pos)
 #define BPWM_INTEN_CMPUIEN3_Pos          (19)
 #define BPWM_INTEN_CMPUIEN3_Msk          (0x1ul << BPWM_INTEN_CMPUIEN3_Pos)
 #define BPWM_INTEN_CMPUIEN4_Pos          (20)
 #define BPWM_INTEN_CMPUIEN4_Msk          (0x1ul << BPWM_INTEN_CMPUIEN4_Pos)
 #define BPWM_INTEN_CMPUIEN5_Pos          (21)
 #define BPWM_INTEN_CMPUIEN5_Msk          (0x1ul << BPWM_INTEN_CMPUIEN5_Pos)
 #define BPWM_INTEN_CMPUIENn_Pos          (16)
 #define BPWM_INTEN_CMPUIENn_Msk          (0x3ful << BPWM_INTEN_CMPUIENn_Pos)
 #define BPWM_INTEN_CMPDIEN0_Pos          (24)
 #define BPWM_INTEN_CMPDIEN0_Msk          (0x1ul << BPWM_INTEN_CMPDIEN0_Pos)
 #define BPWM_INTEN_CMPDIEN1_Pos          (25)
 #define BPWM_INTEN_CMPDIEN1_Msk          (0x1ul << BPWM_INTEN_CMPDIEN1_Pos)
 #define BPWM_INTEN_CMPDIEN2_Pos          (26)
 #define BPWM_INTEN_CMPDIEN2_Msk          (0x1ul << BPWM_INTEN_CMPDIEN2_Pos)
 #define BPWM_INTEN_CMPDIEN3_Pos          (27)
 #define BPWM_INTEN_CMPDIEN3_Msk          (0x1ul << BPWM_INTEN_CMPDIEN3_Pos)
 #define BPWM_INTEN_CMPDIEN4_Pos          (28)
 #define BPWM_INTEN_CMPDIEN4_Msk          (0x1ul << BPWM_INTEN_CMPDIEN4_Pos)
 #define BPWM_INTEN_CMPDIEN5_Pos          (29)
 #define BPWM_INTEN_CMPDIEN5_Msk          (0x1ul << BPWM_INTEN_CMPDIEN5_Pos)
 #define BPWM_INTEN_CMPDIENn_Pos          (24)
 #define BPWM_INTEN_CMPDIENn_Msk          (0x3ful << BPWM_INTEN_CMPDIENn_Pos)
 #define BPWM_INTSTS_ZIF0_Pos             (0)
 #define BPWM_INTSTS_ZIF0_Msk             (0x1ul << BPWM_INTSTS_ZIF0_Pos)
 #define BPWM_INTSTS_PIF0_Pos             (8)
 #define BPWM_INTSTS_PIF0_Msk             (0x1ul << BPWM_INTSTS_PIF0_Pos)
 #define BPWM_INTSTS_CMPUIF0_Pos          (16)
 #define BPWM_INTSTS_CMPUIF0_Msk          (0x1ul << BPWM_INTSTS_CMPUIF0_Pos)
 #define BPWM_INTSTS_CMPUIF1_Pos          (17)
 #define BPWM_INTSTS_CMPUIF1_Msk          (0x1ul << BPWM_INTSTS_CMPUIF1_Pos)
 #define BPWM_INTSTS_CMPUIF2_Pos          (18)
 #define BPWM_INTSTS_CMPUIF2_Msk          (0x1ul << BPWM_INTSTS_CMPUIF2_Pos)
 #define BPWM_INTSTS_CMPUIF3_Pos          (19)
 #define BPWM_INTSTS_CMPUIF3_Msk          (0x1ul << BPWM_INTSTS_CMPUIF3_Pos)
 #define BPWM_INTSTS_CMPUIF4_Pos          (20)
 #define BPWM_INTSTS_CMPUIF4_Msk          (0x1ul << BPWM_INTSTS_CMPUIF4_Pos)
 #define BPWM_INTSTS_CMPUIF5_Pos          (21)
 #define BPWM_INTSTS_CMPUIF5_Msk          (0x1ul << BPWM_INTSTS_CMPUIF5_Pos)
 #define BPWM_INTSTS_CMPUIFn_Pos          (16)
 #define BPWM_INTSTS_CMPUIFn_Msk          (0x3ful << BPWM_INTSTS_CMPUIFn_Pos)
 #define BPWM_INTSTS_CMPDIF0_Pos          (24)
 #define BPWM_INTSTS_CMPDIF0_Msk          (0x1ul << BPWM_INTSTS_CMPDIF0_Pos)
 #define BPWM_INTSTS_CMPDIF1_Pos          (25)
 #define BPWM_INTSTS_CMPDIF1_Msk          (0x1ul << BPWM_INTSTS_CMPDIF1_Pos)
 #define BPWM_INTSTS_CMPDIF2_Pos          (26)
 #define BPWM_INTSTS_CMPDIF2_Msk          (0x1ul << BPWM_INTSTS_CMPDIF2_Pos)
 #define BPWM_INTSTS_CMPDIF3_Pos          (27)
 #define BPWM_INTSTS_CMPDIF3_Msk          (0x1ul << BPWM_INTSTS_CMPDIF3_Pos)
 #define BPWM_INTSTS_CMPDIF4_Pos          (28)
 #define BPWM_INTSTS_CMPDIF4_Msk          (0x1ul << BPWM_INTSTS_CMPDIF4_Pos)
 #define BPWM_INTSTS_CMPDIF5_Pos          (29)
 #define BPWM_INTSTS_CMPDIF5_Msk          (0x1ul << BPWM_INTSTS_CMPDIF5_Pos)
 #define BPWM_INTSTS_CMPDIFn_Pos          (24)
 #define BPWM_INTSTS_CMPDIFn_Msk          (0x3ful << BPWM_INTSTS_CMPDIFn_Pos)
 #define BPWM_EADCTS0_TRGSEL0_Pos         (0)
 #define BPWM_EADCTS0_TRGSEL0_Msk         (0xful << BPWM_EADCTS0_TRGSEL0_Pos)
 #define BPWM_EADCTS0_TRGEN0_Pos          (7)
 #define BPWM_EADCTS0_TRGEN0_Msk          (0x1ul << BPWM_EADCTS0_TRGEN0_Pos)
 #define BPWM_EADCTS0_TRGSEL1_Pos         (8)
 #define BPWM_EADCTS0_TRGSEL1_Msk         (0xful << BPWM_EADCTS0_TRGSEL1_Pos)
 #define BPWM_EADCTS0_TRGEN1_Pos          (15)
 #define BPWM_EADCTS0_TRGEN1_Msk          (0x1ul << BPWM_EADCTS0_TRGEN1_Pos)
 #define BPWM_EADCTS0_TRGSEL2_Pos         (16)
 #define BPWM_EADCTS0_TRGSEL2_Msk         (0xful << BPWM_EADCTS0_TRGSEL2_Pos)
 #define BPWM_EADCTS0_TRGEN2_Pos          (23)
 #define BPWM_EADCTS0_TRGEN2_Msk          (0x1ul << BPWM_EADCTS0_TRGEN2_Pos)
 #define BPWM_EADCTS0_TRGSEL3_Pos         (24)
 #define BPWM_EADCTS0_TRGSEL3_Msk         (0xful << BPWM_EADCTS0_TRGSEL3_Pos)
 #define BPWM_EADCTS0_TRGEN3_Pos          (31)
 #define BPWM_EADCTS0_TRGEN3_Msk          (0x1ul << BPWM_EADCTS0_TRGEN3_Pos)
 #define BPWM_EADCTS1_TRGSEL4_Pos         (0)
 #define BPWM_EADCTS1_TRGSEL4_Msk         (0xful << BPWM_EADCTS1_TRGSEL4_Pos)
 #define BPWM_EADCTS1_TRGEN4_Pos          (7)
 #define BPWM_EADCTS1_TRGEN4_Msk          (0x1ul << BPWM_EADCTS1_TRGEN4_Pos)
 #define BPWM_EADCTS1_TRGSEL5_Pos         (8)
 #define BPWM_EADCTS1_TRGSEL5_Msk         (0xful << BPWM_EADCTS1_TRGSEL5_Pos)
 #define BPWM_EADCTS1_TRGEN5_Pos          (15)
 #define BPWM_EADCTS1_TRGEN5_Msk          (0x1ul << BPWM_EADCTS1_TRGEN5_Pos)
 #define BPWM_SSCTL_SSEN0_Pos             (0)
 #define BPWM_SSCTL_SSEN0_Msk             (0x1ul << BPWM_SSCTL_SSEN0_Pos)
 #define BPWM_SSCTL_SSRC_Pos              (8)
 #define BPWM_SSCTL_SSRC_Msk              (0x3ul << BPWM_SSCTL_SSRC_Pos)
 #define BPWM_SSTRG_CNTSEN_Pos            (0)
 #define BPWM_SSTRG_CNTSEN_Msk            (0x1ul << BPWM_SSTRG_CNTSEN_Pos)
 #define BPWM_STATUS_CNTMAX0_Pos          (0)
 #define BPWM_STATUS_CNTMAX0_Msk          (0x1ul << BPWM_STATUS_CNTMAX0_Pos)
 #define BPWM_STATUS_EADCTRG0_Pos         (16)
 #define BPWM_STATUS_EADCTRG0_Msk         (0x1ul << BPWM_STATUS_EADCTRG0_Pos)
 #define BPWM_STATUS_EADCTRG1_Pos         (17)
 #define BPWM_STATUS_EADCTRG1_Msk         (0x1ul << BPWM_STATUS_EADCTRG1_Pos)
 #define BPWM_STATUS_EADCTRG2_Pos         (18)
 #define BPWM_STATUS_EADCTRG2_Msk         (0x1ul << BPWM_STATUS_EADCTRG2_Pos)
 #define BPWM_STATUS_EADCTRG3_Pos         (19)
 #define BPWM_STATUS_EADCTRG3_Msk         (0x1ul << BPWM_STATUS_EADCTRG3_Pos)
 #define BPWM_STATUS_EADCTRG4_Pos         (20)
 #define BPWM_STATUS_EADCTRG4_Msk         (0x1ul << BPWM_STATUS_EADCTRG4_Pos)
 #define BPWM_STATUS_EADCTRG5_Pos         (21)
 #define BPWM_STATUS_EADCTRG5_Msk         (0x1ul << BPWM_STATUS_EADCTRG5_Pos)
 #define BPWM_STATUS_EADCTRGn_Pos         (16)
 #define BPWM_STATUS_EADCTRGn_Msk         (0x3ful << BPWM_STATUS_EADCTRGn_Pos)
 #define BPWM_CAPINEN_CAPINEN0_Pos        (0)
 #define BPWM_CAPINEN_CAPINEN0_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos)
 #define BPWM_CAPINEN_CAPINEN1_Pos        (1)
 #define BPWM_CAPINEN_CAPINEN1_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos)
 #define BPWM_CAPINEN_CAPINEN2_Pos        (2)
 #define BPWM_CAPINEN_CAPINEN2_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos)
 #define BPWM_CAPINEN_CAPINEN3_Pos        (3)
 #define BPWM_CAPINEN_CAPINEN3_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos)
 #define BPWM_CAPINEN_CAPINEN4_Pos        (4)
 #define BPWM_CAPINEN_CAPINEN4_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos)
 #define BPWM_CAPINEN_CAPINEN5_Pos        (5)
 #define BPWM_CAPINEN_CAPINEN5_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos)
 #define BPWM_CAPINEN_CAPINENn_Pos        (0)
 #define BPWM_CAPINEN_CAPINENn_Msk        (0x3ful << BPWM_CAPINEN_CAPINENn_Pos)
 #define BPWM_CAPCTL_CAPEN0_Pos           (0)
 #define BPWM_CAPCTL_CAPEN0_Msk           (0x1ul << BPWM_CAPCTL_CAPEN0_Pos)
 #define BPWM_CAPCTL_CAPEN1_Pos           (1)
 #define BPWM_CAPCTL_CAPEN1_Msk           (0x1ul << BPWM_CAPCTL_CAPEN1_Pos)
 #define BPWM_CAPCTL_CAPEN2_Pos           (2)
 #define BPWM_CAPCTL_CAPEN2_Msk           (0x1ul << BPWM_CAPCTL_CAPEN2_Pos)
 #define BPWM_CAPCTL_CAPEN3_Pos           (3)
 #define BPWM_CAPCTL_CAPEN3_Msk           (0x1ul << BPWM_CAPCTL_CAPEN3_Pos)
 #define BPWM_CAPCTL_CAPEN4_Pos           (4)
 #define BPWM_CAPCTL_CAPEN4_Msk           (0x1ul << BPWM_CAPCTL_CAPEN4_Pos)
 #define BPWM_CAPCTL_CAPEN5_Pos           (5)
 #define BPWM_CAPCTL_CAPEN5_Msk           (0x1ul << BPWM_CAPCTL_CAPEN5_Pos)
 #define BPWM_CAPCTL_CAPENn_Pos           (0)
 #define BPWM_CAPCTL_CAPENn_Msk           (0x3ful << BPWM_CAPCTL_CAPENn_Pos)
 #define BPWM_CAPCTL_CAPINV0_Pos          (8)
 #define BPWM_CAPCTL_CAPINV0_Msk          (0x1ul << BPWM_CAPCTL_CAPINV0_Pos)
 #define BPWM_CAPCTL_CAPINV1_Pos          (9)
 #define BPWM_CAPCTL_CAPINV1_Msk          (0x1ul << BPWM_CAPCTL_CAPINV1_Pos)
 #define BPWM_CAPCTL_CAPINV2_Pos          (10)
 #define BPWM_CAPCTL_CAPINV2_Msk          (0x1ul << BPWM_CAPCTL_CAPINV2_Pos)
 #define BPWM_CAPCTL_CAPINV3_Pos          (11)
 #define BPWM_CAPCTL_CAPINV3_Msk          (0x1ul << BPWM_CAPCTL_CAPINV3_Pos)
 #define BPWM_CAPCTL_CAPINV4_Pos          (12)
 #define BPWM_CAPCTL_CAPINV4_Msk          (0x1ul << BPWM_CAPCTL_CAPINV4_Pos)
 #define BPWM_CAPCTL_CAPINV5_Pos          (13)
 #define BPWM_CAPCTL_CAPINV5_Msk          (0x1ul << BPWM_CAPCTL_CAPINV5_Pos)
 #define BPWM_CAPCTL_CAPINVn_Pos          (8)
 #define BPWM_CAPCTL_CAPINVn_Msk          (0x3ful << BPWM_CAPCTL_CAPINVn_Pos)
 #define BPWM_CAPCTL_RCRLDEN0_Pos         (16)
 #define BPWM_CAPCTL_RCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos)
 #define BPWM_CAPCTL_RCRLDEN1_Pos         (17)
 #define BPWM_CAPCTL_RCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos)
 #define BPWM_CAPCTL_RCRLDEN2_Pos         (18)
 #define BPWM_CAPCTL_RCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos)
 #define BPWM_CAPCTL_RCRLDEN3_Pos         (19)
 #define BPWM_CAPCTL_RCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos)
 #define BPWM_CAPCTL_RCRLDEN4_Pos         (20)
 #define BPWM_CAPCTL_RCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos)
 #define BPWM_CAPCTL_RCRLDEN5_Pos         (21)
 #define BPWM_CAPCTL_RCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos)
 #define BPWM_CAPCTL_RCRLDENn_Pos         (16)
 #define BPWM_CAPCTL_RCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos)
 #define BPWM_CAPCTL_FCRLDEN0_Pos         (24)
 #define BPWM_CAPCTL_FCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos)
 #define BPWM_CAPCTL_FCRLDEN1_Pos         (25)
 #define BPWM_CAPCTL_FCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos)
 #define BPWM_CAPCTL_FCRLDEN2_Pos         (26)
 #define BPWM_CAPCTL_FCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos)
 #define BPWM_CAPCTL_FCRLDEN3_Pos         (27)
 #define BPWM_CAPCTL_FCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos)
 #define BPWM_CAPCTL_FCRLDEN4_Pos         (28)
 #define BPWM_CAPCTL_FCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos)
 #define BPWM_CAPCTL_FCRLDEN5_Pos         (29)
 #define BPWM_CAPCTL_FCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos)
 #define BPWM_CAPCTL_FCRLDENn_Pos         (24)
 #define BPWM_CAPCTL_FCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos)
 #define BPWM_CAPSTS_CRIFOV0_Pos          (0)
 #define BPWM_CAPSTS_CRIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos)
 #define BPWM_CAPSTS_CRIFOV1_Pos          (1)
 #define BPWM_CAPSTS_CRIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos)
 #define BPWM_CAPSTS_CRIFOV2_Pos          (2)
 #define BPWM_CAPSTS_CRIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos)
 #define BPWM_CAPSTS_CRIFOV3_Pos          (3)
 #define BPWM_CAPSTS_CRIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos)
 #define BPWM_CAPSTS_CRIFOV4_Pos          (4)
 #define BPWM_CAPSTS_CRIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos)
 #define BPWM_CAPSTS_CRIFOV5_Pos          (5)
 #define BPWM_CAPSTS_CRIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos)
 #define BPWM_CAPSTS_CRIFOVn_Pos          (0)
 #define BPWM_CAPSTS_CRIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos)
 #define BPWM_CAPSTS_CFIFOV0_Pos          (8)
 #define BPWM_CAPSTS_CFIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos)
 #define BPWM_CAPSTS_CFIFOV1_Pos          (9)
 #define BPWM_CAPSTS_CFIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos)
 #define BPWM_CAPSTS_CFIFOV2_Pos          (10)
 #define BPWM_CAPSTS_CFIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos)
 #define BPWM_CAPSTS_CFIFOV3_Pos          (11)
 #define BPWM_CAPSTS_CFIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos)
 #define BPWM_CAPSTS_CFIFOV4_Pos          (12)
 #define BPWM_CAPSTS_CFIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos)
 #define BPWM_CAPSTS_CFIFOV5_Pos          (13)
 #define BPWM_CAPSTS_CFIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos)
 #define BPWM_CAPSTS_CFIFOVn_Pos          (8)
 #define BPWM_CAPSTS_CFIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos)
 #define BPWM_RCAPDAT0_RCAPDAT_Pos        (0)
 #define BPWM_RCAPDAT0_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos)
 #define BPWM_FCAPDAT0_FCAPDAT_Pos        (0)
 #define BPWM_FCAPDAT0_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos)
 #define BPWM_RCAPDAT1_RCAPDAT_Pos        (0)
 #define BPWM_RCAPDAT1_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos)
 #define BPWM_FCAPDAT1_FCAPDAT_Pos        (0)
 #define BPWM_FCAPDAT1_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos)
 #define BPWM_RCAPDAT2_RCAPDAT_Pos        (0)
 #define BPWM_RCAPDAT2_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos)
 #define BPWM_FCAPDAT2_FCAPDAT_Pos        (0)
 #define BPWM_FCAPDAT2_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos)
 #define BPWM_RCAPDAT3_RCAPDAT_Pos        (0)
 #define BPWM_RCAPDAT3_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos)
 #define BPWM_FCAPDAT3_FCAPDAT_Pos        (0)
 #define BPWM_FCAPDAT3_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos)
 #define BPWM_RCAPDAT4_RCAPDAT_Pos        (0)
 #define BPWM_RCAPDAT4_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos)
 #define BPWM_FCAPDAT4_FCAPDAT_Pos        (0)
 #define BPWM_FCAPDAT4_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos)
 #define BPWM_RCAPDAT5_RCAPDAT_Pos        (0)
 #define BPWM_RCAPDAT5_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos)
 #define BPWM_FCAPDAT5_FCAPDAT_Pos        (0)
 #define BPWM_FCAPDAT5_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos)
 #define BPWM_CAPIEN_CAPRIENn_Pos         (0)
 #define BPWM_CAPIEN_CAPRIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos)
 #define BPWM_CAPIEN_CAPFIENn_Pos         (8)
 #define BPWM_CAPIEN_CAPFIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos)
 #define BPWM_CAPIF_CAPRIF0_Pos           (0)
 #define BPWM_CAPIF_CAPRIF0_Msk           (0x1ul << BPWM_CAPIF_CAPRIF0_Pos)
 #define BPWM_CAPIF_CAPRIF1_Pos           (1)
 #define BPWM_CAPIF_CAPRIF1_Msk           (0x1ul << BPWM_CAPIF_CAPRIF1_Pos)
 #define BPWM_CAPIF_CAPRIF2_Pos           (2)
 #define BPWM_CAPIF_CAPRIF2_Msk           (0x1ul << BPWM_CAPIF_CAPRIF2_Pos)
 #define BPWM_CAPIF_CAPRIF3_Pos           (3)
 #define BPWM_CAPIF_CAPRIF3_Msk           (0x1ul << BPWM_CAPIF_CAPRIF3_Pos)
 #define BPWM_CAPIF_CAPRIF4_Pos           (4)
 #define BPWM_CAPIF_CAPRIF4_Msk           (0x1ul << BPWM_CAPIF_CAPRIF4_Pos)
 #define BPWM_CAPIF_CAPRIF5_Pos           (5)
 #define BPWM_CAPIF_CAPRIF5_Msk           (0x1ul << BPWM_CAPIF_CAPRIF5_Pos)
 #define BPWM_CAPIF_CAPRIFn_Pos           (0)
 #define BPWM_CAPIF_CAPRIFn_Msk           (0x3ful << BPWM_CAPIF_CAPRIFn_Pos)
 #define BPWM_CAPIF_CAPFIF0_Pos           (8)
 #define BPWM_CAPIF_CAPFIF0_Msk           (0x1ul << BPWM_CAPIF_CAPFIF0_Pos)
 #define BPWM_CAPIF_CAPFIF1_Pos           (9)
 #define BPWM_CAPIF_CAPFIF1_Msk           (0x1ul << BPWM_CAPIF_CAPFIF1_Pos)
 #define BPWM_CAPIF_CAPFIF2_Pos           (10)
 #define BPWM_CAPIF_CAPFIF2_Msk           (0x1ul << BPWM_CAPIF_CAPFIF2_Pos)
 #define BPWM_CAPIF_CAPFIF3_Pos           (11)
 #define BPWM_CAPIF_CAPFIF3_Msk           (0x1ul << BPWM_CAPIF_CAPFIF3_Pos)
 #define BPWM_CAPIF_CAPFIF4_Pos           (12)
 #define BPWM_CAPIF_CAPFIF4_Msk           (0x1ul << BPWM_CAPIF_CAPFIF4_Pos)
 #define BPWM_CAPIF_CAPFIF5_Pos           (13)
 #define BPWM_CAPIF_CAPFIF5_Msk           (0x1ul << BPWM_CAPIF_CAPFIF5_Pos)
 #define BPWM_CAPIF_CAPFIFn_Pos           (8)
 #define BPWM_CAPIF_CAPFIFn_Msk           (0x3ful << BPWM_CAPIF_CAPFIFn_Pos)
 #define BPWM_PBUF_PBUF_Pos               (0)
 #define BPWM_PBUF_PBUF_Msk               (0xfffful << BPWM_PBUF_PBUF_Pos)
 #define BPWM_CMPBUF0_CMPBUF_Pos          (0)
 #define BPWM_CMPBUF0_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos)
 #define BPWM_CMPBUF1_CMPBUF_Pos          (0)
 #define BPWM_CMPBUF1_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos)
 #define BPWM_CMPBUF2_CMPBUF_Pos          (0)
 #define BPWM_CMPBUF2_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos)
 #define BPWM_CMPBUF3_CMPBUF_Pos          (0)
 #define BPWM_CMPBUF3_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos)
 #define BPWM_CMPBUF4_CMPBUF_Pos          (0)
 #define BPWM_CMPBUF4_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos)
 #define BPWM_CMPBUF5_CMPBUF_Pos          (0)
 #define BPWM_CMPBUF5_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos)              /* BPWM_CONST */
  /* end of BPWM register group */ /* end of REGISTER group */

 #if defined ( __CC_ARM   )
 #pragma no_anon_unions
 #endif

 #endif /* __BPWM_REG_H__ */
BPWM_T::WGCTL0
__IO uint32_t WGCTL0
Definition: bpwm_reg.h:2407

BPWM_T::CAPIF
__IO uint32_t CAPIF
Definition: bpwm_reg.h:2449

BPWM_T::STATUS
__IO uint32_t STATUS
Definition: bpwm_reg.h:2437

BPWM_T::POLCTL
__IO uint32_t POLCTL
Definition: bpwm_reg.h:2414

BPWM_T::SSCTL
__IO uint32_t SSCTL
Definition: bpwm_reg.h:2432

BPWM_T::CTL0
__IO uint32_t CTL0
Definition: bpwm_reg.h:2380

BPWM_T::SSTRG
__O uint32_t SSTRG
Definition: bpwm_reg.h:2433

BPWM_T::CLKSRC
__IO uint32_t CLKSRC
Definition: bpwm_reg.h:2385

BPWM_T::CTL1
__IO uint32_t CTL1
Definition: bpwm_reg.h:2381

BPWM_T::CAPIEN
__IO uint32_t CAPIEN
Definition: bpwm_reg.h:2448

BCAPDAT_T::FCAPDAT
__IO uint32_t FCAPDAT
Definition: bpwm_reg.h:68

BPWM_T::CNTEN
__IO uint32_t CNTEN
Definition: bpwm_reg.h:2390

BPWM_T::PBUF
__I uint32_t PBUF
Definition: bpwm_reg.h:2453

BPWM_T::WGCTL1
__IO uint32_t WGCTL1
Definition: bpwm_reg.h:2408

BPWM_T::CAPSTS
__I uint32_t CAPSTS
Definition: bpwm_reg.h:2443

BPWM_T::INTSTS
__IO uint32_t INTSTS
Definition: bpwm_reg.h:2423

BPWM_T::CLKPSC
__IO uint32_t CLKPSC
Definition: bpwm_reg.h:2386

BPWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: bpwm_reg.h:2442

BPWM_T::MSKEN
__IO uint32_t MSKEN
Definition: bpwm_reg.h:2409

BPWM_T::CNT
__I uint32_t CNT
Definition: bpwm_reg.h:2403

BCAPDAT_T::RCAPDAT
__IO uint32_t RCAPDAT
Definition: bpwm_reg.h:67

BPWM_T::MSK
__IO uint32_t MSK
Definition: bpwm_reg.h:2410

BPWM_T::INTEN
__IO uint32_t INTEN
Definition: bpwm_reg.h:2419

BPWM_T::CNTCLR
__IO uint32_t CNTCLR
Definition: bpwm_reg.h:2391

BPWM_T
Definition: bpwm_reg.h:71

BPWM_T::EADCTS1
__IO uint32_t EADCTS1
Definition: bpwm_reg.h:2428

BPWM_T::EADCTS0
__IO uint32_t EADCTS0
Definition: bpwm_reg.h:2427

BPWM_T::CAPINEN
__IO uint32_t CAPINEN
Definition: bpwm_reg.h:2441

BCAPDAT_T
Definition: bpwm_reg.h:26

BPWM_T::POEN
__IO uint32_t POEN
Definition: bpwm_reg.h:2415

BPWM_T::PERIOD
__IO uint32_t PERIOD
Definition: bpwm_reg.h:2395