| M480 BSP V3.05.001 The Board Support Package for M480 Series

epwm.c
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1 /**************************************************************************/
10 #include "NuMicro.h"
11
36 uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
37 {
38 uint32_t u32Src;
39 uint32_t u32EPWMClockSrc;
40 uint32_t u32NearestUnitTimeNsec;
41 uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU;
42
43 if(epwm == EPWM0)
44 {
45 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
46 }
47 else /* (epwm == EPWM1) */
48 {
49 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
50 }
51
52 if(u32Src == 0U)
53 {
54 /* clock source is from PLL clock */
55 u32EPWMClockSrc = CLK_GetPLLClockFreq();
56 }
57 else
58 {
59 /* clock source is from PCLK */
60 SystemCoreClockUpdate();
61 if(epwm == EPWM0)
62 {
63 u32EPWMClockSrc = CLK_GetPCLK0Freq();
64 }
65 else /* (epwm == EPWM1) */
66 {
67 u32EPWMClockSrc = CLK_GetPCLK1Freq();
68 }
69 }
70
71 u32EPWMClockSrc /= 1000U;
72 for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++)
73 {
74 uint32_t u32Exit = 0U;
75 u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc;
76 if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
77 {
78 if(u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */
79 {
80 u32Exit = 1U;
81 }
82 else
83 {
84 u32Exit = 0U;
85 }
86 if(!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc))))
87 {
88 u32Exit = 1U;
89 }
90 else
91 {
92 u32Exit = 0U;
93 }
94 }
95 else
96 {
97 u32Exit = 1U;
98 }
99 if (u32Exit == 1U)
100 {
101 break;
102 }
103 else {}
104 }
105
106 /* convert to real register value */
107 /* every two channels share a prescaler */
108 u16Prescale -= 1U;
109 EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale);
110
111 /* set EPWM to down count type(edge aligned) */
112 (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U));
113 /* set EPWM to auto-reload mode */
114 (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
115 EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR);
116
117 return (u32NearestUnitTimeNsec);
118 }
119
134 uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
135 {
136 uint32_t u32Src;
137 uint32_t u32EPWMClockSrc;
138 uint32_t i;
139 uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
140
141 if(epwm == EPWM0)
142 {
143 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
144 }
145 else /* (epwm == EPWM1) */
146 {
147 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
148 }
149
150 if(u32Src == 0U)
151 {
152 /* clock source is from PLL clock */
153 u32EPWMClockSrc = CLK_GetPLLClockFreq();
154 }
155 else
156 {
157 /* clock source is from PCLK */
158 SystemCoreClockUpdate();
159 if(epwm == EPWM0)
160 {
161 u32EPWMClockSrc = CLK_GetPCLK0Freq();
162 }
163 else /* (epwm == EPWM1) */
164 {
165 u32EPWMClockSrc = CLK_GetPCLK1Freq();
166 }
167 }
168
169 for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */
170 {
171 i = (u32EPWMClockSrc / u32Frequency) / u32Prescale;
172 /* If target value is larger than CNR, need to use a larger prescaler */
173 if(i < (0x10000U))
174 {
175 u32CNR = i;
176 break;
177 }
178 }
179 /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */
180 i = u32EPWMClockSrc / (u32Prescale * u32CNR);
181
182 /* convert to real register value */
183 /* every two channels share a prescaler */
184 u32Prescale -= 1U;
185 EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
186 /* set EPWM to up counter type(edge aligned) and auto-reload mode */
187 (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))|((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum)));
188
189 u32CNR -= 1U;
190 EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
191 EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U);
192
193 (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1U))) | \
194 ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos));
195 (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1U))) | \
196 ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos));
197
198 return(i);
199 }
200
211 void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
212 {
213 (epwm)->CNTEN |= u32ChannelMask;
214 }
215
226 void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
227 {
228 uint32_t i;
229 for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
230 {
231 if(u32ChannelMask & (1UL << i))
232 {
233 (epwm)->PERIOD[i] = 0U;
234 }
235 }
236 }
237
248 void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
249 {
250 (epwm)->CNTEN &= ~u32ChannelMask;
251 }
252
279 void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
280 {
281 if(u32ChannelNum < 4U)
282 {
283 (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U));
284 (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));
285 }
286 else
287 {
288 (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U));
289 (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U));
290 }
291 }
292
302 void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
303 {
304 if(u32ChannelNum < 4U)
305 {
306 (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U));
307 }
308 else
309 {
310 (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U));
311 }
312 }
313
328 int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt)
329 {
330 /* User can write only when PSCENn(n = 0 ~ 5) is 0 */
331 if ((epwm)->EADCPSCCTL & (1UL << u32ChannelNum))
332 return (-1);
333
334 if(u32ChannelNum < 4UL)
335 {
336 (epwm)->EADCPSC0 = ((epwm)->EADCPSC0 & ~((EPWM_EADCPSC0_EADCPSC0_Msk) << (u32ChannelNum << 3))) | \
337 (u32Prescale << (u32ChannelNum << 3));
338 (epwm)->EADCPSCNT0 = ((epwm)->EADCPSCNT0 & ~((EPWM_EADCPSCNT0_PSCNT0_Msk) << (u32ChannelNum << 3))) | \
339 (u32PrescaleCnt << (u32ChannelNum << 3));
340 }
341 else
342 {
343 (epwm)->EADCPSC1 = ((epwm)->EADCPSC1 & ~((EPWM_EADCPSC1_EADCPSC4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \
344 (u32Prescale << ((u32ChannelNum - 4UL) << 3));
345 (epwm)->EADCPSCNT1 = ((epwm)->EADCPSCNT1 & ~((EPWM_EADCPSCNT1_PSCNT4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \
346 (u32PrescaleCnt << ((u32ChannelNum - 4UL) << 3));
347 }
348
349 (epwm)->EADCPSCCTL |= EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum;
350
351 return 0;
352 }
353
363 void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum)
364 {
365 (epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum);
366 }
367
378 void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
379 {
380 (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum);
381 }
382
393 uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
394 {
395 return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL);
396 }
397
412 void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
413 {
414 (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
415 }
416
426 void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
427 {
428 (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \
429 EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum);
430 }
431
442 void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
443 {
444 (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk;
445 }
446
457 uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
458 {
459 return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL);
460 }
461
493 void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
494 {
495 uint32_t i;
496
497 for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
498 {
499 if(u32ChannelMask & (1UL << i))
500 {
501 if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \
502 (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \
503 (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \
504 (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR))
505 {
506 (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk));
507 (epwm)->FAILBRK |= (u32BrakeSource & 0xFU);
508 }
509 else
510 {
511 (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;
512 }
513 }
514
515 if(u32LevelMask & (1UL << i))
516 {
517 if((i & 0x1U) == 0U)
518 {
519 /* set brake action as high level for even channel */
520 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
521 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
522 }
523 else
524 {
525 /* set brake action as high level for odd channel */
526 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
527 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos);
528 }
529 }
530 else
531 {
532 if((i & 0x1U) == 0U)
533 {
534 /* set brake action as low level for even channel */
535 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
536 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
537 }
538 else
539 {
540 /* set brake action as low level for odd channel */
541 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
542 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos);
543 }
544 }
545 }
546 }
547
558 void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
559 {
560 (epwm)->CAPINEN |= u32ChannelMask;
561 (epwm)->CAPCTL |= u32ChannelMask;
562 }
563
574 void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
575 {
576 (epwm)->CAPINEN &= ~u32ChannelMask;
577 (epwm)->CAPCTL &= ~u32ChannelMask;
578 }
579
590 void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
591 {
592 (epwm)->POEN |= u32ChannelMask;
593 }
594
605 void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
606 {
607 (epwm)->POEN &= ~u32ChannelMask;
608 }
609
625 void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
626 {
627 uint32_t u32IsOddCh;
628 u32IsOddCh = u32ChannelNum & 0x1U;
629 (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \
630 (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \
631 u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U));
632 }
633
643 void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
644 {
645 (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U));
646 }
647
660 void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
661 {
662 /* every two channels share the same setting */
663 (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk;
664 (epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration;
665 }
666
677 void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
678 {
679 /* every two channels shares the same setting */
680 (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk;
681 }
682
695 void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
696 {
697 (epwm)->CAPIEN |= (u32Edge << u32ChannelNum);
698 }
699
712 void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
713 {
714 (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
715 }
716
729 void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
730 {
731 (epwm)->CAPIF = (u32Edge << u32ChannelNum);
732 }
733
746 uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
747 {
748 return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \
749 (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
750 }
763 void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
764 {
765 (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
766 }
767
777 void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
778 {
779 (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
780 }
781
791 void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
792 {
793 (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
794 }
795
807 uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
808 {
809 return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
810 }
811
823 void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
824 {
825 (epwm)->INTEN1 |= (0x7UL << u32BrakeSource);
826 }
827
839 void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
840 {
841 (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);
842 }
843
854 void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
855 {
856 (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);
857 }
858
870 uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
871 {
872 return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);
873 }
874
885 void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
886 {
887 (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
888 }
889
899 void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
900 {
901 (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum);
902 }
903
913 void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
914 {
915 (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum);
916 }
917
929 uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
930 {
931 return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL);
932 }
933
943 void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
944 {
945 (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
946 }
947
957 void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
958 {
959 (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
960 }
961
971 void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
972 {
973 (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum);
974 }
975
987 uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
988 {
989 return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL);
990 }
991
1007 void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
1008 {
1009 (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \
1010 (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt) );
1011 }
1012
1022 void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum)
1023 {
1024 (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk));
1025 }
1026
1036 void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1037 {
1038 (epwm)->AINTEN |= (1UL << (u32ChannelNum));
1039 }
1040
1050 void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1051 {
1052 (epwm)->AINTEN &= ~(1UL << (u32ChannelNum));
1053 }
1054
1064 void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1065 {
1066 (epwm)->AINTSTS = (1UL << (u32ChannelNum));
1067 }
1068
1079 uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1080 {
1081 return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL);
1082 }
1083
1093 void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
1094 {
1095 (epwm)->APDMACTL |= (1UL << (u32ChannelNum));
1096 }
1097
1107 void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
1108 {
1109 (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum));
1110 }
1111
1121 void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
1122 {
1123 (epwm)->IFA[u32ChannelNum] |= EPWM_IFA0_STPMOD_Msk;
1124 }
1125
1135 void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
1136 {
1137 (epwm)->IFA[u32ChannelNum] &= ~EPWM_IFA0_STPMOD_Msk;
1138 }
1139
1149 void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
1150 {
1151 (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U));
1152 }
1153
1165 uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
1166 {
1167 return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL);
1168 }
1169
1183 void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
1184 {
1185 (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
1186 }
1187
1201 void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
1202 {
1203 (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
1204 }
1205
1225 void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
1226 {
1227 /* every two channels shares the same setting */
1228 u32ChannelNum >>= 1U;
1229 (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \
1230 (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)));
1231 (epwm)->PHS[(u32ChannelNum)] = u32StartPhase;
1232 }
1233
1234
1246 void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
1247 {
1248 uint32_t i;
1249 for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
1250 {
1251 if(u32ChannelMask & (1UL << i))
1252 {
1253 (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));
1254 }
1255 }
1256 }
1257
1269 void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
1270 {
1271 uint32_t i;
1272 for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)
1273 {
1274 if(u32ChannelMask & (1UL << i))
1275 {
1276 (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));
1277 }
1278 }
1279 }
1280
1300 void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
1301 {
1302 (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \
1303 ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk);
1304 }
1305
1314 void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm)
1315 {
1316 (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk;
1317 }
1318
1327 void EPWM_EnableSyncPinInverse(EPWM_T *epwm)
1328 {
1329 (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk;
1330 }
1331
1340 void EPWM_DisableSyncPinInverse(EPWM_T *epwm)
1341 {
1342 (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk);
1343 }
1344
1362 void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
1363 {
1364 (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \
1365 (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U));
1366 }
1367
1387 void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
1388 {
1389 (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \
1390 (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U));
1391 }
1392
1402 void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum)
1403 {
1404 (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U));
1405 }
1406
1416 void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
1417 {
1418 (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U));
1419 }
1420
1430 void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
1431 {
1432 (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos));
1433 }
1434
1445 void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
1446 {
1447 (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U)));
1448 }
1449
1476 void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable)
1477 {
1478 (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable);
1479 /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */
1480 (epwm)->LEBCNT = (u32BlankingCnt) - 1U;
1481 }
1482
1494 uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
1495 {
1496 return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
1497 }
1498
1508 void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
1509 {
1510 (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
1511 }
1512
1528 void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel)
1529 {
1530 (epwm)->FDEN = ((epwm)->FDEN & ~(EPWM_FDEN_FDCKS0_Msk << (u32ChannelNum))) | \
1531 ((EPWM_FDEN_FDEN0_Msk | ((u32AfterPrescaler) << EPWM_FDEN_FDCKS0_Pos)) << (u32ChannelNum));
1532 (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & ~EPWM_FDCTL0_FDCKSEL_Msk) | (u32ClkSel);
1533 }
1534
1544 void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum)
1545 {
1546 (epwm)->FDEN &= ~(EPWM_FDEN_FDEN0_Msk << (u32ChannelNum));
1547 }
1548
1558 void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
1559 {
1560 (epwm)->FDEN &= ~(EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum));
1561 }
1562
1572 void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
1573 {
1574 (epwm)->FDEN |= (EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum));
1575 }
1576
1587 void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle)
1588 {
1589 (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_DGSMPCYC_Msk)) | \
1590 (EPWM_FDCTL0_FDDGEN_Msk | ((u32DeglitchSmpCycle) << EPWM_FDCTL0_DGSMPCYC_Pos));
1591 }
1592
1602 void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum)
1603 {
1604 (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDDGEN_Msk;
1605 }
1606
1617 void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt)
1618 {
1619 (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_TRMSKCNT_Msk)) | (EPWM_FDCTL0_FDMSKEN_Msk | (u32MaskCnt));
1620 }
1621
1631 void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum)
1632 {
1633 (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDMSKEN_Msk;
1634 }
1635
1645 void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1646 {
1647 (epwm)->FDIEN |= (EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum));
1648 }
1649
1659 void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1660 {
1661 (epwm)->FDIEN &= ~(EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum));
1662 }
1663
1673 void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1674 {
1675 (epwm)->FDSTS = (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum));
1676 }
1677
1688 uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
1689 {
1690 return (((epwm)->FDSTS & (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum))) ? 1UL : 0UL);
1691 }
1692 /* end of group EPWM_EXPORTED_FUNCTIONS */
1694 /* end of group EPWM_Driver */
1696 /* end of group Standard_Driver */
1698
1699 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
EPWM_DisablePDMA
void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
Disables PDMA transfer of selected channel for EPWM capture.
Definition: epwm.c:643
EPWM_FB_EDGE_SYS_BOD
#define EPWM_FB_EDGE_SYS_BOD
Definition: epwm.h:100
EPWM_EADCPSCCTL_PSCEN0_Msk
#define EPWM_EADCPSCCTL_PSCEN0_Msk
Definition: epwm_reg.h:6244
EPWM_ClearFaultDetectInt
void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Clear fault detect interrupt of selected channel.
Definition: epwm.c:1673
EPWM_EnableFaultDetectOutput
void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
Enable fault detect output of selected channel.
Definition: epwm.c:1558
EPWM_ClearAccInt
void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Clear interrupt flag accumulator interrupt of selected channel.
Definition: epwm.c:1064
EPWM_EnableFaultDetectMask
void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt)
Enable fault detect mask function of selected channel.
Definition: epwm.c:1617
EPWM_EnableDutyInt
void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
Enable duty interrupt of selected channel.
Definition: epwm.c:763
EPWM_EnableDACTrigger
void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Enable selected channel to trigger DAC.
Definition: epwm.c:412
EPWM_ConfigOutputChannel
uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type)...
Definition: epwm.c:134
EPWM_DisableCaptureInt
void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Disable capture interrupt of selected channel.
Definition: epwm.c:712
EPWM_CAPIF_CRLIF0_Msk
#define EPWM_CAPIF_CRLIF0_Msk
Definition: epwm_reg.h:6541
EPWM_FB_EDGE_SYS_CSS
#define EPWM_FB_EDGE_SYS_CSS
Definition: epwm.h:99
EPWM_FDSTS_FDIF0_Msk
#define EPWM_FDSTS_FDIF0_Msk
Definition: epwm_reg.h:6226
CLK
#define CLK
Definition: M480.h:368
EPWM_GetPeriodIntFlag
uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get period interrupt of selected channel.
Definition: epwm.c:929
EPWM_STATUS_CNTMAXF0_Msk
#define EPWM_STATUS_CNTMAXF0_Msk
Definition: epwm_reg.h:5890
EPWM_BNF_BRK0PINV_Msk
#define EPWM_BNF_BRK0PINV_Msk
Definition: epwm_reg.h:5284
EPWM_DUTY_INT_UP_COUNT_MATCH_CMP
#define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP
Definition: epwm.h:145
EPWM_DisableBrakeNoiseFilter
void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum)
Disable EPWM brake noise filter function.
Definition: epwm.c:1402
EPWM_SetClockSource
void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
Set EPWM clock source.
Definition: epwm.c:1362
EPWM_T
Definition: epwm_reg.h:71
EPWM_BNF_BK0SRC_Msk
#define EPWM_BNF_BK0SRC_Msk
Definition: epwm_reg.h:5299
EPWM_GetFaultBrakeIntFlag
uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
This function get fault brake interrupt flag of selected source.
Definition: epwm.c:870
EPWM_EnableADCTriggerPrescale
int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt)
Enable and configure trigger ADC prescale.
Definition: epwm.c:328
EPWM_GetAccInt
uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Get interrupt flag accumulator interrupt of selected channel.
Definition: epwm.c:1079
EPWM_FDCTL0_FDMSKEN_Msk
#define EPWM_FDCTL0_FDMSKEN_Msk
Definition: epwm_reg.h:6121
EPWM_EnablePDMA
void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
Enables PDMA transfer of selected channel for EPWM capture.
Definition: epwm.c:625
EPWM_DisablePeriodInt
void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable period interrupt of selected channel.
Definition: epwm.c:899
EPWM_FTCI_FTCMD0_Msk
#define EPWM_FTCI_FTCMD0_Msk
Definition: epwm_reg.h:6640
EPWM_SYNC_SFLTCNT_Msk
#define EPWM_SYNC_SFLTCNT_Msk
Definition: epwm_reg.h:4963
EPWM_DisableCapture
void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
Disable capture of selected channel(s)
Definition: epwm.c:574
EPWM_EADCPSC1_EADCPSC4_Msk
#define EPWM_EADCPSC1_EADCPSC4_Msk
Definition: epwm_reg.h:6274
EPWM_SYNC_SFLTCNT_Pos
#define EPWM_SYNC_SFLTCNT_Pos
Definition: epwm_reg.h:4962
EPWM_BNF_BRK0NFSEL_Msk
#define EPWM_BNF_BRK0NFSEL_Msk
Definition: epwm_reg.h:5278
EPWM_PDMACTL_CHEN0_1_Msk
#define EPWM_PDMACTL_CHEN0_1_Msk
Definition: epwm_reg.h:6460
EPWM_DisableFaultDetect
void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable fault detect of selected channel.
Definition: epwm.c:1544
EPWM_EnableBrakePinInverse
void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
Enable EPWM brake pin inverse function.
Definition: epwm.c:1416
EPWM_FTCI_FTCMU0_Msk
#define EPWM_FTCI_FTCMU0_Msk
Definition: epwm_reg.h:6631
EPWM_EnableZeroInt
void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Enable zero interrupt of selected channel.
Definition: epwm.c:943
EPWM_BRKCTL0_1_BRKAEVEN_Msk
#define EPWM_BRKCTL0_1_BRKAEVEN_Msk
Definition: epwm_reg.h:5347
EPWM_GetDutyIntFlag
uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get duty interrupt flag of selected channel.
Definition: epwm.c:807
EPWM_IFA0_IFAEN_Msk
#define EPWM_IFA0_IFAEN_Msk
Definition: epwm_reg.h:5947
EPWM_TRIGGER_DAC_COMPARE_DOWN
#define EPWM_TRIGGER_DAC_COMPARE_DOWN
Definition: epwm.h:89
EPWM_FDEN_FDCKS0_Msk
#define EPWM_FDEN_FDCKS0_Msk
Definition: epwm_reg.h:6100
EPWM_DisableFaultDetectMask
void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable fault detect mask function of selected channel.
Definition: epwm.c:1631
EPWM_BRKCTL0_1_SYSLBEN_Msk
#define EPWM_BRKCTL0_1_SYSLBEN_Msk
Definition: epwm_reg.h:5344
EPWM_INTEN0_PIEN0_Pos
#define EPWM_INTEN0_PIEN0_Pos
Definition: epwm_reg.h:5514
EPWM_DisableAcc
void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable interrupt flag accumulator of selected channel.
Definition: epwm.c:1022
EPWM_FB_LEVEL_SYS_CSS
#define EPWM_FB_LEVEL_SYS_CSS
Definition: epwm.h:109
EPWM_DisableADCTriggerPrescale
void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable Trigger ADC prescale function.
Definition: epwm.c:363
EPWM_CHANNEL_NUM
#define EPWM_CHANNEL_NUM
Definition: epwm.h:29
EPWM_WGCTL0_ZPCTL0_Msk
#define EPWM_WGCTL0_ZPCTL0_Msk
Definition: epwm_reg.h:5167
EPWM_STATUS_DACTRGF_Msk
#define EPWM_STATUS_DACTRGF_Msk
Definition: epwm_reg.h:5935
CLK_CLKSEL2_EPWM1SEL_Msk
#define CLK_CLKSEL2_EPWM1SEL_Msk
Definition: clk_reg.h:2556
EPWM_SYNC_PHSDIR0_Pos
#define EPWM_SYNC_PHSDIR0_Pos
Definition: epwm_reg.h:4968
EPWM_SET_CNR
#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR)
This macro set the period of the selected channel.
Definition: epwm.h:407
EPWM_FB_LEVEL_SYS_BOD
#define EPWM_FB_LEVEL_SYS_BOD
Definition: epwm.h:110
EPWM_WGCTL1_CMPDCTL0_Msk
#define EPWM_WGCTL1_CMPDCTL0_Msk
Definition: epwm_reg.h:5221
NuMicro.h
NuMicro peripheral access layer header file.
EPWM_IFA0_IFASEL_Pos
#define EPWM_IFA0_IFASEL_Pos
Definition: epwm_reg.h:5943
EPWM_EADCTS1_TRGEN4_Msk
#define EPWM_EADCTS1_TRGEN4_Msk
Definition: epwm_reg.h:5830
EPWM_SYNC_SFLTCSEL_Msk
#define EPWM_SYNC_SFLTCSEL_Msk
Definition: epwm_reg.h:4960
EPWM_SYNC_SFLTCSEL_Pos
#define EPWM_SYNC_SFLTCSEL_Pos
Definition: epwm_reg.h:4959
EPWM_WGCTL0_ZPCTL0_Pos
#define EPWM_WGCTL0_ZPCTL0_Pos
Definition: epwm_reg.h:5166
EPWM_IFA0_IFACNT_Msk
#define EPWM_IFA0_IFACNT_Msk
Definition: epwm_reg.h:5938
EPWM_EnableDeadZone
void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
Enable Dead zone of selected channel.
Definition: epwm.c:660
EPWM_FDIEN_FDIEN0_Msk
#define EPWM_FDIEN_FDIEN0_Msk
Definition: epwm_reg.h:6208
EPWM_BRKCTL0_1_BRKAODD_Msk
#define EPWM_BRKCTL0_1_BRKAODD_Msk
Definition: epwm_reg.h:5350
EPWM_BRKCTL0_1_SYSEBEN_Msk
#define EPWM_BRKCTL0_1_SYSEBEN_Msk
Definition: epwm_reg.h:5329
EPWM_EnableAccInt
void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Enable interrupt flag accumulator interrupt of selected channel.
Definition: epwm.c:1036
EPWM_TRIGGER_DAC_COMPARE_UP
#define EPWM_TRIGGER_DAC_COMPARE_UP
Definition: epwm.h:88
EPWM_ConfigSyncPhase
void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
Configure synchronization phase of selected channel.
Definition: epwm.c:1225
EPWM_SET_PRESCALER
#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler)
This macro set the prescaler of the selected channel.
Definition: epwm.h:348
EPWM_EnableSyncNoiseFilter
void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
Enable EPWM SYNC_IN noise filter function.
Definition: epwm.c:1300
EPWM_DisableFaultDetectInt
void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable fault detect interrupt of selected channel.
Definition: epwm.c:1659
EPWM_DisableZeroInt
void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable zero interrupt of selected channel.
Definition: epwm.c:957
EPWM_GetFaultDetectInt
uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Get fault detect interrupt of selected channel.
Definition: epwm.c:1688
EPWM_DisableSyncPhase
void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
Disable SYNC phase of selected channel(s)
Definition: epwm.c:1269
EPWM_ClearZeroIntFlag
void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Clear zero interrupt of selected channel.
Definition: epwm.c:971
EPWM_OUTPUT_HIGH
#define EPWM_OUTPUT_HIGH
Definition: epwm.h:55
EPWM_BRKCTL0_1_BRKAODD_Pos
#define EPWM_BRKCTL0_1_BRKAODD_Pos
Definition: epwm_reg.h:5349
EPWM_ClearADCTriggerFlag
void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Clear selected channel trigger ADC flag.
Definition: epwm.c:378
EPWM_INTSTS0_PIF0_Pos
#define EPWM_INTSTS0_PIF0_Pos
Definition: epwm_reg.h:5604
EPWM_GetZeroIntFlag
uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get zero interrupt of selected channel.
Definition: epwm.c:987
EPWM_EnableAccStopMode
void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
Enable interrupt flag accumulator stop mode of selected channel.
Definition: epwm.c:1121
EPWM_EnableFaultDetectInt
void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Enable fault detect interrupt of selected channel.
Definition: epwm.c:1645
CLK_GetPCLK1Freq
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:204
EPWM_CTL1_CNTMODE0_Msk
#define EPWM_CTL1_CNTMODE0_Msk
Definition: epwm_reg.h:4912
EPWM_ClearFTDutyIntFlag
void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Clear free trigger duty interrupt flag of selected channel.
Definition: epwm.c:1149
EPWM_DisableAccPDMA
void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable accumulator PDMA of selected channel.
Definition: epwm.c:1107
EPWM_WGCTL1_CMPUCTL0_Msk
#define EPWM_WGCTL1_CMPUCTL0_Msk
Definition: epwm_reg.h:5203
CLK_GetPCLK0Freq
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:164
EPWM_FDCTL0_DGSMPCYC_Msk
#define EPWM_FDCTL0_DGSMPCYC_Msk
Definition: epwm_reg.h:6124
EPWM_CTL1_CNTMODE0_Pos
#define EPWM_CTL1_CNTMODE0_Pos
Definition: epwm_reg.h:4911
EPWM_FB_EDGE_SYS_RAM
#define EPWM_FB_EDGE_SYS_RAM
Definition: epwm.h:101
EPWM_EADCTS0_TRGSEL0_Msk
#define EPWM_EADCTS0_TRGSEL0_Msk
Definition: epwm_reg.h:5803
EPWM_EnableFaultBrake
void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
This function enable fault brake of selected channel(s)
Definition: epwm.c:493
EPWM_DisableFaultDetectDeglitch
void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable fault detect deglitch function of selected channel.
Definition: epwm.c:1602
EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
#define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
Definition: epwm.h:144
EPWM_EnableCaptureInt
void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Enable capture interrupt of selected channel.
Definition: epwm.c:695
EPWM_EADCPSC0_EADCPSC0_Msk
#define EPWM_EADCPSC0_EADCPSC0_Msk
Definition: epwm_reg.h:6262
EPWM_DisableDACTrigger
void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable selected channel to trigger DAC.
Definition: epwm.c:426
EPWM_GetCaptureIntFlag
uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get capture interrupt of selected channel.
Definition: epwm.c:746
EPWM_DisableSyncPinInverse
void EPWM_DisableSyncPinInverse(EPWM_T *epwm)
Disable EPWM SYNC input pin inverse function.
Definition: epwm.c:1340
EPWM_DisableFaultBrakeInt
void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
This function disable fault brake interrupt.
Definition: epwm.c:839
EPWM_ClearFaultBrakeIntFlag
void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
This function clear fault brake interrupt of selected source.
Definition: epwm.c:854
EPWM_ClearWrapAroundFlag
void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Clear the time-base counter reached its maximum value flag of selected channel.
Definition: epwm.c:1508
EPWM_SET_CMR
#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR)
This macro set the comparator of the selected channel.
Definition: epwm.h:372
EPWM_FDCTL0_DGSMPCYC_Pos
#define EPWM_FDCTL0_DGSMPCYC_Pos
Definition: epwm_reg.h:6123
EPWM_CTL1_CNTTYPE0_Msk
#define EPWM_CTL1_CNTTYPE0_Msk
Definition: epwm_reg.h:4894
EPWM_SetBrakePinSource
void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
Set EPWM brake pin source.
Definition: epwm.c:1445
EPWM_IFA0_IFASEL_Msk
#define EPWM_IFA0_IFASEL_Msk
Definition: epwm_reg.h:5944
EPWM_DisableAccStopMode
void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable interrupt flag accumulator stop mode of selected channel.
Definition: epwm.c:1135
EPWM_ForceStop
void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
Stop EPWM generation immediately by clear channel enable bit.
Definition: epwm.c:248
EPWM_DTCTL0_1_DTCNT_Msk
#define EPWM_DTCTL0_1_DTCNT_Msk
Definition: epwm_reg.h:5095
EPWM_PDMACTL_CHSEL0_1_Pos
#define EPWM_PDMACTL_CHSEL0_1_Pos
Definition: epwm_reg.h:6468
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1188
EPWM_TRIGGER_DAC_ZERO
#define EPWM_TRIGGER_DAC_ZERO
Definition: epwm.h:86
EPWM_BNF_BRK1NFEN_Pos
#define EPWM_BNF_BRK1NFEN_Pos
Definition: epwm_reg.h:5286
EPWM_FDCTL0_FDDGEN_Msk
#define EPWM_FDCTL0_FDDGEN_Msk
Definition: epwm_reg.h:6130
EPWM_BRKCTL0_1_BRKAEVEN_Pos
#define EPWM_BRKCTL0_1_BRKAEVEN_Pos
Definition: epwm_reg.h:5346
EPWM_CAPIF_CFLIF0_Msk
#define EPWM_CAPIF_CFLIF0_Msk
Definition: epwm_reg.h:6559
EPWM_DisableDutyInt
void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable duty interrupt of selected channel.
Definition: epwm.c:777
EPWM_SYNC_SINSRC0_Pos
#define EPWM_SYNC_SINSRC0_Pos
Definition: epwm_reg.h:4947
EPWM_GetWrapAroundFlag
uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get the time-base counter reached its maximum value flag of selected channel.
Definition: epwm.c:1494
EPWM_SYNC_PHSEN0_Pos
#define EPWM_SYNC_PHSEN0_Pos
Definition: epwm_reg.h:4938
EPWM_DisableLoadMode
void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Disable load mode of selected channel.
Definition: epwm.c:1201
EPWM_EnableSyncPhase
void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
Enable SYNC phase of selected channel(s)
Definition: epwm.c:1246
EPWM_EnableBrakeNoiseFilter
void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
Enable EPWM brake noise filter function.
Definition: epwm.c:1387
EPWM_INTEN0_ZIEN0_Pos
#define EPWM_INTEN0_ZIEN0_Pos
Definition: epwm_reg.h:5496
EPWM_ClearDutyIntFlag
void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Clear duty interrupt flag of selected channel.
Definition: epwm.c:791
EPWM_INTSTS0_CMPDIF0_Msk
#define EPWM_INTSTS0_CMPDIF0_Msk
Definition: epwm_reg.h:5641
EPWM_SYNC_SINPINV_Msk
#define EPWM_SYNC_SINPINV_Msk
Definition: epwm_reg.h:4966
EPWM_EnableADCTrigger
void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Enable selected channel to trigger ADC.
Definition: epwm.c:279
EPWM_EADCPSCNT1_PSCNT4_Msk
#define EPWM_EADCPSCNT1_PSCNT4_Msk
Definition: epwm_reg.h:6292
EPWM_PDMACTL_CAPMOD0_1_Msk
#define EPWM_PDMACTL_CAPMOD0_1_Msk
Definition: epwm_reg.h:6463
EPWM_SYNC_SNFLTEN_Msk
#define EPWM_SYNC_SNFLTEN_Msk
Definition: epwm_reg.h:4957
EPWM_PDMACTL_CAPORD0_1_Msk
#define EPWM_PDMACTL_CAPORD0_1_Msk
Definition: epwm_reg.h:6466
EPWM_FDEN_FDODIS0_Msk
#define EPWM_FDEN_FDODIS0_Msk
Definition: epwm_reg.h:6082
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
Definition: system_M480.c:29
EPWM_DisableOutput
void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
Disables EPWM output generation of selected channel(s)
Definition: epwm.c:605
EPWM_BNF_BRK0NFSEL_Pos
#define EPWM_BNF_BRK0NFSEL_Pos
Definition: epwm_reg.h:5277
EPWM_ClearCaptureIntFlag
void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Clear capture interrupt of selected channel.
Definition: epwm.c:729
EPWM_BNF_BRK0FCNT_Msk
#define EPWM_BNF_BRK0FCNT_Msk
Definition: epwm_reg.h:5281
EPWM_EADCPSCNT0_PSCNT0_Msk
#define EPWM_EADCPSCNT0_PSCNT0_Msk
Definition: epwm_reg.h:6280
EPWM_WGCTL1_CMPUCTL0_Pos
#define EPWM_WGCTL1_CMPUCTL0_Pos
Definition: epwm_reg.h:5202
EPWM_GetADCTriggerFlag
uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get selected channel trigger ADC flag.
Definition: epwm.c:393
EPWM_EnableOutput
void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
Enables EPWM output generation of selected channel(s)
Definition: epwm.c:590
EPWM_GetFTDutyIntFlag
uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get free trigger duty interrupt flag of selected channel.
Definition: epwm.c:1165
EPWM_CLKSRC_ECLKSRC0_Msk
#define EPWM_CLKSRC_ECLKSRC0_Msk
Definition: epwm_reg.h:4987
EPWM_FDEN_FDEN0_Msk
#define EPWM_FDEN_FDEN0_Msk
Definition: epwm_reg.h:6064
EPWM_FDCTL0_FDCKSEL_Msk
#define EPWM_FDCTL0_FDCKSEL_Msk
Definition: epwm_reg.h:6127
EPWM_WGCTL0_PRDPCTL0_Msk
#define EPWM_WGCTL0_PRDPCTL0_Msk
Definition: epwm_reg.h:5185
EPWM_INTSTS0_CMPUIF0_Msk
#define EPWM_INTSTS0_CMPUIF0_Msk
Definition: epwm_reg.h:5623
EPWM_EnableFaultDetect
void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel)
Enable fault detect of selected channel.
Definition: epwm.c:1528
CLK_CLKSEL2_EPWM0SEL_Msk
#define CLK_CLKSEL2_EPWM0SEL_Msk
Definition: clk_reg.h:2553
EPWM_DisableSyncNoiseFilter
void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm)
Disable EPWM SYNC_IN noise filter function.
Definition: epwm.c:1314
EPWM_EnablePeriodInt
void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
Enable period interrupt of selected channel.
Definition: epwm.c:885
EPWM_EnableFaultBrakeInt
void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
This function enable fault brake interrupt.
Definition: epwm.c:823
EPWM0
#define EPWM0
Definition: M480.h:415
EPWM_FB_LEVEL_SYS_COR
#define EPWM_FB_LEVEL_SYS_COR
Definition: epwm.h:112
EPWM_Stop
void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
Stop EPWM module.
Definition: epwm.c:226
EPWM_BNF_BRK0NFEN_Msk
#define EPWM_BNF_BRK0NFEN_Msk
Definition: epwm_reg.h:5275
EPWM_IFA0_STPMOD_Msk
#define EPWM_IFA0_STPMOD_Msk
Definition: epwm_reg.h:5941
EPWM_PDMACTL_CHSEL0_1_Msk
#define EPWM_PDMACTL_CHSEL0_1_Msk
Definition: epwm_reg.h:6469
EPWM_FDCTL0_TRMSKCNT_Msk
#define EPWM_FDCTL0_TRMSKCNT_Msk
Definition: epwm_reg.h:6118
EPWM_PDMACTL_CAPORD0_1_Pos
#define EPWM_PDMACTL_CAPORD0_1_Pos
Definition: epwm_reg.h:6465
EPWM_DisableDeadZone
void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable Dead zone of selected channel.
Definition: epwm.c:677
EPWM_BNF_BRK0FCNT_Pos
#define EPWM_BNF_BRK0FCNT_Pos
Definition: epwm_reg.h:5280
EPWM_DTCTL0_1_DTEN_Msk
#define EPWM_DTCTL0_1_DTEN_Msk
Definition: epwm_reg.h:5098
EPWM_BNF_BK0SRC_Pos
#define EPWM_BNF_BK0SRC_Pos
Definition: epwm_reg.h:5298
EPWM_ClearPeriodIntFlag
void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Clear period interrupt of selected channel.
Definition: epwm.c:913
EPWM_ClearDACTriggerFlag
void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Clear selected channel trigger DAC flag.
Definition: epwm.c:442
EPWM_EnableAccPDMA
void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
Enable accumulator PDMA of selected channel.
Definition: epwm.c:1093
EPWM_Start
void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
Start EPWM module.
Definition: epwm.c:211
EPWM_DisableAccInt
void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable interrupt flag accumulator interrupt of selected channel.
Definition: epwm.c:1050
EPWM_EnableCapture
void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
Enable capture of selected channel(s)
Definition: epwm.c:558
EPWM_DisableFaultDetectOutput
void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable fault detect output of selected channel.
Definition: epwm.c:1572
EPWM_EnableLoadMode
void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Enable load mode of selected channel.
Definition: epwm.c:1183
EPWM_TRIGGER_DAC_PERIOD
#define EPWM_TRIGGER_DAC_PERIOD
Definition: epwm.h:87
EPWM_OUTPUT_LOW
#define EPWM_OUTPUT_LOW
Definition: epwm.h:54
EPWM_FB_LEVEL_SYS_RAM
#define EPWM_FB_LEVEL_SYS_RAM
Definition: epwm.h:111
EPWM_EnableFaultDetectDeglitch
void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle)
Enable fault detect deglitch function of selected channel.
Definition: epwm.c:1587
EPWM_DisableBrakePinInverse
void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
Disable EPWM brake pin inverse function.
Definition: epwm.c:1430
EPWM_FB_EDGE_SYS_COR
#define EPWM_FB_EDGE_SYS_COR
Definition: epwm.h:102
EPWM_SetLeadingEdgeBlanking
void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable)
Set EPWM leading edge blanking function.
Definition: epwm.c:1476
EPWM_EnableAcc
void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
Enable interrupt flag accumulator of selected channel.
Definition: epwm.c:1007
EPWM_FDEN_FDCKS0_Pos
#define EPWM_FDEN_FDCKS0_Pos
Definition: epwm_reg.h:6099
EPWM_EnableSyncPinInverse
void EPWM_EnableSyncPinInverse(EPWM_T *epwm)
Enable EPWM SYNC input pin inverse function.
Definition: epwm.c:1327
EPWM_STATUS_EADCTRGF0_Msk
#define EPWM_STATUS_EADCTRGF0_Msk
Definition: epwm_reg.h:5917
EPWM_ConfigCaptureChannel
uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
Configure EPWM capture and get the nearest unit time.
Definition: epwm.c:36
EPWM_DisableADCTrigger
void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
Disable selected channel to trigger ADC.
Definition: epwm.c:302
EPWM_EADCTS0_TRGEN0_Msk
#define EPWM_EADCTS0_TRGEN0_Msk
Definition: epwm_reg.h:5806
EPWM_GetDACTriggerFlag
uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
Get selected channel trigger DAC flag.
Definition: epwm.c:457
EPWM_EADCTS1_TRGSEL4_Msk
#define EPWM_EADCTS1_TRGSEL4_Msk
Definition: epwm_reg.h:5827