| M480 BSP V3.05.001 The Board Support Package for M480 Series

spi.h
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1 /**************************************************************************/
9 #ifndef __SPI_H__
10 #define __SPI_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
30 #define SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
31 #define SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
32 #define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
33 #define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
35 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk)
36 #define SPI_MASTER (0x0U)
38 #define SPI_SS (SPI_SSCTL_SS_Msk)
39 #define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
40 #define SPI_SS_ACTIVE_LOW (0x0U)
42 /* SPI Interrupt Mask */
43 #define SPI_UNIT_INT_MASK (0x001U)
44 #define SPI_SSACT_INT_MASK (0x002U)
45 #define SPI_SSINACT_INT_MASK (0x004U)
46 #define SPI_SLVUR_INT_MASK (0x008U)
47 #define SPI_SLVBE_INT_MASK (0x010U)
48 #define SPI_TXUF_INT_MASK (0x040U)
49 #define SPI_FIFO_TXTH_INT_MASK (0x080U)
50 #define SPI_FIFO_RXTH_INT_MASK (0x100U)
51 #define SPI_FIFO_RXOV_INT_MASK (0x200U)
52 #define SPI_FIFO_RXTO_INT_MASK (0x400U)
54 /* SPI Status Mask */
55 #define SPI_BUSY_MASK (0x01U)
56 #define SPI_RX_EMPTY_MASK (0x02U)
57 #define SPI_RX_FULL_MASK (0x04U)
58 #define SPI_TX_EMPTY_MASK (0x08U)
59 #define SPI_TX_FULL_MASK (0x10U)
60 #define SPI_TXRX_RESET_MASK (0x20U)
61 #define SPI_SPIEN_STS_MASK (0x40U)
62 #define SPI_SSLINE_STS_MASK (0x80U)
65 /* I2S Data Width */
66 #define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos)
67 #define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos)
68 #define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos)
69 #define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos)
71 /* I2S Audio Format */
72 #define SPII2S_MONO SPI_I2SCTL_MONO_Msk
73 #define SPII2S_STEREO (0U)
75 /* I2S Data Format */
76 #define SPII2S_FORMAT_I2S (0U<<SPI_I2SCTL_FORMAT_Pos)
77 #define SPII2S_FORMAT_MSB (1U<<SPI_I2SCTL_FORMAT_Pos)
78 #define SPII2S_FORMAT_PCMA (2U<<SPI_I2SCTL_FORMAT_Pos)
79 #define SPII2S_FORMAT_PCMB (3U<<SPI_I2SCTL_FORMAT_Pos)
81 /* I2S Operation mode */
82 #define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk
83 #define SPII2S_MODE_MASTER (0U)
85 /* I2S Record Channel */
86 #define SPII2S_MONO_RIGHT (0U)
87 #define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk
89 /* I2S Channel */
90 #define SPII2S_RIGHT (0U)
91 #define SPII2S_LEFT (1U)
93 /* I2S Interrupt Mask */
94 #define SPII2S_FIFO_TXTH_INT_MASK (0x01U)
95 #define SPII2S_FIFO_RXTH_INT_MASK (0x02U)
96 #define SPII2S_FIFO_RXOV_INT_MASK (0x04U)
97 #define SPII2S_FIFO_RXTO_INT_MASK (0x08U)
98 #define SPII2S_TXUF_INT_MASK (0x10U)
99 #define SPII2S_RIGHT_ZC_INT_MASK (0x20U)
100 #define SPII2S_LEFT_ZC_INT_MASK (0x40U)
102 /* end of group SPI_EXPORTED_CONSTANTS */
103
104
116 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
117
125 #define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
126
134 #define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
135
143 #define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk))
144
152 #define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
153
161 #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
162
170 #define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
171
179 #define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
180
189 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
190
199 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
200
209 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
210
218 #define SPI_READ_RX(spi) ((spi)->RX)
219
228 #define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
229
237 #define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
238
246 #define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
247
255 #define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
256
264 #define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
265
275 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
276
284 #define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
285
293 #define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
294
303 #define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
304
313 #define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
314
322 #define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
323
331 #define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
332
333 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
334 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
335 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
336 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
337
347 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
348 {
349 if(u32ChMask == SPII2S_RIGHT)
350 {
351 i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
352 }
353 else
354 {
355 i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
356 }
357 }
358
368 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
369 {
370 if(u32ChMask == SPII2S_RIGHT)
371 {
372 i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
373 }
374 else
375 {
376 i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
377 }
378 }
379
387 #define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
388
396 #define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
397
405 #define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
406
414 #define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
415
423 #define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
424
432 #define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
433
441 #define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
442
450 #define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
451
459 #define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
460
468 #define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
469
477 #define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
478
486 #define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
487
498 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
499 {
500 u32Ch == SPII2S_MONO_LEFT ?
501 (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
502 (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
503 }
504
513 #define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
514
522 #define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
523
532 #define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
533
543 #define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
544
552 #define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
553
561 #define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
562
563
564
565 /* Function prototype declaration */
566 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
567 void SPI_Close(SPI_T *spi);
568 void SPI_ClearRxFIFO(SPI_T *spi);
569 void SPI_ClearTxFIFO(SPI_T *spi);
570 void SPI_DisableAutoSS(SPI_T *spi);
571 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
572 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
573 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
574 uint32_t SPI_GetBusClock(SPI_T *spi);
575 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
576 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
577 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
578 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
579 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
580
581 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
582 void SPII2S_Close(SPI_T *i2s);
583 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
584 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
585 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
586 void SPII2S_DisableMCLK(SPI_T *i2s);
587 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
588
589 /* end of group SPI_EXPORTED_FUNCTIONS */
591 /* end of group SPI_Driver */
593 /* end of group Standard_Driver */
595
596 #ifdef __cplusplus
597 }
598 #endif
599
600 #endif
601
602 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
SPI_I2SCTL_LZCEN_Msk
#define SPI_I2SCTL_LZCEN_Msk
Definition: spi_reg.h:1305
SPI_I2SCTL_RXLCH_Msk
#define SPI_I2SCTL_RXLCH_Msk
Definition: spi_reg.h:1308
SPII2S_DisableMCLK
void SPII2S_DisableMCLK(SPI_T *i2s)
Disable master clock (MCLK).
Definition: spi.c:1417
SPII2S_DISABLE_TX_ZCD
__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
Disable zero cross detection function.
Definition: spi.h:368
SPI_I2SCTL_RZCEN_Msk
#define SPI_I2SCTL_RZCEN_Msk
Definition: spi_reg.h:1302
SPII2S_Open
uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
This function configures some parameters of I2S interface for general purpose use.
Definition: spi.c:1133
SPII2S_Close
void SPII2S_Close(SPI_T *i2s)
Disable I2S function.
Definition: spi.c:1240
SPII2S_RIGHT
#define SPII2S_RIGHT
Definition: spi.h:90
SPI_T
Definition: spi_reg.h:26
SPI_Close
void SPI_Close(SPI_T *spi)
Disable SPI controller.
Definition: spi.c:259
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock.
Definition: spi.c:347
SPII2S_MONO_LEFT
#define SPII2S_MONO_LEFT
Definition: spi.h:87
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear RX FIFO buffer.
Definition: spi.c:293
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear TX FIFO buffer.
Definition: spi.c:305
SPI_GetIntFlag
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
Get interrupt flag.
Definition: spi.c:793
SPI_ClearIntFlag
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
Clear interrupt flag.
Definition: spi.c:888
SPI_GetStatus
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
Get SPI status.
Definition: spi.c:949
SPII2S_EnableMCLK
uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
Enable master clock (MCLK).
Definition: spi.c:1373
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer.
Definition: spi.c:44
SPII2S_ENABLE_TX_ZCD
__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
Enable zero cross detection function.
Definition: spi.h:347
SPII2S_SET_MONO_RX_CHANNEL
__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
This function sets the recording source channel when mono mode is used.
Definition: spi.h:498
SPII2S_DisableInt
void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
Disable interrupt function.
Definition: spi.c:1320
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave selection function.
Definition: spi.c:316
SPII2S_EnableInt
void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
Enable interrupt function.
Definition: spi.c:1260
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave selection function.
Definition: spi.c:330
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable interrupt function.
Definition: spi.c:627
SPI_T::I2SCTL
__IO uint32_t I2SCTL
Definition: spi_reg.h:1086
SPI_SetFIFO
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
Definition: spi.c:500
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:513
SPII2S_SetFIFO
void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
Definition: spi.c:1430
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable interrupt function.
Definition: spi.c:710