| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
QSPI_T Struct Reference
Control Register

`#include <qspi_reg.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | CLKDIV
__IO uint32_t | SSCTL
__IO uint32_t | PDMACTL
__IO uint32_t | FIFOCTL
__IO uint32_t | STATUS
__O uint32_t | TX
__I uint32_t | RX

## Detailed Description

    @addtogroup QSPI Serial Peripheral Interface Controller(QSPI)
    Memory Mapped Structure for QSPI Controller

Definition at line 26 of file qspi_reg.h.

## Field Documentation

## ◆ CLKDIV

QSPI_T::CLKDIV

[0x0004] QSPI Clock Divider Register

CLKDIV

Offset: 0x04 QSPI Clock Divider Register

Bits | Field | Descriptions
[8:0] | DIVIDER | Clock Divider The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master The frequency is obtained according to the following equation. where is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.

Definition at line 786 of file qspi_reg.h.

## ◆ CTL

QSPI_T::CTL

[0x0000] QSPI Control Register

CTL

Offset: 0x00 QSPI Control Register

Bits | Field | Descriptions
[0] | QSPIEN | QSPI Transfer Control Enable Bit In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 In Slave mode, this device is ready to receive data when this bit is set to 1. 0 = Transfer control Disabled. 1 = Transfer control Enabled. Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0.
[1] | RXNEG | Receive on Negative Edge 0 = Received data input signal is latched on the rising edge of QSPI bus clock. 1 = Received data input signal is latched on the falling edge of QSPI bus clock.
[2] | TXNEG | Transmit on Negative Edge 0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. 1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
[3] | CLKPOL | Clock Polarity 0 = QSPI bus clock is idle low. 1 = QSPI bus clock is idle high.
[7:4] | SUSPITV | Suspend Interval (Master Only) The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word The default value is 0x3 The period of the suspend interval is obtained according to the following equation. (SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle Example: SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. ..... SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
[12:8] | DWIDTH | Data Width This field specifies how many bits can be transmitted / received in one transaction The minimum bit length is 8 bits and can up to 32 bits. DWIDTH = 0x08 .... 8 bits. DWIDTH = 0x09 .... 9 bits. ..... DWIDTH = 0x1F .... 31 bits. DWIDTH = 0x00 .... 32 bits.
[13] | LSB | Send LSB First 0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. 1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
[14] | HALFDPX | QSPI Half-duplex Transfer Enable Bit This bit is used to select full-duplex or half-duplex for QSPI transfer The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 0 = QSPI operates in full-duplex transfer. 1 = QSPI operates in half-duplex transfer.
[15] | RXONLY | Receive-only Mode Enable Bit (Master Only) This bit field is only available in Master mode In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. 0 = Receive-only mode Disabled. 1 = Receive-only mode Enabled.
[16] | TWOBIT | 2-bit Transfer Mode Enable Bit (Only Supported in QSPI0) 0 = 2-Bit Transfer mode Disabled. 1 = 2-Bit Transfer mode Enabled. Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
[17] | UNITIEN | Unit Transfer Interrupt Enable Bit 0 = QSPI unit transfer interrupt Disabled. 1 = QSPI unit transfer interrupt Enabled.
[18] | SLAVE | Slave Mode Control 0 = Master mode. 1 = Slave mode.
[19] | REORDER | Byte Reorder Function Enable Bit 0 = Byte Reorder function Disabled. 1 = Byte Reorder function Enabled A byte suspend interval will be inserted among each byte The period of the byte suspend interval depends on the setting of SUSPITV. Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
[20] | DATDIR | Data Port Direction Control This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 0 = QSPI data is input direction. 1 = QSPI data is output direction.
[21] | DUALIOEN | Dual I/O Mode Enable Bit (Only Supported in QSPI0) 0 = Dual I/O mode Disabled. 1 = Dual I/O mode Enabled.
[22] | QUADIOEN | Quad I/O Mode Enable Bit (Only Supported in QSPI0) 0 = Quad I/O mode Disabled. 1 = Quad I/O mode Enabled.

Definition at line 785 of file qspi_reg.h.

## ◆ FIFOCTL

QSPI_T::FIFOCTL

[0x0010] QSPI FIFO Control Register

FIFOCTL

Offset: 0x10 QSPI FIFO Control Register

Bits | Field | Descriptions
[0] | RXRST | Receive Reset 0 = No effect. 1 = Reset receive FIFO pointer and receive circuit The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
[1] | TXRST | Transmit Reset 0 = No effect. 1 = Reset transmit FIFO pointer and transmit circuit The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
[2] | RXTHIEN | Receive FIFO Threshold Interrupt Enable Bit 0 = RX FIFO threshold interrupt Disabled. 1 = RX FIFO threshold interrupt Enabled.
[3] | TXTHIEN | Transmit FIFO Threshold Interrupt Enable Bit 0 = TX FIFO threshold interrupt Disabled. 1 = TX FIFO threshold interrupt Enabled.
[4] | RXTOIEN | Slave Receive Time-out Interrupt Enable Bit 0 = Receive time-out interrupt Disabled. 1 = Receive time-out interrupt Enabled.
[5] | RXOVIEN | Receive FIFO Overrun Interrupt Enable Bit 0 = Receive FIFO overrun interrupt Disabled. 1 = Receive FIFO overrun interrupt Enabled.
[6] | TXUFPOL | TX Underflow Data Polarity 0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode. 1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode. Note: 1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
[7] | TXUFIEN | TX Underflow Interrupt Enable Bit When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 This bit is used to enable the TX underflow interrupt. 0 = Slave TX underflow interrupt Disabled. 1 = Slave TX underflow interrupt Enabled.
[8] | RXFBCLR | Receive FIFO Buffer Clear 0 = No effect. 1 = Clear receive FIFO pointer The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. Note: The RX shift register will not be cleared.
[9] | TXFBCLR | Transmit FIFO Buffer Clear 0 = No effect. 1 = Clear transmit FIFO pointer The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. Note: The TX shift register will not be cleared.
[26:24] | RXTH | Receive FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
[30:28] | TXTH | Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0

Definition at line 789 of file qspi_reg.h.

## ◆ PDMACTL

QSPI_T::PDMACTL

[0x000c] QSPI PDMA Control Register

PDMACTL

Offset: 0x0C QSPI PDMA Control Register

Bits | Field | Descriptions
[0] | TXPDMAEN | Transmit PDMA Enable Bit 0 = Transmit PDMA function Disabled. 1 = Transmit PDMA function Enabled. Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function User can enable TX PDMA function firstly or enable both functions simultaneously.
[1] | RXPDMAEN | Receive PDMA Enable Bit 0 = Receive PDMA function Disabled. 1 = Receive PDMA function Enabled.
[2] | PDMARST | PDMA Reset 0 = No effect. 1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.

Definition at line 788 of file qspi_reg.h.

## ◆ RX

QSPI_T::RX

[0x0030] QSPI Data Receive Register

RX

Offset: 0x30 QSPI Data Receive Register

Bits | Field | Descriptions
[31:0] | RX | Data Receive Register There are 4-level FIFO buffers in this controller The data receive register holds the data received from QSPI data input pin This is a read only register.

Definition at line 798 of file qspi_reg.h.

## ◆ SSCTL

QSPI_T::SSCTL

[0x0008] QSPI Slave Select Control Register

SSCTL

Offset: 0x08 QSPI Slave Select Control Register

Bits | Field | Descriptions
[0] | SS | Slave Selection Control (Master Only) If AUTOSS bit is cleared to 0, 0 = set the QSPIx_SS line to inactive state. 1 = set the QSPIx_SS line to active state. If the AUTOSS bit is set to 1, 0 = Keep the QSPIx_SS line at inactive state. 1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
[2] | SSACTPOL | Slave Selection Active Polarity This bit defines the active polarity of slave selection signal (QSPIx_SS). 0 = The slave selection signal QSPIx_SS is active low. 1 = The slave selection signal QSPIx_SS is active high.
[3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) 0 = Automatic slave selection function Disabled Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). 1 = Automatic slave selection function Enabled.
[4] | SLV3WIRE | Slave 3-wire Mode Enable Bit (Only Supported in QSPI0) Slave 3-wire mode is only available in QSPI0 In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. 0 = 4-wire bi-direction interface. 1 = 3-wire bi-direction interface.
[5] | SLVTOIEN | Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0) 0 = Slave mode time-out interrupt Disabled. 1 = Slave mode time-out interrupt Enabled.
[6] | SLVTORST | Slave Mode Time-out Reset Control (Only Supported in QSPI0) 0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. 1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
[8] | SLVBEIEN | Slave Mode Bit Count Error Interrupt Enable Bit 0 = Slave mode bit count error interrupt Disabled. 1 = Slave mode bit count error interrupt Enabled.
[9] | SLVURIEN | Slave Mode TX Under Run Interrupt Enable Bit 0 = Slave mode TX under run interrupt Disabled. 1 = Slave mode TX under run interrupt Enabled.
[12] | SSACTIEN | Slave Select Active Interrupt Enable Bit 0 = Slave select active interrupt Disabled. 1 = Slave select active interrupt Enabled.
[13] | SSINAIEN | Slave Select Inactive Interrupt Enable Bit 0 = Slave select inactive interrupt Disabled. 1 = Slave select inactive interrupt Enabled.
[31:16] | SLVTOCNT | Slave Mode Time-out Period (Only Supported in QSPI0) In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active The clock source of the time-out counter is Slave peripheral clock If the value is 0, it indicates the slave mode time-out function is disabled.

Definition at line 787 of file qspi_reg.h.

## ◆ STATUS

QSPI_T::STATUS

[0x0014] QSPI Status Register

STATUS

Offset: 0x14 QSPI Status Register

Bits | Field | Descriptions
[0] | BUSY | Busy Status (Read Only) 0 = QSPI controller is in idle state. 1 = QSPI controller is in busy state. The following listing are the bus busy conditions: a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. b For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. d For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
[1] | UNITIF | Unit Transfer Interrupt Flag 0 = No transaction has been finished since this bit was cleared to 0. 1 = QSPI controller has finished one unit transfer. Note: This bit will be cleared by writing 1 to it.
[2] | SSACTIF | Slave Select Active Interrupt Flag 0 = Slave select active interrupt was cleared or not occurred. 1 = Slave select active interrupt event occurred. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
[3] | SSINAIF | Slave Select Inactive Interrupt Flag 0 = Slave select inactive interrupt was cleared or not occurred. 1 = Slave select inactive interrupt event occurred. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
[4] | SSLINE | Slave Select Line Bus Status (Read Only) 0 = The slave select line status is 0. 1 = The slave select line status is 1. Note: This bit is only available in Slave mode If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
[5] | SLVTOIF | Slave Time-out Interrupt Flag (Only Supported in QSPI0) When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. 0 = Slave time-out is not active. 1 = Slave time-out is active. Note: This bit will be cleared by writing 1 to it.
[6] | SLVBEIF | Slave Mode Bit Count Error Interrupt Flag In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. 0 = No Slave mode bit count error event. 1 = Slave mode bit count error event occurs. Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state This bit will be cleared by writing 1 to it.
[7] | SLVURIF | Slave Mode TX Under Run Interrupt Flag In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. 0 = No Slave TX under run event. 1 = Slave TX under run event occurs. Note: This bit will be cleared by writing 1 to it.
[8] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) 0 = Receive FIFO buffer is not empty. 1 = Receive FIFO buffer is empty.
[9] | RXFULL | Receive FIFO Buffer Full Indicator (Read Only) 0 = Receive FIFO buffer is not full. 1 = Receive FIFO buffer is full.
[10] | RXTHIF | Receive FIFO Threshold Interrupt Flag (Read Only) 0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
[11] | RXOVIF | Receive FIFO Overrun Interrupt Flag When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 0 = No FIFO is overrun. 1 = Receive FIFO is overrun. Note: This bit will be cleared by writing 1 to it.
[12] | RXTOIF | Receive Time-out Interrupt Flag 0 = No receive FIFO time-out event. 1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode When the received FIFO buffer is read by software, the time-out status will be cleared automatically. Note: This bit will be cleared by writing 1 to it.
[15] | QSPIENSTS | QSPI Enable Status (Read Only) 0 = The QSPI controller is disabled. 1 = The QSPI controller is enabled. Note: The QSPI peripheral clock is asynchronous with the system clock In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
[16] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) 0 = Transmit FIFO buffer is not empty. 1 = Transmit FIFO buffer is empty.
[17] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) 0 = Transmit FIFO buffer is not full. 1 = Transmit FIFO buffer is full.
[18] | TXTHIF | Transmit FIFO Threshold Interrupt Flag (Read Only) 0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
[19] | TXUFIF | TX Underflow Interrupt Flag When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. 0 = No effect. 1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. Note 1: This bit will be cleared by writing 1 to it. Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
[23] | TXRXRST | TX or RX Reset Status (Read Only) 0 = The reset function of TXRST or RXRST is done. 1 = Doing the reset function of TXRST or RXRST. Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles User can check the status of this bit to monitor the reset function is doing or done.
[27:24] | RXCNT | Receive FIFO Data Count (Read Only) This bit field indicates the valid data count of receive FIFO buffer.
[31:28] | TXCNT | Transmit FIFO Data Count (Read Only) This bit field indicates the valid data count of transmit FIFO buffer.

Definition at line 790 of file qspi_reg.h.

## ◆ TX

QSPI_T::TX

[0x0020] QSPI Data Transmit Register

TX

Offset: 0x20 QSPI Data Transmit Register

Bits | Field | Descriptions
[31:0] | TX | Data Transmit Register The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in SPI mode. In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.

Definition at line 794 of file qspi_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/qspi_reg.h