| M480 BSP V3.05.001 The Board Support Package for M480 Series

ohci.h
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1 /**************************************************************************/
10 #ifndef _USBH_OHCI_H_
11 #define _USBH_OHCI_H_
12
14
15 struct utr_t;
16 struct udev_t;
17
18 /* OHCI CONTROL AND STATUS REGISTER MASKS */
19
20 /*
21 * Host controller functional state.
22 * for HCFS(HcControl[7:6])
23 */
24 #define HCFS_RESET (0UL << USBH_HcControl_HCFS_Pos)
25 #define HCFS_RESUME (1UL << USBH_HcControl_HCFS_Pos)
26 #define HCFS_OPER (2UL << USBH_HcControl_HCFS_Pos)
27 #define HCFS_SUSPEND (3UL << USBH_HcControl_HCFS_Pos)
28
29
30 /*----------------------------------------------------------------------------------------*/
31 /* Endpoint descriptor */
32 /*----------------------------------------------------------------------------------------*/
33 typedef struct ed_t
34 {
35 /* OHCI spec. Endpoint descriptor */
36 uint32_t Info;
37 uint32_t TailP;
38 uint32_t HeadP;
39 uint32_t NextED;
40 /* The following members are used by USB Host libary. */
41 uint8_t bInterval;
42 uint16_t next_sf; /* for isochronous transfer, recording the next SF */
43 struct ed_t * next; /* point to the next ED in remove list */
44 } ED_T;
45
46 #define ED_CTRL_FA_Pos 0 /* Info[6:0] - Function address */
47 #define ED_CTRL_EN_Pos 7 /* Info[10:7] - Endpoint number */
48 #define ED_CTRL_DIR_Pos 11 /* Info[12:11] - Direction */
49 #define ED_CTRL_MPS_Pos 16 /* Info[26:16] - Maximum packet size */
50
51 #define ED_FUNC_ADDR_Msk (0x7f)
52 #define ED_EP_ADDR_Msk (0xf<<7)
53 #define ED_DIR_Msk (0x3<<11)
54 #define ED_SPEED_Msk (1<<13)
55 #define ED_MAX_PK_SIZE_Msk (0x7ff<<16)
56
57 #define ED_DIR_BY_TD (0<<ED_CTRL_DIR_Pos)
58 #define ED_DIR_OUT (1<<ED_CTRL_DIR_Pos)
59 #define ED_DIR_IN (2<<ED_CTRL_DIR_Pos)
60 #define ED_SPEED_FULL (0<<13) /* Info[13] - 0: is full speed device */
61 #define ED_SPEED_LOW (1<<13) /* Info[13] - 1: is low speed device */
62 #define ED_SKIP (1<<14) /* Info[14] - 1: HC skip this ED */
63 #define ED_FORMAT_GENERAL (0<<15) /* Info[15] - 0: is a general TD */
64 #define ED_FORMAT_ISO (1<<15) /* Info[15] - 1: is an isochronous TD */
65 #define ED_HEADP_HALT (1<<0) /* HeadP[0] - 1: Halt; 0: Not */
66
67
68 /*----------------------------------------------------------------------------------------*/
69 /* Transfer descriptor */
70 /*----------------------------------------------------------------------------------------*/
71 /* general transfer descriptor */
72 typedef struct td_t
73 {
74 uint32_t Info;
75 uint32_t CBP; /* Current Buffer Pointer */
76 uint32_t NextTD; /* Next TD */
77 uint32_t BE; /* Buffer End */
78 uint32_t PSW[4]; /* PSW 0~7 */
79 /* The following members are used by USB Host libary. */
80 uint32_t buff_start; /* Buffer Start */
81 ED_T *ed; /* The ED that this TD belong to. */
82 struct utr_t *utr; /* associated UTR */
83 struct td_t *next; /* point to next TD of the same UTR */
84 } TD_T;
85
86 #define TD_ADDR_MASK 0xFFFFFFFC
87
88 /* Completion codes */
89 enum OCHI_CC_CODE
90 {
91 /* mapping of the OHCI CC status to error codes */
92 CC_NOERROR, /* No Error */
93 CC_CRC, /* CRC Error */
94 CC_BITSTUFF, /* Bit Stuff */
95 CC_DATA_TOGGLE, /* Data Toggle */
96 CC_STALL, /* Stall */
97 CC_NOTRESPONSE, /* DevNotResp */
98 CC_PID_CHECK, /* PIDCheck */
99 CC_UNEXPECTED_PID, /* UnExpPID */
100 CC_DATA_OVERRUN, /* DataOver */
101 CC_DATA_UNDERRUN, /* DataUnder */
102 CC_RESERVED1, /* reserved */
103 CC_RESERVED2, /* reserved */
104 CC_BUFFER_OVERRUN, /* BufferOver */
105 CC_BUFFER_UNDERRUN, /* BuffUnder */
106 CC_NOT_ACCESS /* Not Access */
107 };
108
109 /* TD control field */
110 #define TD_CC 0xF0000000
111 #define TD_CC_GET(td) ((td >>28) & 0x0F)
112 #define TD_CC_SET(td, cc) (td) = ((td) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28)
113 #define TD_T_DATA0 0x02000000
114 #define TD_T_DATA1 0x03000000
115 #define TD_R 0x00040000
116 #define TD_DP 0x00180000
117 #define TD_DP_IN 0x00100000
118 #define TD_DP_OUT 0x00080000
119 #define MAXPSW 8
120 /* steel TD reserved bits to keep driver data */
121 #define TD_TYPE_Msk (0x3<<16)
122 #define TD_TYPE_CTRL (0x0<<16)
123 #define TD_TYPE_BULK (0x1<<16)
124 #define TD_TYPE_INT (0x2<<16)
125 #define TD_TYPE_ISO (0x3<<16)
126 #define TD_CTRL_Msk (0x7<<15)
127 #define TD_CTRL_DATA (1<<15)
128
129
130 /*
131 * The HCCA (Host Controller Communications Area) is a 256 byte
132 * structure defined in the OHCI spec. that the host controller is
133 * told the base address of. It must be 256-byte aligned.
134 */
135 typedef struct
136 {
137 uint32_t int_table[32]; /* Interrupt ED table */
138 uint16_t frame_no; /* current frame number */
139 uint16_t pad1; /* set to 0 on each frame_no change */
140 uint32_t done_head; /* info returned for an interrupt */
141 uint8_t reserved_for_hc[116];
142 } HCCA_T;
143
144
146
147 #endif /* _USBH_OHCI_H_ */