| M480 BSP V3.05.001 The Board Support Package for M480 Series

Macros
Peripheral Memory Base

## Macros
#define | FLASH_BASE ((uint32_t)0x00000000)
#define | SRAM_BASE ((uint32_t)0x20000000)
#define | PERIPH_BASE ((uint32_t)0x40000000)
#define | AHBPERIPH_BASE PERIPH_BASE
#define | APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000)
#define | SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
#define | CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
#define | NMI_BASE (AHBPERIPH_BASE + 0x00300UL)
#define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
#define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
#define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
#define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
#define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
#define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
#define | GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
#define | GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
#define | GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)
#define | GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
#define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
#define | PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
#define | USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
#define | HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)
#define | EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)
#define | FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
#define | SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
#define | SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
#define | EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
#define | HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)
#define | CCAP_BASE (AHBPERIPH_BASE + 0x30000UL)
#define | CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
#define | TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)
#define | WDT_BASE (APBPERIPH_BASE + 0x00000UL)
#define | WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
#define | OPA_BASE (APBPERIPH_BASE + 0x06000UL)
#define | I2S_BASE (APBPERIPH_BASE + 0x08000UL)
#define | EADC1_BASE (APBPERIPH_BASE + 0x0B000UL)
#define | TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)
#define | TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)
#define | EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
#define | BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
#define | QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
#define | SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
#define | SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
#define | UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define | UART2_BASE (APBPERIPH_BASE + 0x32000UL)
#define | UART4_BASE (APBPERIPH_BASE + 0x34000UL)
#define | UART6_BASE (APBPERIPH_BASE + 0x36000UL)
#define | I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
#define | I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
#define | CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
#define | CAN2_BASE (APBPERIPH_BASE + 0x62000UL)
#define | QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
#define | ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
#define | USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
#define | RTC_BASE (APBPERIPH_BASE + 0x01000UL)
#define | EADC_BASE (APBPERIPH_BASE + 0x03000UL)
#define | ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
#define | USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define | OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
#define | HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
#define | TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
#define | TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
#define | EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
#define | BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
#define | SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
#define | SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
#define | QSPI1_BASE (APBPERIPH_BASE + 0x29000UL)
#define | UART1_BASE (APBPERIPH_BASE + 0x31000UL)
#define | UART3_BASE (APBPERIPH_BASE + 0x33000UL)
#define | UART5_BASE (APBPERIPH_BASE + 0x35000UL)
#define | UART7_BASE (APBPERIPH_BASE + 0x37000UL)
#define | I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
#define | CAN1_BASE (APBPERIPH_BASE + 0x61000UL)
#define | QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
#define | ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
#define | TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
#define | USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
#define | CRPT_BASE (0x50080000UL)
#define | SPIM_BASE (0x40007000UL)
#define | SC0_BASE (APBPERIPH_BASE + 0x50000UL)
#define | SC1_BASE (APBPERIPH_BASE + 0x51000UL)
#define | SC2_BASE (APBPERIPH_BASE + 0x52000UL)
#define | DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
#define | DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
#define | DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)
#define | OPA0_BASE (APBPERIPH_BASE + 0x06000UL)

## Detailed Description

Memory Mapped Structure for Peripherals

## Macro Definition Documentation

## ◆ ACMP01_BASE

#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)

Definition at line 327 of file M480.h.

## ◆ AHBPERIPH_BASE

#define AHBPERIPH_BASE PERIPH_BASE

AHB Base Address

Definition at line 267 of file M480.h.

## ◆ APBPERIPH_BASE

#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000)

APB Base Address AHB peripherals

Definition at line 268 of file M480.h.

## ◆ BPWM0_BASE

#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)

Definition at line 307 of file M480.h.

## ◆ BPWM1_BASE

#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)

Definition at line 334 of file M480.h.

## ◆ CAN0_BASE

#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)

Definition at line 317 of file M480.h.

## ◆ CAN1_BASE

#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL)

Definition at line 343 of file M480.h.

## ◆ CAN2_BASE

#define CAN2_BASE (APBPERIPH_BASE + 0x62000UL)

Definition at line 318 of file M480.h.

## ◆ CCAP_BASE

#define CCAP_BASE (AHBPERIPH_BASE + 0x30000UL)

Definition at line 294 of file M480.h.

## ◆ CLK_BASE

#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)

Definition at line 272 of file M480.h.

## ◆ CRC_BASE

#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)

Definition at line 295 of file M480.h.

## ◆ CRPT_BASE

#define CRPT_BASE (0x50080000UL)

Definition at line 348 of file M480.h.

## ◆ DAC0_BASE

#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)

Definition at line 354 of file M480.h.

## ◆ DAC1_BASE

#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)

Definition at line 355 of file M480.h.

## ◆ DACDBG_BASE

#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)

Definition at line 356 of file M480.h.

## ◆ EADC1_BASE

#define EADC1_BASE (APBPERIPH_BASE + 0x0B000UL)

Definition at line 303 of file M480.h.

## ◆ EADC_BASE

#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)

Definition at line 326 of file M480.h.

## ◆ EBI_BASE

#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)

Definition at line 292 of file M480.h.

## ◆ ECAP0_BASE

#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)

Definition at line 320 of file M480.h.

## ◆ ECAP1_BASE

#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)

Definition at line 345 of file M480.h.

## ◆ EMAC_BASE

#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)

Definition at line 288 of file M480.h.

## ◆ EPWM0_BASE

#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)

Definition at line 306 of file M480.h.

## ◆ EPWM1_BASE

#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)

Definition at line 333 of file M480.h.

## ◆ FLASH_BASE

#define FLASH_BASE ((uint32_t)0x00000000)

Flash base address

Definition at line 264 of file M480.h.

## ◆ FMC_BASE

#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)

Definition at line 289 of file M480.h.

## ◆ GPIO_DBCTL_BASE

#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)

Definition at line 283 of file M480.h.

## ◆ GPIO_PIN_DATA_BASE

#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)

Definition at line 284 of file M480.h.

## ◆ GPIOA_BASE

#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)

Definition at line 274 of file M480.h.

## ◆ GPIOB_BASE

#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)

Definition at line 275 of file M480.h.

## ◆ GPIOC_BASE

#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)

Definition at line 276 of file M480.h.

## ◆ GPIOD_BASE

#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)

Definition at line 277 of file M480.h.

## ◆ GPIOE_BASE

#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)

Definition at line 278 of file M480.h.

## ◆ GPIOF_BASE

#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)

Definition at line 279 of file M480.h.

## ◆ GPIOG_BASE

#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)

Definition at line 280 of file M480.h.

## ◆ GPIOH_BASE

#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)

Definition at line 281 of file M480.h.

## ◆ GPIOI_BASE

#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)

Definition at line 282 of file M480.h.

## ◆ HSOTG_BASE

#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)

Definition at line 330 of file M480.h.

## ◆ HSUSBD_BASE

#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)

Definition at line 293 of file M480.h.

## ◆ HSUSBH_BASE

#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)

Definition at line 287 of file M480.h.

## ◆ I2C0_BASE

#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)

Definition at line 315 of file M480.h.

## ◆ I2C1_BASE

#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)

Definition at line 342 of file M480.h.

## ◆ I2C2_BASE

#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)

Definition at line 316 of file M480.h.

## ◆ I2S_BASE

#define I2S_BASE (APBPERIPH_BASE + 0x08000UL)

Definition at line 302 of file M480.h.

## ◆ NMI_BASE

#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL)

Definition at line 273 of file M480.h.

## ◆ OPA0_BASE

#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL)

Definition at line 357 of file M480.h.

## ◆ OPA_BASE

#define OPA_BASE (APBPERIPH_BASE + 0x06000UL)

Definition at line 301 of file M480.h.

## ◆ OTG_BASE

#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)

Definition at line 329 of file M480.h.

## ◆ PDMA_BASE

#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)

Definition at line 285 of file M480.h.

## ◆ PERIPH_BASE

#define PERIPH_BASE ((uint32_t)0x40000000)

Peripheral Base Address

Definition at line 266 of file M480.h.

## ◆ QEI0_BASE

#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)

Definition at line 319 of file M480.h.

## ◆ QEI1_BASE

#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)

Definition at line 344 of file M480.h.

## ◆ QSPI0_BASE

#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)

Definition at line 308 of file M480.h.

## ◆ QSPI1_BASE

#define QSPI1_BASE (APBPERIPH_BASE + 0x29000UL)

Definition at line 337 of file M480.h.

## ◆ RTC_BASE

#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)

Definition at line 325 of file M480.h.

## ◆ SC0_BASE

#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)

Definition at line 351 of file M480.h.

## ◆ SC1_BASE

#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)

Definition at line 352 of file M480.h.

## ◆ SC2_BASE

#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)

Definition at line 353 of file M480.h.

## ◆ SDH0_BASE

#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)

Definition at line 290 of file M480.h.

## ◆ SDH1_BASE

#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)

Definition at line 291 of file M480.h.

## ◆ SPI0_BASE

#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)

Definition at line 335 of file M480.h.

## ◆ SPI1_BASE

#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)

Definition at line 309 of file M480.h.

## ◆ SPI2_BASE

#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)

Definition at line 336 of file M480.h.

## ◆ SPI3_BASE

#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)

Definition at line 310 of file M480.h.

## ◆ SPIM_BASE

#define SPIM_BASE (0x40007000UL)

Definition at line 349 of file M480.h.

## ◆ SRAM_BASE

#define SRAM_BASE ((uint32_t)0x20000000)

SRAM Base Address

Definition at line 265 of file M480.h.

## ◆ SYS_BASE

#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)

Definition at line 271 of file M480.h.

## ◆ TAMPER_BASE

#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)

APB2 peripherals

Definition at line 296 of file M480.h.

## ◆ TIMER0_BASE

#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)

Definition at line 304 of file M480.h.

## ◆ TIMER1_BASE

#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)

Definition at line 305 of file M480.h.

## ◆ TIMER2_BASE

#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)

Definition at line 331 of file M480.h.

## ◆ TIMER3_BASE

#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)

Definition at line 332 of file M480.h.

## ◆ TRNG_BASE

#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)

Definition at line 346 of file M480.h.

## ◆ UART0_BASE

#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)

Definition at line 311 of file M480.h.

## ◆ UART1_BASE

#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)

Definition at line 338 of file M480.h.

## ◆ UART2_BASE

#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)

Definition at line 312 of file M480.h.

## ◆ UART3_BASE

#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)

Definition at line 339 of file M480.h.

## ◆ UART4_BASE

#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)

Definition at line 313 of file M480.h.

## ◆ UART5_BASE

#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)

Definition at line 340 of file M480.h.

## ◆ UART6_BASE

#define UART6_BASE (APBPERIPH_BASE + 0x36000UL)

Definition at line 314 of file M480.h.

## ◆ UART7_BASE

#define UART7_BASE (APBPERIPH_BASE + 0x37000UL)

Definition at line 341 of file M480.h.

## ◆ USBD_BASE

#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)

Definition at line 328 of file M480.h.

## ◆ USBH_BASE

#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)

Definition at line 286 of file M480.h.

## ◆ USCI0_BASE

#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)

APB1 peripherals

Definition at line 321 of file M480.h.

## ◆ USCI1_BASE

#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)

Definition at line 347 of file M480.h.

## ◆ WDT_BASE

#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)

Definition at line 299 of file M480.h.

## ◆ WWDT_BASE

#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)

Definition at line 300 of file M480.h.