| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Structures
clk_reg.h File Reference

CLK register definition header file. More...

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## Data Structures
struct | CLK_T

## Macros
#define | CLK_PWRCTL_HXTEN_Pos (0)
#define | CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos)
#define | CLK_PWRCTL_LXTEN_Pos (1)
#define | CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos)
#define | CLK_PWRCTL_HIRCEN_Pos (2)
#define | CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos)
#define | CLK_PWRCTL_LIRCEN_Pos (3)
#define | CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
#define | CLK_PWRCTL_PDWKDLY_Pos (4)
#define | CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
#define | CLK_PWRCTL_PDWKIEN_Pos (5)
#define | CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
#define | CLK_PWRCTL_PDWKIF_Pos (6)
#define | CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos)
#define | CLK_PWRCTL_PDEN_Pos (7)
#define | CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
#define | CLK_PWRCTL_HXTGAIN_Pos (10)
#define | CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)
#define | CLK_PWRCTL_HXTSELTYP_Pos (12)
#define | CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)
#define | CLK_PWRCTL_HXTTBEN_Pos (13)
#define | CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos)
#define | CLK_PWRCTL_HIRCSTBS_Pos (16)
#define | CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos)
#define | CLK_PWRCTL_HIRC48MEN_Pos (18)
#define | CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos)
#define | CLK_AHBCLK_PDMACKEN_Pos (1)
#define | CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)
#define | CLK_AHBCLK_ISPCKEN_Pos (2)
#define | CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
#define | CLK_AHBCLK_EBICKEN_Pos (3)
#define | CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos)
#define | CLK_AHBCLK_EMACCKEN_Pos (5)
#define | CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos)
#define | CLK_AHBCLK_SDH0CKEN_Pos (6)
#define | CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos)
#define | CLK_AHBCLK_CRCCKEN_Pos (7)
#define | CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)
#define | CLK_AHBCLK_CCAPCKEN_Pos (8)
#define | CLK_AHBCLK_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK_CCAPCKEN_Pos)
#define | CLK_AHBCLK_SENCKEN_Pos (9)
#define | CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos)
#define | CLK_AHBCLK_HSUSBDCKEN_Pos (10)
#define | CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos)
#define | CLK_AHBCLK_CRPTCKEN_Pos (12)
#define | CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos)
#define | CLK_AHBCLK_SPIMCKEN_Pos (14)
#define | CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos)
#define | CLK_AHBCLK_FMCIDLE_Pos (15)
#define | CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)
#define | CLK_AHBCLK_USBHCKEN_Pos (16)
#define | CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)
#define | CLK_AHBCLK_SDH1CKEN_Pos (17)
#define | CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos)
#define | CLK_APBCLK0_WDTCKEN_Pos (0)
#define | CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)
#define | CLK_APBCLK0_RTCCKEN_Pos (1)
#define | CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)
#define | CLK_APBCLK0_TMR0CKEN_Pos (2)
#define | CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)
#define | CLK_APBCLK0_TMR1CKEN_Pos (3)
#define | CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)
#define | CLK_APBCLK0_TMR2CKEN_Pos (4)
#define | CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)
#define | CLK_APBCLK0_TMR3CKEN_Pos (5)
#define | CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)
#define | CLK_APBCLK0_CLKOCKEN_Pos (6)
#define | CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)
#define | CLK_APBCLK0_ACMP01CKEN_Pos (7)
#define | CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos)
#define | CLK_APBCLK0_I2C0CKEN_Pos (8)
#define | CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)
#define | CLK_APBCLK0_I2C1CKEN_Pos (9)
#define | CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)
#define | CLK_APBCLK0_I2C2CKEN_Pos (10)
#define | CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos)
#define | CLK_APBCLK0_QSPI0CKEN_Pos (12)
#define | CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos)
#define | CLK_APBCLK0_SPI0CKEN_Pos (13)
#define | CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)
#define | CLK_APBCLK0_SPI1CKEN_Pos (14)
#define | CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)
#define | CLK_APBCLK0_SPI2CKEN_Pos (15)
#define | CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos)
#define | CLK_APBCLK0_UART0CKEN_Pos (16)
#define | CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)
#define | CLK_APBCLK0_UART1CKEN_Pos (17)
#define | CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)
#define | CLK_APBCLK0_UART2CKEN_Pos (18)
#define | CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)
#define | CLK_APBCLK0_UART3CKEN_Pos (19)
#define | CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)
#define | CLK_APBCLK0_UART4CKEN_Pos (20)
#define | CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos)
#define | CLK_APBCLK0_UART5CKEN_Pos (21)
#define | CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos)
#define | CLK_APBCLK0_UART6CKEN_Pos (22)
#define | CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos)
#define | CLK_APBCLK0_UART7CKEN_Pos (23)
#define | CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos)
#define | CLK_APBCLK0_CAN0CKEN_Pos (24)
#define | CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos)
#define | CLK_APBCLK0_CAN1CKEN_Pos (25)
#define | CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos)
#define | CLK_APBCLK0_OTGCKEN_Pos (26)
#define | CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos)
#define | CLK_APBCLK0_USBDCKEN_Pos (27)
#define | CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)
#define | CLK_APBCLK0_EADCCKEN_Pos (28)
#define | CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)
#define | CLK_APBCLK0_I2S0CKEN_Pos (29)
#define | CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos)
#define | CLK_APBCLK0_HSOTGCKEN_Pos (30)
#define | CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos)
#define | CLK_APBCLK1_SC0CKEN_Pos (0)
#define | CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)
#define | CLK_APBCLK1_SC1CKEN_Pos (1)
#define | CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos)
#define | CLK_APBCLK1_SC2CKEN_Pos (2)
#define | CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos)
#define | CLK_APBCLK1_QSPI1CKEN_Pos (4)
#define | CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos)
#define | CLK_APBCLK1_SPI3CKEN_Pos (6)
#define | CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos)
#define | CLK_APBCLK1_USCI0CKEN_Pos (8)
#define | CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos)
#define | CLK_APBCLK1_USCI1CKEN_Pos (9)
#define | CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos)
#define | CLK_APBCLK1_DACCKEN_Pos (12)
#define | CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos)
#define | CLK_APBCLK1_EPWM0CKEN_Pos (16)
#define | CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos)
#define | CLK_APBCLK1_EPWM1CKEN_Pos (17)
#define | CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos)
#define | CLK_APBCLK1_BPWM0CKEN_Pos (18)
#define | CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos)
#define | CLK_APBCLK1_BPWM1CKEN_Pos (19)
#define | CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos)
#define | CLK_APBCLK1_QEI0CKEN_Pos (22)
#define | CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos)
#define | CLK_APBCLK1_QEI1CKEN_Pos (23)
#define | CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos)
#define | CLK_APBCLK1_TRNGCKEN_Pos (25)
#define | CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos)
#define | CLK_APBCLK1_ECAP0CKEN_Pos (26)
#define | CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos)
#define | CLK_APBCLK1_ECAP1CKEN_Pos (27)
#define | CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos)
#define | CLK_APBCLK1_CAN2CKEN_Pos (28)
#define | CLK_APBCLK1_CAN2CKEN_Msk (0x1ul << CLK_APBCLK1_CAN2CKEN_Pos)
#define | CLK_APBCLK1_OPACKEN_Pos (30)
#define | CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos)
#define | CLK_APBCLK1_EADC1CKEN_Pos (31)
#define | CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos)
#define | CLK_CLKSEL0_HCLKSEL_Pos (0)
#define | CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_STCLKSEL_Pos (3)
#define | CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)
#define | CLK_CLKSEL0_USBSEL_Pos (8)
#define | CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos)
#define | CLK_CLKSEL0_CCAPSEL_Pos (16)
#define | CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos)
#define | CLK_CLKSEL0_SDH0SEL_Pos (20)
#define | CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos)
#define | CLK_CLKSEL0_SDH1SEL_Pos (22)
#define | CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos)
#define | CLK_CLKSEL1_WDTSEL_Pos (0)
#define | CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_Pos (8)
#define | CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_Pos (12)
#define | CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_TMR2SEL_Pos (16)
#define | CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)
#define | CLK_CLKSEL1_TMR3SEL_Pos (20)
#define | CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)
#define | CLK_CLKSEL1_UART0SEL_Pos (24)
#define | CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos)
#define | CLK_CLKSEL1_UART1SEL_Pos (26)
#define | CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos)
#define | CLK_CLKSEL1_CLKOSEL_Pos (28)
#define | CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)
#define | CLK_CLKSEL1_WWDTSEL_Pos (30)
#define | CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)
#define | CLK_CLKSEL2_EPWM0SEL_Pos (0)
#define | CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos)
#define | CLK_CLKSEL2_EPWM1SEL_Pos (1)
#define | CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos)
#define | CLK_CLKSEL2_QSPI0SEL_Pos (2)
#define | CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos)
#define | CLK_CLKSEL2_SPI0SEL_Pos (4)
#define | CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)
#define | CLK_CLKSEL2_SPI1SEL_Pos (6)
#define | CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)
#define | CLK_CLKSEL2_BPWM0SEL_Pos (8)
#define | CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos)
#define | CLK_CLKSEL2_BPWM1SEL_Pos (9)
#define | CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos)
#define | CLK_CLKSEL2_SPI2SEL_Pos (10)
#define | CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos)
#define | CLK_CLKSEL2_SPI3SEL_Pos (12)
#define | CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos)
#define | CLK_CLKSEL3_SC0SEL_Pos (0)
#define | CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)
#define | CLK_CLKSEL3_SC1SEL_Pos (2)
#define | CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos)
#define | CLK_CLKSEL3_SC2SEL_Pos (4)
#define | CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos)
#define | CLK_CLKSEL3_RTCSEL_Pos (8)
#define | CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos)
#define | CLK_CLKSEL3_QSPI1SEL_Pos (12)
#define | CLK_CLKSEL3_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL3_QSPI1SEL_Pos)
#define | CLK_CLKSEL3_I2S0SEL_Pos (16)
#define | CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos)
#define | CLK_CLKSEL3_UART6SEL_Pos (20)
#define | CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos)
#define | CLK_CLKSEL3_UART7SEL_Pos (22)
#define | CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos)
#define | CLK_CLKSEL3_UART2SEL_Pos (24)
#define | CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos)
#define | CLK_CLKSEL3_UART3SEL_Pos (26)
#define | CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos)
#define | CLK_CLKSEL3_UART4SEL_Pos (28)
#define | CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos)
#define | CLK_CLKSEL3_UART5SEL_Pos (30)
#define | CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos)
#define | CLK_CLKDIV0_HCLKDIV_Pos (0)
#define | CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos)
#define | CLK_CLKDIV0_USBDIV_Pos (4)
#define | CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos)
#define | CLK_CLKDIV0_UART0DIV_Pos (8)
#define | CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos)
#define | CLK_CLKDIV0_UART1DIV_Pos (12)
#define | CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos)
#define | CLK_CLKDIV0_EADCDIV_Pos (16)
#define | CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos)
#define | CLK_CLKDIV0_SDH0DIV_Pos (24)
#define | CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos)
#define | CLK_CLKDIV1_SC0DIV_Pos (0)
#define | CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos)
#define | CLK_CLKDIV1_SC1DIV_Pos (8)
#define | CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos)
#define | CLK_CLKDIV1_SC2DIV_Pos (16)
#define | CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos)
#define | CLK_CLKDIV2_I2SDIV_Pos (0)
#define | CLK_CLKDIV2_I2SDIV_Msk (0xful << CLK_CLKDIV2_I2SDIV_Pos)
#define | CLK_CLKDIV2_EADC1DIV_Pos (24)
#define | CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos)
#define | CLK_CLKDIV3_CCAPDIV_Pos (0)
#define | CLK_CLKDIV3_CCAPDIV_Msk (0xfful << CLK_CLKDIV3_CCAPDIV_Pos)
#define | CLK_CLKDIV3_VSENSEDIV_Pos (8)
#define | CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos)
#define | CLK_CLKDIV3_EMACDIV_Pos (16)
#define | CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos)
#define | CLK_CLKDIV3_SDH1DIV_Pos (24)
#define | CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos)
#define | CLK_CLKDIV4_UART2DIV_Pos (0)
#define | CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos)
#define | CLK_CLKDIV4_UART3DIV_Pos (4)
#define | CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos)
#define | CLK_CLKDIV4_UART4DIV_Pos (8)
#define | CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos)
#define | CLK_CLKDIV4_UART5DIV_Pos (12)
#define | CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos)
#define | CLK_CLKDIV4_UART6DIV_Pos (16)
#define | CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos)
#define | CLK_CLKDIV4_UART7DIV_Pos (20)
#define | CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos)
#define | CLK_PCLKDIV_APB0DIV_Pos (0)
#define | CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos)
#define | CLK_PCLKDIV_APB1DIV_Pos (4)
#define | CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos)
#define | CLK_PLLCTL_FBDIV_Pos (0)
#define | CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
#define | CLK_PLLCTL_INDIV_Pos (9)
#define | CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
#define | CLK_PLLCTL_OUTDIV_Pos (14)
#define | CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
#define | CLK_PLLCTL_PD_Pos (16)
#define | CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
#define | CLK_PLLCTL_BP_Pos (17)
#define | CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
#define | CLK_PLLCTL_OE_Pos (18)
#define | CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
#define | CLK_PLLCTL_PLLSRC_Pos (19)
#define | CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
#define | CLK_PLLCTL_STBSEL_Pos (23)
#define | CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos)
#define | CLK_STATUS_HXTSTB_Pos (0)
#define | CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos)
#define | CLK_STATUS_LXTSTB_Pos (1)
#define | CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos)
#define | CLK_STATUS_PLLSTB_Pos (2)
#define | CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos)
#define | CLK_STATUS_LIRCSTB_Pos (3)
#define | CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
#define | CLK_STATUS_HIRCSTB_Pos (4)
#define | CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos)
#define | CLK_STATUS_HIRC48MSTB_Pos (6)
#define | CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos)
#define | CLK_STATUS_CLKSFAIL_Pos (7)
#define | CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
#define | CLK_CLKOCTL_FREQSEL_Pos (0)
#define | CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
#define | CLK_CLKOCTL_CLKOEN_Pos (4)
#define | CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
#define | CLK_CLKOCTL_DIV1EN_Pos (5)
#define | CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
#define | CLK_CLKOCTL_CLK1HZEN_Pos (6)
#define | CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)
#define | CLK_CLKDCTL_HXTFDEN_Pos (4)
#define | CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)
#define | CLK_CLKDCTL_HXTFIEN_Pos (5)
#define | CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)
#define | CLK_CLKDCTL_LXTFDEN_Pos (12)
#define | CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)
#define | CLK_CLKDCTL_LXTFIEN_Pos (13)
#define | CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)
#define | CLK_CLKDCTL_HXTFQDEN_Pos (16)
#define | CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)
#define | CLK_CLKDCTL_HXTFQIEN_Pos (17)
#define | CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)
#define | CLK_CLKDSTS_HXTFIF_Pos (0)
#define | CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)
#define | CLK_CLKDSTS_LXTFIF_Pos (1)
#define | CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)
#define | CLK_CLKDSTS_HXTFQIF_Pos (8)
#define | CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)
#define | CLK_CDUPB_UPERBD_Pos (0)
#define | CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos)
#define | CLK_CDLOWB_LOWERBD_Pos (0)
#define | CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos)
#define | CLK_PMUCTL_PDMSEL_Pos (0)
#define | CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos)
#define | CLK_PMUCTL_DPDHOLDEN_Pos (3)
#define | CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos)
#define | CLK_PMUCTL_SRETSEL_Pos (4)
#define | CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos)
#define | CLK_PMUCTL_WKTMREN_Pos (8)
#define | CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos)
#define | CLK_PMUCTL_WKTMRIS_Pos (9)
#define | CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos)
#define | CLK_PMUCTL_WKPINEN_Pos (16)
#define | CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos)
#define | CLK_PMUCTL_ACMPSPWK_Pos (18)
#define | CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos)
#define | CLK_PMUCTL_RTCWKEN_Pos (23)
#define | CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos)
#define | CLK_PMUCTL_WKPINEN1_Pos (24)
#define | CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos)
#define | CLK_PMUCTL_WKPINEN2_Pos (26)
#define | CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos)
#define | CLK_PMUCTL_WKPINEN3_Pos (28)
#define | CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos)
#define | CLK_PMUCTL_WKPINEN4_Pos (30)
#define | CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos)
#define | CLK_PMUSTS_PINWK_Pos (0)
#define | CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos)
#define | CLK_PMUSTS_TMRWK_Pos (1)
#define | CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos)
#define | CLK_PMUSTS_RTCWK_Pos (2)
#define | CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos)
#define | CLK_PMUSTS_PINWK1_Pos (3)
#define | CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos)
#define | CLK_PMUSTS_PINWK2_Pos (4)
#define | CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos)
#define | CLK_PMUSTS_PINWK3_Pos (5)
#define | CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos)
#define | CLK_PMUSTS_PINWK4_Pos (6)
#define | CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos)
#define | CLK_PMUSTS_GPAWK_Pos (8)
#define | CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos)
#define | CLK_PMUSTS_GPBWK_Pos (9)
#define | CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos)
#define | CLK_PMUSTS_GPCWK_Pos (10)
#define | CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos)
#define | CLK_PMUSTS_GPDWK_Pos (11)
#define | CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos)
#define | CLK_PMUSTS_LVRWK_Pos (12)
#define | CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos)
#define | CLK_PMUSTS_BODWK_Pos (13)
#define | CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos)
#define | CLK_PMUSTS_ACMPWK_Pos (14)
#define | CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos)
#define | CLK_PMUSTS_CLRWK_Pos (31)
#define | CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos)
#define | CLK_LDOCTL_PDBIASEN_Pos (18)
#define | CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos)
#define | CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0)
#define | CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)
#define | CLK_PASWKCTL_WKEN_Pos (0)
#define | CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos)
#define | CLK_PASWKCTL_PRWKEN_Pos (1)
#define | CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos)
#define | CLK_PASWKCTL_PFWKEN_Pos (2)
#define | CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos)
#define | CLK_PASWKCTL_WKPSEL_Pos (4)
#define | CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos)
#define | CLK_PASWKCTL_DBEN_Pos (8)
#define | CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos)
#define | CLK_PBSWKCTL_WKEN_Pos (0)
#define | CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos)
#define | CLK_PBSWKCTL_PRWKEN_Pos (1)
#define | CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos)
#define | CLK_PBSWKCTL_PFWKEN_Pos (2)
#define | CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos)
#define | CLK_PBSWKCTL_WKPSEL_Pos (4)
#define | CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos)
#define | CLK_PBSWKCTL_DBEN_Pos (8)
#define | CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos)
#define | CLK_PCSWKCTL_WKEN_Pos (0)
#define | CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos)
#define | CLK_PCSWKCTL_PRWKEN_Pos (1)
#define | CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos)
#define | CLK_PCSWKCTL_PFWKEN_Pos (2)
#define | CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos)
#define | CLK_PCSWKCTL_WKPSEL_Pos (4)
#define | CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos)
#define | CLK_PCSWKCTL_DBEN_Pos (8)
#define | CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos)
#define | CLK_PDSWKCTL_WKEN_Pos (0)
#define | CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos)
#define | CLK_PDSWKCTL_PRWKEN_Pos (1)
#define | CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos)
#define | CLK_PDSWKCTL_PFWKEN_Pos (2)
#define | CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos)
#define | CLK_PDSWKCTL_WKPSEL_Pos (4)
#define | CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos)
#define | CLK_PDSWKCTL_DBEN_Pos (8)
#define | CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos)
#define | CLK_IOPDCTL_IOHR_Pos (0)
#define | CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos)

## Detailed Description

CLK register definition header file.

Version
  V1.00 SPDX-License-Identifier: Apache-2.0

Copyright
  (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.

Definition in file clk_reg.h.