| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
DSCT_T Struct Reference
Control Register

`#include <pdma_reg.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | SA
__IO uint32_t | DA
__IO uint32_t | NEXT

## Detailed Description

    @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
    Memory Mapped Structure for PDMA Controller

Definition at line 27 of file pdma_reg.h.

## Field Documentation

## ◆ CTL

DSCT_T::CTL

[0x0000] Descriptor Table Control Register of PDMA Channel n.

CTL

Offset: 0x00 Descriptor Table Control Register of PDMA Channel n.

Bits | Field | Descriptions
[1:0] | OPMODE | PDMA Operation Mode Selection 00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. 01 = Basic mode: The descriptor table only has one task When this task is finished, the PDMA_INTSTS[n] will be asserted. 10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. 11 = Reserved. Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
[2] | TXTYPE | Transfer Type 0 = Burst transfer type. 1 = Single transfer type.
[6:4] | BURSIZE | Burst Size This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. 000 = 128 Transfers. 001 = 64 Transfers. 010 = 32 Transfers. 011 = 16 Transfers. 100 = 8 Transfers. 101 = 4 Transfers. 110 = 2 Transfers. 111 = 1 Transfers. Note: This field is only useful in burst transfer type.
[7] | TBINTDIS | Table Interrupt Disable Bit This field can be used to decide whether to enable table interrupt or not If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. 0 = Table interrupt Enabled. 1 = Table interrupt Disabled.
[9:8] | SAINC | Source Address Increment This field is used to set the source address increment size. 11 = No increment (fixed address). Others = Increment and size is depended on TXWIDTH selection.
[11:10] | DAINC | Destination Address Increment This field is used to set the destination address increment size. 11 = No increment (fixed address). Others = Increment and size is depended on TXWIDTH selection.
[13:12] | TXWIDTH | Transfer Width Selection This field is used for transfer width. 00 = One byte (8 bit) is transferred for every operation. 01= One half-word (16 bit) is transferred for every operation. 10 = One word (32-bit) is transferred for every operation. 11 = Reserved. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
[14] | TXACK | Transfer Acknowledge Selection 0 = transfer ack when transfer done. 1 = transfer ack when PDMA get transfer data.
[15] | STRIDEEN | Stride Mode Enable Bit 0 = Stride transfer mode Disabled. 1 = Stride transfer mode Enabled.
[31:16] | TXCNT | Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer data, this field will be decrease immediately.

Definition at line 229 of file pdma_reg.h.

## ◆ DA

DSCT_T::DA

[0x0008] Destination Address Register of PDMA Channel n

DA

Offset: 0x08 Destination Address Register of PDMA Channel n

Bits | Field | Descriptions
[31:0] | DA | PDMA Transfer Destination Address Register This field indicates a 32-bit destination address of PDMA controller.

Definition at line 231 of file pdma_reg.h.

## ◆ NEXT

DSCT_T::NEXT

[0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n

NEXT

Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n

Bits | Field | Descriptions
[15:0] | EXENEXT | PDMA Execution Next Descriptor Table Offset This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. Note: write operation is useless in this field.
[31:16] | NEXT | PDMA Next Descriptor Table Offset. This field indicates the offset of the next descriptor table address in system memory. Write Operation: If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. Read Operation: When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. Note1: The descriptor table address must be word boundary. Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.

Definition at line 232 of file pdma_reg.h.

## ◆ SA

DSCT_T::SA

[0x0004] Source Address Register of PDMA Channel n

SA

Offset: 0x04 Source Address Register of PDMA Channel n

Bits | Field | Descriptions
[31:0] | SA | PDMA Transfer Source Address Register This field indicates a 32-bit source address of PDMA controller.

Definition at line 230 of file pdma_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/pdma_reg.h