| M480 BSP V3.05.001 The Board Support Package for M480 Series

Macros | Typedefs | Enumerations
M480.h File Reference

M480 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro M480 MCU. More...

`#include "core_cm4.h"`
`#include "system_M480.h"`
`#include <stdint.h>`
`#include "sys_reg.h"`
`#include "clk_reg.h"`
`#include "fmc_reg.h"`
`#include "gpio_reg.h"`
`#include "pdma_reg.h"`
`#include "timer_reg.h"`
`#include "wdt_reg.h"`
`#include "wwdt_reg.h"`
`#include "rtc_reg.h"`
`#include "epwm_reg.h"`
`#include "bpwm_reg.h"`
`#include "qei_reg.h"`
`#include "ecap_reg.h"`
`#include "uart_reg.h"`
`#include "emac_reg.h"`
`#include "sc_reg.h"`
`#include "i2s_reg.h"`
`#include "spi_reg.h"`
`#include "qspi_reg.h"`
`#include "spim_reg.h"`
`#include "i2c_reg.h"`
`#include "uuart_reg.h"`
`#include "uspi_reg.h"`
`#include "ui2c_reg.h"`
`#include "can_reg.h"`
`#include "sdh_reg.h"`
`#include "ebi_reg.h"`
`#include "usbd_reg.h"`
`#include "hsusbd_reg.h"`
`#include "usbh_reg.h"`
`#include "hsusbh_reg.h"`
`#include "otg_reg.h"`
`#include "hsotg_reg.h"`
`#include "crc_reg.h"`
`#include "crypto_reg.h"`
`#include "trng_reg.h"`
`#include "eadc_reg.h"`
`#include "dac_reg.h"`
`#include "acmp_reg.h"`
`#include "opa_reg.h"`
`#include "ccap_reg.h"`
`#include "sys.h"`
`#include "clk.h"`
`#include "acmp.h"`
`#include "dac.h"`
`#include "emac.h"`
`#include "uart.h"`
`#include "usci_spi.h"`
`#include "gpio.h"`
`#include "ccap.h"`
`#include "ecap.h"`
`#include "qei.h"`
`#include "timer.h"`
`#include "timer_pwm.h"`
`#include "pdma.h"`
`#include "crypto.h"`
`#include "trng.h"`
`#include "fmc.h"`
`#include "spim.h"`
`#include "i2c.h"`
`#include "i2s.h"`
`#include "epwm.h"`
`#include "eadc.h"`
`#include "bpwm.h"`
`#include "wdt.h"`
`#include "wwdt.h"`
`#include "opa.h"`
`#include "crc.h"`
`#include "ebi.h"`
`#include "usci_i2c.h"`
`#include "scuart.h"`
`#include "sc.h"`
`#include "spi.h"`
`#include "qspi.h"`
`#include "can.h"`
`#include "rtc.h"`
`#include "usci_uart.h"`
`#include "sdh.h"`
`#include "usbd.h"`
`#include "hsusbd.h"`
`#include "otg.h"`
`#include "hsotg.h"`

Go to the source code of this file.

## Macros
#define | __CM4_REV 0x0201UL
#define | __NVIC_PRIO_BITS 4UL
#define | __Vendor_SysTickConfig 0UL
#define | __MPU_PRESENT 1UL
#define | __FPU_PRESENT 1UL
#define | FLASH_BASE ((uint32_t)0x00000000)
#define | SRAM_BASE ((uint32_t)0x20000000)
#define | PERIPH_BASE ((uint32_t)0x40000000)
#define | AHBPERIPH_BASE PERIPH_BASE
#define | APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000)
#define | SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
#define | CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
#define | NMI_BASE (AHBPERIPH_BASE + 0x00300UL)
#define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
#define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
#define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
#define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
#define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
#define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
#define | GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
#define | GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
#define | GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)
#define | GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
#define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
#define | PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
#define | USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
#define | HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)
#define | EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)
#define | FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
#define | SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
#define | SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
#define | EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
#define | HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)
#define | CCAP_BASE (AHBPERIPH_BASE + 0x30000UL)
#define | CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
#define | TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)
#define | WDT_BASE (APBPERIPH_BASE + 0x00000UL)
#define | WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
#define | OPA_BASE (APBPERIPH_BASE + 0x06000UL)
#define | I2S_BASE (APBPERIPH_BASE + 0x08000UL)
#define | EADC1_BASE (APBPERIPH_BASE + 0x0B000UL)
#define | TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)
#define | TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)
#define | EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
#define | BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
#define | QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
#define | SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
#define | SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
#define | UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define | UART2_BASE (APBPERIPH_BASE + 0x32000UL)
#define | UART4_BASE (APBPERIPH_BASE + 0x34000UL)
#define | UART6_BASE (APBPERIPH_BASE + 0x36000UL)
#define | I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
#define | I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
#define | CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
#define | CAN2_BASE (APBPERIPH_BASE + 0x62000UL)
#define | QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
#define | ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
#define | USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
#define | RTC_BASE (APBPERIPH_BASE + 0x01000UL)
#define | EADC_BASE (APBPERIPH_BASE + 0x03000UL)
#define | ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
#define | USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define | OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
#define | HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
#define | TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
#define | TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
#define | EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
#define | BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
#define | SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
#define | SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
#define | QSPI1_BASE (APBPERIPH_BASE + 0x29000UL)
#define | UART1_BASE (APBPERIPH_BASE + 0x31000UL)
#define | UART3_BASE (APBPERIPH_BASE + 0x33000UL)
#define | UART5_BASE (APBPERIPH_BASE + 0x35000UL)
#define | UART7_BASE (APBPERIPH_BASE + 0x37000UL)
#define | I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
#define | CAN1_BASE (APBPERIPH_BASE + 0x61000UL)
#define | QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
#define | ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
#define | TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
#define | USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
#define | CRPT_BASE (0x50080000UL)
#define | SPIM_BASE (0x40007000UL)
#define | SC0_BASE (APBPERIPH_BASE + 0x50000UL)
#define | SC1_BASE (APBPERIPH_BASE + 0x51000UL)
#define | SC2_BASE (APBPERIPH_BASE + 0x52000UL)
#define | DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
#define | DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
#define | DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)
#define | OPA0_BASE (APBPERIPH_BASE + 0x06000UL)
#define | SYS ((SYS_T *) SYS_BASE)
#define | CLK ((CLK_T *) CLK_BASE)
#define | NMI ((NMI_T *) NMI_BASE)
#define | PA ((GPIO_T *) GPIOA_BASE)
#define | PB ((GPIO_T *) GPIOB_BASE)
#define | PC ((GPIO_T *) GPIOC_BASE)
#define | PD ((GPIO_T *) GPIOD_BASE)
#define | PE ((GPIO_T *) GPIOE_BASE)
#define | PF ((GPIO_T *) GPIOF_BASE)
#define | PG ((GPIO_T *) GPIOG_BASE)
#define | PH ((GPIO_T *) GPIOH_BASE)
#define | GPA ((GPIO_T *) GPIOA_BASE)
#define | GPB ((GPIO_T *) GPIOB_BASE)
#define | GPC ((GPIO_T *) GPIOC_BASE)
#define | GPD ((GPIO_T *) GPIOD_BASE)
#define | GPE ((GPIO_T *) GPIOE_BASE)
#define | GPF ((GPIO_T *) GPIOF_BASE)
#define | GPG ((GPIO_T *) GPIOG_BASE)
#define | GPH ((GPIO_T *) GPIOH_BASE)
#define | GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
#define | PDMA ((PDMA_T *) PDMA_BASE)
#define | USBH ((USBH_T *) USBH_BASE)
#define | HSUSBH ((HSUSBH_T *) HSUSBH_BASE)
#define | EMAC ((EMAC_T *) EMAC_BASE)
#define | FMC ((FMC_T *) FMC_BASE)
#define | SDH0 ((SDH_T *) SDH0_BASE)
#define | SDH1 ((SDH_T *) SDH1_BASE)
#define | EBI ((EBI_T *) EBI_BASE)
#define | CRC ((CRC_T *) CRC_BASE)
#define | TAMPER ((TAMPER_T *) TAMPER_BASE)
#define | WDT ((WDT_T *) WDT_BASE)
#define | WWDT ((WWDT_T *) WWDT_BASE)
#define | RTC ((RTC_T *) RTC_BASE)
#define | EADC ((EADC_T *) EADC_BASE)
#define | EADC0 ((EADC_T *) EADC_BASE)
#define | EADC1 ((EADC_T *) EADC1_BASE)
#define | ACMP01 ((ACMP_T *) ACMP01_BASE)
#define | I2S0 ((I2S_T *) I2S_BASE)
#define | USBD ((USBD_T *) USBD_BASE)
#define | OTG ((OTG_T *) OTG_BASE)
#define | HSUSBD ((HSUSBD_T *)HSUSBD_BASE)
#define | HSOTG ((HSOTG_T *) HSOTG_BASE)
#define | TIMER0 ((TIMER_T *) TIMER0_BASE)
#define | TIMER1 ((TIMER_T *) TIMER1_BASE)
#define | TIMER2 ((TIMER_T *) TIMER2_BASE)
#define | TIMER3 ((TIMER_T *) TIMER3_BASE)
#define | EPWM0 ((EPWM_T *) EPWM0_BASE)
#define | EPWM1 ((EPWM_T *) EPWM1_BASE)
#define | BPWM0 ((BPWM_T *) BPWM0_BASE)
#define | BPWM1 ((BPWM_T *) BPWM1_BASE)
#define | ECAP0 ((ECAP_T *) ECAP0_BASE)
#define | ECAP1 ((ECAP_T *) ECAP1_BASE)
#define | QEI0 ((QEI_T *) QEI0_BASE)
#define | QEI1 ((QEI_T *) QEI1_BASE)
#define | QSPI0 ((QSPI_T *) QSPI0_BASE)
#define | QSPI1 ((QSPI_T *) QSPI1_BASE)
#define | SPI0 ((SPI_T *) SPI0_BASE)
#define | SPI1 ((SPI_T *) SPI1_BASE)
#define | SPI2 ((SPI_T *) SPI2_BASE)
#define | SPI3 ((SPI_T *) SPI3_BASE)
#define | UART0 ((UART_T *) UART0_BASE)
#define | UART1 ((UART_T *) UART1_BASE)
#define | UART2 ((UART_T *) UART2_BASE)
#define | UART3 ((UART_T *) UART3_BASE)
#define | UART4 ((UART_T *) UART4_BASE)
#define | UART5 ((UART_T *) UART5_BASE)
#define | UART6 ((UART_T *) UART6_BASE)
#define | UART7 ((UART_T *) UART7_BASE)
#define | I2C0 ((I2C_T *) I2C0_BASE)
#define | I2C1 ((I2C_T *) I2C1_BASE)
#define | I2C2 ((I2C_T *) I2C2_BASE)
#define | SC0 ((SC_T *) SC0_BASE)
#define | SC1 ((SC_T *) SC1_BASE)
#define | SC2 ((SC_T *) SC2_BASE)
#define | CAN0 ((CAN_T *) CAN0_BASE)
#define | CAN1 ((CAN_T *) CAN1_BASE)
#define | CAN2 ((CAN_T *) CAN2_BASE)
#define | CRPT ((CRPT_T *) CRPT_BASE)
#define | TRNG ((TRNG_T *) TRNG_BASE)
#define | SPIM ((volatile SPIM_T *) SPIM_BASE)
#define | DAC0 ((DAC_T *) DAC0_BASE)
#define | DAC1 ((DAC_T *) DAC1_BASE)
#define | USPI0 ((USPI_T *) USCI0_BASE)
#define | USPI1 ((USPI_T *) USCI1_BASE)
#define | OPA ((OPA_T *) OPA_BASE)
#define | UI2C0 ((UI2C_T *) USCI0_BASE)
#define | UI2C1 ((UI2C_T *) USCI1_BASE)
#define | UUART0 ((UUART_T *) USCI0_BASE)
#define | UUART1 ((UUART_T *) USCI1_BASE)
#define | CCAP ((CCAP_T *) CCAP_BASE)
#define | M8(addr) (*((vu8 *) (addr)))
| Get a 8-bit unsigned value from specified address. More...
#define | M16(addr) (*((vu16 *) (addr)))
| Get a 16-bit unsigned value from specified address. More...
#define | M32(addr) (*((vu32 *) (addr)))
| Get a 32-bit unsigned value from specified address. More...
#define | outpw(port, value) *((volatile unsigned int *)(port)) = (value)
| Set a 32-bit unsigned value to specified I/O port. More...
#define | inpw(port) (*((volatile unsigned int *)(port)))
| Get a 32-bit unsigned value from specified I/O port. More...
#define | outps(port, value) *((volatile unsigned short *)(port)) = (value)
| Set a 16-bit unsigned value to specified I/O port. More...
#define | inps(port) (*((volatile unsigned short *)(port)))
| Get a 16-bit unsigned value from specified I/O port. More...
#define | outpb(port, value) *((volatile unsigned char *)(port)) = (value)
| Set a 8-bit unsigned value to specified I/O port. More...
#define | inpb(port) (*((volatile unsigned char *)(port)))
| Get a 8-bit unsigned value from specified I/O port. More...
#define | outp32(port, value) *((volatile unsigned int *)(port)) = (value)
| Set a 32-bit unsigned value to specified I/O port. More...
#define | inp32(port) (*((volatile unsigned int *)(port)))
| Get a 32-bit unsigned value from specified I/O port. More...
#define | outp16(port, value) *((volatile unsigned short *)(port)) = (value)
| Set a 16-bit unsigned value to specified I/O port. More...
#define | inp16(port) (*((volatile unsigned short *)(port)))
| Get a 16-bit unsigned value from specified I/O port. More...
#define | outp8(port, value) *((volatile unsigned char *)(port)) = (value)
| Set a 8-bit unsigned value to specified I/O port. More...
#define | inp8(port) (*((volatile unsigned char *)(port)))
| Get a 8-bit unsigned value from specified I/O port. More...
#define | NULL (0)
| NULL pointer. More...
#define | TRUE (1UL)
| Boolean true, define to use in API parameters or return value. More...
#define | FALSE (0UL)
| Boolean false, define to use in API parameters or return value. More...
#define | ENABLE (1UL)
| Enable, define to use in API parameters. More...
#define | DISABLE (0UL)
| Disable, define to use in API parameters. More...
#define | BIT0 (0x00000001UL)
| Bit 0 mask of an 32 bit integer. More...
#define | BIT1 (0x00000002UL)
| Bit 1 mask of an 32 bit integer. More...
#define | BIT2 (0x00000004UL)
| Bit 2 mask of an 32 bit integer. More...
#define | BIT3 (0x00000008UL)
| Bit 3 mask of an 32 bit integer. More...
#define | BIT4 (0x00000010UL)
| Bit 4 mask of an 32 bit integer. More...
#define | BIT5 (0x00000020UL)
| Bit 5 mask of an 32 bit integer. More...
#define | BIT6 (0x00000040UL)
| Bit 6 mask of an 32 bit integer. More...
#define | BIT7 (0x00000080UL)
| Bit 7 mask of an 32 bit integer. More...
#define | BIT8 (0x00000100UL)
| Bit 8 mask of an 32 bit integer. More...
#define | BIT9 (0x00000200UL)
| Bit 9 mask of an 32 bit integer. More...
#define | BIT10 (0x00000400UL)
| Bit 10 mask of an 32 bit integer. More...
#define | BIT11 (0x00000800UL)
| Bit 11 mask of an 32 bit integer. More...
#define | BIT12 (0x00001000UL)
| Bit 12 mask of an 32 bit integer. More...
#define | BIT13 (0x00002000UL)
| Bit 13 mask of an 32 bit integer. More...
#define | BIT14 (0x00004000UL)
| Bit 14 mask of an 32 bit integer. More...
#define | BIT15 (0x00008000UL)
| Bit 15 mask of an 32 bit integer. More...
#define | BIT16 (0x00010000UL)
| Bit 16 mask of an 32 bit integer. More...
#define | BIT17 (0x00020000UL)
| Bit 17 mask of an 32 bit integer. More...
#define | BIT18 (0x00040000UL)
| Bit 18 mask of an 32 bit integer. More...
#define | BIT19 (0x00080000UL)
| Bit 19 mask of an 32 bit integer. More...
#define | BIT20 (0x00100000UL)
| Bit 20 mask of an 32 bit integer. More...
#define | BIT21 (0x00200000UL)
| Bit 21 mask of an 32 bit integer. More...
#define | BIT22 (0x00400000UL)
| Bit 22 mask of an 32 bit integer. More...
#define | BIT23 (0x00800000UL)
| Bit 23 mask of an 32 bit integer. More...
#define | BIT24 (0x01000000UL)
| Bit 24 mask of an 32 bit integer. More...
#define | BIT25 (0x02000000UL)
| Bit 25 mask of an 32 bit integer. More...
#define | BIT26 (0x04000000UL)
| Bit 26 mask of an 32 bit integer. More...
#define | BIT27 (0x08000000UL)
| Bit 27 mask of an 32 bit integer. More...
#define | BIT28 (0x10000000UL)
| Bit 28 mask of an 32 bit integer. More...
#define | BIT29 (0x20000000UL)
| Bit 29 mask of an 32 bit integer. More...
#define | BIT30 (0x40000000UL)
| Bit 30 mask of an 32 bit integer. More...
#define | BIT31 (0x80000000UL)
| Bit 31 mask of an 32 bit integer. More...
#define | BYTE0_Msk (0x000000FFUL)
| Mask to get bit0~bit7 from a 32 bit integer. More...
#define | BYTE1_Msk (0x0000FF00UL)
| Mask to get bit8~bit15 from a 32 bit integer. More...
#define | BYTE2_Msk (0x00FF0000UL)
| Mask to get bit16~bit23 from a 32 bit integer. More...
#define | BYTE3_Msk (0xFF000000UL)
| Mask to get bit24~bit31 from a 32 bit integer. More...
#define | GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) )
#define | GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8)
#define | GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16)
#define | GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24)

## Typedefs
typedef enum IRQn | IRQn_Type
typedef volatile unsigned char | vu8
| Define 8-bit unsigned volatile data type. More...
typedef volatile unsigned short | vu16
| Define 16-bit unsigned volatile data type. More...
typedef volatile unsigned long | vu32
| Define 32-bit unsigned volatile data type. More...

## Enumerations
enum | IRQn { NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, BOD_IRQn = 0, IRC_IRQn = 1, PWRWU_IRQn = 2, RAMPE_IRQn = 3, CKFAIL_IRQn = 4, RTC_IRQn = 6, TAMPER_IRQn = 7, WDT_IRQn = 8, WWDT_IRQn = 9, EINT0_IRQn = 10, EINT1_IRQn = 11, EINT2_IRQn = 12, EINT3_IRQn = 13, EINT4_IRQn = 14, EINT5_IRQn = 15, GPA_IRQn = 16, GPB_IRQn = 17, GPC_IRQn = 18, GPD_IRQn = 19, GPE_IRQn = 20, GPF_IRQn = 21, QSPI0_IRQn = 22, SPI0_IRQn = 23, BRAKE0_IRQn = 24, EPWM0P0_IRQn = 25, EPWM0P1_IRQn = 26, EPWM0P2_IRQn = 27, BRAKE1_IRQn = 28, EPWM1P0_IRQn = 29, EPWM1P1_IRQn = 30, EPWM1P2_IRQn = 31, TMR0_IRQn = 32, TMR1_IRQn = 33, TMR2_IRQn = 34, TMR3_IRQn = 35, UART0_IRQn = 36, UART1_IRQn = 37, I2C0_IRQn = 38, I2C1_IRQn = 39, PDMA_IRQn = 40, DAC_IRQn = 41, EADC00_IRQn = 42, EADC01_IRQn = 43, ACMP01_IRQn = 44, EADC02_IRQn = 46, EADC03_IRQn = 47, UART2_IRQn = 48, UART3_IRQn = 49, QSPI1_IRQn = 50, SPI1_IRQn = 51, SPI2_IRQn = 52, USBD_IRQn = 53, USBH_IRQn = 54, USBOTG_IRQn = 55, CAN0_IRQn = 56, CAN1_IRQn = 57, SC0_IRQn = 58, SC1_IRQn = 59, SC2_IRQn = 60, SPI3_IRQn = 62, EMAC_TX_IRQn = 66, EMAC_RX_IRQn = 67, SDH0_IRQn = 64, USBD20_IRQn = 65, I2S0_IRQn = 68, OPA_IRQn = 70, CRPT_IRQn = 71, GPG_IRQn = 72, EINT6_IRQn = 73, UART4_IRQn = 74, UART5_IRQn = 75, USCI0_IRQn = 76, USCI1_IRQn = 77, BPWM0_IRQn = 78, BPWM1_IRQn = 79, SPIM_IRQn = 80, CCAP_IRQn = 81, I2C2_IRQn = 82, QEI0_IRQn = 84, QEI1_IRQn = 85, ECAP0_IRQn = 86, ECAP1_IRQn = 87, GPH_IRQn = 88, EINT7_IRQn = 89, SDH1_IRQn = 90, HSUSBH_IRQn = 92, USBOTG20_IRQn = 93, TRNG_IRQn = 101, UART6_IRQn = 102, UART7_IRQn = 103, EADC10_IRQn = 104, EADC11_IRQn = 105, EADC12_IRQn = 106, EADC13_IRQn = 107, CAN2_IRQn = 108 }

## Detailed Description

M480 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro M480 MCU.

Version
  V1.00 SPDX-License-Identifier: Apache-2.0

Copyright
  (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.

Definition in file M480.h.