| M480 BSP V3.05.001 The Board Support Package for M480 Series

Macros
CLK Exported Constants
Standard Driver » CLK Driver

## Macros
#define | FREQ_25MHZ
#define | FREQ_50MHZ
#define | FREQ_72MHZ
#define | FREQ_80MHZ
#define | FREQ_100MHZ
#define | FREQ_125MHZ
#define | FREQ_160MHZ
#define | FREQ_192MHZ
#define | FREQ_200MHZ
#define | FREQ_250MHZ
#define | FREQ_500MHZ
#define | CLK_CLKSEL0_HCLKSEL_HXT
#define | CLK_CLKSEL0_HCLKSEL_LXT
#define | CLK_CLKSEL0_HCLKSEL_PLL
#define | CLK_CLKSEL0_HCLKSEL_LIRC
#define | CLK_CLKSEL0_HCLKSEL_HIRC
#define | CLK_CLKSEL0_STCLKSEL_HXT
#define | CLK_CLKSEL0_STCLKSEL_LXT
#define | CLK_CLKSEL0_STCLKSEL_HXT_DIV2
#define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
#define | CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
#define | CLK_CLKSEL0_STCLKSEL_HCLK
#define | CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)
#define | CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)
#define | CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)
#define | CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)
#define | CLK_CLKSEL0_SDH0SEL_HXT
#define | CLK_CLKSEL0_SDH0SEL_PLL
#define | CLK_CLKSEL0_SDH0SEL_HIRC
#define | CLK_CLKSEL0_SDH0SEL_HCLK
#define | CLK_CLKSEL0_SDH1SEL_HXT
#define | CLK_CLKSEL0_SDH1SEL_PLL
#define | CLK_CLKSEL0_SDH1SEL_HIRC
#define | CLK_CLKSEL0_SDH1SEL_HCLK
#define | CLK_CLKSEL0_USBSEL_RC48M
#define | CLK_CLKSEL0_USBSEL_PLL
#define | CLK_CLKSEL1_WDTSEL_LXT
#define | CLK_CLKSEL1_WDTSEL_LIRC
#define | CLK_CLKSEL1_WDTSEL_HCLK_DIV2048
#define | CLK_CLKSEL1_TMR0SEL_HXT
#define | CLK_CLKSEL1_TMR0SEL_LXT
#define | CLK_CLKSEL1_TMR0SEL_LIRC
#define | CLK_CLKSEL1_TMR0SEL_HIRC
#define | CLK_CLKSEL1_TMR0SEL_PCLK0
#define | CLK_CLKSEL1_TMR0SEL_EXT
#define | CLK_CLKSEL1_TMR1SEL_HXT
#define | CLK_CLKSEL1_TMR1SEL_LXT
#define | CLK_CLKSEL1_TMR1SEL_LIRC
#define | CLK_CLKSEL1_TMR1SEL_HIRC
#define | CLK_CLKSEL1_TMR1SEL_PCLK0
#define | CLK_CLKSEL1_TMR1SEL_EXT
#define | CLK_CLKSEL1_TMR2SEL_HXT
#define | CLK_CLKSEL1_TMR2SEL_LXT
#define | CLK_CLKSEL1_TMR2SEL_LIRC
#define | CLK_CLKSEL1_TMR2SEL_HIRC
#define | CLK_CLKSEL1_TMR2SEL_PCLK1
#define | CLK_CLKSEL1_TMR2SEL_EXT
#define | CLK_CLKSEL1_TMR3SEL_HXT
#define | CLK_CLKSEL1_TMR3SEL_LXT
#define | CLK_CLKSEL1_TMR3SEL_LIRC
#define | CLK_CLKSEL1_TMR3SEL_HIRC
#define | CLK_CLKSEL1_TMR3SEL_PCLK1
#define | CLK_CLKSEL1_TMR3SEL_EXT
#define | CLK_CLKSEL1_UART0SEL_HXT
#define | CLK_CLKSEL1_UART0SEL_LXT
#define | CLK_CLKSEL1_UART0SEL_PLL
#define | CLK_CLKSEL1_UART0SEL_HIRC
#define | CLK_CLKSEL1_UART1SEL_HXT
#define | CLK_CLKSEL1_UART1SEL_LXT
#define | CLK_CLKSEL1_UART1SEL_PLL
#define | CLK_CLKSEL1_UART1SEL_HIRC
#define | CLK_CLKSEL1_CLKOSEL_HXT
#define | CLK_CLKSEL1_CLKOSEL_LXT
#define | CLK_CLKSEL1_CLKOSEL_HIRC
#define | CLK_CLKSEL1_CLKOSEL_HCLK
#define | CLK_CLKSEL1_WWDTSEL_LIRC
#define | CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048
#define | CLK_CLKSEL2_QSPI0SEL_HXT
#define | CLK_CLKSEL2_QSPI0SEL_PLL
#define | CLK_CLKSEL2_QSPI0SEL_HIRC
#define | CLK_CLKSEL2_QSPI0SEL_PCLK0
#define | CLK_CLKSEL2_SPI0SEL_HXT
#define | CLK_CLKSEL2_SPI0SEL_PLL
#define | CLK_CLKSEL2_SPI0SEL_HIRC
#define | CLK_CLKSEL2_SPI0SEL_PCLK1
#define | CLK_CLKSEL2_SPI1SEL_HXT
#define | CLK_CLKSEL2_SPI1SEL_PLL
#define | CLK_CLKSEL2_SPI1SEL_HIRC
#define | CLK_CLKSEL2_SPI1SEL_PCLK0
#define | CLK_CLKSEL2_EPWM0SEL_PLL
#define | CLK_CLKSEL2_EPWM0SEL_PCLK0
#define | CLK_CLKSEL2_EPWM1SEL_PLL
#define | CLK_CLKSEL2_EPWM1SEL_PCLK1
#define | CLK_CLKSEL2_BPWM0SEL_PLL
#define | CLK_CLKSEL2_BPWM0SEL_PCLK0
#define | CLK_CLKSEL2_BPWM1SEL_PLL
#define | CLK_CLKSEL2_BPWM1SEL_PCLK1
#define | CLK_CLKSEL2_SPI2SEL_HXT
#define | CLK_CLKSEL2_SPI2SEL_PLL
#define | CLK_CLKSEL2_SPI2SEL_HIRC
#define | CLK_CLKSEL2_SPI2SEL_PCLK1
#define | CLK_CLKSEL2_SPI3SEL_HXT
#define | CLK_CLKSEL2_SPI3SEL_PLL
#define | CLK_CLKSEL2_SPI3SEL_HIRC
#define | CLK_CLKSEL2_SPI3SEL_PCLK0
#define | CLK_CLKSEL3_SC0SEL_HXT
#define | CLK_CLKSEL3_SC0SEL_PLL
#define | CLK_CLKSEL3_SC0SEL_HIRC
#define | CLK_CLKSEL3_SC0SEL_PCLK0
#define | CLK_CLKSEL3_SC1SEL_HXT
#define | CLK_CLKSEL3_SC1SEL_PLL
#define | CLK_CLKSEL3_SC1SEL_HIRC
#define | CLK_CLKSEL3_SC1SEL_PCLK1
#define | CLK_CLKSEL3_SC2SEL_HXT
#define | CLK_CLKSEL3_SC2SEL_PLL
#define | CLK_CLKSEL3_SC2SEL_HIRC
#define | CLK_CLKSEL3_SC2SEL_PCLK0
#define | CLK_CLKSEL3_RTCSEL_LXT
#define | CLK_CLKSEL3_RTCSEL_LIRC
#define | CLK_CLKSEL3_QSPI1SEL_HXT
#define | CLK_CLKSEL3_QSPI1SEL_PLL
#define | CLK_CLKSEL3_QSPI1SEL_HIRC
#define | CLK_CLKSEL3_QSPI1SEL_PCLK1
#define | CLK_CLKSEL3_I2S0SEL_HXT
#define | CLK_CLKSEL3_I2S0SEL_PLL
#define | CLK_CLKSEL3_I2S0SEL_HIRC
#define | CLK_CLKSEL3_I2S0SEL_PCLK0
#define | CLK_CLKSEL3_UART2SEL_HXT
#define | CLK_CLKSEL3_UART2SEL_LXT
#define | CLK_CLKSEL3_UART2SEL_PLL
#define | CLK_CLKSEL3_UART2SEL_HIRC
#define | CLK_CLKSEL3_UART3SEL_HXT
#define | CLK_CLKSEL3_UART3SEL_LXT
#define | CLK_CLKSEL3_UART3SEL_PLL
#define | CLK_CLKSEL3_UART3SEL_HIRC
#define | CLK_CLKSEL3_UART4SEL_HXT
#define | CLK_CLKSEL3_UART4SEL_LXT
#define | CLK_CLKSEL3_UART4SEL_PLL
#define | CLK_CLKSEL3_UART4SEL_HIRC
#define | CLK_CLKSEL3_UART5SEL_HXT
#define | CLK_CLKSEL3_UART5SEL_LXT
#define | CLK_CLKSEL3_UART5SEL_PLL
#define | CLK_CLKSEL3_UART5SEL_HIRC
#define | CLK_CLKSEL3_UART6SEL_HXT
#define | CLK_CLKSEL3_UART6SEL_LXT
#define | CLK_CLKSEL3_UART6SEL_PLL
#define | CLK_CLKSEL3_UART6SEL_HIRC
#define | CLK_CLKSEL3_UART7SEL_HXT
#define | CLK_CLKSEL3_UART7SEL_LXT
#define | CLK_CLKSEL3_UART7SEL_PLL
#define | CLK_CLKSEL3_UART7SEL_HIRC
#define | CLK_CLKDIV0_HCLK(x)
#define | CLK_CLKDIV0_USB(x)
#define | CLK_CLKDIV0_SDH0(x)
#define | CLK_CLKDIV0_UART0(x)
#define | CLK_CLKDIV0_UART1(x)
#define | CLK_CLKDIV0_EADC(x)
#define | CLK_CLKDIV1_SC0(x)
#define | CLK_CLKDIV1_SC1(x)
#define | CLK_CLKDIV1_SC2(x)
#define | CLK_CLKDIV2_I2S0(x) (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos)
#define | CLK_CLKDIV2_EADC1(x) (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos)
#define | CLK_CLKDIV3_CCAP(x) (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos)
#define | CLK_CLKDIV3_VSENSE(x) (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos)
#define | CLK_CLKDIV3_EMAC(x)
#define | CLK_CLKDIV3_SDH1(x)
#define | CLK_CLKDIV4_UART2(x)
#define | CLK_CLKDIV4_UART3(x)
#define | CLK_CLKDIV4_UART4(x)
#define | CLK_CLKDIV4_UART5(x)
#define | CLK_CLKDIV4_UART6(x) (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos)
#define | CLK_CLKDIV4_UART7(x) (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos)
#define | CLK_PCLKDIV_PCLK0DIV1
#define | CLK_PCLKDIV_PCLK0DIV2
#define | CLK_PCLKDIV_PCLK0DIV4
#define | CLK_PCLKDIV_PCLK0DIV8
#define | CLK_PCLKDIV_PCLK0DIV16
#define | CLK_PCLKDIV_PCLK1DIV1
#define | CLK_PCLKDIV_PCLK1DIV2
#define | CLK_PCLKDIV_PCLK1DIV4
#define | CLK_PCLKDIV_PCLK1DIV8
#define | CLK_PCLKDIV_PCLK1DIV16
#define | CLK_PCLKDIV_APB0DIV_DIV1
#define | CLK_PCLKDIV_APB0DIV_DIV2
#define | CLK_PCLKDIV_APB0DIV_DIV4
#define | CLK_PCLKDIV_APB0DIV_DIV8
#define | CLK_PCLKDIV_APB0DIV_DIV16
#define | CLK_PCLKDIV_APB1DIV_DIV1
#define | CLK_PCLKDIV_APB1DIV_DIV2
#define | CLK_PCLKDIV_APB1DIV_DIV4
#define | CLK_PCLKDIV_APB1DIV_DIV8
#define | CLK_PCLKDIV_APB1DIV_DIV16
#define | CLK_PLLCTL_PLLSRC_HXT
#define | CLK_PLLCTL_PLLSRC_HIRC
#define | CLK_PLLCTL_NF(x)
#define | CLK_PLLCTL_NR(x)
#define | CLK_PLLCTL_NO_1
#define | CLK_PLLCTL_NO_2
#define | CLK_PLLCTL_NO_4
#define | CLK_PLLCTL_72MHz_HXT
#define | CLK_PLLCTL_80MHz_HXT
#define | CLK_PLLCTL_144MHz_HXT
#define | CLK_PLLCTL_160MHz_HXT
#define | CLK_PLLCTL_192MHz_HXT
#define | CLK_PLLCTL_72MHz_HIRC
#define | CLK_PLLCTL_80MHz_HIRC
#define | CLK_PLLCTL_144MHz_HIRC
#define | CLK_PLLCTL_160MHz_HIRC
#define | CLK_PLLCTL_192MHz_HIRC
#define | MODULE_APBCLK(x)
#define | MODULE_CLKSEL(x)
#define | MODULE_CLKSEL_Msk(x)
#define | MODULE_CLKSEL_Pos(x)
#define | MODULE_CLKDIV(x)
#define | MODULE_CLKDIV_Msk(x)
#define | MODULE_CLKDIV_Pos(x)
#define | MODULE_IP_EN_Pos(x)
#define | MODULE_NoMsk
#define | NA
#define | MODULE_APBCLK_ENC(x)
#define | MODULE_CLKSEL_ENC(x)
#define | MODULE_CLKSEL_Msk_ENC(x)
#define | MODULE_CLKSEL_Pos_ENC(x)
#define | MODULE_CLKDIV_ENC(x)
#define | MODULE_CLKDIV_Msk_ENC(x)
#define | MODULE_CLKDIV_Pos_ENC(x)
#define | MODULE_IP_EN_Pos_ENC(x)
#define | PDMA_MODULE
#define | ISP_MODULE
#define | EBI_MODULE
#define | USBH_MODULE
#define | EMAC_MODULE
#define | SDH0_MODULE
#define | CRC_MODULE
#define | CCAP_MODULE
#define | SEN_MODULE
#define | HSUSBD_MODULE
#define | CRPT_MODULE
#define | SPIM_MODULE
#define | FMCIDLE_MODULE
#define | SDH1_MODULE
#define | WDT_MODULE
#define | RTC_MODULE
#define | TMR0_MODULE
#define | TMR1_MODULE
#define | TMR2_MODULE
#define | TMR3_MODULE
#define | CLKO_MODULE
#define | WWDT_MODULE
#define | ACMP01_MODULE
#define | I2C0_MODULE
#define | I2C1_MODULE
#define | I2C2_MODULE
#define | QSPI0_MODULE
#define | SPI0_MODULE
#define | SPI1_MODULE
#define | SPI2_MODULE
#define | UART0_MODULE
#define | UART1_MODULE
#define | UART2_MODULE
#define | UART3_MODULE
#define | UART4_MODULE
#define | UART5_MODULE
#define | UART6_MODULE
#define | UART7_MODULE
#define | CAN0_MODULE
#define | CAN1_MODULE
#define | OTG_MODULE
#define | USBD_MODULE
#define | EADC_MODULE
#define | I2S0_MODULE
#define | HSOTG_MODULE
#define | SC0_MODULE
#define | SC1_MODULE
#define | SC2_MODULE
#define | QSPI1_MODULE
#define | SPI3_MODULE
#define | USCI0_MODULE
#define | USCI1_MODULE
#define | DAC_MODULE
#define | CAN2_MODULE
#define | EPWM0_MODULE
#define | EPWM1_MODULE
#define | BPWM0_MODULE
#define | BPWM1_MODULE
#define | QEI0_MODULE
#define | QEI1_MODULE
#define | TRNG_MODULE
#define | ECAP0_MODULE
#define | ECAP1_MODULE
#define | OPA_MODULE
#define | EADC1_MODULE
#define | CLK_PMUCTL_PDMSEL_PD
#define | CLK_PMUCTL_PDMSEL_LLPD
#define | CLK_PMUCTL_PDMSEL_FWPD
#define | CLK_PMUCTL_PDMSEL_SPD0
#define | CLK_PMUCTL_PDMSEL_SPD1
#define | CLK_PMUCTL_PDMSEL_DPD
#define | CLK_PMUCTL_WKTMRIS_128
#define | CLK_PMUCTL_WKTMRIS_256
#define | CLK_PMUCTL_WKTMRIS_512
#define | CLK_PMUCTL_WKTMRIS_1024
#define | CLK_PMUCTL_WKTMRIS_4096
#define | CLK_PMUCTL_WKTMRIS_8192
#define | CLK_PMUCTL_WKTMRIS_16384
#define | CLK_PMUCTL_WKTMRIS_65536
#define | CLK_PMUCTL_WKTMRIS_131072
#define | CLK_PMUCTL_WKTMRIS_262144
#define | CLK_PMUCTL_WKTMRIS_524288
#define | CLK_PMUCTL_WKTMRIS_1048576
#define | CLK_SWKDBCTL_SWKDBCLKSEL_1
#define | CLK_SWKDBCTL_SWKDBCLKSEL_2
#define | CLK_SWKDBCTL_SWKDBCLKSEL_4
#define | CLK_SWKDBCTL_SWKDBCLKSEL_8
#define | CLK_SWKDBCTL_SWKDBCLKSEL_16
#define | CLK_SWKDBCTL_SWKDBCLKSEL_32
#define | CLK_SWKDBCTL_SWKDBCLKSEL_64
#define | CLK_SWKDBCTL_SWKDBCLKSEL_128
#define | CLK_SWKDBCTL_SWKDBCLKSEL_256
#define | CLK_SWKDBCTL_SWKDBCLKSEL_2x256
#define | CLK_SWKDBCTL_SWKDBCLKSEL_4x256
#define | CLK_SWKDBCTL_SWKDBCLKSEL_8x256
#define | CLK_SWKDBCTL_SWKDBCLKSEL_16x256
#define | CLK_SWKDBCTL_SWKDBCLKSEL_32x256
#define | CLK_SWKDBCTL_SWKDBCLKSEL_64x256
#define | CLK_SWKDBCTL_SWKDBCLKSEL_128x256
#define | CLK_DPDWKPIN_DISABLE
#define | CLK_DPDWKPIN_RISING
#define | CLK_DPDWKPIN_FALLING
#define | CLK_DPDWKPIN_BOTHEDGE
#define | CLK_DPDWKPIN0_DISABLE
#define | CLK_DPDWKPIN0_RISING
#define | CLK_DPDWKPIN0_FALLING
#define | CLK_DPDWKPIN0_BOTHEDGE
#define | CLK_DPDWKPIN1_DISABLE
#define | CLK_DPDWKPIN1_RISING
#define | CLK_DPDWKPIN1_FALLING
#define | CLK_DPDWKPIN1_BOTHEDGE
#define | CLK_DPDWKPIN2_DISABLE
#define | CLK_DPDWKPIN2_RISING
#define | CLK_DPDWKPIN2_FALLING
#define | CLK_DPDWKPIN2_BOTHEDGE
#define | CLK_DPDWKPIN3_DISABLE
#define | CLK_DPDWKPIN3_RISING
#define | CLK_DPDWKPIN3_FALLING
#define | CLK_DPDWKPIN3_BOTHEDGE
#define | CLK_DPDWKPIN4_DISABLE
#define | CLK_DPDWKPIN4_RISING
#define | CLK_DPDWKPIN4_FALLING
#define | CLK_DPDWKPIN4_BOTHEDGE
#define | CLK_SPDWKPIN_ENABLE
#define | CLK_SPDWKPIN_RISING
#define | CLK_SPDWKPIN_FALLING
#define | CLK_SPDWKPIN_DEBOUNCEEN
#define | CLK_SPDWKPIN_DEBOUNCEDIS
#define | CLK_SPDSRETSEL_NO
#define | CLK_SPDSRETSEL_16K
#define | CLK_SPDSRETSEL_32K
#define | CLK_SPDSRETSEL_64K
#define | CLK_SPDSRETSEL_128K
#define | CLK_DISABLE_WKTMR(void)
#define | CLK_ENABLE_WKTMR(void)
#define | CLK_DISABLE_DPDWKPIN(void)
#define | CLK_DISABLE_DPDWKPIN0(void)
#define | CLK_DISABLE_DPDWKPIN1(void)
#define | CLK_DISABLE_DPDWKPIN2(void)
#define | CLK_DISABLE_DPDWKPIN3(void)
#define | CLK_DISABLE_DPDWKPIN4(void)
#define | CLK_DISABLE_SPDACMP(void)
#define | CLK_ENABLE_SPDACMP(void)
#define | CLK_DISABLE_RTCWK(void)
#define | CLK_ENABLE_RTCWK(void)

## Detailed Description

## Macro Definition Documentation

## ◆ ACMP01_MODULE

#define ACMP01_MODULE

ACMP01 Module

Definition at line 386 of file clk.h.

## ◆ BPWM0_MODULE

#define BPWM0_MODULE

BPWM0 Module

Definition at line 420 of file clk.h.

## ◆ BPWM1_MODULE

#define BPWM1_MODULE

BPWM1 Module

Definition at line 421 of file clk.h.

## ◆ CAN0_MODULE

#define CAN0_MODULE

CAN0 Module

Definition at line 402 of file clk.h.

## ◆ CAN1_MODULE

#define CAN1_MODULE

CAN1 Module

Definition at line 403 of file clk.h.

## ◆ CAN2_MODULE

#define CAN2_MODULE

CAN2 Module

Definition at line 417 of file clk.h.

## ◆ CCAP_MODULE

#define CCAP_MODULE

CCAP Module

Definition at line 371 of file clk.h.

## ◆ CLK_CLKDIV0_EADC

#define CLK_CLKDIV0_EADC | ( |  | x | ) |

CLKDIV0 Setting for EADC clock divider. It could be 1~256

Definition at line 255 of file clk.h.

## ◆ CLK_CLKDIV0_HCLK

#define CLK_CLKDIV0_HCLK | ( |  | x | ) |

CLKDIV0 Setting for HCLK clock divider. It could be 1~16

Definition at line 250 of file clk.h.

## ◆ CLK_CLKDIV0_SDH0

#define CLK_CLKDIV0_SDH0 | ( |  | x | ) |

CLKDIV0 Setting for SDH0 clock divider. It could be 1~256

Definition at line 252 of file clk.h.

## ◆ CLK_CLKDIV0_UART0

#define CLK_CLKDIV0_UART0 | ( |  | x | ) |

CLKDIV0 Setting for UART0 clock divider. It could be 1~16

Definition at line 253 of file clk.h.

## ◆ CLK_CLKDIV0_UART1

#define CLK_CLKDIV0_UART1 | ( |  | x | ) |

CLKDIV0 Setting for UART1 clock divider. It could be 1~16

Definition at line 254 of file clk.h.

## ◆ CLK_CLKDIV0_USB

#define CLK_CLKDIV0_USB | ( |  | x | ) |

CLKDIV0 Setting for USB clock divider. It could be 1~16

Definition at line 251 of file clk.h.

## ◆ CLK_CLKDIV1_SC0

#define CLK_CLKDIV1_SC0 | ( |  | x | ) |

CLKDIV1 Setting for SC0 clock divider. It could be 1~256

Definition at line 260 of file clk.h.

## ◆ CLK_CLKDIV1_SC1

#define CLK_CLKDIV1_SC1 | ( |  | x | ) |

CLKDIV1 Setting for SC1 clock divider. It could be 1~256

Definition at line 261 of file clk.h.

## ◆ CLK_CLKDIV1_SC2

#define CLK_CLKDIV1_SC2 | ( |  | x | ) |

CLKDIV1 Setting for SC2 clock divider. It could be 1~256

Definition at line 262 of file clk.h.

## ◆ CLK_CLKDIV2_EADC1

#define CLK_CLKDIV2_EADC1 | ( |  | x | ) | (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos)

CLKDIV2 Setting for EADC1 clock divider. It could be 1~256

Definition at line 268 of file clk.h.

## ◆ CLK_CLKDIV2_I2S0

#define CLK_CLKDIV2_I2S0 | ( |  | x | ) | (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos)

CLKDIV2 Setting for I2S0 clock divider. It could be 1~16

Definition at line 267 of file clk.h.

## ◆ CLK_CLKDIV3_CCAP

#define CLK_CLKDIV3_CCAP | ( |  | x | ) | (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos)

CLKDIV3 Setting for CCAP clock divider. It could be 1~256

Definition at line 273 of file clk.h.

## ◆ CLK_CLKDIV3_EMAC

#define CLK_CLKDIV3_EMAC | ( |  | x | ) |

CLKDIV3 Setting for EMAC clock divider. It could be 1~256

Definition at line 275 of file clk.h.

## ◆ CLK_CLKDIV3_SDH1

#define CLK_CLKDIV3_SDH1 | ( |  | x | ) |

CLKDIV3 Setting for SDH1 clock divider. It could be 1~256

Definition at line 276 of file clk.h.

## ◆ CLK_CLKDIV3_VSENSE

#define CLK_CLKDIV3_VSENSE | ( |  | x | ) | (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos)

CLKDIV3 Setting for VSENSE clock divider. It could be 1~256

Definition at line 274 of file clk.h.

## ◆ CLK_CLKDIV4_UART2

#define CLK_CLKDIV4_UART2 | ( |  | x | ) |

CLKDIV4 Setting for UART2 clock divider. It could be 1~16

Definition at line 281 of file clk.h.

## ◆ CLK_CLKDIV4_UART3

#define CLK_CLKDIV4_UART3 | ( |  | x | ) |

CLKDIV4 Setting for UART3 clock divider. It could be 1~16

Definition at line 282 of file clk.h.

## ◆ CLK_CLKDIV4_UART4

#define CLK_CLKDIV4_UART4 | ( |  | x | ) |

CLKDIV4 Setting for UART4 clock divider. It could be 1~16

Definition at line 283 of file clk.h.

## ◆ CLK_CLKDIV4_UART5

#define CLK_CLKDIV4_UART5 | ( |  | x | ) |

CLKDIV4 Setting for UART5 clock divider. It could be 1~16

Definition at line 284 of file clk.h.

## ◆ CLK_CLKDIV4_UART6

#define CLK_CLKDIV4_UART6 | ( |  | x | ) | (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos)

CLKDIV4 Setting for UART6 clock divider. It could be 1~16

Definition at line 285 of file clk.h.

## ◆ CLK_CLKDIV4_UART7

#define CLK_CLKDIV4_UART7 | ( |  | x | ) | (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos)

CLKDIV4 Setting for UART7 clock divider. It could be 1~16

Definition at line 286 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_HCLK [1/2]

#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from HCLK

Definition at line 76 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_HCLK [2/2]

#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from HCLK

Definition at line 76 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_HIRC [1/2]

#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from HIRC

Select CCAP clock source from high speed oscillator

Definition at line 75 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_HIRC [2/2]

#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from HIRC

Select CCAP clock source from high speed oscillator

Definition at line 75 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_HXT [1/2]

#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from HXT

Select CCAP clock source from high speed crystal

Definition at line 73 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_HXT [2/2]

#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from HXT

Select CCAP clock source from high speed crystal

Definition at line 73 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_PLL [1/2]

#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from PLL

Definition at line 74 of file clk.h.

## ◆ CLK_CLKSEL0_CCAPSEL_PLL [2/2]

#define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)

Select CCAP clock source from PLL

Definition at line 74 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HIRC

#define CLK_CLKSEL0_HCLKSEL_HIRC

Select HCLK clock source from high speed oscillator

Definition at line 50 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HXT

#define CLK_CLKSEL0_HCLKSEL_HXT

Select HCLK clock source from high speed crystal

Definition at line 46 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LIRC

#define CLK_CLKSEL0_HCLKSEL_LIRC

Select HCLK clock source from low speed oscillator

Definition at line 49 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LXT

#define CLK_CLKSEL0_HCLKSEL_LXT

Select HCLK clock source from low speed crystal

Definition at line 47 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_PLL

#define CLK_CLKSEL0_HCLKSEL_PLL

Select HCLK clock source from PLL

Definition at line 48 of file clk.h.

## ◆ CLK_CLKSEL0_SDH0SEL_HCLK

#define CLK_CLKSEL0_SDH0SEL_HCLK

Select SDH0 clock source from HCLK

Definition at line 81 of file clk.h.

## ◆ CLK_CLKSEL0_SDH0SEL_HIRC

#define CLK_CLKSEL0_SDH0SEL_HIRC

Select SDH0 clock source from high speed oscillator

Definition at line 80 of file clk.h.

## ◆ CLK_CLKSEL0_SDH0SEL_HXT

#define CLK_CLKSEL0_SDH0SEL_HXT

Select SDH0 clock source from high speed crystal

Definition at line 78 of file clk.h.

## ◆ CLK_CLKSEL0_SDH0SEL_PLL

#define CLK_CLKSEL0_SDH0SEL_PLL

Select SDH0 clock source from PLL

Definition at line 79 of file clk.h.

## ◆ CLK_CLKSEL0_SDH1SEL_HCLK

#define CLK_CLKSEL0_SDH1SEL_HCLK

Select SDH1 clock source from HCLK

Definition at line 86 of file clk.h.

## ◆ CLK_CLKSEL0_SDH1SEL_HIRC

#define CLK_CLKSEL0_SDH1SEL_HIRC

Select SDH1 clock source from high speed oscillator

Definition at line 85 of file clk.h.

## ◆ CLK_CLKSEL0_SDH1SEL_HXT

#define CLK_CLKSEL0_SDH1SEL_HXT

Select SDH1 clock source from high speed crystal

Definition at line 83 of file clk.h.

## ◆ CLK_CLKSEL0_SDH1SEL_PLL

#define CLK_CLKSEL0_SDH1SEL_PLL

Select SDH1 clock source from PLL

Definition at line 84 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK

#define CLK_CLKSEL0_STCLKSEL_HCLK

Select SysTick clock source from HCLK

Definition at line 57 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK_DIV2

#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2

Select SysTick clock source from HCLK/2

Definition at line 55 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

Select SysTick clock source from HIRC/2

Definition at line 56 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HXT

#define CLK_CLKSEL0_STCLKSEL_HXT

Select SysTick clock source from high speed crystal

Definition at line 52 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HXT_DIV2

#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2

Select SysTick clock source from HXT/2

Definition at line 54 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_LXT

#define CLK_CLKSEL0_STCLKSEL_LXT

Select SysTick clock source from low speed crystal

Definition at line 53 of file clk.h.

## ◆ CLK_CLKSEL0_USBSEL_PLL

#define CLK_CLKSEL0_USBSEL_PLL

Select USB clock source from PLL

Definition at line 89 of file clk.h.

## ◆ CLK_CLKSEL0_USBSEL_RC48M

#define CLK_CLKSEL0_USBSEL_RC48M

Select USB clock source from RC48M

Definition at line 88 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_HCLK

#define CLK_CLKSEL1_CLKOSEL_HCLK

Select CLKO clock source from HCLK

Definition at line 139 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_HIRC

#define CLK_CLKSEL1_CLKOSEL_HIRC

Select CLKO clock source from high speed oscillator

Definition at line 138 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_HXT

#define CLK_CLKSEL1_CLKOSEL_HXT

Select CLKO clock source from high speed crystal

Definition at line 136 of file clk.h.

## ◆ CLK_CLKSEL1_CLKOSEL_LXT

#define CLK_CLKSEL1_CLKOSEL_LXT

Select CLKO clock source from low speed crystal

Definition at line 137 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_EXT

#define CLK_CLKSEL1_TMR0SEL_EXT

Select TMR0 clock source from external trigger

Definition at line 103 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HIRC

#define CLK_CLKSEL1_TMR0SEL_HIRC

Select TMR0 clock source from high speed oscillator

Definition at line 101 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HXT

#define CLK_CLKSEL1_TMR0SEL_HXT

Select TMR0 clock source from high speed crystal

Definition at line 98 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_LIRC

#define CLK_CLKSEL1_TMR0SEL_LIRC

Select TMR0 clock source from low speed oscillator

Definition at line 100 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_LXT

#define CLK_CLKSEL1_TMR0SEL_LXT

Select TMR0 clock source from low speed crystal

Definition at line 99 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_PCLK0

#define CLK_CLKSEL1_TMR0SEL_PCLK0

Select TMR0 clock source from PCLK0

Definition at line 102 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_EXT

#define CLK_CLKSEL1_TMR1SEL_EXT

Select TMR1 clock source from external trigger

Definition at line 110 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HIRC

#define CLK_CLKSEL1_TMR1SEL_HIRC

Select TMR1 clock source from high speed oscillator

Definition at line 108 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HXT

#define CLK_CLKSEL1_TMR1SEL_HXT

Select TMR1 clock source from high speed crystal

Definition at line 105 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_LIRC

#define CLK_CLKSEL1_TMR1SEL_LIRC

Select TMR1 clock source from low speed oscillator

Definition at line 107 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_LXT

#define CLK_CLKSEL1_TMR1SEL_LXT

Select TMR1 clock source from low speed crystal

Definition at line 106 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_PCLK0

#define CLK_CLKSEL1_TMR1SEL_PCLK0

Select TMR1 clock source from PCLK0

Definition at line 109 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_EXT

#define CLK_CLKSEL1_TMR2SEL_EXT

Select TMR2 clock source from external trigger

Definition at line 117 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_HIRC

#define CLK_CLKSEL1_TMR2SEL_HIRC

Select TMR2 clock source from high speed oscillator

Definition at line 115 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_HXT

#define CLK_CLKSEL1_TMR2SEL_HXT

Select TMR2 clock source from high speed crystal

Definition at line 112 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_LIRC

#define CLK_CLKSEL1_TMR2SEL_LIRC

Select TMR2 clock source from low speed oscillator

Definition at line 114 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_LXT

#define CLK_CLKSEL1_TMR2SEL_LXT

Select TMR2 clock source from low speed crystal

Definition at line 113 of file clk.h.

## ◆ CLK_CLKSEL1_TMR2SEL_PCLK1

#define CLK_CLKSEL1_TMR2SEL_PCLK1

Select TMR2 clock source from PCLK1

Definition at line 116 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_EXT

#define CLK_CLKSEL1_TMR3SEL_EXT

Select TMR3 clock source from external trigger

Definition at line 124 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_HIRC

#define CLK_CLKSEL1_TMR3SEL_HIRC

Select TMR3 clock source from high speed oscillator

Definition at line 122 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_HXT

#define CLK_CLKSEL1_TMR3SEL_HXT

Select TMR3 clock source from high speed crystal

Definition at line 119 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_LIRC

#define CLK_CLKSEL1_TMR3SEL_LIRC

Select TMR3 clock source from low speed oscillator

Definition at line 121 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_LXT

#define CLK_CLKSEL1_TMR3SEL_LXT

Select TMR3 clock source from low speed crystal

Definition at line 120 of file clk.h.

## ◆ CLK_CLKSEL1_TMR3SEL_PCLK1

#define CLK_CLKSEL1_TMR3SEL_PCLK1

Select TMR3 clock source from PCLK1

Definition at line 123 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_HIRC

#define CLK_CLKSEL1_UART0SEL_HIRC

Select UART0 clock source from high speed oscillator

Definition at line 129 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_HXT

#define CLK_CLKSEL1_UART0SEL_HXT

Select UART0 clock source from high speed crystal

Definition at line 126 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_LXT

#define CLK_CLKSEL1_UART0SEL_LXT

Select UART0 clock source from low speed crystal

Definition at line 127 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_PLL

#define CLK_CLKSEL1_UART0SEL_PLL

Select UART0 clock source from PLL

Definition at line 128 of file clk.h.

## ◆ CLK_CLKSEL1_UART1SEL_HIRC

#define CLK_CLKSEL1_UART1SEL_HIRC

Select UART1 clock source from high speed oscillator

Definition at line 134 of file clk.h.

## ◆ CLK_CLKSEL1_UART1SEL_HXT

#define CLK_CLKSEL1_UART1SEL_HXT

Select UART1 clock source from high speed crystal

Definition at line 131 of file clk.h.

## ◆ CLK_CLKSEL1_UART1SEL_LXT

#define CLK_CLKSEL1_UART1SEL_LXT

Select UART1 clock source from low speed crystal

Definition at line 132 of file clk.h.

## ◆ CLK_CLKSEL1_UART1SEL_PLL

#define CLK_CLKSEL1_UART1SEL_PLL

Select UART1 clock source from PLL

Definition at line 133 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_HCLK_DIV2048

#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048

Select WDT clock source from HCLK/2048

Definition at line 96 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_LIRC

#define CLK_CLKSEL1_WDTSEL_LIRC

Select WDT clock source from low speed oscillator

Definition at line 95 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_LXT

#define CLK_CLKSEL1_WDTSEL_LXT

Select WDT clock source from low speed crystal

Definition at line 94 of file clk.h.

## ◆ CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048

#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048

Select WWDT clock source from HCLK/2048

Definition at line 142 of file clk.h.

## ◆ CLK_CLKSEL1_WWDTSEL_LIRC

#define CLK_CLKSEL1_WWDTSEL_LIRC

Select WWDT clock source from low speed oscillator

Definition at line 141 of file clk.h.

## ◆ CLK_CLKSEL2_BPWM0SEL_PCLK0

#define CLK_CLKSEL2_BPWM0SEL_PCLK0

Select BPWM0 clock source from PCLK0

Definition at line 170 of file clk.h.

## ◆ CLK_CLKSEL2_BPWM0SEL_PLL

#define CLK_CLKSEL2_BPWM0SEL_PLL

Select BPWM0 clock source from PLL

Definition at line 169 of file clk.h.

## ◆ CLK_CLKSEL2_BPWM1SEL_PCLK1

#define CLK_CLKSEL2_BPWM1SEL_PCLK1

Select BPWM1 clock source from PCLK1

Definition at line 173 of file clk.h.

## ◆ CLK_CLKSEL2_BPWM1SEL_PLL

#define CLK_CLKSEL2_BPWM1SEL_PLL

Select BPWM1 clock source from PLL

Definition at line 172 of file clk.h.

## ◆ CLK_CLKSEL2_EPWM0SEL_PCLK0

#define CLK_CLKSEL2_EPWM0SEL_PCLK0

Select EPWM0 clock source from PCLK0

Definition at line 164 of file clk.h.

## ◆ CLK_CLKSEL2_EPWM0SEL_PLL

#define CLK_CLKSEL2_EPWM0SEL_PLL

Select EPWM0 clock source from PLL

Definition at line 163 of file clk.h.

## ◆ CLK_CLKSEL2_EPWM1SEL_PCLK1

#define CLK_CLKSEL2_EPWM1SEL_PCLK1

Select EPWM1 clock source from PCLK1

Definition at line 167 of file clk.h.

## ◆ CLK_CLKSEL2_EPWM1SEL_PLL

#define CLK_CLKSEL2_EPWM1SEL_PLL

Select EPWM1 clock source from PLL

Definition at line 166 of file clk.h.

## ◆ CLK_CLKSEL2_QSPI0SEL_HIRC

#define CLK_CLKSEL2_QSPI0SEL_HIRC

Select QSPI0 clock source from high speed oscillator

Definition at line 150 of file clk.h.

## ◆ CLK_CLKSEL2_QSPI0SEL_HXT

#define CLK_CLKSEL2_QSPI0SEL_HXT

Select QSPI0 clock source from high speed crystal

Definition at line 148 of file clk.h.

## ◆ CLK_CLKSEL2_QSPI0SEL_PCLK0

#define CLK_CLKSEL2_QSPI0SEL_PCLK0

Select QSPI0 clock source from PCLK0

Definition at line 151 of file clk.h.

## ◆ CLK_CLKSEL2_QSPI0SEL_PLL

#define CLK_CLKSEL2_QSPI0SEL_PLL

Select QSPI0 clock source from PLL

Definition at line 149 of file clk.h.

## ◆ CLK_CLKSEL2_SPI0SEL_HIRC

#define CLK_CLKSEL2_SPI0SEL_HIRC

Select SPI0 clock source from high speed oscillator

Definition at line 155 of file clk.h.

## ◆ CLK_CLKSEL2_SPI0SEL_HXT

#define CLK_CLKSEL2_SPI0SEL_HXT

Select SPI0 clock source from high speed crystal

Definition at line 153 of file clk.h.

## ◆ CLK_CLKSEL2_SPI0SEL_PCLK1

#define CLK_CLKSEL2_SPI0SEL_PCLK1

Select SPI0 clock source from PCLK1

Definition at line 156 of file clk.h.

## ◆ CLK_CLKSEL2_SPI0SEL_PLL

#define CLK_CLKSEL2_SPI0SEL_PLL

Select SPI0 clock source from PLL

Definition at line 154 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_HIRC

#define CLK_CLKSEL2_SPI1SEL_HIRC

Select SPI1 clock source from high speed oscillator

Definition at line 160 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_HXT

#define CLK_CLKSEL2_SPI1SEL_HXT

Select SPI1 clock source from high speed crystal

Definition at line 158 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_PCLK0

#define CLK_CLKSEL2_SPI1SEL_PCLK0

Select SPI1 clock source from PCLK0

Definition at line 161 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_PLL

#define CLK_CLKSEL2_SPI1SEL_PLL

Select SPI1 clock source from PLL

Definition at line 159 of file clk.h.

## ◆ CLK_CLKSEL2_SPI2SEL_HIRC

#define CLK_CLKSEL2_SPI2SEL_HIRC

Select SPI2 clock source from high speed oscillator

Definition at line 177 of file clk.h.

## ◆ CLK_CLKSEL2_SPI2SEL_HXT

#define CLK_CLKSEL2_SPI2SEL_HXT

Select SPI2 clock source from high speed crystal

Definition at line 175 of file clk.h.

## ◆ CLK_CLKSEL2_SPI2SEL_PCLK1

#define CLK_CLKSEL2_SPI2SEL_PCLK1

Select SPI2 clock source from PCLK1

Definition at line 178 of file clk.h.

## ◆ CLK_CLKSEL2_SPI2SEL_PLL

#define CLK_CLKSEL2_SPI2SEL_PLL

Select SPI2 clock source from PLL

Definition at line 176 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_HIRC

#define CLK_CLKSEL2_SPI3SEL_HIRC

Select SPI3 clock source from high speed oscillator

Definition at line 182 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_HXT

#define CLK_CLKSEL2_SPI3SEL_HXT

Select SPI3 clock source from high speed crystal

Definition at line 180 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_PCLK0

#define CLK_CLKSEL2_SPI3SEL_PCLK0

Select SPI3 clock source from PCLK0

Definition at line 183 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_PLL

#define CLK_CLKSEL2_SPI3SEL_PLL

Select SPI3 clock source from PLL

Definition at line 181 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_HIRC

#define CLK_CLKSEL3_I2S0SEL_HIRC

Select I2S0 clock source from high speed oscillator

Definition at line 214 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_HXT

#define CLK_CLKSEL3_I2S0SEL_HXT

Select I2S0 clock source from high speed crystal

Definition at line 212 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_PCLK0

#define CLK_CLKSEL3_I2S0SEL_PCLK0

Select I2S0 clock source from PCLK0

Definition at line 215 of file clk.h.

## ◆ CLK_CLKSEL3_I2S0SEL_PLL

#define CLK_CLKSEL3_I2S0SEL_PLL

Select I2S0 clock source from PLL

Definition at line 213 of file clk.h.

## ◆ CLK_CLKSEL3_QSPI1SEL_HIRC

#define CLK_CLKSEL3_QSPI1SEL_HIRC

Select QSPI1 clock source from high speed oscillator

Definition at line 209 of file clk.h.

## ◆ CLK_CLKSEL3_QSPI1SEL_HXT

#define CLK_CLKSEL3_QSPI1SEL_HXT

Select QSPI1 clock source from high speed crystal

Definition at line 207 of file clk.h.

## ◆ CLK_CLKSEL3_QSPI1SEL_PCLK1

#define CLK_CLKSEL3_QSPI1SEL_PCLK1

Select QSPI1 clock source from PCLK1

Definition at line 210 of file clk.h.

## ◆ CLK_CLKSEL3_QSPI1SEL_PLL

#define CLK_CLKSEL3_QSPI1SEL_PLL

Select QSPI1 clock source from PLL

Definition at line 208 of file clk.h.

## ◆ CLK_CLKSEL3_RTCSEL_LIRC

#define CLK_CLKSEL3_RTCSEL_LIRC

Select RTC clock source from low speed oscillator

Definition at line 205 of file clk.h.

## ◆ CLK_CLKSEL3_RTCSEL_LXT

#define CLK_CLKSEL3_RTCSEL_LXT

Select RTC clock source from low speed crystal

Definition at line 204 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_HIRC

#define CLK_CLKSEL3_SC0SEL_HIRC

Select SC0 clock source from high speed oscillator

Definition at line 191 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_HXT

#define CLK_CLKSEL3_SC0SEL_HXT

Select SC0 clock source from high speed crystal

Definition at line 189 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_PCLK0

#define CLK_CLKSEL3_SC0SEL_PCLK0

Select SC0 clock source from PCLK0

Definition at line 192 of file clk.h.

## ◆ CLK_CLKSEL3_SC0SEL_PLL

#define CLK_CLKSEL3_SC0SEL_PLL

Select SC0 clock source from PLL

Definition at line 190 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_HIRC

#define CLK_CLKSEL3_SC1SEL_HIRC

Select SC1 clock source from high speed oscillator

Definition at line 196 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_HXT

#define CLK_CLKSEL3_SC1SEL_HXT

Select SC1 clock source from high speed crystal

Definition at line 194 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_PCLK1

#define CLK_CLKSEL3_SC1SEL_PCLK1

Select SC1 clock source from PCLK1

Definition at line 197 of file clk.h.

## ◆ CLK_CLKSEL3_SC1SEL_PLL

#define CLK_CLKSEL3_SC1SEL_PLL

Select SC1 clock source from PLL

Definition at line 195 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_HIRC

#define CLK_CLKSEL3_SC2SEL_HIRC

Select SC2 clock source from high speed oscillator

Definition at line 201 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_HXT

#define CLK_CLKSEL3_SC2SEL_HXT

Select SC2 clock source from high speed crystal

Definition at line 199 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_PCLK0

#define CLK_CLKSEL3_SC2SEL_PCLK0

Select SC2 clock source from PCLK0

Definition at line 202 of file clk.h.

## ◆ CLK_CLKSEL3_SC2SEL_PLL

#define CLK_CLKSEL3_SC2SEL_PLL

Select SC2 clock source from PLL

Definition at line 200 of file clk.h.

## ◆ CLK_CLKSEL3_UART2SEL_HIRC

#define CLK_CLKSEL3_UART2SEL_HIRC

Select UART2 clock source from high speed oscillator

Definition at line 220 of file clk.h.

## ◆ CLK_CLKSEL3_UART2SEL_HXT

#define CLK_CLKSEL3_UART2SEL_HXT

Select UART2 clock source from high speed crystal

Definition at line 217 of file clk.h.

## ◆ CLK_CLKSEL3_UART2SEL_LXT

#define CLK_CLKSEL3_UART2SEL_LXT

Select UART2 clock source from low speed crystal

Definition at line 218 of file clk.h.

## ◆ CLK_CLKSEL3_UART2SEL_PLL

#define CLK_CLKSEL3_UART2SEL_PLL

Select UART2 clock source from PLL

Definition at line 219 of file clk.h.

## ◆ CLK_CLKSEL3_UART3SEL_HIRC

#define CLK_CLKSEL3_UART3SEL_HIRC

Select UART3 clock source from high speed oscillator

Definition at line 225 of file clk.h.

## ◆ CLK_CLKSEL3_UART3SEL_HXT

#define CLK_CLKSEL3_UART3SEL_HXT

Select UART3 clock source from high speed crystal

Definition at line 222 of file clk.h.

## ◆ CLK_CLKSEL3_UART3SEL_LXT

#define CLK_CLKSEL3_UART3SEL_LXT

Select UART3 clock source from low speed crystal

Definition at line 223 of file clk.h.

## ◆ CLK_CLKSEL3_UART3SEL_PLL

#define CLK_CLKSEL3_UART3SEL_PLL

Select UART3 clock source from PLL

Definition at line 224 of file clk.h.

## ◆ CLK_CLKSEL3_UART4SEL_HIRC

#define CLK_CLKSEL3_UART4SEL_HIRC

Select UART4 clock source from high speed oscillator

Definition at line 230 of file clk.h.

## ◆ CLK_CLKSEL3_UART4SEL_HXT

#define CLK_CLKSEL3_UART4SEL_HXT

Select UART4 clock source from high speed crystal

Definition at line 227 of file clk.h.

## ◆ CLK_CLKSEL3_UART4SEL_LXT

#define CLK_CLKSEL3_UART4SEL_LXT

Select UART4 clock source from low speed crystal

Definition at line 228 of file clk.h.

## ◆ CLK_CLKSEL3_UART4SEL_PLL

#define CLK_CLKSEL3_UART4SEL_PLL

Select UART4 clock source from PLL

Definition at line 229 of file clk.h.

## ◆ CLK_CLKSEL3_UART5SEL_HIRC

#define CLK_CLKSEL3_UART5SEL_HIRC

Select UART5 clock source from high speed oscillator

Definition at line 235 of file clk.h.

## ◆ CLK_CLKSEL3_UART5SEL_HXT

#define CLK_CLKSEL3_UART5SEL_HXT

Select UART5 clock source from high speed crystal

Definition at line 232 of file clk.h.

## ◆ CLK_CLKSEL3_UART5SEL_LXT

#define CLK_CLKSEL3_UART5SEL_LXT

Select UART5 clock source from low speed crystal

Definition at line 233 of file clk.h.

## ◆ CLK_CLKSEL3_UART5SEL_PLL

#define CLK_CLKSEL3_UART5SEL_PLL

Select UART5 clock source from PLL

Definition at line 234 of file clk.h.

## ◆ CLK_CLKSEL3_UART6SEL_HIRC

#define CLK_CLKSEL3_UART6SEL_HIRC

Select UART6 clock source from high speed oscillator

Definition at line 240 of file clk.h.

## ◆ CLK_CLKSEL3_UART6SEL_HXT

#define CLK_CLKSEL3_UART6SEL_HXT

Select UART6 clock source from high speed crystal

Definition at line 237 of file clk.h.

## ◆ CLK_CLKSEL3_UART6SEL_LXT

#define CLK_CLKSEL3_UART6SEL_LXT

Select UART6 clock source from low speed crystal

Definition at line 238 of file clk.h.

## ◆ CLK_CLKSEL3_UART6SEL_PLL

#define CLK_CLKSEL3_UART6SEL_PLL

Select UART6 clock source from PLL

Definition at line 239 of file clk.h.

## ◆ CLK_CLKSEL3_UART7SEL_HIRC

#define CLK_CLKSEL3_UART7SEL_HIRC

Select UART7 clock source from high speed oscillator

Definition at line 245 of file clk.h.

## ◆ CLK_CLKSEL3_UART7SEL_HXT

#define CLK_CLKSEL3_UART7SEL_HXT

Select UART7 clock source from high speed crystal

Definition at line 242 of file clk.h.

## ◆ CLK_CLKSEL3_UART7SEL_LXT

#define CLK_CLKSEL3_UART7SEL_LXT

Select UART7 clock source from low speed crystal

Definition at line 243 of file clk.h.

## ◆ CLK_CLKSEL3_UART7SEL_PLL

#define CLK_CLKSEL3_UART7SEL_PLL

Select UART7 clock source from PLL

Definition at line 244 of file clk.h.

## ◆ CLK_DISABLE_DPDWKPIN

#define CLK_DISABLE_DPDWKPIN | ( |  | void | ) |

Disable Wake-up pin at Deep Power-down mode

Definition at line 526 of file clk.h.

## ◆ CLK_DISABLE_DPDWKPIN0

#define CLK_DISABLE_DPDWKPIN0 | ( |  | void | ) |

Disable Wake-up pin0 (GPC.0) at Deep Power-down mode

Definition at line 527 of file clk.h.

## ◆ CLK_DISABLE_DPDWKPIN1

#define CLK_DISABLE_DPDWKPIN1 | ( |  | void | ) |

Disable Wake-up pin1 (GPB.0) at Deep Power-down mode

Definition at line 528 of file clk.h.

## ◆ CLK_DISABLE_DPDWKPIN2

#define CLK_DISABLE_DPDWKPIN2 | ( |  | void | ) |

Disable Wake-up pin2 (GPB.2) at Deep Power-down mode

Definition at line 529 of file clk.h.

## ◆ CLK_DISABLE_DPDWKPIN3

#define CLK_DISABLE_DPDWKPIN3 | ( |  | void | ) |

Disable Wake-up pin3 (GPB.12) at Deep Power-down mode

Definition at line 530 of file clk.h.

## ◆ CLK_DISABLE_DPDWKPIN4

#define CLK_DISABLE_DPDWKPIN4 | ( |  | void | ) |

Disable Wake-up pin4 (GPF.6) at Deep Power-down mode

Definition at line 531 of file clk.h.

## ◆ CLK_DISABLE_RTCWK

#define CLK_DISABLE_RTCWK | ( |  | void | ) |

Disable RTC Wake-up at Standby or Deep Power-down mode

Definition at line 534 of file clk.h.

## ◆ CLK_DISABLE_SPDACMP

#define CLK_DISABLE_SPDACMP | ( |  | void | ) |

Disable ACMP wake-up at Standby Power-down mode

Definition at line 532 of file clk.h.

## ◆ CLK_DISABLE_WKTMR

#define CLK_DISABLE_WKTMR | ( |  | void | ) |

Disable Wake-up timer at Standby or Deep Power-down mode

Definition at line 524 of file clk.h.

## ◆ CLK_DPDWKPIN0_BOTHEDGE

#define CLK_DPDWKPIN0_BOTHEDGE

Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode

Definition at line 487 of file clk.h.

## ◆ CLK_DPDWKPIN0_DISABLE

#define CLK_DPDWKPIN0_DISABLE

Disable Wake-up pin0 (GPC.0) at Deep Power-down mode

Definition at line 484 of file clk.h.

## ◆ CLK_DPDWKPIN0_FALLING

#define CLK_DPDWKPIN0_FALLING

Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode

Definition at line 486 of file clk.h.

## ◆ CLK_DPDWKPIN0_RISING

#define CLK_DPDWKPIN0_RISING

Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode

Definition at line 485 of file clk.h.

## ◆ CLK_DPDWKPIN1_BOTHEDGE

#define CLK_DPDWKPIN1_BOTHEDGE

Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode

Definition at line 492 of file clk.h.

## ◆ CLK_DPDWKPIN1_DISABLE

#define CLK_DPDWKPIN1_DISABLE

Disable Wake-up pin1 (GPB.0) at Deep Power-down mode

Definition at line 489 of file clk.h.

## ◆ CLK_DPDWKPIN1_FALLING

#define CLK_DPDWKPIN1_FALLING

Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode

Definition at line 491 of file clk.h.

## ◆ CLK_DPDWKPIN1_RISING

#define CLK_DPDWKPIN1_RISING

Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode

Definition at line 490 of file clk.h.

## ◆ CLK_DPDWKPIN2_BOTHEDGE

#define CLK_DPDWKPIN2_BOTHEDGE

Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode

Definition at line 497 of file clk.h.

## ◆ CLK_DPDWKPIN2_DISABLE

#define CLK_DPDWKPIN2_DISABLE

Disable Wake-up pin2 (GPB.2) at Deep Power-down mode

Definition at line 494 of file clk.h.

## ◆ CLK_DPDWKPIN2_FALLING

#define CLK_DPDWKPIN2_FALLING

Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode

Definition at line 496 of file clk.h.

## ◆ CLK_DPDWKPIN2_RISING

#define CLK_DPDWKPIN2_RISING

Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode

Definition at line 495 of file clk.h.

## ◆ CLK_DPDWKPIN3_BOTHEDGE

#define CLK_DPDWKPIN3_BOTHEDGE

Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode

Definition at line 502 of file clk.h.

## ◆ CLK_DPDWKPIN3_DISABLE

#define CLK_DPDWKPIN3_DISABLE

Disable Wake-up pin3 (GPB.12) at Deep Power-down mode

Definition at line 499 of file clk.h.

## ◆ CLK_DPDWKPIN3_FALLING

#define CLK_DPDWKPIN3_FALLING

Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode

Definition at line 501 of file clk.h.

## ◆ CLK_DPDWKPIN3_RISING

#define CLK_DPDWKPIN3_RISING

Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode

Definition at line 500 of file clk.h.

## ◆ CLK_DPDWKPIN4_BOTHEDGE

#define CLK_DPDWKPIN4_BOTHEDGE

Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode

Definition at line 507 of file clk.h.

## ◆ CLK_DPDWKPIN4_DISABLE

#define CLK_DPDWKPIN4_DISABLE

Disable Wake-up pin4 (GPF.6) at Deep Power-down mode

Definition at line 504 of file clk.h.

## ◆ CLK_DPDWKPIN4_FALLING

#define CLK_DPDWKPIN4_FALLING

Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode

Definition at line 506 of file clk.h.

## ◆ CLK_DPDWKPIN4_RISING

#define CLK_DPDWKPIN4_RISING

Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode

Definition at line 505 of file clk.h.

## ◆ CLK_DPDWKPIN_BOTHEDGE

#define CLK_DPDWKPIN_BOTHEDGE

Enable Wake-up pin both edge at Deep Power-down mode

Definition at line 482 of file clk.h.

## ◆ CLK_DPDWKPIN_DISABLE

#define CLK_DPDWKPIN_DISABLE

Disable Wake-up pin at Deep Power-down mode

Definition at line 479 of file clk.h.

## ◆ CLK_DPDWKPIN_FALLING

#define CLK_DPDWKPIN_FALLING

Enable Wake-up pin falling edge at Deep Power-down mode

Definition at line 481 of file clk.h.

## ◆ CLK_DPDWKPIN_RISING

#define CLK_DPDWKPIN_RISING

Enable Wake-up pin rising edge at Deep Power-down mode

Definition at line 480 of file clk.h.

## ◆ CLK_ENABLE_RTCWK

#define CLK_ENABLE_RTCWK | ( |  | void | ) |

Enable RTC Wake-up at Standby or Deep Power-down mode

Definition at line 535 of file clk.h.

## ◆ CLK_ENABLE_SPDACMP

#define CLK_ENABLE_SPDACMP | ( |  | void | ) |

Enable ACMP wake-up at Standby Power-down mode

Definition at line 533 of file clk.h.

## ◆ CLK_ENABLE_WKTMR

#define CLK_ENABLE_WKTMR | ( |  | void | ) |

Enable Wake-up timer at Standby or Deep Power-down mode

Definition at line 525 of file clk.h.

## ◆ CLK_PCLKDIV_APB0DIV_DIV1

#define CLK_PCLKDIV_APB0DIV_DIV1

PCLKDIV Setting for PCLK0 = HCLK

Definition at line 302 of file clk.h.

## ◆ CLK_PCLKDIV_APB0DIV_DIV16

#define CLK_PCLKDIV_APB0DIV_DIV16

PCLKDIV Setting for PCLK0 = 1/16 HCLK

Definition at line 306 of file clk.h.

## ◆ CLK_PCLKDIV_APB0DIV_DIV2

#define CLK_PCLKDIV_APB0DIV_DIV2

PCLKDIV Setting for PCLK0 = 1/2 HCLK

Definition at line 303 of file clk.h.

## ◆ CLK_PCLKDIV_APB0DIV_DIV4

#define CLK_PCLKDIV_APB0DIV_DIV4

PCLKDIV Setting for PCLK0 = 1/4 HCLK

Definition at line 304 of file clk.h.

## ◆ CLK_PCLKDIV_APB0DIV_DIV8

#define CLK_PCLKDIV_APB0DIV_DIV8

PCLKDIV Setting for PCLK0 = 1/8 HCLK

Definition at line 305 of file clk.h.

## ◆ CLK_PCLKDIV_APB1DIV_DIV1

#define CLK_PCLKDIV_APB1DIV_DIV1

PCLKDIV Setting for PCLK1 = HCLK

Definition at line 307 of file clk.h.

## ◆ CLK_PCLKDIV_APB1DIV_DIV16

#define CLK_PCLKDIV_APB1DIV_DIV16

PCLKDIV Setting for PCLK1 = 1/16 HCLK

Definition at line 311 of file clk.h.

## ◆ CLK_PCLKDIV_APB1DIV_DIV2

#define CLK_PCLKDIV_APB1DIV_DIV2

PCLKDIV Setting for PCLK1 = 1/2 HCLK

Definition at line 308 of file clk.h.

## ◆ CLK_PCLKDIV_APB1DIV_DIV4

#define CLK_PCLKDIV_APB1DIV_DIV4

PCLKDIV Setting for PCLK1 = 1/4 HCLK

Definition at line 309 of file clk.h.

## ◆ CLK_PCLKDIV_APB1DIV_DIV8

#define CLK_PCLKDIV_APB1DIV_DIV8

PCLKDIV Setting for PCLK1 = 1/8 HCLK

Definition at line 310 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK0DIV1

#define CLK_PCLKDIV_PCLK0DIV1

PCLKDIV Setting for PCLK0 = HCLK

Definition at line 291 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK0DIV16

#define CLK_PCLKDIV_PCLK0DIV16

PCLKDIV Setting for PCLK0 = 1/16 HCLK

Definition at line 295 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK0DIV2

#define CLK_PCLKDIV_PCLK0DIV2

PCLKDIV Setting for PCLK0 = 1/2 HCLK

Definition at line 292 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK0DIV4

#define CLK_PCLKDIV_PCLK0DIV4

PCLKDIV Setting for PCLK0 = 1/4 HCLK

Definition at line 293 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK0DIV8

#define CLK_PCLKDIV_PCLK0DIV8

PCLKDIV Setting for PCLK0 = 1/8 HCLK

Definition at line 294 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK1DIV1

#define CLK_PCLKDIV_PCLK1DIV1

PCLKDIV Setting for PCLK1 = HCLK

Definition at line 296 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK1DIV16

#define CLK_PCLKDIV_PCLK1DIV16

PCLKDIV Setting for PCLK1 = 1/16 HCLK

Definition at line 300 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK1DIV2

#define CLK_PCLKDIV_PCLK1DIV2

PCLKDIV Setting for PCLK1 = 1/2 HCLK

Definition at line 297 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK1DIV4

#define CLK_PCLKDIV_PCLK1DIV4

PCLKDIV Setting for PCLK1 = 1/4 HCLK

Definition at line 298 of file clk.h.

## ◆ CLK_PCLKDIV_PCLK1DIV8

#define CLK_PCLKDIV_PCLK1DIV8

PCLKDIV Setting for PCLK1 = 1/8 HCLK

Definition at line 299 of file clk.h.

## ◆ CLK_PLLCTL_144MHz_HIRC

#define CLK_PLLCTL_144MHz_HIRC

Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC)

Definition at line 334 of file clk.h.

## ◆ CLK_PLLCTL_144MHz_HXT

#define CLK_PLLCTL_144MHz_HXT

Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal)

Definition at line 328 of file clk.h.

## ◆ CLK_PLLCTL_160MHz_HIRC

#define CLK_PLLCTL_160MHz_HIRC

Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC)

Definition at line 335 of file clk.h.

## ◆ CLK_PLLCTL_160MHz_HXT

#define CLK_PLLCTL_160MHz_HXT

Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal)

Definition at line 329 of file clk.h.

## ◆ CLK_PLLCTL_192MHz_HIRC

#define CLK_PLLCTL_192MHz_HIRC

Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC)

Definition at line 336 of file clk.h.

## ◆ CLK_PLLCTL_192MHz_HXT

#define CLK_PLLCTL_192MHz_HXT

Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal)

Definition at line 330 of file clk.h.

## ◆ CLK_PLLCTL_72MHz_HIRC

#define CLK_PLLCTL_72MHz_HIRC

Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC)

Definition at line 332 of file clk.h.

## ◆ CLK_PLLCTL_72MHz_HXT

#define CLK_PLLCTL_72MHz_HXT

Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal)

Definition at line 326 of file clk.h.

## ◆ CLK_PLLCTL_80MHz_HIRC

#define CLK_PLLCTL_80MHz_HIRC

Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC)

Definition at line 333 of file clk.h.

## ◆ CLK_PLLCTL_80MHz_HXT

#define CLK_PLLCTL_80MHz_HXT

Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal)

Definition at line 327 of file clk.h.

## ◆ CLK_PLLCTL_NF

#define CLK_PLLCTL_NF | ( |  | x | ) |

x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz.

Definition at line 319 of file clk.h.

## ◆ CLK_PLLCTL_NO_1

#define CLK_PLLCTL_NO_1

For output divider is 1

Definition at line 322 of file clk.h.

## ◆ CLK_PLLCTL_NO_2

#define CLK_PLLCTL_NO_2

For output divider is 2

Definition at line 323 of file clk.h.

## ◆ CLK_PLLCTL_NO_4

#define CLK_PLLCTL_NO_4

For output divider is 4

Definition at line 324 of file clk.h.

## ◆ CLK_PLLCTL_NR

#define CLK_PLLCTL_NR | ( |  | x | ) |

x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz

Definition at line 320 of file clk.h.

## ◆ CLK_PLLCTL_PLLSRC_HIRC

#define CLK_PLLCTL_PLLSRC_HIRC

For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz

Definition at line 317 of file clk.h.

## ◆ CLK_PLLCTL_PLLSRC_HXT

#define CLK_PLLCTL_PLLSRC_HXT

For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz

Definition at line 316 of file clk.h.

## ◆ CLK_PMUCTL_PDMSEL_DPD

#define CLK_PMUCTL_PDMSEL_DPD

Select power down mode is Deep Power-down mode

Definition at line 438 of file clk.h.

## ◆ CLK_PMUCTL_PDMSEL_FWPD

#define CLK_PMUCTL_PDMSEL_FWPD

Select power down mode is Fast wake-up Power-down mode

Definition at line 435 of file clk.h.

## ◆ CLK_PMUCTL_PDMSEL_LLPD

#define CLK_PMUCTL_PDMSEL_LLPD

Select power down mode is Low leakage Power-down mode

Definition at line 434 of file clk.h.

## ◆ CLK_PMUCTL_PDMSEL_PD

#define CLK_PMUCTL_PDMSEL_PD

Select power down mode is Power-down mode

Definition at line 433 of file clk.h.

## ◆ CLK_PMUCTL_PDMSEL_SPD0

#define CLK_PMUCTL_PDMSEL_SPD0

Select power down mode is Standby Power-down mode 0

Definition at line 436 of file clk.h.

## ◆ CLK_PMUCTL_PDMSEL_SPD1

#define CLK_PMUCTL_PDMSEL_SPD1

Select power down mode is Standby Power-down mode 1

Definition at line 437 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_1024

#define CLK_PMUCTL_WKTMRIS_1024

Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms)

Definition at line 446 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_1048576

#define CLK_PMUCTL_WKTMRIS_1048576

Select Wake-up Timer Time-out Interval is 1048576 OSC10K clocks (104857.6ms)

Definition at line 454 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_128

#define CLK_PMUCTL_WKTMRIS_128

Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms)

Definition at line 443 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_131072

#define CLK_PMUCTL_WKTMRIS_131072

Select Wake-up Timer Time-out Interval is 131072 OSC10K clocks (13107.2 ms)

Definition at line 451 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_16384

#define CLK_PMUCTL_WKTMRIS_16384

Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms)

Definition at line 449 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_256

#define CLK_PMUCTL_WKTMRIS_256

Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms)

Definition at line 444 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_262144

#define CLK_PMUCTL_WKTMRIS_262144

Select Wake-up Timer Time-out Interval is 262144 OSC10K clocks (26214.4 ms)

Definition at line 452 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_4096

#define CLK_PMUCTL_WKTMRIS_4096

Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms)

Definition at line 447 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_512

#define CLK_PMUCTL_WKTMRIS_512

Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms)

Definition at line 445 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_524288

#define CLK_PMUCTL_WKTMRIS_524288

Select Wake-up Timer Time-out Interval is 524288 OSC10K clocks (52428.8ms)

Definition at line 453 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_65536

#define CLK_PMUCTL_WKTMRIS_65536

Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms)

Definition at line 450 of file clk.h.

## ◆ CLK_PMUCTL_WKTMRIS_8192

#define CLK_PMUCTL_WKTMRIS_8192

Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms)

Definition at line 448 of file clk.h.

## ◆ CLK_SPDSRETSEL_128K

#define CLK_SPDSRETSEL_128K

128K SRAM retention when chip enter SPD mode

Definition at line 522 of file clk.h.

## ◆ CLK_SPDSRETSEL_16K

#define CLK_SPDSRETSEL_16K

16K SRAM retention when chip enter SPD mode

Definition at line 519 of file clk.h.

## ◆ CLK_SPDSRETSEL_32K

#define CLK_SPDSRETSEL_32K

32K SRAM retention when chip enter SPD mode

Definition at line 520 of file clk.h.

## ◆ CLK_SPDSRETSEL_64K

#define CLK_SPDSRETSEL_64K

64K SRAM retention when chip enter SPD mode

Definition at line 521 of file clk.h.

## ◆ CLK_SPDSRETSEL_NO

#define CLK_SPDSRETSEL_NO

No SRAM retention when chip enter SPD mode

Definition at line 518 of file clk.h.

## ◆ CLK_SPDWKPIN_DEBOUNCEDIS

#define CLK_SPDWKPIN_DEBOUNCEDIS

Disable Standby power-down pin De-bounce function

Definition at line 516 of file clk.h.

## ◆ CLK_SPDWKPIN_DEBOUNCEEN

#define CLK_SPDWKPIN_DEBOUNCEEN

Enable Standby power-down pin De-bounce function

Definition at line 515 of file clk.h.

## ◆ CLK_SPDWKPIN_ENABLE

#define CLK_SPDWKPIN_ENABLE

Enable Standby Power-down Pin Wake-up

Definition at line 512 of file clk.h.

## ◆ CLK_SPDWKPIN_FALLING

#define CLK_SPDWKPIN_FALLING

Standby Power-down Wake-up on Standby Power-down Pin falling edge

Definition at line 514 of file clk.h.

## ◆ CLK_SPDWKPIN_RISING

#define CLK_SPDWKPIN_RISING

Standby Power-down Wake-up on Standby Power-down Pin rising edge

Definition at line 513 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_1

#define CLK_SWKDBCTL_SWKDBCLKSEL_1

Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks

Definition at line 459 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_128

#define CLK_SWKDBCTL_SWKDBCLKSEL_128

Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks

Definition at line 466 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_128x256

#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256

Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks

Definition at line 474 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_16

#define CLK_SWKDBCTL_SWKDBCLKSEL_16

Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks

Definition at line 463 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_16x256

#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256

Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks

Definition at line 471 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_2

#define CLK_SWKDBCTL_SWKDBCLKSEL_2

Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks

Definition at line 460 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_256

#define CLK_SWKDBCTL_SWKDBCLKSEL_256

Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks

Definition at line 467 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_2x256

#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256

Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks

Definition at line 468 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_32

#define CLK_SWKDBCTL_SWKDBCLKSEL_32

Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks

Definition at line 464 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_32x256

#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256

Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks

Definition at line 472 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_4

#define CLK_SWKDBCTL_SWKDBCLKSEL_4

Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks

Definition at line 461 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_4x256

#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256

Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks

Definition at line 469 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_64

#define CLK_SWKDBCTL_SWKDBCLKSEL_64

Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks

Definition at line 465 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_64x256

#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256

Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks

Definition at line 473 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_8

#define CLK_SWKDBCTL_SWKDBCLKSEL_8

Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks

Definition at line 462 of file clk.h.

## ◆ CLK_SWKDBCTL_SWKDBCLKSEL_8x256

#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256

Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks

Definition at line 470 of file clk.h.

## ◆ CLKO_MODULE

#define CLKO_MODULE

CLKO Module

Definition at line 384 of file clk.h.

## ◆ CRC_MODULE

#define CRC_MODULE

CRC Module

Definition at line 370 of file clk.h.

## ◆ CRPT_MODULE

#define CRPT_MODULE

CRPT Module

Definition at line 374 of file clk.h.

## ◆ DAC_MODULE

#define DAC_MODULE

DAC Module

Definition at line 416 of file clk.h.

## ◆ EADC1_MODULE

#define EADC1_MODULE

EADC1 Module

Definition at line 428 of file clk.h.

## ◆ EADC_MODULE

#define EADC_MODULE

EADC Module

Definition at line 406 of file clk.h.

## ◆ EBI_MODULE

#define EBI_MODULE

EBI Module

Definition at line 366 of file clk.h.

## ◆ ECAP0_MODULE

#define ECAP0_MODULE

ECAP0 Module

Definition at line 425 of file clk.h.

## ◆ ECAP1_MODULE

#define ECAP1_MODULE

ECAP1 Module

Definition at line 426 of file clk.h.

## ◆ EMAC_MODULE

#define EMAC_MODULE

EMAC Module

Definition at line 368 of file clk.h.

## ◆ EPWM0_MODULE

#define EPWM0_MODULE

EPWM0 Module

Definition at line 418 of file clk.h.

## ◆ EPWM1_MODULE

#define EPWM1_MODULE

EPWM1 Module

Definition at line 419 of file clk.h.

## ◆ FMCIDLE_MODULE

#define FMCIDLE_MODULE

FMCIDLE Module

Definition at line 376 of file clk.h.

## ◆ FREQ_100MHZ

#define FREQ_100MHZ

100 MHz

Definition at line 35 of file clk.h.

## ◆ FREQ_125MHZ

#define FREQ_125MHZ

125 MHz

Definition at line 36 of file clk.h.

## ◆ FREQ_160MHZ

#define FREQ_160MHZ

160 MHz

Definition at line 37 of file clk.h.

## ◆ FREQ_192MHZ

#define FREQ_192MHZ

192 MHz

Definition at line 38 of file clk.h.

## ◆ FREQ_200MHZ

#define FREQ_200MHZ

200 MHz

Definition at line 39 of file clk.h.

## ◆ FREQ_250MHZ

#define FREQ_250MHZ

250 MHz

Definition at line 40 of file clk.h.

## ◆ FREQ_25MHZ

#define FREQ_25MHZ

25 MHz

Definition at line 31 of file clk.h.

## ◆ FREQ_500MHZ

#define FREQ_500MHZ

500 MHz

Definition at line 41 of file clk.h.

## ◆ FREQ_50MHZ

#define FREQ_50MHZ

50 MHz

Definition at line 32 of file clk.h.

## ◆ FREQ_72MHZ

#define FREQ_72MHZ

72 MHz

Definition at line 33 of file clk.h.

## ◆ FREQ_80MHZ

#define FREQ_80MHZ

80 MHz

Definition at line 34 of file clk.h.

## ◆ HSOTG_MODULE

#define HSOTG_MODULE

HSOTG Module

Definition at line 408 of file clk.h.

## ◆ HSUSBD_MODULE

#define HSUSBD_MODULE

HSUSBD Module

Definition at line 373 of file clk.h.

## ◆ I2C0_MODULE

#define I2C0_MODULE

I2C0 Module

Definition at line 387 of file clk.h.

## ◆ I2C1_MODULE

#define I2C1_MODULE

I2C1 Module

Definition at line 388 of file clk.h.

## ◆ I2C2_MODULE

#define I2C2_MODULE

I2C2 Module

Definition at line 389 of file clk.h.

## ◆ I2S0_MODULE

#define I2S0_MODULE

I2S0 Module

Definition at line 407 of file clk.h.

## ◆ ISP_MODULE

#define ISP_MODULE

ISP Module

Definition at line 365 of file clk.h.

## ◆ MODULE_APBCLK

#define MODULE_APBCLK | ( |  | x | ) |

Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1

Definition at line 344 of file clk.h.

## ◆ MODULE_APBCLK_ENC

#define MODULE_APBCLK_ENC | ( |  | x | ) |

MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1

Definition at line 355 of file clk.h.

## ◆ MODULE_CLKDIV

#define MODULE_CLKDIV | ( |  | x | ) |

Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4

Definition at line 348 of file clk.h.

## ◆ MODULE_CLKDIV_ENC

#define MODULE_CLKDIV_ENC | ( |  | x | ) |

APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4

Definition at line 359 of file clk.h.

## ◆ MODULE_CLKDIV_Msk

#define MODULE_CLKDIV_Msk | ( |  | x | ) |

Calculate CLKDIV mask offset on MODULE index

Definition at line 349 of file clk.h.

## ◆ MODULE_CLKDIV_Msk_ENC

#define MODULE_CLKDIV_Msk_ENC | ( |  | x | ) |

CLKDIV mask offset on MODULE index

Definition at line 360 of file clk.h.

## ◆ MODULE_CLKDIV_Pos

#define MODULE_CLKDIV_Pos | ( |  | x | ) |

Calculate CLKDIV position offset on MODULE index

Definition at line 350 of file clk.h.

## ◆ MODULE_CLKDIV_Pos_ENC

#define MODULE_CLKDIV_Pos_ENC | ( |  | x | ) |

CLKDIV position offset on MODULE index

Definition at line 361 of file clk.h.

## ◆ MODULE_CLKSEL

#define MODULE_CLKSEL | ( |  | x | ) |

Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3

Definition at line 345 of file clk.h.

## ◆ MODULE_CLKSEL_ENC

#define MODULE_CLKSEL_ENC | ( |  | x | ) |

CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3

Definition at line 356 of file clk.h.

## ◆ MODULE_CLKSEL_Msk

#define MODULE_CLKSEL_Msk | ( |  | x | ) |

Calculate CLKSEL mask offset on MODULE index

Definition at line 346 of file clk.h.

## ◆ MODULE_CLKSEL_Msk_ENC

#define MODULE_CLKSEL_Msk_ENC | ( |  | x | ) |

CLKSEL mask offset on MODULE index

Definition at line 357 of file clk.h.

## ◆ MODULE_CLKSEL_Pos

#define MODULE_CLKSEL_Pos | ( |  | x | ) |

Calculate CLKSEL position offset on MODULE index

Definition at line 347 of file clk.h.

## ◆ MODULE_CLKSEL_Pos_ENC

#define MODULE_CLKSEL_Pos_ENC | ( |  | x | ) |

CLKSEL position offset on MODULE index

Definition at line 358 of file clk.h.

## ◆ MODULE_IP_EN_Pos

#define MODULE_IP_EN_Pos | ( |  | x | ) |

Calculate APBCLK offset on MODULE index

Definition at line 351 of file clk.h.

## ◆ MODULE_IP_EN_Pos_ENC

#define MODULE_IP_EN_Pos_ENC | ( |  | x | ) |

AHBCLK/APBCLK offset on MODULE index

Definition at line 362 of file clk.h.

## ◆ MODULE_NoMsk

#define MODULE_NoMsk

Not mask on MODULE index

Definition at line 352 of file clk.h.

## ◆ NA

#define NA

Not Available

Definition at line 353 of file clk.h.

## ◆ OPA_MODULE

#define OPA_MODULE

OPA Module

Definition at line 427 of file clk.h.

## ◆ OTG_MODULE

#define OTG_MODULE

OTG Module

Definition at line 404 of file clk.h.

## ◆ PDMA_MODULE

#define PDMA_MODULE

PDMA Module

Definition at line 364 of file clk.h.

## ◆ QEI0_MODULE

#define QEI0_MODULE

QEI0 Module

Definition at line 422 of file clk.h.

## ◆ QEI1_MODULE

#define QEI1_MODULE

QEI1 Module

Definition at line 423 of file clk.h.

## ◆ QSPI0_MODULE

#define QSPI0_MODULE

QSPI0 Module

Definition at line 390 of file clk.h.

## ◆ QSPI1_MODULE

#define QSPI1_MODULE

QSPI1 Module

Definition at line 412 of file clk.h.

## ◆ RTC_MODULE

#define RTC_MODULE

RTC Module

Definition at line 379 of file clk.h.

## ◆ SC0_MODULE

#define SC0_MODULE

SC0 Module

Definition at line 409 of file clk.h.

## ◆ SC1_MODULE

#define SC1_MODULE

SC1 Module

Definition at line 410 of file clk.h.

## ◆ SC2_MODULE

#define SC2_MODULE

SC2 Module

Definition at line 411 of file clk.h.

## ◆ SDH0_MODULE

#define SDH0_MODULE

SDH0 Module

Definition at line 369 of file clk.h.

## ◆ SDH1_MODULE

#define SDH1_MODULE

SDH1 Module

Definition at line 377 of file clk.h.

## ◆ SEN_MODULE

#define SEN_MODULE

SEN Module

Definition at line 372 of file clk.h.

## ◆ SPI0_MODULE

#define SPI0_MODULE

SPI0 Module

Definition at line 391 of file clk.h.

## ◆ SPI1_MODULE

#define SPI1_MODULE

SPI1 Module

Definition at line 392 of file clk.h.

## ◆ SPI2_MODULE

#define SPI2_MODULE

SPI2 Module

Definition at line 393 of file clk.h.

## ◆ SPI3_MODULE

#define SPI3_MODULE

SPI3 Module

Definition at line 413 of file clk.h.

## ◆ SPIM_MODULE

#define SPIM_MODULE

SPIM Module

Definition at line 375 of file clk.h.

## ◆ TMR0_MODULE

#define TMR0_MODULE

TMR0 Module

Definition at line 380 of file clk.h.

## ◆ TMR1_MODULE

#define TMR1_MODULE

TMR1 Module

Definition at line 381 of file clk.h.

## ◆ TMR2_MODULE

#define TMR2_MODULE

TMR2 Module

Definition at line 382 of file clk.h.

## ◆ TMR3_MODULE

#define TMR3_MODULE

TMR3 Module

Definition at line 383 of file clk.h.

## ◆ TRNG_MODULE

#define TRNG_MODULE

TRNG Module

Definition at line 424 of file clk.h.

## ◆ UART0_MODULE

#define UART0_MODULE

UART0 Module

Definition at line 394 of file clk.h.

## ◆ UART1_MODULE

#define UART1_MODULE

UART1 Module

Definition at line 395 of file clk.h.

## ◆ UART2_MODULE

#define UART2_MODULE

UART2 Module

Definition at line 396 of file clk.h.

## ◆ UART3_MODULE

#define UART3_MODULE

UART3 Module

Definition at line 397 of file clk.h.

## ◆ UART4_MODULE

#define UART4_MODULE

UART4 Module

Definition at line 398 of file clk.h.

## ◆ UART5_MODULE

#define UART5_MODULE

UART5 Module

Definition at line 399 of file clk.h.

## ◆ UART6_MODULE

#define UART6_MODULE

UART6 Module

Definition at line 400 of file clk.h.

## ◆ UART7_MODULE

#define UART7_MODULE

UART7 Module

Definition at line 401 of file clk.h.

## ◆ USBD_MODULE

#define USBD_MODULE

USBD Module

Definition at line 405 of file clk.h.

## ◆ USBH_MODULE

#define USBH_MODULE

USBH Module

Definition at line 367 of file clk.h.

## ◆ USCI0_MODULE

#define USCI0_MODULE

USCI0 Module

Definition at line 414 of file clk.h.

## ◆ USCI1_MODULE

#define USCI1_MODULE

USCI1 Module

Definition at line 415 of file clk.h.

## ◆ WDT_MODULE

#define WDT_MODULE

WDT Module

Definition at line 378 of file clk.h.

## ◆ WWDT_MODULE

#define WWDT_MODULE

WWDT Module

Definition at line 385 of file clk.h.