| M480 BSP V3.05.001 The Board Support Package for M480 Series

system_M480.c
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1 /**************************************************************************/
10 #include "NuMicro.h"
11
12
13 /*----------------------------------------------------------------------------
14 DEFINES
15 *----------------------------------------------------------------------------*/
16
17
18 /*----------------------------------------------------------------------------
19 Clock Variable definitions
20 *----------------------------------------------------------------------------*/
21 uint32_t SystemCoreClock = __SYSTEM_CLOCK;
22 uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
23 uint32_t PllClock = __HSI;
24 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
25
26 /*----------------------------------------------------------------------------
27 Clock functions
28 *----------------------------------------------------------------------------*/
29 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
30 {
31 uint32_t u32Freq, u32ClkSrc;
32 uint32_t u32HclkDiv;
33
34 /* Update PLL Clock */
35 PllClock = CLK_GetPLLClockFreq();
36
37 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
38
39 if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
40 {
41 /* Use PLL clock */
42 u32Freq = PllClock;
43 }
44 else
45 {
46 /* Use the clock sources directly */
47 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
48 }
49
50 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
51
52 /* Update System Core Clock */
53 SystemCoreClock = u32Freq / u32HclkDiv;
54
55
56 //if(SystemCoreClock == 0)
57 // __BKPT(0);
58
59 CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
60 }
61
70 static __INLINE void HXTInit(void)
71 {
72 PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
73
74 }
75
82 void SystemInit (void)
83 {
84 /* Add your system initialize code here.
85 Do not use global variables because this function is called before
86 reaching pre-main. RW section maybe overwritten afterwards. */
87
88
89 /* FPU settings ------------------------------------------------------------*/
90 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
91 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
92 (3UL << 11*2) ); /* set CP11 Full Access */
93 #endif
94
95 /* Set access cycle for CPU @ 192MHz */
96 FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
97 /* Configure power down bias, must set 1 before entering power down mode.
98 So set it at the very beginning */
99 CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
100 /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
101 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
102 RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
103 RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
104 RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
105 RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
106 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
107 HXTInit();
108
109 }
110 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
RTC_GPIOCTL0_CTLSEL2_Msk
#define RTC_GPIOCTL0_CTLSEL2_Msk
Definition: rtc_reg.h:1994
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_M480.c:21
CLK
#define CLK
Definition: M480.h:368
RTC_GPIOCTL1_CTLSEL4_Msk
#define RTC_GPIOCTL1_CTLSEL4_Msk
Definition: rtc_reg.h:2018
CLK_CLKSEL0_HCLKSEL_PLL
#define CLK_CLKSEL0_HCLKSEL_PLL
Definition: clk.h:48
RTC_GPIOCTL0_CTLSEL1_Msk
#define RTC_GPIOCTL0_CTLSEL1_Msk
Definition: rtc_reg.h:1982
SystemInit
void SystemInit(void)
Initialize the System.
Definition: system_M480.c:82
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
Definition: system_M480.c:29
CyclesPerUs
uint32_t CyclesPerUs
Definition: system_M480.c:22
NuMicro.h
NuMicro peripheral access layer header file.
__SYSTEM_CLOCK
#define __SYSTEM_CLOCK
Definition: system_M480.h:41
RTC_GPIOCTL1_CTLSEL7_Msk
#define RTC_GPIOCTL1_CTLSEL7_Msk
Definition: rtc_reg.h:2054
GPIO_MODE_MODE3_Msk
#define GPIO_MODE_MODE3_Msk
Definition: gpio_reg.h:591
RTC_GPIOCTL0_CTLSEL0_Msk
#define RTC_GPIOCTL0_CTLSEL0_Msk
Definition: rtc_reg.h:1970
CLK_LDOCTL_PDBIASEN_Msk
#define CLK_LDOCTL_PDBIASEN_Msk
Definition: clk_reg.h:2856
RTC_GPIOCTL1_CTLSEL5_Msk
#define RTC_GPIOCTL1_CTLSEL5_Msk
Definition: rtc_reg.h:2030
RTC_GPIOCTL1_CTLSEL6_Msk
#define RTC_GPIOCTL1_CTLSEL6_Msk
Definition: rtc_reg.h:2042
CLK_CLKSEL0_HCLKSEL_Msk
#define CLK_CLKSEL0_HCLKSEL_Msk
Definition: clk_reg.h:2508
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1188
__LIRC
#define __LIRC
Definition: system_M480.h:37
CLK_APBCLK0_RTCCKEN_Msk
#define CLK_APBCLK0_RTCCKEN_Msk
Definition: clk_reg.h:2361
FMC
#define FMC
Definition: M480.h:391
HXTInit
static __INLINE void HXTInit(void)
Set PF.2 and PF.3 to input mode.
Definition: system_M480.c:70
PllClock
uint32_t PllClock
Definition: system_M480.c:23
FMC_CYCCTL_CYCLE_Msk
#define FMC_CYCCTL_CYCLE_Msk
Definition: fmc_reg.h:1079
__LXT
#define __LXT
Definition: system_M480.h:33
__HIRC
#define __HIRC
Definition: system_M480.h:36
PF
#define PF
Definition: M480.h:375
__HSI
#define __HSI
Definition: system_M480.h:25
RTC
#define RTC
Definition: M480.h:400
gau32ClkSrcTbl
uint32_t gau32ClkSrcTbl[]
Definition: system_M480.c:24
CLK_CLKDIV0_HCLKDIV_Msk
#define CLK_CLKDIV0_HCLKDIV_Msk
Definition: clk_reg.h:2616
GPIO_MODE_MODE2_Msk
#define GPIO_MODE_MODE2_Msk
Definition: gpio_reg.h:588
__HXT
#define __HXT
Definition: system_M480.h:29
FMC_CYCCTL_CYCLE_Pos
#define FMC_CYCCTL_CYCLE_Pos
Definition: fmc_reg.h:1078
RTC_GPIOCTL0_CTLSEL3_Msk
#define RTC_GPIOCTL0_CTLSEL3_Msk
Definition: rtc_reg.h:2006