| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
RTC_T Struct Reference
Control Register

`#include <rtc_reg.h>`

## Data Fields
__IO uint32_t | INIT
__IO uint32_t | RWEN
__IO uint32_t | FREQADJ
__IO uint32_t | TIME
__IO uint32_t | CAL
__IO uint32_t | CLKFMT
__IO uint32_t | WEEKDAY
__IO uint32_t | TALM
__IO uint32_t | CALM
__I uint32_t | LEAPYEAR
__IO uint32_t | INTEN
__IO uint32_t | INTSTS
__IO uint32_t | TICK
__IO uint32_t | TAMSK
__IO uint32_t | CAMSK
__IO uint32_t | SPRCTL
__IO uint32_t | SPR [20]
__IO uint32_t | LXTCTL
__IO uint32_t | GPIOCTL0
__IO uint32_t | GPIOCTL1
__IO uint32_t | DSTCTL
__IO uint32_t | TAMPCTL
__IO uint32_t | TAMPSEED
__I uint32_t | TAMPTIME
__I uint32_t | TAMPCAL

## Detailed Description

    @addtogroup RTC Real Time Clock Controller(RTC)
    Memory Mapped Structure for RTC Controller

Definition at line 26 of file rtc_reg.h.

## Field Documentation

## ◆ CAL

RTC_T::CAL

[0x0010] RTC Calendar Loading Register

CAL

Offset: 0x10 RTC Calendar Loading Register

Bits | Field | Descriptions
[3:0] | DAY | 1-Day Calendar Digit (0~9)
[5:4] | TENDAY | 10-Day Calendar Digit (0~3)
[11:8] | MON | 1-Month Calendar Digit (0~9)
[12] | TENMON | 10-Month Calendar Digit (0~1)
[19:16] | YEAR | 1-Year Calendar Digit (0~9)
[23:20] | TENYEAR | 10-Year Calendar Digit (0~9)

Definition at line 1658 of file rtc_reg.h.

## ◆ CALM

RTC_T::CALM

[0x0020] RTC Calendar Alarm Register

CALM

Offset: 0x20 RTC Calendar Alarm Register

Bits | Field | Descriptions
[3:0] | DAY | 1-Day Calendar Digit of Alarm Setting (0~9)
[5:4] | TENDAY | 10-Day Calendar Digit of Alarm Setting (0~3)
[11:8] | MON | 1-Month Calendar Digit of Alarm Setting (0~9)
[12] | TENMON | 10-Month Calendar Digit of Alarm Setting (0~1)
[19:16] | YEAR | 1-Year Calendar Digit of Alarm Setting (0~9)
[23:20] | TENYEAR | 10-Year Calendar Digit of Alarm Setting (0~9)

Definition at line 1662 of file rtc_reg.h.

## ◆ CAMSK

RTC_T::CAMSK

[0x0038] RTC Calendar Alarm Mask Register

CAMSK

Offset: 0x38 RTC Calendar Alarm Mask Register

Bits | Field | Descriptions
[0] | MDAY | Mask 1-Day Calendar Digit of Alarm Setting (0~9)
[1] | MTENDAY | Mask 10-Day Calendar Digit of Alarm Setting (0~3)
[2] | MMON | Mask 1-Month Calendar Digit of Alarm Setting (0~9)
[3] | MTENMON | Mask 10-Month Calendar Digit of Alarm Setting (0~1)
[4] | MYEAR | Mask 1-Year Calendar Digit of Alarm Setting (0~9)
[5] | MTENYEAR | Mask 10-Year Calendar Digit of Alarm Setting (0~9)

Definition at line 1668 of file rtc_reg.h.

## ◆ CLKFMT

RTC_T::CLKFMT

[0x0014] RTC Time Scale Selection Register

CLKFMT

Offset: 0x14 RTC Time Scale Selection Register

Bits | Field | Descriptions
[0] | 24HEN | 24-hour / 12-hour Time Scale Selection Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 0 = 12-hour time scale with AM and PM indication selected. 1 = 24-hour time scale selected.

Definition at line 1659 of file rtc_reg.h.

## ◆ DSTCTL

RTC_T::DSTCTL

[0x0110] RTC Daylight Saving Time Control Register

DSTCTL

Offset: 0x110 RTC Daylight Saving Time Control Register

Bits | Field | Descriptions
[0] | ADDHR | Add 1 Hour 0 = No effect. 1 = Indicates RTC hour digit has been added one hour for summer time change.
[1] | SUBHR | Subtract 1 Hour 0 = No effect. 1 = Indicates RTC hour digit has been subtracted one hour for winter time change.
[2] | DSBAK | Daylight Saving Back 0= Normal mode. 1= Daylight saving mode.

Definition at line 1680 of file rtc_reg.h.

## ◆ FREQADJ

RTC_T::FREQADJ

[0x0008] RTC Frequency Compensation Register

FREQADJ

Offset: 0x08 RTC Frequency Compensation Register

Bits | Field | Descriptions
[21:0] | FREQADJ | Frequency Compensation Register (M480) User must to get actual LXT frequency for RTC application. FCR = 0x200000 * (32768 / LXT frequency). Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.
[5:0] | FRACTION | Fraction Part (M480LD) Formula: FRACTION = (fraction part of detected value) X 64. Note: Digit in FCR must be expressed as hexadecimal number.
[12:8] | INTEGER | Integer Part (M480LD) 00000 = Integer part of detected value is 32752. 00001 = Integer part of detected value is 32753. 00010 = Integer part of detected value is 32754. 00011 = Integer part of detected value is 32755. 00100 = Integer part of detected value is 32756. 00101 = Integer part of detected value is 32757. 00110 = Integer part of detected value is 32758. 00111 = Integer part of detected value is 32759. 01000 = Integer part of detected value is 32760. 01001 = Integer part of detected value is 32761. 01010 = Integer part of detected value is 32762. 01011 = Integer part of detected value is 32763. 01100 = Integer part of detected value is 32764. 01101 = Integer part of detected value is 32765. 01110 = Integer part of detected value is 32766. 01111 = Integer part of detected value is 32767. 10000 = Integer part of detected value is 32768. 10001 = Integer part of detected value is 32769. 10010 = Integer part of detected value is 32770. 10011 = Integer part of detected value is 32771. 10100 = Integer part of detected value is 32772. 10101 = Integer part of detected value is 32773. 10110 = Integer part of detected value is 32774. 10111 = Integer part of detected value is 32775. 11000 = Integer part of detected value is 32776. 11001 = Integer part of detected value is 32777. 11010 = Integer part of detected value is 32778. 11011 = Integer part of detected value is 32779. 11100 = Integer part of detected value is 32780. 11101 = Integer part of detected value is 32781. 11110 = Integer part of detected value is 32782. 11111 = Integer part of detected value is 32783.
[31] | FCR_BUSY | Frequency Compensation Register Write Operation Busy (Read Only) (M480LD) 0 = The new register write operation is acceptable. 1 = The last write operation is in progress and new register write operation prohibited. Note: This bit is only used when DYN_COMP_EN(RTC_CLKFMT[16]) enabled.

Definition at line 1656 of file rtc_reg.h.

## ◆ GPIOCTL0

RTC_T::GPIOCTL0

[0x0104] RTC GPIO Control 0 Register

GPIOCTL0

Offset: 0x104 RTC GPIO Control 0 Register

Bits | Field | Descriptions
[1:0] | OPMODE0 | IO Operation Mode 00 = PF.4 is input only mode, without pull-up resistor. 01 = PF.4 is output push pull mode. 10 = PF.4 is open drain mode. 11 = PF.4 is quasi-bidirectional mode with internal pull up.
[2] | DOUT0 | IO Output Data 0 = PF.4 output low. 1 = PF.4 output high.
[3] | CTLSEL0 | IO Pin State Backup Selection When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 0 = PF.4 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL0 = 1 when system power is turned off. 1 = PF.4 pin I/O function is controlled by VBAT power domain. PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1. Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
[5:4] | PUSEL0 | IO Pull-up and Pull-down Enable Determine PF.4 I/O pull-up or pull-down. 00 = PF.4 pull-up and pull-up disable. 01 = PF.4 pull-down enable. 10 = PF.4 pull-up enable. 11 = PF.4 pull-up and pull-up disable. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE0 set as input tri-state mode.
[9:8] | OPMODE1 | IO Operation Mode 00 = PF.5 is input only mode, without pull-up resistor. 01 = PF.5 is output push pull mode. 10 = PF.5 is open drain mode. 11 = PF.5 is quasi-bidirectional mode with internal pull up.
[10] | DOUT1 | IO Output Data 0 = PF.5 output low. 1 = PF.5 output high.
[11] | CTLSEL1 | IO Pin State Backup Selection When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 0 = PF.5 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL1 = 1 when system power is turned off. 1 = PF.5 pin I/O function is controlled by VBAT power domain. PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1. Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
[13:12] | PUSEL1 | IO Pull-up and Pull-down Enable Determine PF.5 I/O pull-up or pull-down. 00 = PF.5 pull-up and pull-up disable. 01 = PF.5 pull-down enable. 10 = PF.5 pull-up enable. 11 = PF.5 pull-up and pull-up disable. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE1 set as input tri-state mode.
[17:16] | OPMODE2 | IO Operation Mode 00 = PF.6 is input only mode, without pull-up resistor. 01 = PF.6 is output push pull mode. 10 = PF.6 is open drain mode. 11 = PF.6 is quasi-bidirectional mode with internal pull up.
[18] | DOUT2 | IO Output Data 0 = PF.6 output low. 1 = PF.6 output high.
[19] | CTLSEL2 | IO Pin State Backup Selection When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 0 = PF.6 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL2 = 1 when system power is turned off. 1 = PF.6 pin I/O function is controlled by VBAT power domain. PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1. Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
[21:20] | PUSEL2 | IO Pull-up and Pull-down Enable Determine PF.6 I/O pull-up or pull-down. 00 = PF.6 pull-up and pull-up disable. 01 = PF.6 pull-down enable. 10 = PF.6 pull-up enable. 11 = PF.6 pull-up and pull-up disable. Note1: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE2 set as input tri-state mode.
[25:24] | OPMODE3 | IO Operation Mode 00 = PF.7 is input only mode, without pull-up resistor. 01 = PF.7 is output push pull mode. 10 = PF.7 is open drain mode. 11 = PF.7 is quasi-bidirectional mode.
[26] | DOUT3 | IO Output Data 0 = PF.7 output low. 1 = PF.7 output high.
[27] | CTLSEL3 | IO Pin State Backup Selection When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 0 = PF.7 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL3 = 1 when system power is turned off. 1 = PF.7 pin I/O function is controlled by VBAT power domain. PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1. Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
[29:28] | PUSEL3 | IO Pull-up and Pull-down Enable Determine PF.7 I/O pull-up or pull-down. 00 = PF.7 pull-up and pull-down disable. 01 = PF.7 pull-down enable. 10 = PF.7 pull-up enable. 11 = PF.7 pull-up and pull-down disable. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE3 set as input tri-state mode.

Definition at line 1675 of file rtc_reg.h.

## ◆ GPIOCTL1

RTC_T::GPIOCTL1

[0x0108] RTC GPIO Control 1 Register

GPIOCTL1

Offset: 0x108 RTC GPIO Control 1 Register

Bits | Field | Descriptions
[1:0] | OPMODE4 | IO Operation Mode 00 = PF.8 is input only mode, without pull-up resistor. 01 = PF.8 is output push pull mode. 10 = PF.8 is open drain mode. 11 = PF.8 is quasi-bidirectional mode.
[2] | DOUT4 | IO Output Data 0 = PF.8 output low. 1 = PF.8 output high.
[3] | CTLSEL4 | IO Pin State Backup Selection When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 0 = PF.8 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL4 = 1 when system power is turned off. 1 = PF.8 pin I/O function is controlled by VBAT power domain. PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1. Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
[5:4] | PUSEL4 | IO Pull-up and Pull-down Enable Determine PF.8 I/O pull-up or pull-down. 00 = PF.8 pull-up and pull-down disable. 01 = PF.8 pull-down enable. 10 = PF.8 pull-up enable. 11 = PF.8 pull-up and pull-down disable. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE4 set as input tri-state mode.
[9:8] | OPMODE5 | IO Operation Mode 00 = PF.9 is input only mode, without pull-up resistor. 01 = PF.9 is output push pull mode. 10 = PF.9 is open drain mode. 11 = PF.9 is quasi-bidirectional mode.
[10] | DOUT5 | IO Output Data 0 = PF.9 output low. 1 = PF.9 output high.
[11] | CTLSEL5 | IO Pin State Backup Selection When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 0 = PF.9 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL5 = 1 when system power is turned off. 1 = PF.9 pin I/O function is controlled by VBAT power domain. PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1. Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
[13:12] | PUSEL5 | IO Pull-up and Pull-down Enable Determine PF.9 I/O pull-up or pull-down. 00 = PF.9 pull-up and pull-down disable. 01 = PF.9 pull-down enable. 10 = PF.9 pull-up enable. 11 = PF.9 pull-up and pull-down disable. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE5 set as input tri-state mode.
[17:16] | OPMODE6 | IO Operation Mode 00 = PF.10 is input only mode, without pull-up resistor. 01 = PF.10 is output push pull mode. 10 = PF.10 is open drain mode. 11 = PF.10 is quasi-bidirectional mode.
[18] | DOUT6 | IO Output Data 0 = PF.10 output low. 1 = PF.10 output high.
[19] | CTLSEL6 | IO Pin State Backup Selection When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 0 = PF.10 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL6 = 1 when system power is turned off. 1 = PF.10 pin I/O function is controlled by VBAT power domain. PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1. Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
[21:20] | PUSEL6 | IO Pull-up and Pull-down Enable Determine PF.10 I/O pull-up or pull-down. 00 = PF.10 pull-up and pull-down disable. 01 = PF.10 pull-down enable. 10 = PF.10 pull-up enable. 11 = PF.10 pull-up and pull-down disable. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE6 set as input tri-state mode.
[25:24] | OPMODE7 | IO Operation Mode 00 = PF.11 is input only mode, without pull-up resistor. 01 = PF.11 is output push pull mode. 10 = PF.11 is open drain mode. 11 = PF.11 is quasi-bidirectional mode.
[26] | DOUT7 | IO Output Data 0 = PF.11 output low. 1 = PF.11 output high.
[27] | CTLSEL7 | IO Pin State Backup Selection When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 0 = PF.11 pin I/O function is controlled by GPIO module. Hardware auto becomes CTLSEL7 = 1 when system power is turned off. 1 = PF.11 pin I/O function is controlled by VBAT power domain. PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1. Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
[29:28] | PUSEL7 | IO Pull-up and Pull-down Enable Determine PF.11 I/O pull-up or pull-down. 00 = PF.11 pull-up and pull-down disable. 01 = PF.11 pull-down enable. 10 = PF.11 pull-up enable. 11 = PF.11 pull-up and pull-down disable. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode. The independent pull-down control register only valid when OPMODE7 set as input tri-state mode.

Definition at line 1676 of file rtc_reg.h.

## ◆ INIT

RTC_T::INIT

[0x0000] RTC Initiation Register

INIT

Offset: 0x00 RTC Initiation Register

Bits | Field | Descriptions
[0] | INIT_ACTIVE | RTC Active Status (Read Only) 0 = RTC is at reset state. 1 = RTC is at normal active state.
[31:1] | INIT | RTC Initiation (Write Only) When RTC block is powered on, RTC is at reset state User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. The INIT is a write-only field and read value will be always 0.

Definition at line 1654 of file rtc_reg.h.

## ◆ INTEN

RTC_T::INTEN

[0x0028] RTC Interrupt Enable Register

INTEN

Offset: 0x28 RTC Interrupt Enable Register

Bits | Field | Descriptions
[0] | ALMIEN | Alarm Interrupt Enable Bit Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. 0 = RTC Alarm interrupt Disabled. 1 = RTC Alarm interrupt Enabled.
[1] | TICKIEN | Time Tick Interrupt Enable Bit Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. 0 = RTC Time Tick interrupt Disabled. 1 = RTC Time Tick interrupt Enabled.
[8] | TAMP0IEN | Tamper 0 Interrupt Enable Bit Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. 0 = Tamper 0 interrupt Disabled. 1 = Tamper 0 interrupt Enabled.
[9] | TAMP1IEN | Tamper 1 or Pair 0 Interrupt Enable Bit Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. 0 = Tamper 1 or Pair 0 interrupt Disabled. 1 = Tamper 1 or Pair 0 interrupt Enabled.
[10] | TAMP2IEN | Tamper 2 Interrupt Enable Bit Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. 0 = Tamper 2 interrupt Disabled. 1 = Tamper 2 interrupt Enabled.
[11] | TAMP3IEN | Tamper 3 or Pair 1 Interrupt Enable Bit Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. 0 = Tamper 3 or Pair 1 interrupt Disabled. 1 = Tamper 3 or Pair 1 interrupt Enabled.
[12] | TAMP4IEN | Tamper 4 Interrupt Enable Bit Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. 0 = Tamper 4 interrupt Disabled. 1 = Tamper 4 interrupt Enabled.
[13] | TAMP5IEN | Tamper 5 or Pair 2 Interrupt Enable Bit Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. 0 = Tamper 5 or Pair 2 interrupt Disabled. 1 = Tamper 5 or Pair 2 interrupt Enabled.

Definition at line 1664 of file rtc_reg.h.

## ◆ INTSTS

RTC_T::INTSTS

[0x002c] RTC Interrupt Status Register

INTSTS

Offset: 0x2C RTC Interrupt Status Register

Bits | Field | Descriptions
[0] | ALMIF | RTC Alarm Interrupt Flag 0 = Alarm condition is not matched. 1 = Alarm condition is matched. Note: Write 1 to clear this bit.
[1] | TICKIF | RTC Time Tick Interrupt Flag 0 = Tick condition does not occur. 1 = Tick condition occur. Note: Write 1 to clear this bit.
[8] | TAMP0IF | Tamper 0 Interrupt Flag This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). 0 = No Tamper 0 interrupt flag is generated. 1 = Tamper 0 interrupt flag is generated. Note1: Write 1 to clear this bit. Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
[9] | TAMP1IF | Tamper 1 or Pair 0 Interrupt Flag This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. 0 = No Tamper 1 or Pair 0 interrupt flag is generated. 1 = Tamper 1 or Pair 0 interrupt flag is generated. Note1: Write 1 to clear this bit. Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
[10] | TAMP2IF | Tamper 2 Interrupt Flag This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). 0 = No Tamper 2 interrupt flag is generated. 1 = Tamper 2 interrupt flag is generated. Note1: Write 1 to clear this bit. Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
[11] | TAMP3IF | Tamper 3 or Pair 1 Interrupt Flag This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. 0 = No Tamper 3 or Pair 1 interrupt flag is generated. 1 = Tamper 3 or Pair 1 interrupt flag is generated. Note1: Write 1 to clear this bit. Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
[12] | TAMP4IF | Tamper 4 Interrupt Flag This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). 0 = No Tamper 4 interrupt flag is generated. 1 = Tamper 4 interrupt flag is generated. Note1: Write 1 to clear this bit. Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
[13] | TAMP5IF | Tamper 5 or Pair 2 Interrupt Flag This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. 0 = No Tamper 5 or Pair 2 interrupt flag is generated. 1 = Tamper 5 or Pair 2 interrupt flag is generated. Note1: Write 1 to clear this bit. Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.

Definition at line 1665 of file rtc_reg.h.

## ◆ LEAPYEAR

RTC_T::LEAPYEAR

[0x0024] RTC Leap Year Indicator Register

LEAPYEAR

Offset: 0x24 RTC Leap Year Indicator Register

Bits | Field | Descriptions
[0] | LEAPYEAR | Leap Year Indication Register (Read Only) 0 = This year is not a leap year. 1 = This year is leap year.

Definition at line 1663 of file rtc_reg.h.

## ◆ LXTCTL

RTC_T::LXTCTL

[0x0100] RTC 32.768 kHz Oscillator Control Register

LXTCTL

Offset: 0x100 RTC 32.768 kHz Oscillator Control Register

Bits | Field | Descriptions
[2:1] | GAIN | Oscillator Gain Option User can select oscillator gain according to crystal external loading and operating temperature range The larger gain value corresponding to stronger driving capability and higher power consumption. 00 = L0 mode. 01 = L1 mode. 10 = L2 mode. 11 = L3 mode.

Definition at line 1674 of file rtc_reg.h.

## ◆ RWEN

RTC_T::RWEN

[0x0004] RTC Access Enable Register

RWEN

Offset: 0x04 RTC Access Enable Register

Bits | Field | Descriptions
[16] | RWENF | RTC Register Access Enable Flag (Read Only) 0 = RTC register read/write Disabled. 1 = RTC register read/write Enabled. Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
[24] | RTCBUSY | RTC Write Busy Flag This bit indicates RTC registers are writable or not. 0: RTC registers are writable. 1: RTC registers can't write, RTC under Busy Status. Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.

Definition at line 1655 of file rtc_reg.h.

## ◆ SPR

RTC_T::SPR[20]

[0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19

SPR[20]

Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19

Bits | Field | Descriptions
[31:0] | SPARE | Spare Register This field is used to store back-up information defined by user. This field will be cleared by hardware automatically once a tamper pin event is detected. Before storing back-up information in to RTC_SPRx register, user should check REWNF (RTC_RWEN[16]) is enabled.

Definition at line 1670 of file rtc_reg.h.

## ◆ SPRCTL

RTC_T::SPRCTL

[0x003c] RTC Spare Functional Control Register

SPRCTL

Offset: 0x3C RTC Spare Functional Control Register

Bits | Field | Descriptions
[2] | SPRRWEN | Spare Register Enable Bit 0 = Spare register is Disabled. 1 = Spare register is Enabled. Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
[5] | SPRCSTS | SPR Clear Flag This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected. 0 = Spare register content is not cleared. 1 = Spare register content is cleared. Writes 1 to clear this bit. Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero.

Definition at line 1669 of file rtc_reg.h.

## ◆ TALM

RTC_T::TALM

[0x001c] RTC Time Alarm Register

TALM

Offset: 0x1C RTC Time Alarm Register

Bits | Field | Descriptions
[3:0] | SEC | 1-Sec Time Digit of Alarm Setting (0~9)
[6:4] | TENSEC | 10-Sec Time Digit of Alarm Setting (0~5)
[11:8] | MIN | 1-Min Time Digit of Alarm Setting (0~9)
[14:12] | TENMIN | 10-Min Time Digit of Alarm Setting (0~5)
[19:16] | HR | 1-Hour Time Digit of Alarm Setting (0~9)
[21:20] | TENHR | 10-Hour Time Digit of Alarm Setting (0~2) When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message).

Definition at line 1661 of file rtc_reg.h.

## ◆ TAMPCAL

RTC_T::TAMPCAL

[0x0134] RTC Tamper Calendar Register

TAMPCAL

Offset: 0x134 RTC Tamper Calendar Register

Bits | Field | Descriptions
[3:0] | DAY | 1-Day Calendar Digit of TAMPER Calendar (0~9)
[5:4] | TENDAY | 10-Day Calendar Digit of TAMPER Calendar (0~3)
[11:8] | MON | 1-Month Calendar Digit of TAMPER Calendar (0~9)
[12] | TENMON | 10-Month Calendar Digit of TAMPER Calendar (0~1)
[19:16] | YEAR | 1-Year Calendar Digit of TAMPER Calendar (0~9)
[23:20] | TENYEAR | 10-Year Calendar Digit of TAMPER Calendar (0~9)

Definition at line 1693 of file rtc_reg.h.

## ◆ TAMPCTL

RTC_T::TAMPCTL

[0x0120] RTC Tamper Pin Control Register

TAMPCTL

Offset: 0x120 RTC Tamper Pin Control Register

Bits | Field | Descriptions
[0] | DYN1ISS | Dynamic Pair 1 Input Source Select This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. 0 = Tamper input is from Tamper 2. 1 = Tamper input is from Tamper 0. Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
[1] | DYN2ISS | Dynamic Pair 2 Input Source Select This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. 0 = Tamper input is from Tamper 4. 1 = Tamper input is from Tamper 0. Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
[3:2] | DYNSRC | Dynamic Reference Pattern This fields determine the new reference pattern when current pattern run out in dynamic pair mode. 00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out. 01 = The new reference pattern is repeated previous random value when the reference pattern run out. 11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
[4] | SEEDRLD | Reload New Seed for PRNG Engine Setting this bit, the tamper configuration will be reload. 0 = Generating key based on the current seed. 1 = Reload new seed. Note: Before set this bit, the tamper configuration should be set to complete.
[7:5] | DYNRATE | Dynamic Change Rate This item is choice the dynamic tamper output change rate. 000 = 210 * RTC_CLK. 001 = 211 * RTC_CLK. 010 = 212 * RTC_CLK. 011 = 213 * RTC_CLK. 100 = 214 * RTC_CLK. 101 = 215 * RTC_CLK. 110 = 216 * RTC_CLK. 111 = 217 * RTC_CLK. Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
[8] | TAMP0EN | Tamper0 Detect Enable Bit 0 = Tamper 0 detect Disabled. 1 = Tamper 0 detect Enabled. Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
[9] | TAMP0LV | Tamper 0 Level This bit depend on level attribute of tamper pin for static tamper detection. 0 = Detect voltage level is low. 1 = Detect voltage level is high.
[10] | TAMP0DBEN | Tamper 0 De-bounce Enable Bit 0 = Tamper 0 de-bounce Disabled. 1 = Tamper 0 de-bounce Enabled.
[12] | TAMP1EN | Tamper 1 Detect Enable Bit 0 = Tamper 1 detect Disabled. 1 = Tamper 1 detect Enabled. Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
[13] | TAMP1LV | Tamper 1 Level This bit depend on level attribute of tamper pin for static tamper detection. 0 = Detect voltage level is low. 1 = Detect voltage level is high.
[14] | TAMP1DBEN | Tamper 1 De-bounce Enable Bit 0 = Tamper 1 de-bounce Disabled. 1 = Tamper 1 de-bounce Enabled.
[15] | DYNPR0EN | Dynamic Pair 0 Enable Bit 0 = Static detect. 1 = Dynamic detect.
[16] | TAMP2EN | Tamper 2 Detect Enable Bit 0 = Tamper 2 detect Disabled. 1 = Tamper 2 detect Enabled. Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
[17] | TAMP2LV | Tamper 2 Level This bit depend on level attribute of tamper pin for static tamper detection. 0 = Detect voltage level is low. 1 = Detect voltage level is high.
[18] | TAMP2DBEN | Tamper 2 De-bounce Enable Bit 0 = Tamper 2 de-bounce Disabled. 1 = Tamper 2 de-bounce Enabled.
[20] | TAMP3EN | Tamper 3 Detect Enable Bit 0 = Tamper 3 detect Disabled. 1 = Tamper 3 detect Enabled. Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
[21] | TAMP3LV | Tamper 3 Level This bit depend on level attribute of tamper pin for static tamper detection. 0 = Detect voltage level is low. 1 = Detect voltage level is high.
[22] | TAMP3DBEN | Tamper 3 De-bounce Enable Bit 0 = Tamper 3 de-bounce Disabled. 1 = Tamper 3 de-bounce Enabled.
[23] | DYNPR1EN | Dynamic Pair 1 Enable Bit 0 = Static detect. 1 = Dynamic detect.
[24] | TAMP4EN | Tamper4 Detect Enable Bit 0 = Tamper 4 detect Disabled. 1 = Tamper 4 detect Enabled. Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
[25] | TAMP4LV | Tamper 4 Level This bit depends on level attribute of tamper pin for static tamper detection. 0 = Detect voltage level is low. 1 = Detect voltage level is high.
[26] | TAMP4DBEN | Tamper 4 De-bounce Enable Bit 0 = Tamper 4 de-bounce Disabled. 1 = Tamper 4 de-bounce Enabled.
[28] | TAMP5EN | Tamper 5 Detect Enable Bit 0 = Tamper 5 detect Disabled. 1 = Tamper 5 detect Enabled. Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
[29] | TAMP5LV | Tamper 5 Level This bit depend on level attribute of tamper pin for static tamper detection. 0 = Detect voltage level is low. 1 = Detect voltage level is high.
[30] | TAMP5DBEN | Tamper 5 De-bounce Enable Bit 0 = Tamper 5 de-bounce Disabled. 1 = Tamper 5 de-bounce Enabled.
[31] | DYNPR2EN | Dynamic Pair 2 Enable Bit 0 = Static detect. 1 = Dynamic detect.

Definition at line 1684 of file rtc_reg.h.

## ◆ TAMPSEED

RTC_T::TAMPSEED

[0x0128] RTC Tamper Dynamic Seed Register

TAMPSEED

Offset: 0x128 RTC Tamper Dynamic Seed Register

Bits | Field | Descriptions
[31:0] | SEED | Seed Value

Definition at line 1688 of file rtc_reg.h.

## ◆ TAMPTIME

RTC_T::TAMPTIME

[0x0130] RTC Tamper Time Register

TAMPTIME

Offset: 0x130 RTC Tamper Time Register

Bits | Field | Descriptions
[3:0] | SEC | 1-Sec Time Digit of TAMPER Time (0~9)
[6:4] | TENSEC | 10-Sec Time Digit of TAMPER Time (0~5)
[11:8] | MIN | 1-Min Time Digit of TAMPER Time (0~9)
[14:12] | TENMIN | 10-Min Time Digit of TAMPER Time (0~5)
[19:16] | HR | 1-Hour Time Digit of TAMPER Time (0~9)
[21:20] | TENHR | 10-Hour Time Digit of TAMPER Time (0~2) Note: 24-hour time scale only.

Definition at line 1692 of file rtc_reg.h.

## ◆ TAMSK

RTC_T::TAMSK

[0x0034] RTC Time Alarm Mask Register

TAMSK

Offset: 0x34 RTC Time Alarm Mask Register

Bits | Field | Descriptions
[0] | MSEC | Mask 1-Sec Time Digit of Alarm Setting (0~9)
[1] | MTENSEC | Mask 10-Sec Time Digit of Alarm Setting (0~5)
[2] | MMIN | Mask 1-Min Time Digit of Alarm Setting (0~9)
[3] | MTENMIN | Mask 10-Min Time Digit of Alarm Setting (0~5)
[4] | MHR | Mask 1-Hour Time Digit of Alarm Setting (0~9)
[5] | MTENHR | Mask 10-Hour Time Digit of Alarm Setting (0~2)

Definition at line 1667 of file rtc_reg.h.

## ◆ TICK

RTC_T::TICK

[0x0030] RTC Time Tick Register

TICK

Offset: 0x30 RTC Time Tick Register

Bits | Field | Descriptions
[2:0] | TICK | Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 000 = Time tick is 1 second. 001 = Time tick is 1/2 second. 010 = Time tick is 1/4 second. 011 = Time tick is 1/8 second. 100 = Time tick is 1/16 second. 101 = Time tick is 1/32 second. 110 = Time tick is 1/64 second. 111 = Time tick is 1/128 second. Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.

Definition at line 1666 of file rtc_reg.h.

## ◆ TIME

RTC_T::TIME

[0x000c] RTC Time Loading Register

TIME

Offset: 0x0C RTC Time Loading Register

Bits | Field | Descriptions
[3:0] | SEC | 1-Sec Time Digit (0~9)
[6:4] | TENSEC | 10-Sec Time Digit (0~5)
[11:8] | MIN | 1-Min Time Digit (0~9)
[14:12] | TENMIN | 10-Min Time Digit (0~5)
[19:16] | HR | 1-Hour Time Digit (0~9)
[21:20] | TENHR | 10-Hour Time Digit (0~2) When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message).

Definition at line 1657 of file rtc_reg.h.

## ◆ WEEKDAY

RTC_T::WEEKDAY

[0x0018] RTC Day of the Week Register

WEEKDAY

Offset: 0x18 RTC Day of the Week Register

Bits | Field | Descriptions
[2:0] | WEEKDAY | Day of the Week Register 000 = Sunday. 001 = Monday. 010 = Tuesday. 011 = Wednesday. 100 = Thursday. 101 = Friday. 110 = Saturday. 111 = Reserved.

Definition at line 1660 of file rtc_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/rtc_reg.h