| M480 BSP V3.05.001 The Board Support Package for M480 Series

i2c.c
Go to the documentation of this file.
1 /**************************************************************************/
9 #include "NuMicro.h"
10
37 uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
38 {
39 uint32_t u32Div;
40 uint32_t u32Pclk;
41
42 if(i2c == I2C1)
43 {
44 u32Pclk = CLK_GetPCLK1Freq();
45 }
46 else
47 {
48 u32Pclk = CLK_GetPCLK0Freq();
49 }
50
51 u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
52 i2c->CLKDIV = u32Div;
53
54 /* Enable I2C */
55 i2c->CTL0 |= I2C_CTL0_I2CEN_Msk;
56
57 return (u32Pclk / ((u32Div + 1U) << 2U));
58 }
59
71 void I2C_Close(I2C_T *i2c)
72 {
73 /* Reset I2C Controller */
74 if((uint32_t)i2c == I2C0_BASE)
75 {
76 SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
77 SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
78 }
79 else if((uint32_t)i2c == I2C1_BASE)
80 {
81 SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
82 SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
83 }
84 else if((uint32_t)i2c == I2C2_BASE)
85 {
86 SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk;
87 SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk;
88 }
89
90 /* Disable I2C */
91 i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk;
92 }
93
104 void I2C_ClearTimeoutFlag(I2C_T *i2c)
105 {
106 i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
107 }
108
123 void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
124 {
125 uint32_t u32Reg = 0U;
126
127 if(u8Start)
128 {
129 u32Reg |= I2C_CTL_STA;
130 }
131
132 if(u8Stop)
133 {
134 u32Reg |= I2C_CTL_STO;
135 }
136
137 if(u8Si)
138 {
139 u32Reg |= I2C_CTL_SI;
140 }
141
142 if(u8Ack)
143 {
144 u32Reg |= I2C_CTL_AA;
145 }
146
147 i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg;
148 }
149
160 void I2C_DisableInt(I2C_T *i2c)
161 {
162 i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk;
163 }
164
175 void I2C_EnableInt(I2C_T *i2c)
176 {
177 i2c->CTL0 |= I2C_CTL0_INTEN_Msk;
178 }
179
189 uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
190 {
191 uint32_t u32Divider = i2c->CLKDIV;
192 uint32_t u32Pclk;
193
194 if(i2c == I2C1)
195 {
196 u32Pclk = CLK_GetPCLK1Freq();
197 }
198 else
199 {
200 u32Pclk = CLK_GetPCLK0Freq();
201 }
202
203 return (u32Pclk / ((u32Divider + 1U) << 2U));
204 }
205
216 uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
217 {
218 uint32_t u32Div;
219 uint32_t u32Pclk;
220
221 if(i2c == I2C1)
222 {
223 u32Pclk = CLK_GetPCLK1Freq();
224 }
225 else
226 {
227 u32Pclk = CLK_GetPCLK0Freq();
228 }
229
230 u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */
231 i2c->CLKDIV = u32Div;
232
233 return (u32Pclk / ((u32Div + 1U) << 2U));
234 }
235
245 uint32_t I2C_GetIntFlag(I2C_T *i2c)
246 {
247 uint32_t u32Value;
248
249 if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk)
250 {
251 u32Value = 1U;
252 }
253 else
254 {
255 u32Value = 0U;
256 }
257
258 return u32Value;
259 }
260
270 uint32_t I2C_GetStatus(I2C_T *i2c)
271 {
272 return (i2c->STATUS0);
273 }
274
284 uint8_t I2C_GetData(I2C_T *i2c)
285 {
286 return (uint8_t)(i2c->DAT);
287 }
288
299 void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
300 {
301 i2c->DAT = u8Data;
302 }
303
318 void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
319 {
320 switch(u8SlaveNo)
321 {
322 case 1:
323 i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
324 break;
325 case 2:
326 i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
327 break;
328 case 3:
329 i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
330 break;
331 case 0:
332 default:
333 i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode;
334 break;
335 }
336 }
337
350 void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
351 {
352 switch(u8SlaveNo)
353 {
354 case 1:
355 i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U;
356 break;
357 case 2:
358 i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U;
359 break;
360 case 3:
361 i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U;
362 break;
363 case 0:
364 default:
365 i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U;
366 break;
367 }
368 }
369
382 void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
383 {
384 if(u8LongTimeout)
385 {
386 i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
387 }
388 else
389 {
390 i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
391 }
392
393 i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
394 }
395
406 void I2C_DisableTimeout(I2C_T *i2c)
407 {
408 i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
409 }
410
421 void I2C_EnableWakeup(I2C_T *i2c)
422 {
423 i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
424 }
425
436 void I2C_DisableWakeup(I2C_T *i2c)
437 {
438 i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
439 }
440
451 uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
452 {
453 return (i2c->BUSSTS);
454 }
455
467 void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
468 {
469 i2c->BUSSTS = u8SMBusIntFlag;
470 }
471
483 void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
484 {
485 i2c->PKTSIZE = u32PktSize;
486 }
487
499 void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
500 {
501 /* Clear BMHEN, BMDEN of BUSCTL Register */
502 i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);
503
504 /* Set SMBus Host/Device Mode, and enable Bus Management*/
505 if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE)
506 {
507 i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);
508 }
509 else
510 {
511 i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);
512 }
513 }
514
525 void I2C_SMBusClose(I2C_T *i2c)
526 {
527
528 i2c->BUSCTL = 0x00U;
529 }
530
542 void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
543 {
544 i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
545
546 if(u8PECTxEn)
547 {
548 i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);
549 }
550 else
551 {
552 i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;
553 }
554 }
555
566 uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
567 {
568 return (uint8_t)i2c->PKTCRC;
569 }
570
584 void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
585 {
586 uint32_t u32Div, u32Hclk_kHz;
587
588 i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
589 u32Hclk_kHz = u32Hclk / 1000U;
590 u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U;
591 if(u32Div > 255U)
592 {
593 i2c->BUSTOUT = 0xFFU;
594 }
595 else
596 {
597 i2c->BUSTOUT = u32Div;
598 }
599
600 }
601
616 void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
617 {
618 uint32_t u32Div, u32Pclk_kHz;
619
620 i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
621
622 /* DIV4 disabled */
623 i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
624 u32Pclk_kHz = u32Pclk / 1000U;
625 u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
626 if(u32Div <= 0xFFU)
627 {
628 i2c->BUSTOUT = u32Div;
629 }
630 else
631 {
632 /* DIV4 enabled */
633 i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
634 i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
635 }
636 }
637
652 void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
653 {
654 uint32_t u32Div, u32Pclk_kHz;
655
656 i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
657
658 /* DIV4 disabled */
659 i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
660 u32Pclk_kHz = u32Pclk / 1000U;
661 u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
662 if(u32Div <= 0xFFU)
663 {
664 i2c->CLKTOUT = u32Div;
665 }
666 else
667 {
668 /* DIV4 enabled */
669 i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
670 i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
671 }
672 }
673
674
689 uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
690 {
691 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
692
693 I2C_START(i2c);
694 while(u8Xfering && (u8Err == 0u))
695 {
696 I2C_WAIT_READY(i2c) {}
697 switch(I2C_GET_STATUS(i2c))
698 {
699 case 0x08u:
700 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
701 u8Ctrl = I2C_CTL_SI; /* Clear SI */
702 break;
703 case 0x18u: /* Slave Address ACK */
704 I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */
705 break;
706 case 0x20u: /* Slave Address NACK */
707 case 0x30u: /* Master transmit data NACK */
708 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
709 u8Err = 1u;
710 break;
711 case 0x28u:
712 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
713 u8Xfering = 0u;
714 break;
715 case 0x38u: /* Arbitration Lost */
716 default: /* Unknow status */
717 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
718 u8Ctrl = I2C_CTL_SI;
719 u8Err = 1u;
720 break;
721 }
722 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
723 }
724 return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
725 }
726
741 uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen)
742 {
743 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
744 uint32_t u32txLen = 0u;
745
746 I2C_START(i2c); /* Send START */
747 while(u8Xfering && (u8Err == 0u))
748 {
749 I2C_WAIT_READY(i2c) {}
750 switch(I2C_GET_STATUS(i2c))
751 {
752 case 0x08u:
753 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
754 u8Ctrl = I2C_CTL_SI; /* Clear SI */
755 break;
756 case 0x18u: /* Slave Address ACK */
757 case 0x28u:
758 if(u32txLen < u32wLen)
759 {
760 I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */
761 }
762 else
763 {
764 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
765 u8Xfering = 0u;
766 }
767 break;
768 case 0x20u: /* Slave Address NACK */
769 case 0x30u: /* Master transmit data NACK */
770 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
771 u8Err = 1u;
772 break;
773 case 0x38u: /* Arbitration Lost */
774 default: /* Unknow status */
775 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
776 u8Ctrl = I2C_CTL_SI;
777 u8Err = 1u;
778 break;
779 }
780 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
781 }
782 return u32txLen; /* Return bytes length that have been transmitted */
783 }
784
800 uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)
801 {
802 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
803 uint32_t u32txLen = 0u;
804
805 I2C_START(i2c); /* Send START */
806 while(u8Xfering && (u8Err == 0u))
807 {
808 I2C_WAIT_READY(i2c) {}
809 switch(I2C_GET_STATUS(i2c))
810 {
811 case 0x08u:
812 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */
813 u8Ctrl = I2C_CTL_SI; /* Clear SI */
814 break;
815 case 0x18u: /* Slave Address ACK */
816 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
817 break;
818 case 0x20u: /* Slave Address NACK */
819 case 0x30u: /* Master transmit data NACK */
820 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
821 u8Err = 1u;
822 break;
823 case 0x28u:
824 if(u32txLen < 1u)
825 {
826 I2C_SET_DATA(i2c, data);
827 u32txLen++;
828 }
829 else
830 {
831 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
832 u8Xfering = 0u;
833 }
834 break;
835 case 0x38u: /* Arbitration Lost */
836 default: /* Unknow status */
837 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
838 u8Ctrl = I2C_CTL_SI;
839 u8Err = 1u;
840 break;
841 }
842 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
843 }
844 return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
845 }
846
847
863 uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen)
864 {
865 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
866 uint32_t u32txLen = 0u;
867
868 I2C_START(i2c); /* Send START */
869 while(u8Xfering && (u8Err == 0u))
870 {
871 I2C_WAIT_READY(i2c) {}
872 switch(I2C_GET_STATUS(i2c))
873 {
874 case 0x08u:
875 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
876 u8Ctrl = I2C_CTL_SI;
877 break;
878 case 0x18u: /* Slave Address ACK */
879 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
880 break;
881 case 0x20u: /* Slave Address NACK */
882 case 0x30u: /* Master transmit data NACK */
883 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
884 u8Err = 1u;
885 break;
886 case 0x28u:
887 if(u32txLen < u32wLen)
888 {
889 I2C_SET_DATA(i2c, data[u32txLen++]);
890 }
891 else
892 {
893 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
894 u8Xfering = 0u;
895 }
896 break;
897 case 0x38u: /* Arbitration Lost */
898 default: /* Unknow status */
899 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
900 u8Ctrl = I2C_CTL_SI;
901 u8Err = 1u;
902 break;
903 }
904 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
905 }
906
907 return u32txLen; /* Return bytes length that have been transmitted */
908 }
909
925 uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)
926 {
927 uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
928 uint32_t u32txLen = 0u;
929
930 I2C_START(i2c); /* Send START */
931 while(u8Xfering && (u8Err == 0u))
932 {
933 I2C_WAIT_READY(i2c) {}
934 switch(I2C_GET_STATUS(i2c))
935 {
936 case 0x08u:
937 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
938 u8Ctrl = I2C_CTL_SI; /* Clear SI */
939 break;
940 case 0x18u: /* Slave Address ACK */
941 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
942 break;
943 case 0x20u: /* Slave Address NACK */
944 case 0x30u: /* Master transmit data NACK */
945 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
946 u8Err = 1u;
947 break;
948 case 0x28u:
949 if(u8Addr)
950 {
951 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
952 u8Addr = 0u;
953 }
954 else if((u32txLen < 1u) && (u8Addr == 0u))
955 {
956 I2C_SET_DATA(i2c, data);
957 u32txLen++;
958 }
959 else
960 {
961 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
962 u8Xfering = 0u;
963 }
964 break;
965 case 0x38u: /* Arbitration Lost */
966 default: /* Unknow status */
967 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
968 u8Ctrl = I2C_CTL_SI;
969 u8Err = 1u;
970 break;
971 }
972 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
973 }
974 return (u8Err | u8Xfering); /* return (Success)/(Fail) status */
975 }
976
977
993 uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen)
994 {
995 uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
996 uint32_t u32txLen = 0u;
997
998 I2C_START(i2c); /* Send START */
999 while(u8Xfering && (u8Err == 0u))
1000 {
1001 I2C_WAIT_READY(i2c) {}
1002 switch(I2C_GET_STATUS(i2c))
1003 {
1004 case 0x08u:
1005 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1006 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1007 break;
1008 case 0x18u: /* Slave Address ACK */
1009 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
1010 break;
1011 case 0x20u: /* Slave Address NACK */
1012 case 0x30u: /* Master transmit data NACK */
1013 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1014 u8Err = 1u;
1015 break;
1016 case 0x28u:
1017 if(u8Addr)
1018 {
1019 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
1020 u8Addr = 0u;
1021 }
1022 else if((u32txLen < u32wLen) && (u8Addr == 0u))
1023 {
1024 I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/
1025 }
1026 else
1027 {
1028 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1029 u8Xfering = 0u;
1030 }
1031 break;
1032 case 0x38u: /* Arbitration Lost */
1033 default: /* Unknow status */
1034 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1035 u8Ctrl = I2C_CTL_SI;
1036 u8Err = 1u;
1037 break;
1038 }
1039 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1040 }
1041 return u32txLen; /* Return bytes length that have been transmitted */
1042 }
1043
1055 uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
1056 {
1057 uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;
1058
1059 I2C_START(i2c); /* Send START */
1060 while(u8Xfering && (u8Err == 0u))
1061 {
1062 I2C_WAIT_READY(i2c) {}
1063 switch(I2C_GET_STATUS(i2c))
1064 {
1065 case 0x08u:
1066 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1067 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1068 break;
1069 case 0x40u: /* Slave Address ACK */
1070 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1071 break;
1072 case 0x48u: /* Slave Address NACK */
1073 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1074 u8Err = 1u;
1075 break;
1076 case 0x58u:
1077 rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1078 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1079 u8Xfering = 0u;
1080 break;
1081 case 0x38u: /* Arbitration Lost */
1082 default: /* Unknow status */
1083 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1084 u8Ctrl = I2C_CTL_SI;
1085 u8Err = 1u;
1086 break;
1087 }
1088 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1089 }
1090 if(u8Err)
1091 {
1092 rdata = 0u; /* If occurs error, return 0 */
1093 }
1094 return rdata; /* Return read data */
1095 }
1096
1097
1112 uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen)
1113 {
1114 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
1115 uint32_t u32rxLen = 0u;
1116
1117 I2C_START(i2c); /* Send START */
1118 while(u8Xfering && (u8Err == 0u))
1119 {
1120 I2C_WAIT_READY(i2c) {}
1121 switch(I2C_GET_STATUS(i2c))
1122 {
1123 case 0x08u:
1124 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1125 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1126 break;
1127 case 0x40u: /* Slave Address ACK */
1128 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1129 break;
1130 case 0x48u: /* Slave Address NACK */
1131 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1132 u8Err = 1u;
1133 break;
1134 case 0x50u:
1135 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1136 if(u32rxLen < (u32rLen - 1u))
1137 {
1138 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1139 }
1140 else
1141 {
1142 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1143 }
1144 break;
1145 case 0x58u:
1146 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1147 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1148 u8Xfering = 0u;
1149 break;
1150 case 0x38u: /* Arbitration Lost */
1151 default: /* Unknow status */
1152 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1153 u8Ctrl = I2C_CTL_SI;
1154 u8Err = 1u;
1155 break;
1156 }
1157 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1158 }
1159 return u32rxLen; /* Return bytes length that have been received */
1160 }
1161
1162
1176 uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
1177 {
1178 uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;
1179
1180 I2C_START(i2c); /* Send START */
1181 while(u8Xfering && (u8Err == 0u))
1182 {
1183 I2C_WAIT_READY(i2c) {}
1184 switch(I2C_GET_STATUS(i2c))
1185 {
1186 case 0x08u:
1187 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1188 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1189 break;
1190 case 0x18u: /* Slave Address ACK */
1191 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
1192 break;
1193 case 0x20u: /* Slave Address NACK */
1194 case 0x30u: /* Master transmit data NACK */
1195 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1196 u8Err = 1u;
1197 break;
1198 case 0x28u:
1199 u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
1200 break;
1201 case 0x10u:
1202 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1203 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1204 break;
1205 case 0x40u: /* Slave Address ACK */
1206 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1207 break;
1208 case 0x48u: /* Slave Address NACK */
1209 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1210 u8Err = 1u;
1211 break;
1212 case 0x58u:
1213 rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
1214 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1215 u8Xfering = 0u;
1216 break;
1217 case 0x38u: /* Arbitration Lost */
1218 default: /* Unknow status */
1219 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1220 u8Ctrl = I2C_CTL_SI;
1221 u8Err = 1u;
1222 break;
1223 }
1224 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1225 }
1226 if(u8Err)
1227 {
1228 rdata = 0u; /* If occurs error, return 0 */
1229 }
1230 return rdata; /* Return read data */
1231 }
1232
1248 uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen)
1249 {
1250 uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
1251 uint32_t u32rxLen = 0u;
1252
1253 I2C_START(i2c); /* Send START */
1254 while(u8Xfering && (u8Err == 0u))
1255 {
1256 I2C_WAIT_READY(i2c) {}
1257 switch(I2C_GET_STATUS(i2c))
1258 {
1259 case 0x08u:
1260 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1261 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1262 break;
1263 case 0x18u: /* Slave Address ACK */
1264 I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */
1265 break;
1266 case 0x20u: /* Slave Address NACK */
1267 case 0x30u: /* Master transmit data NACK */
1268 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1269 u8Err = 1u;
1270 break;
1271 case 0x28u:
1272 u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
1273 break;
1274 case 0x10u:
1275 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1276 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1277 break;
1278 case 0x40u: /* Slave Address ACK */
1279 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1280 break;
1281 case 0x48u: /* Slave Address NACK */
1282 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1283 u8Err = 1u;
1284 break;
1285 case 0x50u:
1286 rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
1287 if(u32rxLen < (u32rLen - 1u))
1288 {
1289 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1290 }
1291 else
1292 {
1293 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1294 }
1295 break;
1296 case 0x58u:
1297 rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
1298 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1299 u8Xfering = 0u;
1300 break;
1301 case 0x38u: /* Arbitration Lost */
1302 default: /* Unknow status */
1303 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1304 u8Ctrl = I2C_CTL_SI;
1305 u8Err = 1u;
1306 break;
1307 }
1308 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1309 }
1310 return u32rxLen; /* Return bytes length that have been received */
1311 }
1312
1326 uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
1327 {
1328 uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u;
1329
1330 I2C_START(i2c); /* Send START */
1331 while(u8Xfering && (u8Err == 0u))
1332 {
1333 I2C_WAIT_READY(i2c) {}
1334 switch(I2C_GET_STATUS(i2c))
1335 {
1336 case 0x08u:
1337 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1338 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1339 break;
1340 case 0x18u: /* Slave Address ACK */
1341 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
1342 break;
1343 case 0x20u: /* Slave Address NACK */
1344 case 0x30u: /* Master transmit data NACK */
1345 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1346 u8Err = 1u;
1347 break;
1348 case 0x28u:
1349 if(u8Addr)
1350 {
1351 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
1352 u8Addr = 0u;
1353 }
1354 else
1355 {
1356 u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */
1357 }
1358 break;
1359 case 0x10u:
1360 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1361 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1362 break;
1363 case 0x40u: /* Slave Address ACK */
1364 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1365 break;
1366 case 0x48u: /* Slave Address NACK */
1367 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1368 u8Err = 1u;
1369 break;
1370 case 0x58u:
1371 rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1372 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1373 u8Xfering = 0u;
1374 break;
1375 case 0x38u: /* Arbitration Lost */
1376 default: /* Unknow status */
1377 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1378 u8Ctrl = I2C_CTL_SI;
1379 u8Err = 1u;
1380 break;
1381 }
1382 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1383 }
1384 if(u8Err)
1385 {
1386 rdata = 0u; /* If occurs error, return 0 */
1387 }
1388 return rdata; /* Return read data */
1389 }
1390
1406 uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen)
1407 {
1408 uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
1409 uint32_t u32rxLen = 0u;
1410
1411 I2C_START(i2c); /* Send START */
1412 while(u8Xfering && (u8Err == 0u))
1413 {
1414 I2C_WAIT_READY(i2c) {}
1415 switch(I2C_GET_STATUS(i2c))
1416 {
1417 case 0x08u:
1418 I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */
1419 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1420 break;
1421 case 0x18u: /* Slave Address ACK */
1422 I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */
1423 break;
1424 case 0x20u: /* Slave Address NACK */
1425 case 0x30u: /* Master transmit data NACK */
1426 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1427 u8Err = 1u;
1428 break;
1429 case 0x28u:
1430 if(u8Addr)
1431 {
1432 I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */
1433 u8Addr = 0u;
1434 }
1435 else
1436 {
1437 u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */
1438 }
1439 break;
1440 case 0x10u:
1441 I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
1442 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1443 break;
1444 case 0x40u: /* Slave Address ACK */
1445 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1446 break;
1447 case 0x48u: /* Slave Address NACK */
1448 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1449 u8Err = 1u;
1450 break;
1451 case 0x50u:
1452 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1453 if(u32rxLen < (u32rLen - 1u))
1454 {
1455 u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
1456 }
1457 else
1458 {
1459 u8Ctrl = I2C_CTL_SI; /* Clear SI */
1460 }
1461 break;
1462 case 0x58u:
1463 rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
1464 u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
1465 u8Xfering = 0u;
1466 break;
1467 case 0x38u: /* Arbitration Lost */
1468 default: /* Unknow status */
1469 I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */
1470 u8Ctrl = I2C_CTL_SI;
1471 u8Err = 1u;
1472 break;
1473 }
1474 I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */
1475 }
1476 return u32rxLen; /* Return bytes length that have been received */
1477 }
1478
1479 /* end of group I2C_EXPORTED_FUNCTIONS */
1481 /* end of group I2C_Driver */
1483 /* end of group Standard_Driver */
1485
1486 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
I2C_BUSCTL_BMHEN_Msk
#define I2C_BUSCTL_BMHEN_Msk
Definition: i2c_reg.h:1215
I2C_T::PKTSIZE
__IO uint32_t PKTSIZE
Definition: i2c_reg.h:1070
I2C_START
#define I2C_START(i2c)
The macro is used to set START condition of I2C Bus.
Definition: i2c.h:85
I2C_T::BUSSTS
__IO uint32_t BUSSTS
Definition: i2c_reg.h:1069
I2C_T::ADDR2
__IO uint32_t ADDR2
Definition: i2c_reg.h:1053
I2C_CTL_SI_AA
#define I2C_CTL_SI_AA
Definition: i2c.h:38
I2C_DisableInt
void I2C_DisableInt(I2C_T *i2c)
Disable Interrupt of I2C Controller.
Definition: i2c.c:160
I2C_T::WKCTL
__IO uint32_t WKCTL
Definition: i2c_reg.h:1062
I2C_ClearTimeoutFlag
void I2C_ClearTimeoutFlag(I2C_T *i2c)
Clear Time-out Counter flag.
Definition: i2c.c:104
I2C_Close
void I2C_Close(I2C_T *i2c)
Disable specify I2C Controller.
Definition: i2c.c:71
I2C_WriteMultiBytesOneReg
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen)
Specify a byte register address and write multi bytes to Slave.
Definition: i2c.c:863
I2C_EnableInt
void I2C_EnableInt(I2C_T *i2c)
Enable Interrupt of I2C Controller.
Definition: i2c.c:175
I2C_WriteMultiBytesTwoRegs
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen)
Specify two bytes register address and write multi bytes to Slave.
Definition: i2c.c:993
I2C_BUSCTL_BUSEN_Msk
#define I2C_BUSCTL_BUSEN_Msk
Definition: i2c_reg.h:1227
I2C_WriteByte
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
Write a byte to Slave.
Definition: i2c.c:689
I2C_SetBusClockFreq
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
Set I2C Bus Clock.
Definition: i2c.c:216
I2C_EnableWakeup
void I2C_EnableWakeup(I2C_T *i2c)
Enable I2C Wake-up Function.
Definition: i2c.c:421
I2C_CTL_SI
#define I2C_CTL_SI
Definition: i2c.h:37
I2C_SMBH_ENABLE
#define I2C_SMBH_ENABLE
Definition: i2c.h:52
I2C_T::ADDRMSK0
__IO uint32_t ADDRMSK0
Definition: i2c_reg.h:1055
I2C_T::BUSTOUT
__IO uint32_t BUSTOUT
Definition: i2c_reg.h:1072
I2C_T
Definition: i2c_reg.h:26
SYS_IPRST1_I2C2RST_Msk
#define SYS_IPRST1_I2C2RST_Msk
Definition: sys_reg.h:4918
I2C_GetBusClockFreq
uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
Get I2C Bus Clock.
Definition: i2c.c:189
I2C_GetIntFlag
uint32_t I2C_GetIntFlag(I2C_T *i2c)
Get Interrupt Flag.
Definition: i2c.c:245
I2C_CTL0_INTEN_Msk
#define I2C_CTL0_INTEN_Msk
Definition: i2c_reg.h:1098
I2C_EnableTimeout
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
Enable Time-out Counter Function and support Long Time-out.
Definition: i2c.c:382
I2C_DisableTimeout
void I2C_DisableTimeout(I2C_T *i2c)
Disable Time-out Counter Function.
Definition: i2c.c:406
I2C0_BASE
#define I2C0_BASE
Definition: M480.h:315
I2C_SMBusClose
void I2C_SMBusClose(I2C_T *i2c)
Disable SMBus function.
Definition: i2c.c:525
SYS_IPRST1_I2C1RST_Msk
#define SYS_IPRST1_I2C1RST_Msk
Definition: sys_reg.h:4915
I2C_T::ADDR0
__IO uint32_t ADDR0
Definition: i2c_reg.h:1047
NuMicro.h
NuMicro peripheral access layer header file.
I2C_SET_DATA
#define I2C_SET_DATA(i2c, u8Data)
Write a Data to I2C Data Register.
Definition: i2c.h:122
I2C_T::CLKTOUT
__IO uint32_t CLKTOUT
Definition: i2c_reg.h:1073
SYS
#define SYS
Definition: M480.h:367
I2C_T::STATUS0
__I uint32_t STATUS0
Definition: i2c_reg.h:1049
I2C_T::ADDRMSK1
__IO uint32_t ADDRMSK1
Definition: i2c_reg.h:1056
I2C_SMBusGetStatus
uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
To get SMBus Status.
Definition: i2c.c:451
I2C_CTL_STO
#define I2C_CTL_STO
Definition: i2c.h:40
I2C_T::ADDRMSK3
__IO uint32_t ADDRMSK3
Definition: i2c_reg.h:1058
I2C_T::ADDRMSK2
__IO uint32_t ADDRMSK2
Definition: i2c_reg.h:1057
I2C1_BASE
#define I2C1_BASE
Definition: M480.h:342
I2C_ReadByteOneReg
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
Specify a byte register address and read a byte from Slave.
Definition: i2c.c:1176
I2C_ReadMultiBytes
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen)
Read multi bytes from Slave.
Definition: i2c.c:1112
CLK_GetPCLK1Freq
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:204
I2C_GetData
uint8_t I2C_GetData(I2C_T *i2c)
Read a Byte from I2C Bus.
Definition: i2c.c:284
I2C_TOCTL_TOCEN_Msk
#define I2C_TOCTL_TOCEN_Msk
Definition: i2c_reg.h:1122
CLK_GetPCLK0Freq
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:164
I2C_SMBusOpen
void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
Init SMBus Host/Device Mode.
Definition: i2c.c:499
I2C_BUSCTL_PECEN_Msk
#define I2C_BUSCTL_PECEN_Msk
Definition: i2c_reg.h:1209
I2C_DisableWakeup
void I2C_DisableWakeup(I2C_T *i2c)
Disable I2C Wake-up Function.
Definition: i2c.c:436
I2C_CTL_STA_SI
#define I2C_CTL_STA_SI
Definition: i2c.h:33
I2C_SMBusTimeout
void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
Calculate Time-out of SMBus active period.
Definition: i2c.c:616
I2C_T::CTL0
__IO uint32_t CTL0
Definition: i2c_reg.h:1046
I2C_BUSCTL_BMDEN_Msk
#define I2C_BUSCTL_BMDEN_Msk
Definition: i2c_reg.h:1212
I2C_CTL_STO_SI
#define I2C_CTL_STO_SI
Definition: i2c.h:35
I2C_SMBusGetPECValue
uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
Get SMBus CRC value.
Definition: i2c.c:566
I2C_WAIT_READY
#define I2C_WAIT_READY(i2c)
The macro is used to wait I2C bus status get ready.
Definition: i2c.h:97
I2C_GetStatus
uint32_t I2C_GetStatus(I2C_T *i2c)
Get I2C Bus Status Code.
Definition: i2c.c:270
I2C2_BASE
#define I2C2_BASE
Definition: M480.h:316
I2C_CTL0_I2CEN_Msk
#define I2C_CTL0_I2CEN_Msk
Definition: i2c_reg.h:1095
I2C_SMBusIdleTimeout
void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
Calculate Time-out of SMBus idle period.
Definition: i2c.c:584
I2C_TOCTL_TOCDIV4_Msk
#define I2C_TOCTL_TOCDIV4_Msk
Definition: i2c_reg.h:1119
I2C_GET_STATUS
#define I2C_GET_STATUS(i2c)
Get I2C Bus status code.
Definition: i2c.h:134
I2C_ReadByteTwoRegs
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
Specify two bytes register address and read a byte from Slave.
Definition: i2c.c:1326
I2C_WriteByteOneReg
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)
Specify a byte register address and write a byte to Slave.
Definition: i2c.c:800
I2C_ReadMultiBytesTwoRegs
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen)
Specify two bytes register address and read multi bytes from Slave.
Definition: i2c.c:1406
I2C_SMBusClearInterruptFlag
void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
Clear SMBus Interrupt Flag.
Definition: i2c.c:467
I2C_T::TOCTL
__IO uint32_t TOCTL
Definition: i2c_reg.h:1051
I2C_SetSlaveAddrMask
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
Configure the mask bits of 7-bit Slave Address.
Definition: i2c.c:350
I2C_T::ADDR1
__IO uint32_t ADDR1
Definition: i2c_reg.h:1052
I2C_T::CLKDIV
__IO uint32_t CLKDIV
Definition: i2c_reg.h:1050
I2C_GET_DATA
#define I2C_GET_DATA(i2c)
The macro is used to Read I2C Bus Data Register.
Definition: i2c.h:109
I2C_BUSCTL_TIDLE_Msk
#define I2C_BUSCTL_TIDLE_Msk
Definition: i2c_reg.h:1233
I2C_TOCTL_TOIF_Msk
#define I2C_TOCTL_TOIF_Msk
Definition: i2c_reg.h:1116
I2C_ReadByte
uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
Read a byte from Slave.
Definition: i2c.c:1055
I2C_T::BUSCTL
__IO uint32_t BUSCTL
Definition: i2c_reg.h:1067
I2C_CTL_STA
#define I2C_CTL_STA
Definition: i2c.h:39
I2C_CTL_AA
#define I2C_CTL_AA
Definition: i2c.h:41
I2C_CTL0_SI_Msk
#define I2C_CTL0_SI_Msk
Definition: i2c_reg.h:1086
I2C1
#define I2C1
Definition: M480.h:438
I2C_WriteByteTwoRegs
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)
Specify two bytes register address and Write a byte to Slave.
Definition: i2c.c:925
I2C_SetData
void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
Send a byte to I2C Bus.
Definition: i2c.c:299
I2C_SMBusSetPacketByteCount
void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
Set SMBus Bytes Counts of Transmission or Reception.
Definition: i2c.c:483
I2C_T::ADDR3
__IO uint32_t ADDR3
Definition: i2c_reg.h:1054
SYS_IPRST1_I2C0RST_Msk
#define SYS_IPRST1_I2C0RST_Msk
Definition: sys_reg.h:4912
I2C_ReadMultiBytesOneReg
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen)
Specify a byte register address and read multi bytes from Slave.
Definition: i2c.c:1248
I2C_SMBusClockLoTimeout
void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
Calculate Cumulative Clock low Time-out of SMBus active period.
Definition: i2c.c:652
I2C_T::PKTCRC
__I uint32_t PKTCRC
Definition: i2c_reg.h:1071
I2C_WriteMultiBytes
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen)
Write multi bytes to Slave.
Definition: i2c.c:741
I2C_WKCTL_WKEN_Msk
#define I2C_WKCTL_WKEN_Msk
Definition: i2c_reg.h:1155
I2C_SetSlaveAddr
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
Set 7-bit Slave Address and GC Mode.
Definition: i2c.c:318
I2C_SMBusPECTxEnable
void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
Enable SMBus PEC Transmit Function.
Definition: i2c.c:542
I2C_Open
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
Enable specify I2C Controller and set Clock Divider.
Definition: i2c.c:37
I2C_BUSCTL_PECTXEN_Msk
#define I2C_BUSCTL_PECTXEN_Msk
Definition: i2c_reg.h:1230
I2C_Trigger
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
Set Control bit of I2C Controller.
Definition: i2c.c:123
I2C_SET_CONTROL_REG
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl)
The macro is used to set I2C bus condition at One Time.
Definition: i2c.h:73
I2C_T::DAT
__IO uint32_t DAT
Definition: i2c_reg.h:1048