| M480 BSP V3.05.001 The Board Support Package for M480 Series

sdh_reg.h
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1 /**************************************************************************/
9 #ifndef __SDH_REG_H__
10 #define __SDH_REG_H__
11
12 #if defined ( __CC_ARM )
13 #pragma anon_unions
14 #endif
15
26 typedef struct
27 {
28
754 __IO uint32_t FB[32];
755 __I uint32_t RESERVE0[224];
758 __IO uint32_t DMACTL;
759 __I uint32_t RESERVE1[1];
762 __IO uint32_t DMASA;
763 __I uint32_t DMABCNT;
764 __IO uint32_t DMAINTEN;
765 __IO uint32_t DMAINTSTS;
766 __I uint32_t RESERVE2[250];
769 __IO uint32_t GCTL;
770 __IO uint32_t GINTEN;
771 __I uint32_t GINTSTS;
772 __I uint32_t RESERVE3[5];
775 __IO uint32_t CTL;
776 __IO uint32_t CMDARG;
777 __IO uint32_t INTEN;
778 __IO uint32_t INTSTS;
779 __I uint32_t RESP0;
780 __I uint32_t RESP1;
781 __IO uint32_t BLEN;
782 __IO uint32_t TOUT;
784 } SDH_T;
785
786
792 #define SDH_DMACTL_DMAEN_Pos (0)
793 #define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos)
795 #define SDH_DMACTL_DMARST_Pos (1)
796 #define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos)
798 #define SDH_DMACTL_SGEN_Pos (3)
799 #define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos)
801 #define SDH_DMACTL_DMABUSY_Pos (9)
802 #define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos)
804 #define SDH_DMASA_ORDER_Pos (0)
805 #define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos)
807 #define SDH_DMASA_DMASA_Pos (1)
808 #define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos)
810 #define SDH_DMABCNT_BCNT_Pos (0)
811 #define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos)
813 #define SDH_DMAINTEN_ABORTIEN_Pos (0)
814 #define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos)
816 #define SDH_DMAINTEN_WEOTIEN_Pos (1)
817 #define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos)
819 #define SDH_DMAINTSTS_ABORTIF_Pos (0)
820 #define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos)
822 #define SDH_DMAINTSTS_WEOTIF_Pos (1)
823 #define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos)
825 #define SDH_GCTL_GCTLRST_Pos (0)
826 #define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos)
828 #define SDH_GCTL_SDEN_Pos (1)
829 #define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos)
831 #define SDH_GINTEN_DTAIEN_Pos (0)
832 #define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos)
834 #define SDH_GINTSTS_DTAIF_Pos (0)
835 #define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos)
837 #define SDH_CTL_COEN_Pos (0)
838 #define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos)
840 #define SDH_CTL_RIEN_Pos (1)
841 #define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos)
843 #define SDH_CTL_DIEN_Pos (2)
844 #define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos)
846 #define SDH_CTL_DOEN_Pos (3)
847 #define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos)
849 #define SDH_CTL_R2EN_Pos (4)
850 #define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos)
852 #define SDH_CTL_CLK74OEN_Pos (5)
853 #define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos)
855 #define SDH_CTL_CLK8OEN_Pos (6)
856 #define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos)
858 #define SDH_CTL_CLKKEEP_Pos (7)
859 #define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos)
861 #define SDH_CTL_CMDCODE_Pos (8)
862 #define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos)
864 #define SDH_CTL_CTLRST_Pos (14)
865 #define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos)
867 #define SDH_CTL_DBW_Pos (15)
868 #define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos)
870 #define SDH_CTL_BLKCNT_Pos (16)
871 #define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos)
873 #define SDH_CTL_SDNWR_Pos (24)
874 #define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos)
876 #define SDH_CMDARG_ARGUMENT_Pos (0)
877 #define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos)
879 #define SDH_INTEN_BLKDIEN_Pos (0)
880 #define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos)
882 #define SDH_INTEN_CRCIEN_Pos (1)
883 #define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos)
885 #define SDH_INTEN_CDIEN_Pos (8)
886 #define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos)
888 #define SDH_INTEN_RTOIEN_Pos (12)
889 #define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos)
891 #define SDH_INTEN_DITOIEN_Pos (13)
892 #define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos)
894 #define SDH_INTEN_WKIEN_Pos (14)
895 #define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos)
897 #define SDH_INTEN_CDSRC_Pos (30)
898 #define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos)
900 #define SDH_INTSTS_BLKDIF_Pos (0)
901 #define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos)
903 #define SDH_INTSTS_CRCIF_Pos (1)
904 #define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos)
906 #define SDH_INTSTS_CRC7_Pos (2)
907 #define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos)
909 #define SDH_INTSTS_CRC16_Pos (3)
910 #define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos)
912 #define SDH_INTSTS_CRCSTS_Pos (4)
913 #define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos)
915 #define SDH_INTSTS_DAT0STS_Pos (7)
916 #define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos)
918 #define SDH_INTSTS_CDIF_Pos (8)
919 #define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos)
921 #define SDH_INTSTS_RTOIF_Pos (12)
922 #define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos)
924 #define SDH_INTSTS_DITOIF_Pos (13)
925 #define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos)
927 #define SDH_INTSTS_CDSTS_Pos (16)
928 #define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos)
930 #define SDH_INTSTS_DAT1STS_Pos (18)
931 #define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos)
933 #define SDH_RESP0_RESPTK0_Pos (0)
934 #define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos)
936 #define SDH_RESP1_RESPTK1_Pos (0)
937 #define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos)
939 #define SDH_BLEN_BLKLEN_Pos (0)
940 #define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos)
942 #define SDH_TOUT_TOUT_Pos (0)
943 #define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /* SDH_CONST */
946 /* end of SDH register group */ /* end of REGISTER group */
948
949 #if defined ( __CC_ARM )
950 #pragma no_anon_unions
951 #endif
952
953 #endif /* __SDH_REG_H__ */
954
SDH_T::GINTSTS
__I uint32_t GINTSTS
Definition: sdh_reg.h:771
SDH_T::DMACTL
__IO uint32_t DMACTL
Definition: sdh_reg.h:758
SDH_T::RESP0
__I uint32_t RESP0
Definition: sdh_reg.h:779
SDH_T::DMAINTEN
__IO uint32_t DMAINTEN
Definition: sdh_reg.h:764
SDH_T::CTL
__IO uint32_t CTL
Definition: sdh_reg.h:775
SDH_T::DMABCNT
__I uint32_t DMABCNT
Definition: sdh_reg.h:763
SDH_T::INTEN
__IO uint32_t INTEN
Definition: sdh_reg.h:777
SDH_T::INTSTS
__IO uint32_t INTSTS
Definition: sdh_reg.h:778
SDH_T::BLEN
__IO uint32_t BLEN
Definition: sdh_reg.h:781
SDH_T
Definition: sdh_reg.h:26
SDH_T::GINTEN
__IO uint32_t GINTEN
Definition: sdh_reg.h:770
SDH_T::GCTL
__IO uint32_t GCTL
Definition: sdh_reg.h:769
SDH_T::RESP1
__I uint32_t RESP1
Definition: sdh_reg.h:780
SDH_T::DMASA
__IO uint32_t DMASA
Definition: sdh_reg.h:762
SDH_T::TOUT
__IO uint32_t TOUT
Definition: sdh_reg.h:782
SDH_T::DMAINTSTS
__IO uint32_t DMAINTSTS
Definition: sdh_reg.h:765
SDH_T::CMDARG
__IO uint32_t CMDARG
Definition: sdh_reg.h:776