| M480 BSP V3.05.001 The Board Support Package for M480 Series

i2s_reg.h
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1 /**************************************************************************/
9 #ifndef __I2S_REG_H__
10 #define __I2S_REG_H__
11
12 #if defined ( __CC_ARM )
13 #pragma anon_unions
14 #endif
15
26 typedef struct
27 {
28
29
988 __IO uint32_t CTL0;
989 __IO uint32_t CLKDIV;
990 __IO uint32_t IEN;
991 __IO uint32_t STATUS0;
992 __O uint32_t TXFIFO;
993 __I uint32_t RXFIFO;
994 __I uint32_t RESERVE0[2];
997 __IO uint32_t CTL1;
998 __IO uint32_t STATUS1;
1000 } I2S_T;
1001
1007 #define I2S_CTL0_I2SEN_Pos (0)
1008 #define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos)
1010 #define I2S_CTL0_TXEN_Pos (1)
1011 #define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos)
1013 #define I2S_CTL0_RXEN_Pos (2)
1014 #define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos)
1016 #define I2S_CTL0_MUTE_Pos (3)
1017 #define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos)
1019 #define I2S_CTL0_DATWIDTH_Pos (4)
1020 #define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos)
1022 #define I2S_CTL0_MONO_Pos (6)
1023 #define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos)
1025 #define I2S_CTL0_ORDER_Pos (7)
1026 #define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos)
1028 #define I2S_CTL0_SLAVE_Pos (8)
1029 #define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos)
1031 #define I2S_CTL0_MCLKEN_Pos (15)
1032 #define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos)
1034 #define I2S_CTL0_TXFBCLR_Pos (18)
1035 #define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos)
1037 #define I2S_CTL0_RXFBCLR_Pos (19)
1038 #define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos)
1040 #define I2S_CTL0_TXPDMAEN_Pos (20)
1041 #define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos)
1043 #define I2S_CTL0_RXPDMAEN_Pos (21)
1044 #define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos)
1046 #define I2S_CTL0_RXLCH_Pos (23)
1047 #define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos)
1049 #define I2S_CTL0_FORMAT_Pos (24)
1050 #define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos)
1052 #define I2S_CTL0_PCMSYNC_Pos (27)
1053 #define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos)
1055 #define I2S_CTL0_CHWIDTH_Pos (28)
1056 #define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos)
1058 #define I2S_CTL0_TDMCHNUM_Pos (30)
1059 #define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos)
1061 #define I2S_CLKDIV_MCLKDIV_Pos (0)
1062 #define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos)
1064 #define I2S_CLKDIV_BCLKDIV_Pos (8)
1065 #define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos)
1067 #define I2S_IEN_RXUDFIEN_Pos (0)
1068 #define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos)
1070 #define I2S_IEN_RXOVFIEN_Pos (1)
1071 #define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos)
1073 #define I2S_IEN_RXTHIEN_Pos (2)
1074 #define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos)
1076 #define I2S_IEN_TXUDFIEN_Pos (8)
1077 #define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos)
1079 #define I2S_IEN_TXOVFIEN_Pos (9)
1080 #define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos)
1082 #define I2S_IEN_TXTHIEN_Pos (10)
1083 #define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos)
1085 #define I2S_IEN_CH0ZCIEN_Pos (16)
1086 #define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos)
1088 #define I2S_IEN_CH1ZCIEN_Pos (17)
1089 #define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos)
1091 #define I2S_IEN_CH2ZCIEN_Pos (18)
1092 #define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos)
1094 #define I2S_IEN_CH3ZCIEN_Pos (19)
1095 #define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos)
1097 #define I2S_IEN_CH4ZCIEN_Pos (20)
1098 #define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos)
1100 #define I2S_IEN_CH5ZCIEN_Pos (21)
1101 #define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos)
1103 #define I2S_IEN_CH6ZCIEN_Pos (22)
1104 #define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos)
1106 #define I2S_IEN_CH7ZCIEN_Pos (23)
1107 #define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos)
1109 #define I2S_STATUS0_I2SINT_Pos (0)
1110 #define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos)
1112 #define I2S_STATUS0_I2SRXINT_Pos (1)
1113 #define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos)
1115 #define I2S_STATUS0_I2STXINT_Pos (2)
1116 #define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos)
1118 #define I2S_STATUS0_DATACH_Pos (3)
1119 #define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos)
1121 #define I2S_STATUS0_RXUDIF_Pos (8)
1122 #define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos)
1124 #define I2S_STATUS0_RXOVIF_Pos (9)
1125 #define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos)
1127 #define I2S_STATUS0_RXTHIF_Pos (10)
1128 #define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos)
1130 #define I2S_STATUS0_RXFULL_Pos (11)
1131 #define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos)
1133 #define I2S_STATUS0_RXEMPTY_Pos (12)
1134 #define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos)
1136 #define I2S_STATUS0_TXUDIF_Pos (16)
1137 #define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos)
1139 #define I2S_STATUS0_TXOVIF_Pos (17)
1140 #define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos)
1142 #define I2S_STATUS0_TXTHIF_Pos (18)
1143 #define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos)
1145 #define I2S_STATUS0_TXFULL_Pos (19)
1146 #define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos)
1148 #define I2S_STATUS0_TXEMPTY_Pos (20)
1149 #define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos)
1151 #define I2S_STATUS0_TXBUSY_Pos (21)
1152 #define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos)
1154 #define I2S_TXFIFO_TXFIFO_Pos (0)
1155 #define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos)
1157 #define I2S_RXFIFO_RXFIFO_Pos (0)
1158 #define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos)
1160 #define I2S_CTL1_CH0ZCEN_Pos (0)
1161 #define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos)
1163 #define I2S_CTL1_CH1ZCEN_Pos (1)
1164 #define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos)
1166 #define I2S_CTL1_CH2ZCEN_Pos (2)
1167 #define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos)
1169 #define I2S_CTL1_CH3ZCEN_Pos (3)
1170 #define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos)
1172 #define I2S_CTL1_CH4ZCEN_Pos (4)
1173 #define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos)
1175 #define I2S_CTL1_CH5ZCEN_Pos (5)
1176 #define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos)
1178 #define I2S_CTL1_CH6ZCEN_Pos (6)
1179 #define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos)
1181 #define I2S_CTL1_CH7ZCEN_Pos (7)
1182 #define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos)
1184 #define I2S_CTL1_TXTH_Pos (8)
1185 #define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos)
1187 #define I2S_CTL1_RXTH_Pos (16)
1188 #define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos)
1190 #define I2S_CTL1_PBWIDTH_Pos (24)
1191 #define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos)
1193 #define I2S_CTL1_PB16ORD_Pos (25)
1194 #define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos)
1196 #define I2S_STATUS1_CH0ZCIF_Pos (0)
1197 #define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos)
1199 #define I2S_STATUS1_CH1ZCIF_Pos (1)
1200 #define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos)
1202 #define I2S_STATUS1_CH2ZCIF_Pos (2)
1203 #define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos)
1205 #define I2S_STATUS1_CH3ZCIF_Pos (3)
1206 #define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos)
1208 #define I2S_STATUS1_CH4ZCIF_Pos (4)
1209 #define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos)
1211 #define I2S_STATUS1_CH5ZCIF_Pos (5)
1212 #define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos)
1214 #define I2S_STATUS1_CH6ZCIF_Pos (6)
1215 #define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos)
1217 #define I2S_STATUS1_CH7ZCIF_Pos (7)
1218 #define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos)
1220 #define I2S_STATUS1_TXCNT_Pos (8)
1221 #define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos)
1223 #define I2S_STATUS1_RXCNT_Pos (16)
1224 #define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /* I2S_CONST */
1227 /* end of I2S register group */ /* end of REGISTER group */
1229
1230 #if defined ( __CC_ARM )
1231 #pragma no_anon_unions
1232 #endif
1233
1234 #endif /* __I2S_REG_H__ */
I2S_T::CTL1
__IO uint32_t CTL1
Definition: i2s_reg.h:997
I2S_T::STATUS0
__IO uint32_t STATUS0
Definition: i2s_reg.h:991
I2S_T
Definition: i2s_reg.h:26
I2S_T::CLKDIV
__IO uint32_t CLKDIV
Definition: i2s_reg.h:989
I2S_T::TXFIFO
__O uint32_t TXFIFO
Definition: i2s_reg.h:992
I2S_T::STATUS1
__IO uint32_t STATUS1
Definition: i2s_reg.h:998
I2S_T::RXFIFO
__I uint32_t RXFIFO
Definition: i2s_reg.h:993
I2S_T::CTL0
__IO uint32_t CTL0
Definition: i2s_reg.h:988
I2S_T::IEN
__IO uint32_t IEN
Definition: i2s_reg.h:990