| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
SDH_T Struct Reference
Control Register

`#include <sdh_reg.h>`

## Data Fields
__IO uint32_t | FB [32]
__IO uint32_t | DMACTL
__IO uint32_t | DMASA
__I uint32_t | DMABCNT
__IO uint32_t | DMAINTEN
__IO uint32_t | DMAINTSTS
__IO uint32_t | GCTL
__IO uint32_t | GINTEN
__I uint32_t | GINTSTS
__IO uint32_t | CTL
__IO uint32_t | CMDARG
__IO uint32_t | INTEN
__IO uint32_t | INTSTS
__I uint32_t | RESP0
__I uint32_t | RESP1
__IO uint32_t | BLEN
__IO uint32_t | TOUT

## Detailed Description

    @addtogroup SDH SD Card Host Interface(SDH)
    Memory Mapped Structure for SDH Controller

Definition at line 26 of file sdh_reg.h.

## Field Documentation

## ◆ BLEN

SDH_T::BLEN

[0x0838] SD Block Length Register

BLEN

Offset: 0x838 SD Block Length Register

Bits | Field | Descriptions
[10:0] | BLKLEN | SD BLOCK LENGTH in Byte Unit An 11-bit value specifies the SD transfer byte count of a block The actual byte count is equal to BLKLEN+1. Note: The default SD block length is 512 bytes

Definition at line 781 of file sdh_reg.h.

## ◆ CMDARG

SDH_T::CMDARG

[0x0824] SD Command Argument Register

CMDARG

Offset: 0x824 SD Command Argument Register

Bits | Field | Descriptions
[31:0] | ARGUMENT | SD Command Argument This register contains a 32-bit value specifies the argument of SD command from host controller to SD card Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.

Definition at line 776 of file sdh_reg.h.

## ◆ CTL

SDH_T::CTL

[0x0820] SD Control and Status Register

CTL

Offset: 0x820 SD Control and Status Register

Bits | Field | Descriptions
[0] | COEN | Command Output Enable Bit 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 1 = Enabled, SD host will output a command to SD card. Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
[1] | RIEN | Response Input Enable Bit 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 1 = Enabled, SD host will wait to receive a response from SD card. Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
[2] | DIEN | Data Input Enable Bit 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
[3] | DOEN | Data Output Enable Bit 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
[4] | R2EN | Response R2 Input Enable Bit 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
[5] | CLK74OEN | Initial 74 Clock Cycles Output Enable Bit 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 1 = Enabled, SD host will output 74 clock cycles to SD card. Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
[6] | CLK8OEN | Generating 8 Clock Cycles Output Enable Bit 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) 1 = Enabled, SD host will output 8 clock cycles. Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
[7] | CLKKEEP | SD Clock Enable Control 0 = SD host decided when to output clock and when to disable clock output automatically. 1 = SD clock always keeps free running.
[13:8] | CMDCODE | SD Command Code This register contains the SD command code (0x00 - 0x3F).
[14] | CTLRST | Software Engine Reset 0 = No effect. 1 = Reset the internal state machine and counters The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared) This bit will be auto cleared after few clock cycles.
[15] | DBW | SD Data Bus Width (for 1-bit / 4-bit Selection) 0 = Data bus width is 1-bit. 1 = Data bus width is 4-bit.
[23:16] | BLKCNT | Block Counts to Be Transferred or Received This field contains the block counts for data-in and data-out transfer For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance Don't fill 0x0 to this field. Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
[27:24] | SDNWR | NWR Parameter for Block Write Operation This value indicates the NWR parameter for data block write operation in SD clock counts The actual clock cycle will be SDNWR+1.

Definition at line 775 of file sdh_reg.h.

## ◆ DMABCNT

SDH_T::DMABCNT

[0x040c] DMA Transfer Byte Count Register

DMABCNT

Offset: 0x40C DMA Transfer Byte Count Register

Bits | Field | Descriptions
[25:0] | BCNT | DMA Transfer Byte Count (Read Only) This field indicates the remained byte count of DMA transfer The value of this field is valid only when DMA is busy; otherwise, it is 0.

Definition at line 763 of file sdh_reg.h.

## ◆ DMACTL

SDH_T::DMACTL

[0x0400] DMA Control and Status Register

DMACTL

Offset: 0x400 DMA Control and Status Register

Bits | Field | Descriptions
[0] | DMAEN | DMA Engine Enable Bit 0 = DMA Disabled. 1 = DMA Enabled. If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. Note: If target abort is occurred, DMAEN will be cleared.
[1] | DMARST | Software Engine Reset 0 = No effect. 1 = Reset internal state machine and pointers The contents of control register will not be cleared This bit will auto be cleared after few clock cycles. Note: The software reset DMA related registers.
[3] | SGEN | Scatter-gather Function Enable Bit 0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). 1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table The format of these Pads' will be described later).
[9] | DMABUSY | DMA Transfer Is in Progress This bit indicates if SD Host is granted and doing DMA transfer or not. 0 = DMA transfer is not in progress. 1 = DMA transfer is in progress.

Definition at line 758 of file sdh_reg.h.

## ◆ DMAINTEN

SDH_T::DMAINTEN

[0x0410] DMA Interrupt Enable Control Register

DMAINTEN

Offset: 0x410 DMA Interrupt Enable Control Register

Bits | Field | Descriptions
[0] | ABORTIEN | DMA Read/Write Target Abort Interrupt Enable Bit 0 = Target abort interrupt generation Disabled during DMA transfer. 1 = Target abort interrupt generation Enabled during DMA transfer.
[1] | WEOTIEN | Wrong EOT Encountered Interrupt Enable Bit 0 = Interrupt generation Disabled when wrong EOT is encountered. 1 = Interrupt generation Enabled when wrong EOT is encountered.

Definition at line 764 of file sdh_reg.h.

## ◆ DMAINTSTS

SDH_T::DMAINTSTS

[0x0414] DMA Interrupt Status Register

DMAINTSTS

Offset: 0x414 DMA Interrupt Status Register

Bits | Field | Descriptions
[0] | ABORTIF | DMA Read/Write Target Abort Interrupt Flag 0 = No bus ERROR response received. 1 = Bus ERROR response received. Note1: This bit is read only, but can be cleared by writing '1' to it. Note2: When DMA's bus master received ERROR response, it means that target abort is happened DMA will stop transfer and respond this event and then go to IDLE state When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
[1] | WEOTIF | Wrong EOT Encountered Interrupt Flag When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. 0 = No EOT encountered before DMA transfer finished. 1 = EOT encountered before DMA transfer finished. Note: This bit is read only, but can be cleared by writing '1' to it.

Definition at line 765 of file sdh_reg.h.

## ◆ DMASA

SDH_T::DMASA

[0x0408] DMA Transfer Starting Address Register

DMASA

Offset: 0x408 DMA Transfer Starting Address Register

Bits | Field | Descriptions
[0] | ORDER | Determined to the PAD Table Fetching Is in Order or Out of Order 0 = PAD table is fetched in order. 1 = PAD table is fetched out of order. Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
[31:1] | DMASA | DMA Transfer Starting Address This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.

Definition at line 762 of file sdh_reg.h.

## ◆ FB

SDH_T::FB

Shared Buffer (FIFO)

FB

Offset: 0x00~0x7C Shared Buffer (FIFO)

Bits | Field | Descriptions
[31:0] | BUFFER | Shared Buffer Buffer for DMA transfer

Definition at line 754 of file sdh_reg.h.

## ◆ GCTL

SDH_T::GCTL

[0x0800] Global Control and Status Register

GCTL

Offset: 0x800 Global Control and Status Register

Bits | Field | Descriptions
[0] | GCTLRST | Software Engine Reset 0 = No effect. 1 = Reset SD host The contents of control register will not be cleared This bit will auto cleared after reset complete.
[1] | SDEN | Secure Digital Functionality Enable Bit 0 = SD functionality disabled. 1 = SD functionality enabled.

Definition at line 769 of file sdh_reg.h.

## ◆ GINTEN

SDH_T::GINTEN

[0x0804] Global Interrupt Control Register

GINTEN

Offset: 0x804 Global Interrupt Control Register

Bits | Field | Descriptions
[0] | DTAIEN | DMA READ/WRITE Target Abort Interrupt Enable Bit 0 = DMA READ/WRITE target abort interrupt generation disabled. 1 = DMA READ/WRITE target abort interrupt generation enabled.

Definition at line 770 of file sdh_reg.h.

## ◆ GINTSTS

SDH_T::GINTSTS

[0x0808] Global Interrupt Status Register

GINTSTS

Offset: 0x808 Global Interrupt Status Register

Bits | Field | Descriptions
[0] | DTAIF | DMA READ/WRITE Target Abort Interrupt Flag (Read Only) This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation When Target Abort is occurred, please reset all engine. 0 = No bus ERROR response received. 1 = Bus ERROR response received. Note: This bit is read only, but can be cleared by writing '1' to it.

Definition at line 771 of file sdh_reg.h.

## ◆ INTEN

SDH_T::INTEN

[0x0828] SD Interrupt Control Register

INTEN

Offset: 0x828 SD Interrupt Control Register

Bits | Field | Descriptions
[0] | BLKDIEN | Block Transfer Done Interrupt Enable Bit 0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable. 1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled.
[1] | CRCIEN | CRC7, CRC16 and CRC Status Error Interrupt Enable Bit 0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable. 1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled.
[8] | CDIEN | SD Card Detection Interrupt Enable Bit Enable/Disable interrupts generation of SD controller when card is inserted or removed. 0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable. 1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled.
[12] | RTOIEN | Response Time-out Interrupt Enable Bit Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out Time-out value is specified at TOUT register. 0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled. 1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled.
[13] | DITOIEN | Data Input Time-out Interrupt Enable Bit Enable/Disable interrupts generation of SD controller when data input time-out Time-out value is specified at TOUT register. 0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled. 1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled.
[14] | WKIEN | Wake-up Signal Generating Enable Bit Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. 0 = SD Card interrupt to wake-up chip Disabled. 1 = SD Card interrupt to wake-up chip Enabled.
[30] | CDSRC | SD Card Detect Source Selection 0 = From SD card's DAT3 pin. Host need clock to got data on pin DAT3 Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. 1 = From GPIO pin.

Definition at line 777 of file sdh_reg.h.

## ◆ INTSTS

SDH_T::INTSTS

[0x082c] SD Interrupt Status Register

INTSTS

Offset: 0x82C SD Interrupt Status Register

Bits | Field | Descriptions
[0] | BLKDIF | Block Transfer Done Interrupt Flag (Read Only) This bit indicates that SD host has finished all data-in or data-out block transfer If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. 0 = Not finished yet. 1 = Done. Note: This bit is read only, but can be cleared by writing '1' to it.
[1] | CRCIF | CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer When CRC error is occurred, software should reset SD engine Some response (ex R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag In this condition, software should ignore CRC error and clears this bit manually. 0 = No CRC error is occurred. 1 = CRC error is occurred. Note: This bit is read only, but can be cleared by writing '1' to it.
[2] | CRC7 | CRC7 Check Status (Read Only) SD host will check CRC7 correctness during each response in If that response does not contain CRC7 information (ex R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. 0 = Fault. 1 = OK.
[3] | CRC16 | CRC16 Check Status of Data-in Transfer (Read Only) SD host will check CRC16 correctness after data-in transfer. 0 = Fault. 1 = OK.
[6:4] | CRCSTS | CRC Status Value of Data-out Transfer (Read Only) SD host will record CRC status of data-out transfer Software could use this value to identify what type of error is during data-out transfer. 010 = Positive CRC status. 101 = Negative CRC status. 111 = SD card programming error occurs.
[7] | DAT0STS | DAT0 Pin Status of Current Selected SD Port (Read Only) This bit is the DAT0 pin status of current selected SD port.
[8] | CDIF | SD Card Detection Interrupt Flag (Read Only) This bit indicates that SD card is inserted or removed Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active. 0 = No card is inserted or removed. 1 = There is a card inserted in or removed from SD. Note: This bit is read only, but can be cleared by writing '1' to it.
[12] | RTOIF | Response Time-out Interrupt Flag (Read Only) This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). 0 = Not time-out. 1 = Response time-out. Note: This bit is read only, but can be cleared by writing '1' to it.
[13] | DITOIF | Data Input Time-out Interrupt Flag (Read Only) This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). 0 = Not time-out. 1 = Data input time-out. Note: This bit is read only, but can be cleared by writing '1' to it.
[16] | CDSTS | Card Detect Status of SD (Read Only) This bit indicates the card detect pin status of SD, and is used for card detection When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal. If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. 0 = Card removed. 1 = Card inserted. If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:. 0 = Card inserted. 1 = Card removed.
[18] | DAT1STS | DAT1 Pin Status of SD Port (Read Only) This bit indicates the DAT1 pin status of SD port.

Definition at line 778 of file sdh_reg.h.

## ◆ RESP0

SDH_T::RESP0

[0x0830] SD Receiving Response Token Register 0

RESP0

Offset: 0x830 SD Receiving Response Token Register 0

Bits | Field | Descriptions
[31:0] | RESPTK0 | SD Receiving Response Token 0 SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set This field contains response bit 47-16 of the response token.

Definition at line 779 of file sdh_reg.h.

## ◆ RESP1

SDH_T::RESP1

[0x0834] SD Receiving Response Token Register 1

RESP1

Offset: 0x834 SD Receiving Response Token Register 1

Bits | Field | Descriptions
[7:0] | RESPTK1 | SD Receiving Response Token 1 SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set This register contains the bit 15-8 of the response token.

Definition at line 780 of file sdh_reg.h.

## ◆ TOUT

SDH_T::TOUT

[0x083c] SD Response/Data-in Time-out Register

TOUT

Offset: 0x83C SD Response/Data-in Time-out Register

Bits | Field | Descriptions
[23:0] | TOUT | SD Response/Data-in Time-out Value A 24-bit value specifies the time-out counts of response and data input SD host controller will wait start bit of response or data-in until this value reached The time period depends on SD engine clock frequency Do not write a small number into this field, or you may never get response or data due to time-out. Note: Filling 0x0 into this field will disable hardware time-out function.

Definition at line 782 of file sdh_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/sdh_reg.h