| M480 BSP V3.05.001 The Board Support Package for M480 Series

ccap_reg.h
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1 /**************************************************************************/
9 #ifndef __CCAP_REG_H__
10 #define __CCAP_REG_H__
11
12 #if defined ( __CC_ARM )
13 #pragma anon_unions
14 #endif
15
27 typedef struct {
28
29
691 __IO uint32_t CTL;
692 __IO uint32_t PAR;
693 __IO uint32_t INT;
694 __IO uint32_t POSTERIZE;
695 __IO uint32_t MD;
696 __IO uint32_t MDADDR;
697 __IO uint32_t MDYADDR;
698 __IO uint32_t SEPIA;
699 __IO uint32_t CWSP;
700 __IO uint32_t CWS;
701 __IO uint32_t PKTSL;
702 __IO uint32_t PLNSL;
703 __IO uint32_t FRCTL;
704 __IO uint32_t STRIDE;
706 uint32_t RESERVE0[1];
708 __IO uint32_t FIFOTH;
709 __IO uint32_t CMPADDR;
710 __IO uint32_t LUMA_Y1_THD;
711 __IO uint32_t PKTSM;
713 uint32_t RESERVE2[5];
715 __IO uint32_t PKTBA0;
716 } CCAP_T;
717
723 #define CCAP_CTL_CCAPEN_Pos (0)
724 #define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos)
726 #define CCAP_CTL_ADDRSW_Pos (3)
727 #define CCAP_CTL_ADDRSW_Msk (0x1ul << CCAP_CTL_ADDRSW_Pos)
729 #define CCAP_CTL_PLNEN_Pos (5)
730 #define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos)
732 #define CCAP_CTL_PKTEN_Pos (6)
733 #define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos)
735 #define CCAP_CTL_MONO_Pos (7)
736 #define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos)
738 #define CCAP_CTL_SHUTTER_Pos (16)
739 #define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos)
741 #define CCAP_CTL_MY4_SWAP_Pos (17)
742 #define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos)
744 #define CCAP_CTL_MY8_MY4_Pos (18)
745 #define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos)
747 #define CCAP_CTL_Luma_Y_One_Pos (19)
748 #define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos)
750 #define CCAP_CTL_UPDATE_Pos (20)
751 #define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos)
753 #define CCAP_CTL_VPRST_Pos (24)
754 #define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos)
756 #define CCAP_PAR_INFMT_Pos (0)
757 #define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos)
759 #define CCAP_PAR_SENTYPE_Pos (1)
760 #define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos)
762 #define CCAP_PAR_INDATORD_Pos (2)
763 #define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos)
765 #define CCAP_PAR_OUTFMT_Pos (4)
766 #define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos)
768 #define CCAP_PAR_RANGE_Pos (6)
769 #define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos)
771 #define CCAP_PAR_PLNFMT_Pos (7)
772 #define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_PLNFMT_Pos)
774 #define CCAP_PAR_PCLKP_Pos (8)
775 #define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos)
777 #define CCAP_PAR_HSP_Pos (9)
778 #define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos)
780 #define CCAP_PAR_VSP_Pos (10)
781 #define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos)
783 #define CCAP_PAR_COLORCTL_Pos (11)
784 #define CCAP_PAR_COLORCTL_Msk (0x3ul << CCAP_PAR_COLORCTL_Pos)
786 #define CCAP_PAR_FBB_Pos (18)
787 #define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos)
789 #define CCAP_INT_VINTF_Pos (0)
790 #define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos)
792 #define CCAP_INT_MEINTF_Pos (1)
793 #define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos)
795 #define CCAP_INT_ADDRMINTF_Pos (3)
796 #define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos)
798 #define CCAP_INT_MDINTF_Pos (4)
799 #define CCAP_INT_MDINTF_Msk (0x1ul << CCAP_INT_MDINTF_Pos)
801 #define CCAP_INT_VIEN_Pos (16)
802 #define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos)
804 #define CCAP_INT_MEIEN_Pos (17)
805 #define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos)
807 #define CCAP_INT_ADDRMIEN_Pos (19)
808 #define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos)
810 #define CCAP_CWSP_CWSADDRH_Pos (0)
811 #define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos)
813 #define CCAP_CWSP_CWSADDRV_Pos (16)
814 #define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos)
816 #define CCAP_CWS_CWW_Pos (0)
817 #define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos)
818 #define CCAP_CWS_CWH_Pos (16)
819 #define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos)
821 #define CCAP_PKTSL_PKTSHML_Pos (0)
822 #define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos)
824 #define CCAP_PKTSL_PKTSHNL_Pos (8)
825 #define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos)
827 #define CCAP_PKTSL_PKTSVML_Pos (16)
828 #define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos)
830 #define CCAP_PKTSL_PKTSVNL_Pos (24)
831 #define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos)
833 #define CCAP_FRCTL_FRM_Pos (0)
834 #define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos)
836 #define CCAP_FRCTL_FRN_Pos (8)
837 #define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos)
839 #define CCAP_STRIDE_PKTSTRIDE_Pos (0)
840 #define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos)
842 #define CCAP_STRIDE_PLNSTRIDE_Pos (16)
843 #define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos)
845 #define CCAP_FIFOTH_PLNVFTH_Pos (0)
846 #define CCAP_FIFOTH_PLNVFTH_Msk (0xful << CCAP_FIFOTH_PLNVFTH_Pos)
848 #define CCAP_FIFOTH_PLNUFTH_Pos (8)
849 #define CCAP_FIFOTH_PLNUFTH_Msk (0xful << CCAP_FIFOTH_PLNUFTH_Pos)
851 #define CCAP_FIFOTH_PLNYFTH_Pos (16)
852 #define CCAP_FIFOTH_PLNYFTH_Msk (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos)
854 #define CCAP_FIFOTH_PKTFTH_Pos (24)
855 #define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos)
857 #define CCAP_FIFOTH_OVF_Pos (31)
858 #define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos)
860 #define CCAP_CMPADDR_CMPADDR_Pos (0)
861 #define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos)
863 #define CCAP_PKTSM_PKTSHMH_Pos (0)
864 #define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos)
866 #define CCAP_PKTSM_PKTSHNH_Pos (8)
867 #define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos)
869 #define CCAP_PKTSM_PKTSVMH_Pos (16)
870 #define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos)
872 #define CCAP_PKTSM_PKTSVNH_Pos (24)
873 #define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos)
875 #define CCAP_PKTBA0_BASEADDR_Pos (0)
876 #define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /* CCAP_CONST */
879 /* end of CCAP register group */ /* end of REGISTER group */
881
882 #if defined ( __CC_ARM )
883 #pragma no_anon_unions
884 #endif
885
886 #endif /* __CCAP_REG_H__ */
CCAP_T::CMPADDR
__IO uint32_t CMPADDR
Definition: ccap_reg.h:709
CCAP_T
Definition: ccap_reg.h:27
CCAP_T::PLNSL
__IO uint32_t PLNSL
Definition: ccap_reg.h:702
CCAP_T::CWS
__IO uint32_t CWS
Definition: ccap_reg.h:700
CCAP_T::CWSP
__IO uint32_t CWSP
Definition: ccap_reg.h:699
CCAP_T::PKTSL
__IO uint32_t PKTSL
Definition: ccap_reg.h:701
CCAP_T::STRIDE
__IO uint32_t STRIDE
Definition: ccap_reg.h:704
CCAP_T::CTL
__IO uint32_t CTL
Definition: ccap_reg.h:691
CCAP_T::PKTBA0
__IO uint32_t PKTBA0
Definition: ccap_reg.h:715
CCAP_T::INT
__IO uint32_t INT
Definition: ccap_reg.h:693
CCAP_T::MDYADDR
__IO uint32_t MDYADDR
Definition: ccap_reg.h:697
CCAP_T::FRCTL
__IO uint32_t FRCTL
Definition: ccap_reg.h:703
CCAP_T::FIFOTH
__IO uint32_t FIFOTH
Definition: ccap_reg.h:708
CCAP_T::PKTSM
__IO uint32_t PKTSM
Definition: ccap_reg.h:711
CCAP_T::PAR
__IO uint32_t PAR
Definition: ccap_reg.h:692
CCAP_T::MDADDR
__IO uint32_t MDADDR
Definition: ccap_reg.h:696
CCAP_T::POSTERIZE
__IO uint32_t POSTERIZE
Definition: ccap_reg.h:694
CCAP_T::MD
__IO uint32_t MD
Definition: ccap_reg.h:695
CCAP_T::SEPIA
__IO uint32_t SEPIA
Definition: ccap_reg.h:698
CCAP_T::LUMA_Y1_THD
__IO uint32_t LUMA_Y1_THD
Definition: ccap_reg.h:710