| M480 BSP V3.05.001 The Board Support Package for M480 Series

Macros
SYS Exported Constants
Standard Driver » SYS Driver

## Macros
#define | PDMA_RST
#define | EBI_RST
#define | EMAC_RST
#define | SDH0_RST
#define | CRC_RST
#define | CCAP_RST
#define | HSUSBD_RST
#define | CRPT_RST
#define | SPIM_RST
#define | USBH_RST
#define | SDH1_RST
#define | GPIO_RST
#define | TMR0_RST
#define | TMR1_RST
#define | TMR2_RST
#define | TMR3_RST
#define | ACMP01_RST
#define | I2C0_RST
#define | I2C1_RST
#define | I2C2_RST
#define | QSPI0_RST
#define | SPI0_RST
#define | SPI1_RST
#define | SPI2_RST
#define | UART0_RST
#define | UART1_RST
#define | UART2_RST
#define | UART3_RST
#define | UART4_RST
#define | UART5_RST
#define | UART6_RST
#define | UART7_RST
#define | CAN0_RST
#define | CAN1_RST
#define | OTG_RST
#define | USBD_RST
#define | EADC_RST
#define | I2S0_RST
#define | HSOTG_RST
#define | TRNG_RST
#define | SC0_RST
#define | SC1_RST
#define | SC2_RST
#define | QSPI1_RST
#define | SPI3_RST
#define | USCI0_RST
#define | USCI1_RST
#define | DAC_RST
#define | EPWM0_RST
#define | EPWM1_RST
#define | BPWM0_RST
#define | BPWM1_RST
#define | QEI0_RST
#define | QEI1_RST
#define | ECAP0_RST
#define | ECAP1_RST
#define | CAN2_RST
#define | OPA_RST
#define | EADC1_RST
#define | SYS_BODCTL_BOD_RST_EN
#define | SYS_BODCTL_BOD_INTERRUPT_EN
#define | SYS_BODCTL_BODVL_3_0V
#define | SYS_BODCTL_BODVL_2_8V
#define | SYS_BODCTL_BODVL_2_6V
#define | SYS_BODCTL_BODVL_2_4V
#define | SYS_BODCTL_BODVL_2_2V
#define | SYS_BODCTL_BODVL_2_0V
#define | SYS_BODCTL_BODVL_1_8V
#define | SYS_BODCTL_BODVL_1_6V
#define | SYS_VREFCTL_VREF_PIN
#define | SYS_VREFCTL_VREF_1_6V
#define | SYS_VREFCTL_VREF_2_0V
#define | SYS_VREFCTL_VREF_2_5V
#define | SYS_VREFCTL_VREF_3_0V
#define | SYS_VREFCTL_VREF_AVDD
#define | SYS_USBPHY_USBROLE_STD_USBD
#define | SYS_USBPHY_USBROLE_STD_USBH
#define | SYS_USBPHY_USBROLE_ID_DEPH
#define | SYS_USBPHY_USBROLE_ON_THE_GO
#define | SYS_USBPHY_HSUSBROLE_STD_USBD
#define | SYS_USBPHY_HSUSBROLE_STD_USBH
#define | SYS_USBPHY_HSUSBROLE_ID_DEPH
#define | SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos)
#define | SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos)
#define | SYS_GPA_MFPL_PA0MFP_GPIO
#define | SYS_GPA_MFPL_PA0MFP_SPIM_MOSI
#define | SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0
#define | SYS_GPA_MFPL_PA0MFP_SPI0_MOSI
#define | SYS_GPA_MFPL_PA0MFP_SD1_DAT0
#define | SYS_GPA_MFPL_PA0MFP_SC0_CLK
#define | SYS_GPA_MFPL_PA0MFP_UART0_RXD
#define | SYS_GPA_MFPL_PA0MFP_UART1_nRTS
#define | SYS_GPA_MFPL_PA0MFP_I2C2_SDA
#define | SYS_GPA_MFPL_PA0MFP_CCAP_DATA6
#define | SYS_GPA_MFPL_PA0MFP_BPWM0_CH0
#define | SYS_GPA_MFPL_PA0MFP_EPWM0_CH5
#define | SYS_GPA_MFPL_PA0MFP_DAC0_ST
#define | SYS_GPA_MFPL_PA1MFP_GPIO
#define | SYS_GPA_MFPL_PA1MFP_SPIM_MISO
#define | SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0
#define | SYS_GPA_MFPL_PA1MFP_SPI0_MISO
#define | SYS_GPA_MFPL_PA1MFP_SD1_DAT1
#define | SYS_GPA_MFPL_PA1MFP_SC0_DAT
#define | SYS_GPA_MFPL_PA1MFP_UART0_TXD
#define | SYS_GPA_MFPL_PA1MFP_UART1_nCTS
#define | SYS_GPA_MFPL_PA1MFP_I2C2_SCL
#define | SYS_GPA_MFPL_PA1MFP_CCAP_DATA7
#define | SYS_GPA_MFPL_PA1MFP_BPWM0_CH1
#define | SYS_GPA_MFPL_PA1MFP_EPWM0_CH4
#define | SYS_GPA_MFPL_PA1MFP_DAC1_ST
#define | SYS_GPA_MFPL_PA2MFP_GPIO
#define | SYS_GPA_MFPL_PA2MFP_SPIM_CLK
#define | SYS_GPA_MFPL_PA2MFP_QSPI0_CLK
#define | SYS_GPA_MFPL_PA2MFP_SPI0_CLK
#define | SYS_GPA_MFPL_PA2MFP_SD1_DAT2
#define | SYS_GPA_MFPL_PA2MFP_SC0_RST
#define | SYS_GPA_MFPL_PA2MFP_UART4_RXD
#define | SYS_GPA_MFPL_PA2MFP_UART1_RXD
#define | SYS_GPA_MFPL_PA2MFP_I2C1_SDA
#define | SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS
#define | SYS_GPA_MFPL_PA2MFP_BPWM0_CH2
#define | SYS_GPA_MFPL_PA2MFP_EPWM0_CH3
#define | SYS_GPA_MFPL_PA3MFP_GPIO
#define | SYS_GPA_MFPL_PA3MFP_SPIM_SS
#define | SYS_GPA_MFPL_PA3MFP_QSPI0_SS
#define | SYS_GPA_MFPL_PA3MFP_SPI0_SS
#define | SYS_GPA_MFPL_PA3MFP_SD1_DAT3
#define | SYS_GPA_MFPL_PA3MFP_SC0_PWR
#define | SYS_GPA_MFPL_PA3MFP_UART4_TXD
#define | SYS_GPA_MFPL_PA3MFP_UART1_TXD
#define | SYS_GPA_MFPL_PA3MFP_I2C1_SCL
#define | SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL
#define | SYS_GPA_MFPL_PA3MFP_BPWM0_CH3
#define | SYS_GPA_MFPL_PA3MFP_EPWM0_CH2
#define | SYS_GPA_MFPL_PA3MFP_QEI0_B
#define | SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1
#define | SYS_GPA_MFPL_PA4MFP_GPIO
#define | SYS_GPA_MFPL_PA4MFP_SPIM_D3
#define | SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1
#define | SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK
#define | SYS_GPA_MFPL_PA4MFP_SD1_CLK
#define | SYS_GPA_MFPL_PA4MFP_SC0_nCD
#define | SYS_GPA_MFPL_PA4MFP_UART0_nRTS
#define | SYS_GPA_MFPL_PA4MFP_UART5_RXD
#define | SYS_GPA_MFPL_PA4MFP_I2C0_SDA
#define | SYS_GPA_MFPL_PA4MFP_CAN0_RXD
#define | SYS_GPA_MFPL_PA4MFP_UART0_RXD
#define | SYS_GPA_MFPL_PA4MFP_BPWM0_CH4
#define | SYS_GPA_MFPL_PA4MFP_EPWM0_CH1
#define | SYS_GPA_MFPL_PA4MFP_QEI0_A
#define | SYS_GPA_MFPL_PA5MFP_GPIO
#define | SYS_GPA_MFPL_PA5MFP_SPIM_D2
#define | SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1
#define | SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK
#define | SYS_GPA_MFPL_PA5MFP_SD1_CMD
#define | SYS_GPA_MFPL_PA5MFP_SC2_nCD
#define | SYS_GPA_MFPL_PA5MFP_UART0_nCTS
#define | SYS_GPA_MFPL_PA5MFP_UART5_TXD
#define | SYS_GPA_MFPL_PA5MFP_I2C0_SCL
#define | SYS_GPA_MFPL_PA5MFP_CAN0_TXD
#define | SYS_GPA_MFPL_PA5MFP_UART0_TXD
#define | SYS_GPA_MFPL_PA5MFP_BPWM0_CH5
#define | SYS_GPA_MFPL_PA5MFP_EPWM0_CH0
#define | SYS_GPA_MFPL_PA5MFP_QEI0_INDEX
#define | SYS_GPA_MFPL_PA6MFP_GPIO
#define | SYS_GPA_MFPL_PA6MFP_EBI_AD6
#define | SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR
#define | SYS_GPA_MFPL_PA6MFP_SPI1_SS
#define | SYS_GPA_MFPL_PA6MFP_SD1_nCD
#define | SYS_GPA_MFPL_PA6MFP_SC2_CLK
#define | SYS_GPA_MFPL_PA6MFP_UART0_RXD
#define | SYS_GPA_MFPL_PA6MFP_I2C1_SDA
#define | SYS_GPA_MFPL_PA6MFP_QSPI1_MOSI1
#define | SYS_GPA_MFPL_PA6MFP_EPWM1_CH5
#define | SYS_GPA_MFPL_PA6MFP_BPWM1_CH3
#define | SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT
#define | SYS_GPA_MFPL_PA6MFP_TM3
#define | SYS_GPA_MFPL_PA6MFP_INT0
#define | SYS_GPA_MFPL_PA7MFP_GPIO
#define | SYS_GPA_MFPL_PA7MFP_EBI_AD7
#define | SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV
#define | SYS_GPA_MFPL_PA7MFP_SPI1_CLK
#define | SYS_GPA_MFPL_PA7MFP_SC2_DAT
#define | SYS_GPA_MFPL_PA7MFP_UART0_TXD
#define | SYS_GPA_MFPL_PA7MFP_I2C1_SCL
#define | SYS_GPA_MFPL_PA7MFP_QSPI1_MISO1
#define | SYS_GPA_MFPL_PA7MFP_EPWM1_CH4
#define | SYS_GPA_MFPL_PA7MFP_BPWM1_CH2
#define | SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT
#define | SYS_GPA_MFPL_PA7MFP_TM2
#define | SYS_GPA_MFPL_PA7MFP_INT1
#define | SYS_GPA_MFPH_PA8MFP_GPIO
#define | SYS_GPA_MFPH_PA8MFP_OPA1_P
#define | SYS_GPA_MFPH_PA8MFP_EADC1_CH4
#define | SYS_GPA_MFPH_PA8MFP_EBI_ALE
#define | SYS_GPA_MFPH_PA8MFP_SC2_CLK
#define | SYS_GPA_MFPH_PA8MFP_SPI2_MOSI
#define | SYS_GPA_MFPH_PA8MFP_SD1_DAT0
#define | SYS_GPA_MFPH_PA8MFP_USCI0_CTL1
#define | SYS_GPA_MFPH_PA8MFP_UART1_RXD
#define | SYS_GPA_MFPH_PA8MFP_UART7_RXD
#define | SYS_GPA_MFPH_PA8MFP_BPWM0_CH3
#define | SYS_GPA_MFPH_PA8MFP_QEI1_B
#define | SYS_GPA_MFPH_PA8MFP_ECAP0_IC2
#define | SYS_GPA_MFPH_PA8MFP_TM3_EXT
#define | SYS_GPA_MFPH_PA8MFP_INT4
#define | SYS_GPA_MFPH_PA9MFP_GPIO
#define | SYS_GPA_MFPH_PA9MFP_OPA1_N
#define | SYS_GPA_MFPH_PA9MFP_EADC1_CH5
#define | SYS_GPA_MFPH_PA9MFP_EBI_MCLK
#define | SYS_GPA_MFPH_PA9MFP_SC2_DAT
#define | SYS_GPA_MFPH_PA9MFP_SPI2_MISO
#define | SYS_GPA_MFPH_PA9MFP_SD1_DAT1
#define | SYS_GPA_MFPH_PA9MFP_USCI0_DAT1
#define | SYS_GPA_MFPH_PA9MFP_UART1_TXD
#define | SYS_GPA_MFPH_PA9MFP_UART7_TXD
#define | SYS_GPA_MFPH_PA9MFP_BPWM0_CH2
#define | SYS_GPA_MFPH_PA9MFP_QEI1_A
#define | SYS_GPA_MFPH_PA9MFP_ECAP0_IC1
#define | SYS_GPA_MFPH_PA9MFP_TM2_EXT
#define | SYS_GPA_MFPH_PA9MFP_SWDH_DAT
#define | SYS_GPA_MFPH_PA10MFP_GPIO
#define | SYS_GPA_MFPH_PA10MFP_ACMP1_P0
#define | SYS_GPA_MFPH_PA10MFP_OPA1_O
#define | SYS_GPA_MFPH_PA10MFP_EADC1_CH6
#define | SYS_GPA_MFPH_PA10MFP_EBI_nWR
#define | SYS_GPA_MFPH_PA10MFP_SC2_RST
#define | SYS_GPA_MFPH_PA10MFP_SPI2_CLK
#define | SYS_GPA_MFPH_PA10MFP_SD1_DAT2
#define | SYS_GPA_MFPH_PA10MFP_USCI0_DAT0
#define | SYS_GPA_MFPH_PA10MFP_I2C2_SDA
#define | SYS_GPA_MFPH_PA10MFP_UART6_RXD
#define | SYS_GPA_MFPH_PA10MFP_BPWM0_CH1
#define | SYS_GPA_MFPH_PA10MFP_QEI1_INDEX
#define | SYS_GPA_MFPH_PA10MFP_ECAP0_IC0
#define | SYS_GPA_MFPH_PA10MFP_TM1_EXT
#define | SYS_GPA_MFPH_PA10MFP_DAC0_ST
#define | SYS_GPA_MFPH_PA10MFP_SWDH_CLK
#define | SYS_GPA_MFPH_PA11MFP_GPIO
#define | SYS_GPA_MFPH_PA11MFP_ACMP0_P0
#define | SYS_GPA_MFPH_PA11MFP_EADC1_CH7
#define | SYS_GPA_MFPH_PA11MFP_EBI_nRD
#define | SYS_GPA_MFPH_PA11MFP_SC2_PWR
#define | SYS_GPA_MFPH_PA11MFP_SPI2_SS
#define | SYS_GPA_MFPH_PA11MFP_SD1_DAT3
#define | SYS_GPA_MFPH_PA11MFP_USCI0_CLK
#define | SYS_GPA_MFPH_PA11MFP_I2C2_SCL
#define | SYS_GPA_MFPH_PA11MFP_UART6_TXD
#define | SYS_GPA_MFPH_PA11MFP_BPWM0_CH0
#define | SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT
#define | SYS_GPA_MFPH_PA11MFP_TM0_EXT
#define | SYS_GPA_MFPH_PA11MFP_DAC1_ST
#define | SYS_GPA_MFPH_PA12MFP_GPIO
#define | SYS_GPA_MFPH_PA12MFP_I2S0_BCLK
#define | SYS_GPA_MFPH_PA12MFP_UART4_TXD
#define | SYS_GPA_MFPH_PA12MFP_I2C1_SCL
#define | SYS_GPA_MFPH_PA12MFP_SPI2_SS
#define | SYS_GPA_MFPH_PA12MFP_CAN0_TXD
#define | SYS_GPA_MFPH_PA12MFP_SC2_PWR
#define | SYS_GPA_MFPH_PA12MFP_BPWM1_CH2
#define | SYS_GPA_MFPH_PA12MFP_QEI1_INDEX
#define | SYS_GPA_MFPH_PA12MFP_USB_VBUS
#define | SYS_GPA_MFPH_PA13MFP_GPIO
#define | SYS_GPA_MFPH_PA13MFP_I2S0_MCLK
#define | SYS_GPA_MFPH_PA13MFP_UART4_RXD
#define | SYS_GPA_MFPH_PA13MFP_I2C1_SDA
#define | SYS_GPA_MFPH_PA13MFP_SPI2_CLK
#define | SYS_GPA_MFPH_PA13MFP_CAN0_RXD
#define | SYS_GPA_MFPH_PA13MFP_SC2_RST
#define | SYS_GPA_MFPH_PA13MFP_BPWM1_CH3
#define | SYS_GPA_MFPH_PA13MFP_QEI1_A
#define | SYS_GPA_MFPH_PA13MFP_USB_D_N
#define | SYS_GPA_MFPH_PA14MFP_GPIO
#define | SYS_GPA_MFPH_PA14MFP_I2S0_DI
#define | SYS_GPA_MFPH_PA14MFP_UART0_TXD
#define | SYS_GPA_MFPH_PA14MFP_SPI2_MISO
#define | SYS_GPA_MFPH_PA14MFP_I2C2_SCL
#define | SYS_GPA_MFPH_PA14MFP_SC2_DAT
#define | SYS_GPA_MFPH_PA14MFP_BPWM1_CH4
#define | SYS_GPA_MFPH_PA14MFP_QEI1_B
#define | SYS_GPA_MFPH_PA14MFP_USB_D_P
#define | SYS_GPA_MFPH_PA15MFP_GPIO
#define | SYS_GPA_MFPH_PA15MFP_I2S0_DO
#define | SYS_GPA_MFPH_PA15MFP_UART0_RXD
#define | SYS_GPA_MFPH_PA15MFP_SPI2_MOSI
#define | SYS_GPA_MFPH_PA15MFP_I2C2_SDA
#define | SYS_GPA_MFPH_PA15MFP_SC2_CLK
#define | SYS_GPA_MFPH_PA15MFP_BPWM1_CH5
#define | SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN
#define | SYS_GPA_MFPH_PA15MFP_USB_OTG_ID
#define | SYS_GPB_MFPL_PB0MFP_GPIO
#define | SYS_GPB_MFPL_PB0MFP_EADC0_CH0
#define | SYS_GPB_MFPL_PB0MFP_EADC1_CH8
#define | SYS_GPB_MFPL_PB0MFP_OPA0_P
#define | SYS_GPB_MFPL_PB0MFP_EBI_ADR9
#define | SYS_GPB_MFPL_PB0MFP_SD0_CMD
#define | SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK
#define | SYS_GPB_MFPL_PB0MFP_UART2_RXD
#define | SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK
#define | SYS_GPB_MFPL_PB0MFP_I2C1_SDA
#define | SYS_GPB_MFPL_PB0MFP_EPWM0_CH5
#define | SYS_GPB_MFPL_PB0MFP_EPWM1_CH5
#define | SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1
#define | SYS_GPB_MFPL_PB1MFP_GPIO
#define | SYS_GPB_MFPL_PB1MFP_EADC0_CH1
#define | SYS_GPB_MFPL_PB1MFP_OPA0_N
#define | SYS_GPB_MFPL_PB1MFP_EADC1_CH9
#define | SYS_GPB_MFPL_PB1MFP_EBI_ADR8
#define | SYS_GPB_MFPL_PB1MFP_SD0_CLK
#define | SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR
#define | SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK
#define | SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK
#define | SYS_GPB_MFPL_PB1MFP_UART2_TXD
#define | SYS_GPB_MFPL_PB1MFP_USCI1_CLK
#define | SYS_GPB_MFPL_PB1MFP_I2C1_SCL
#define | SYS_GPB_MFPL_PB1MFP_I2S0_LRCK
#define | SYS_GPB_MFPL_PB1MFP_EPWM0_CH4
#define | SYS_GPB_MFPL_PB1MFP_EPWM1_CH4
#define | SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0
#define | SYS_GPB_MFPL_PB2MFP_GPIO
#define | SYS_GPB_MFPL_PB2MFP_ACMP0_P1
#define | SYS_GPB_MFPL_PB2MFP_EADC0_CH2
#define | SYS_GPB_MFPL_PB2MFP_OPA0_O
#define | SYS_GPB_MFPL_PB2MFP_EADC1_CH10
#define | SYS_GPB_MFPL_PB2MFP_EBI_ADR3
#define | SYS_GPB_MFPL_PB2MFP_SD0_DAT0
#define | SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV
#define | SYS_GPB_MFPL_PB2MFP_SPI1_SS
#define | SYS_GPB_MFPL_PB2MFP_UART1_RXD
#define | SYS_GPB_MFPL_PB2MFP_UART5_nCTS
#define | SYS_GPB_MFPL_PB2MFP_USCI1_DAT0
#define | SYS_GPB_MFPL_PB2MFP_SC0_PWR
#define | SYS_GPB_MFPL_PB2MFP_I2S0_DO
#define | SYS_GPB_MFPL_PB2MFP_EPWM0_CH3
#define | SYS_GPB_MFPL_PB2MFP_I2C1_SDA (0x0CUL<<SYS_GPB_MFPL_PB2MFP_Pos)
#define | SYS_GPB_MFPL_PB2MFP_TM3
#define | SYS_GPB_MFPL_PB2MFP_INT3
#define | SYS_GPB_MFPL_PB3MFP_GPIO
#define | SYS_GPB_MFPL_PB3MFP_ACMP0_N
#define | SYS_GPB_MFPL_PB3MFP_EADC0_CH3
#define | SYS_GPB_MFPL_PB3MFP_EADC1_CH11
#define | SYS_GPB_MFPL_PB3MFP_EBI_ADR2
#define | SYS_GPB_MFPL_PB3MFP_SD0_DAT1
#define | SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1
#define | SYS_GPB_MFPL_PB3MFP_SPI1_CLK
#define | SYS_GPB_MFPL_PB3MFP_UART1_TXD
#define | SYS_GPB_MFPL_PB3MFP_UART5_nRTS
#define | SYS_GPB_MFPL_PB3MFP_USCI1_DAT1
#define | SYS_GPB_MFPL_PB3MFP_SC0_RST
#define | SYS_GPB_MFPL_PB3MFP_I2S0_DI
#define | SYS_GPB_MFPL_PB3MFP_EPWM0_CH2
#define | SYS_GPB_MFPL_PB3MFP_I2C1_SCL (0x0CUL<<SYS_GPB_MFPL_PB3MFP_Pos)
#define | SYS_GPB_MFPL_PB3MFP_TM2
#define | SYS_GPB_MFPL_PB3MFP_INT2
#define | SYS_GPB_MFPL_PB4MFP_GPIO
#define | SYS_GPB_MFPL_PB4MFP_ACMP1_P1
#define | SYS_GPB_MFPL_PB4MFP_EADC0_CH4
#define | SYS_GPB_MFPL_PB4MFP_EBI_ADR1
#define | SYS_GPB_MFPL_PB4MFP_SD0_DAT2
#define | SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0
#define | SYS_GPB_MFPL_PB4MFP_SPI1_MOSI
#define | SYS_GPB_MFPL_PB4MFP_I2C0_SDA
#define | SYS_GPB_MFPL_PB4MFP_UART5_RXD
#define | SYS_GPB_MFPL_PB4MFP_USCI1_CTL1
#define | SYS_GPB_MFPL_PB4MFP_SC0_DAT
#define | SYS_GPB_MFPL_PB4MFP_I2S0_MCLK
#define | SYS_GPB_MFPL_PB4MFP_EPWM0_CH1
#define | SYS_GPB_MFPL_PB4MFP_UART2_RXD
#define | SYS_GPB_MFPL_PB4MFP_TM1
#define | SYS_GPB_MFPL_PB4MFP_INT1
#define | SYS_GPB_MFPL_PB5MFP_GPIO
#define | SYS_GPB_MFPL_PB5MFP_ACMP1_N
#define | SYS_GPB_MFPL_PB5MFP_EADC0_CH5
#define | SYS_GPB_MFPL_PB5MFP_EBI_ADR0
#define | SYS_GPB_MFPL_PB5MFP_SD0_DAT3
#define | SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK
#define | SYS_GPB_MFPL_PB5MFP_SPI1_MISO
#define | SYS_GPB_MFPL_PB5MFP_I2C0_SCL
#define | SYS_GPB_MFPL_PB5MFP_UART5_TXD
#define | SYS_GPB_MFPL_PB5MFP_USCI1_CTL0
#define | SYS_GPB_MFPL_PB5MFP_SC0_CLK
#define | SYS_GPB_MFPL_PB5MFP_I2S0_BCLK
#define | SYS_GPB_MFPL_PB5MFP_EPWM0_CH0
#define | SYS_GPB_MFPL_PB5MFP_UART2_TXD
#define | SYS_GPB_MFPL_PB5MFP_TM0
#define | SYS_GPB_MFPL_PB5MFP_INT0
#define | SYS_GPB_MFPL_PB6MFP_GPIO
#define | SYS_GPB_MFPL_PB6MFP_EADC0_CH6
#define | SYS_GPB_MFPL_PB6MFP_EBI_nWRH
#define | SYS_GPB_MFPL_PB6MFP_EMAC_PPS
#define | SYS_GPB_MFPL_PB6MFP_USCI1_DAT1
#define | SYS_GPB_MFPL_PB6MFP_CAN1_RXD
#define | SYS_GPB_MFPL_PB6MFP_UART1_RXD
#define | SYS_GPB_MFPL_PB6MFP_SD1_CLK
#define | SYS_GPB_MFPL_PB6MFP_EBI_nCS1
#define | SYS_GPB_MFPL_PB6MFP_BPWM1_CH5
#define | SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1
#define | SYS_GPB_MFPL_PB6MFP_EPWM1_CH5
#define | SYS_GPB_MFPL_PB6MFP_INT4
#define | SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN
#define | SYS_GPB_MFPL_PB6MFP_ACMP1_O
#define | SYS_GPB_MFPL_PB7MFP_GPIO
#define | SYS_GPB_MFPL_PB7MFP_EADC0_CH7
#define | SYS_GPB_MFPL_PB7MFP_EBI_nWRL
#define | SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN
#define | SYS_GPB_MFPL_PB7MFP_USCI1_DAT0
#define | SYS_GPB_MFPL_PB7MFP_CAN1_TXD
#define | SYS_GPB_MFPL_PB7MFP_UART1_TXD
#define | SYS_GPB_MFPL_PB7MFP_SD1_CMD
#define | SYS_GPB_MFPL_PB7MFP_EBI_nCS0
#define | SYS_GPB_MFPL_PB7MFP_BPWM1_CH4
#define | SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0
#define | SYS_GPB_MFPL_PB7MFP_EPWM1_CH4
#define | SYS_GPB_MFPL_PB7MFP_INT5
#define | SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST
#define | SYS_GPB_MFPL_PB7MFP_ACMP0_O
#define | SYS_GPB_MFPH_PB8MFP_GPIO
#define | SYS_GPB_MFPH_PB8MFP_EADC0_CH8
#define | SYS_GPB_MFPH_PB8MFP_EBI_ADR19
#define | SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1
#define | SYS_GPB_MFPH_PB8MFP_USCI1_CLK
#define | SYS_GPB_MFPH_PB8MFP_UART0_RXD
#define | SYS_GPB_MFPH_PB8MFP_UART1_nRTS
#define | SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS
#define | SYS_GPB_MFPH_PB8MFP_UART7_RXD
#define | SYS_GPB_MFPH_PB8MFP_I2C0_SDA
#define | SYS_GPB_MFPH_PB8MFP_BPWM1_CH3
#define | SYS_GPB_MFPH_PB8MFP_SPI3_MOSI
#define | SYS_GPB_MFPH_PB8MFP_CAN2_RXD
#define | SYS_GPB_MFPH_PB8MFP_INT6
#define | SYS_GPB_MFPH_PB9MFP_GPIO
#define | SYS_GPB_MFPH_PB9MFP_EADC0_CH9
#define | SYS_GPB_MFPH_PB9MFP_EBI_ADR18
#define | SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0
#define | SYS_GPB_MFPH_PB9MFP_USCI1_CTL1
#define | SYS_GPB_MFPH_PB9MFP_UART0_TXD
#define | SYS_GPB_MFPH_PB9MFP_UART1_nCTS
#define | SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL
#define | SYS_GPB_MFPH_PB9MFP_UART7_TXD
#define | SYS_GPB_MFPH_PB9MFP_I2C0_SCL
#define | SYS_GPB_MFPH_PB9MFP_BPWM1_CH2
#define | SYS_GPB_MFPH_PB9MFP_SPI3_MISO
#define | SYS_GPB_MFPH_PB9MFP_CAN2_TXD
#define | SYS_GPB_MFPH_PB9MFP_INT7
#define | SYS_GPB_MFPH_PB9MFP_CCAP_HSYNC
#define | SYS_GPB_MFPH_PB10MFP_GPIO
#define | SYS_GPB_MFPH_PB10MFP_EADC0_CH10
#define | SYS_GPB_MFPH_PB10MFP_EBI_ADR17
#define | SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO
#define | SYS_GPB_MFPH_PB10MFP_USCI1_CTL0
#define | SYS_GPB_MFPH_PB10MFP_UART0_nRTS
#define | SYS_GPB_MFPH_PB10MFP_UART4_RXD
#define | SYS_GPB_MFPH_PB10MFP_I2C1_SDA
#define | SYS_GPB_MFPH_PB10MFP_CAN0_RXD
#define | SYS_GPB_MFPH_PB10MFP_BPWM1_CH1
#define | SYS_GPB_MFPH_PB10MFP_SPI3_SS
#define | SYS_GPB_MFPH_PB10MFP_CCAP_VSYNC
#define | SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN
#define | SYS_GPB_MFPH_PB11MFP_GPIO
#define | SYS_GPB_MFPH_PB11MFP_EADC0_CH11
#define | SYS_GPB_MFPH_PB11MFP_EBI_ADR16
#define | SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC
#define | SYS_GPB_MFPH_PB11MFP_UART0_nCTS
#define | SYS_GPB_MFPH_PB11MFP_UART4_TXD
#define | SYS_GPB_MFPH_PB11MFP_I2C1_SCL
#define | SYS_GPB_MFPH_PB11MFP_CAN0_TXD
#define | SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK
#define | SYS_GPB_MFPH_PB11MFP_BPWM1_CH0
#define | SYS_GPB_MFPH_PB11MFP_SPI3_CLK
#define | SYS_GPB_MFPH_PB11MFP_CCAP_SFIELD
#define | SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST
#define | SYS_GPB_MFPH_PB12MFP_GPIO
#define | SYS_GPB_MFPH_PB12MFP_ACMP0_P2
#define | SYS_GPB_MFPH_PB12MFP_ACMP1_P2
#define | SYS_GPB_MFPH_PB12MFP_DAC0_OUT
#define | SYS_GPB_MFPH_PB12MFP_EADC0_CH12
#define | SYS_GPB_MFPH_PB12MFP_EADC1_CH12
#define | SYS_GPB_MFPH_PB12MFP_EBI_AD15
#define | SYS_GPB_MFPH_PB12MFP_SC1_CLK
#define | SYS_GPB_MFPH_PB12MFP_SPI0_MOSI
#define | SYS_GPB_MFPH_PB12MFP_USCI0_CLK
#define | SYS_GPB_MFPH_PB12MFP_UART0_RXD
#define | SYS_GPB_MFPH_PB12MFP_UART3_nCTS
#define | SYS_GPB_MFPH_PB12MFP_I2C2_SDA
#define | SYS_GPB_MFPH_PB12MFP_SD0_nCD
#define | SYS_GPB_MFPH_PB12MFP_CCAP_SCLK
#define | SYS_GPB_MFPH_PB12MFP_EPWM1_CH3
#define | SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3
#define | SYS_GPB_MFPH_PB12MFP_TM3_EXT
#define | SYS_GPB_MFPH_PB13MFP_GPIO
#define | SYS_GPB_MFPH_PB13MFP_ACMP0_P3
#define | SYS_GPB_MFPH_PB13MFP_ACMP1_P3
#define | SYS_GPB_MFPH_PB13MFP_DAC1_OUT
#define | SYS_GPB_MFPH_PB13MFP_EADC0_CH13
#define | SYS_GPB_MFPH_PB13MFP_EADC1_CH13
#define | SYS_GPB_MFPH_PB13MFP_EBI_AD14
#define | SYS_GPB_MFPH_PB13MFP_SC1_DAT
#define | SYS_GPB_MFPH_PB13MFP_SPI0_MISO
#define | SYS_GPB_MFPH_PB13MFP_USCI0_DAT0
#define | SYS_GPB_MFPH_PB13MFP_UART0_TXD
#define | SYS_GPB_MFPH_PB13MFP_UART3_nRTS
#define | SYS_GPB_MFPH_PB13MFP_I2C2_SCL
#define | SYS_GPB_MFPH_PB13MFP_CCAP_PIXCLK
#define | SYS_GPB_MFPH_PB13MFP_EPWM1_CH2
#define | SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2
#define | SYS_GPB_MFPH_PB13MFP_TM2_EXT
#define | SYS_GPB_MFPH_PB14MFP_GPIO
#define | SYS_GPB_MFPH_PB14MFP_EADC0_CH14
#define | SYS_GPB_MFPH_PB14MFP_EADC1_CH14
#define | SYS_GPB_MFPH_PB14MFP_EBI_AD13
#define | SYS_GPB_MFPH_PB14MFP_SC1_RST
#define | SYS_GPB_MFPH_PB14MFP_SPI0_CLK
#define | SYS_GPB_MFPH_PB14MFP_USCI0_DAT1
#define | SYS_GPB_MFPH_PB14MFP_UART0_nRTS
#define | SYS_GPB_MFPH_PB14MFP_UART3_RXD
#define | SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS
#define | SYS_GPB_MFPH_PB14MFP_EPWM1_CH1
#define | SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1
#define | SYS_GPB_MFPH_PB14MFP_TM1_EXT
#define | SYS_GPB_MFPH_PB14MFP_CLKO
#define | SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST (0x0FUL<<SYS_GPB_MFPH_PB14MFP_Pos)
#define | SYS_GPB_MFPH_PB15MFP_GPIO
#define | SYS_GPB_MFPH_PB15MFP_EADC0_CH15
#define | SYS_GPB_MFPH_PB15MFP_EADC1_CH15
#define | SYS_GPB_MFPH_PB15MFP_EBI_AD12
#define | SYS_GPB_MFPH_PB15MFP_SC1_PWR
#define | SYS_GPB_MFPH_PB15MFP_SPI0_SS
#define | SYS_GPB_MFPH_PB15MFP_USCI0_CTL1
#define | SYS_GPB_MFPH_PB15MFP_UART0_nCTS
#define | SYS_GPB_MFPH_PB15MFP_UART3_TXD
#define | SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL
#define | SYS_GPB_MFPH_PB15MFP_EPWM0_BRAKE1
#define | SYS_GPB_MFPH_PB15MFP_EPWM1_CH0
#define | SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0
#define | SYS_GPB_MFPH_PB15MFP_TM0_EXT
#define | SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN
#define | SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN
#define | SYS_GPC_MFPL_PC0MFP_GPIO
#define | SYS_GPC_MFPL_PC0MFP_EBI_AD0
#define | SYS_GPC_MFPL_PC0MFP_SPIM_MOSI
#define | SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0
#define | SYS_GPC_MFPL_PC0MFP_SC1_CLK
#define | SYS_GPC_MFPL_PC0MFP_I2S0_LRCK
#define | SYS_GPC_MFPL_PC0MFP_SPI1_SS
#define | SYS_GPC_MFPL_PC0MFP_UART2_RXD
#define | SYS_GPC_MFPL_PC0MFP_I2C0_SDA
#define | SYS_GPC_MFPL_PC0MFP_CAN2_RXD
#define | SYS_GPC_MFPL_PC0MFP_EPWM1_CH5
#define | SYS_GPC_MFPL_PC0MFP_CCAP_DATA0
#define | SYS_GPC_MFPL_PC0MFP_ACMP1_O
#define | SYS_GPC_MFPL_PC0MFP_EADC1_ST
#define | SYS_GPC_MFPL_PC1MFP_GPIO
#define | SYS_GPC_MFPL_PC1MFP_EBI_AD1
#define | SYS_GPC_MFPL_PC1MFP_SPIM_MISO
#define | SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0
#define | SYS_GPC_MFPL_PC1MFP_SC1_DAT
#define | SYS_GPC_MFPL_PC1MFP_I2S0_DO
#define | SYS_GPC_MFPL_PC1MFP_SPI1_CLK
#define | SYS_GPC_MFPL_PC1MFP_UART2_TXD
#define | SYS_GPC_MFPL_PC1MFP_I2C0_SCL
#define | SYS_GPC_MFPL_PC1MFP_CAN2_TXD
#define | SYS_GPC_MFPL_PC1MFP_EPWM1_CH4
#define | SYS_GPC_MFPL_PC1MFP_CCAP_DATA1
#define | SYS_GPC_MFPL_PC1MFP_ACMP0_O
#define | SYS_GPC_MFPL_PC1MFP_EADC0_ST
#define | SYS_GPC_MFPL_PC2MFP_GPIO
#define | SYS_GPC_MFPL_PC2MFP_EBI_AD2
#define | SYS_GPC_MFPL_PC2MFP_SPIM_CLK
#define | SYS_GPC_MFPL_PC2MFP_QSPI0_CLK
#define | SYS_GPC_MFPL_PC2MFP_SC1_RST
#define | SYS_GPC_MFPL_PC2MFP_I2S0_DI
#define | SYS_GPC_MFPL_PC2MFP_SPI1_MOSI
#define | SYS_GPC_MFPL_PC2MFP_UART2_nCTS
#define | SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS
#define | SYS_GPC_MFPL_PC2MFP_CAN1_RXD
#define | SYS_GPC_MFPL_PC2MFP_UART3_RXD
#define | SYS_GPC_MFPL_PC2MFP_EPWM1_CH3
#define | SYS_GPC_MFPL_PC2MFP_CCAP_DATA2
#define | SYS_GPC_MFPL_PC2MFP_QSPI1_MOSI0
#define | SYS_GPC_MFPL_PC3MFP_GPIO
#define | SYS_GPC_MFPL_PC3MFP_EBI_AD3
#define | SYS_GPC_MFPL_PC3MFP_SPIM_SS
#define | SYS_GPC_MFPL_PC3MFP_QSPI0_SS
#define | SYS_GPC_MFPL_PC3MFP_SC1_PWR
#define | SYS_GPC_MFPL_PC3MFP_I2S0_MCLK
#define | SYS_GPC_MFPL_PC3MFP_SPI1_MISO
#define | SYS_GPC_MFPL_PC3MFP_UART2_nRTS
#define | SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL
#define | SYS_GPC_MFPL_PC3MFP_CAN1_TXD
#define | SYS_GPC_MFPL_PC3MFP_UART3_TXD
#define | SYS_GPC_MFPL_PC3MFP_EPWM1_CH2
#define | SYS_GPC_MFPL_PC3MFP_CCAP_DATA3
#define | SYS_GPC_MFPL_PC3MFP_QSPI1_MISO0
#define | SYS_GPC_MFPL_PC4MFP_GPIO
#define | SYS_GPC_MFPL_PC4MFP_EBI_AD4
#define | SYS_GPC_MFPL_PC4MFP_SPIM_D3
#define | SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1
#define | SYS_GPC_MFPL_PC4MFP_SC1_nCD
#define | SYS_GPC_MFPL_PC4MFP_I2S0_BCLK
#define | SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK
#define | SYS_GPC_MFPL_PC4MFP_UART2_RXD
#define | SYS_GPC_MFPL_PC4MFP_I2C1_SDA
#define | SYS_GPC_MFPL_PC4MFP_CAN0_RXD
#define | SYS_GPC_MFPL_PC4MFP_UART4_RXD
#define | SYS_GPC_MFPL_PC4MFP_EPWM1_CH1
#define | SYS_GPC_MFPL_PC4MFP_CCAP_DATA4
#define | SYS_GPC_MFPL_PC4MFP_QSPI1_CLK
#define | SYS_GPC_MFPL_PC5MFP_GPIO
#define | SYS_GPC_MFPL_PC5MFP_EBI_AD5
#define | SYS_GPC_MFPL_PC5MFP_SPIM_D2
#define | SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1
#define | SYS_GPC_MFPL_PC5MFP_UART2_TXD
#define | SYS_GPC_MFPL_PC5MFP_I2C1_SCL
#define | SYS_GPC_MFPL_PC5MFP_CAN0_TXD
#define | SYS_GPC_MFPL_PC5MFP_UART4_TXD
#define | SYS_GPC_MFPL_PC5MFP_EPWM1_CH0
#define | SYS_GPC_MFPL_PC5MFP_CCAP_DATA5
#define | SYS_GPC_MFPL_PC5MFP_QSPI1_SS
#define | SYS_GPC_MFPL_PC6MFP_GPIO
#define | SYS_GPC_MFPL_PC6MFP_EBI_AD8
#define | SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1
#define | SYS_GPC_MFPL_PC6MFP_SPI1_MOSI
#define | SYS_GPC_MFPL_PC6MFP_UART4_RXD
#define | SYS_GPC_MFPL_PC6MFP_SC2_RST
#define | SYS_GPC_MFPL_PC6MFP_UART0_nRTS
#define | SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS
#define | SYS_GPC_MFPL_PC6MFP_UART6_RXD
#define | SYS_GPC_MFPL_PC6MFP_EPWM1_CH3
#define | SYS_GPC_MFPL_PC6MFP_BPWM1_CH1
#define | SYS_GPC_MFPL_PC6MFP_TM1
#define | SYS_GPC_MFPL_PC6MFP_INT2
#define | SYS_GPC_MFPL_PC7MFP_GPIO
#define | SYS_GPC_MFPL_PC7MFP_EBI_AD9
#define | SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0
#define | SYS_GPC_MFPL_PC7MFP_SPI1_MISO
#define | SYS_GPC_MFPL_PC7MFP_UART4_TXD
#define | SYS_GPC_MFPL_PC7MFP_SC2_PWR
#define | SYS_GPC_MFPL_PC7MFP_UART0_nCTS
#define | SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL
#define | SYS_GPC_MFPL_PC7MFP_UART6_TXD
#define | SYS_GPC_MFPL_PC7MFP_EPWM1_CH2
#define | SYS_GPC_MFPL_PC7MFP_BPWM1_CH0
#define | SYS_GPC_MFPL_PC7MFP_TM0
#define | SYS_GPC_MFPL_PC7MFP_INT3
#define | SYS_GPC_MFPH_PC8MFP_GPIO
#define | SYS_GPC_MFPH_PC8MFP_EBI_ADR16
#define | SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK
#define | SYS_GPC_MFPH_PC8MFP_I2C0_SDA
#define | SYS_GPC_MFPH_PC8MFP_UART4_nCTS
#define | SYS_GPC_MFPH_PC8MFP_UART1_RXD
#define | SYS_GPC_MFPH_PC8MFP_EPWM1_CH1
#define | SYS_GPC_MFPH_PC8MFP_BPWM1_CH4
#define | SYS_GPC_MFPH_PC9MFP_GPIO
#define | SYS_GPC_MFPH_PC9MFP_EBI_ADR7
#define | SYS_GPC_MFPH_PC9MFP_UART6_nCTS
#define | SYS_GPC_MFPH_PC9MFP_SPI3_SS
#define | SYS_GPC_MFPH_PC9MFP_UART3_RXD
#define | SYS_GPC_MFPH_PC9MFP_CAN1_RXD
#define | SYS_GPC_MFPH_PC9MFP_EPWM1_CH3
#define | SYS_GPC_MFPH_PC9MFP_EADC1_ST
#define | SYS_GPC_MFPH_PC10MFP_GPIO
#define | SYS_GPC_MFPH_PC10MFP_EBI_ADR6
#define | SYS_GPC_MFPH_PC10MFP_UART6_nRTS
#define | SYS_GPC_MFPH_PC10MFP_SPI3_CLK
#define | SYS_GPC_MFPH_PC10MFP_UART3_TXD
#define | SYS_GPC_MFPH_PC10MFP_CAN1_TXD
#define | SYS_GPC_MFPH_PC10MFP_ECAP1_IC0
#define | SYS_GPC_MFPH_PC10MFP_EPWM1_CH2
#define | SYS_GPC_MFPH_PC10MFP_EADC1_ST
#define | SYS_GPC_MFPH_PC11MFP_GPIO
#define | SYS_GPC_MFPH_PC11MFP_EBI_ADR5
#define | SYS_GPC_MFPH_PC11MFP_UART0_RXD
#define | SYS_GPC_MFPH_PC11MFP_I2C0_SDA
#define | SYS_GPC_MFPH_PC11MFP_UART6_RXD
#define | SYS_GPC_MFPH_PC11MFP_SPI3_MOSI
#define | SYS_GPC_MFPH_PC11MFP_ECAP1_IC1
#define | SYS_GPC_MFPH_PC11MFP_EPWM1_CH1
#define | SYS_GPC_MFPH_PC11MFP_ACMP1_O
#define | SYS_GPC_MFPH_PC12MFP_GPIO
#define | SYS_GPC_MFPH_PC12MFP_EBI_ADR4
#define | SYS_GPC_MFPH_PC12MFP_UART0_TXD
#define | SYS_GPC_MFPH_PC12MFP_I2C0_SCL
#define | SYS_GPC_MFPH_PC12MFP_UART6_TXD
#define | SYS_GPC_MFPH_PC12MFP_SPI3_MISO
#define | SYS_GPC_MFPH_PC12MFP_SC0_nCD
#define | SYS_GPC_MFPH_PC12MFP_ECAP1_IC2
#define | SYS_GPC_MFPH_PC12MFP_EPWM1_CH0
#define | SYS_GPC_MFPH_PC12MFP_ACMP0_O
#define | SYS_GPC_MFPH_PC13MFP_GPIO
#define | SYS_GPC_MFPH_PC13MFP_EADC1_CH3
#define | SYS_GPC_MFPH_PC13MFP_EBI_ADR10
#define | SYS_GPC_MFPH_PC13MFP_SC2_nCD
#define | SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK
#define | SYS_GPC_MFPH_PC13MFP_CAN1_TXD
#define | SYS_GPC_MFPH_PC13MFP_USCI0_CTL0
#define | SYS_GPC_MFPH_PC13MFP_UART2_TXD
#define | SYS_GPC_MFPH_PC13MFP_BPWM0_CH4
#define | SYS_GPC_MFPH_PC13MFP_CLKO
#define | SYS_GPC_MFPH_PC13MFP_EADC0_ST
#define | SYS_GPC_MFPH_PC14MFP_GPIO
#define | SYS_GPC_MFPH_PC14MFP_EBI_AD11
#define | SYS_GPC_MFPH_PC14MFP_SC1_nCD
#define | SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK
#define | SYS_GPC_MFPH_PC14MFP_USCI0_CTL0
#define | SYS_GPC_MFPH_PC14MFP_QSPI0_CLK
#define | SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN
#define | SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK
#define | SYS_GPC_MFPH_PC14MFP_TM1
#define | SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST
#define | SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST
#define | SYS_GPD_MFPL_PD0MFP_GPIO
#define | SYS_GPD_MFPL_PD0MFP_EBI_AD13
#define | SYS_GPD_MFPL_PD0MFP_USCI0_CLK
#define | SYS_GPD_MFPL_PD0MFP_SPI0_MOSI
#define | SYS_GPD_MFPL_PD0MFP_UART3_RXD
#define | SYS_GPD_MFPL_PD0MFP_I2C2_SDA
#define | SYS_GPD_MFPL_PD0MFP_SC2_CLK
#define | SYS_GPD_MFPL_PD0MFP_TM2
#define | SYS_GPD_MFPL_PD1MFP_GPIO
#define | SYS_GPD_MFPL_PD1MFP_EBI_AD12
#define | SYS_GPD_MFPL_PD1MFP_USCI0_DAT0
#define | SYS_GPD_MFPL_PD1MFP_SPI0_MISO
#define | SYS_GPD_MFPL_PD1MFP_UART3_TXD
#define | SYS_GPD_MFPL_PD1MFP_I2C2_SCL
#define | SYS_GPD_MFPL_PD1MFP_SC2_DAT
#define | SYS_GPD_MFPL_PD2MFP_GPIO
#define | SYS_GPD_MFPL_PD2MFP_EBI_AD11
#define | SYS_GPD_MFPL_PD2MFP_USCI0_DAT1
#define | SYS_GPD_MFPL_PD2MFP_SPI0_CLK
#define | SYS_GPD_MFPL_PD2MFP_UART3_nCTS
#define | SYS_GPD_MFPL_PD2MFP_SC2_RST
#define | SYS_GPD_MFPL_PD2MFP_UART0_RXD
#define | SYS_GPD_MFPL_PD3MFP_GPIO
#define | SYS_GPD_MFPL_PD3MFP_EBI_AD10
#define | SYS_GPD_MFPL_PD3MFP_USCI0_CTL1
#define | SYS_GPD_MFPL_PD3MFP_SPI0_SS
#define | SYS_GPD_MFPL_PD3MFP_UART3_nRTS
#define | SYS_GPD_MFPL_PD3MFP_USCI1_CTL0
#define | SYS_GPD_MFPL_PD3MFP_SC2_PWR
#define | SYS_GPD_MFPL_PD3MFP_SC1_nCD
#define | SYS_GPD_MFPL_PD3MFP_UART0_TXD
#define | SYS_GPD_MFPL_PD4MFP_GPIO
#define | SYS_GPD_MFPL_PD4MFP_USCI0_CTL0
#define | SYS_GPD_MFPL_PD4MFP_I2C1_SDA
#define | SYS_GPD_MFPL_PD4MFP_SPI1_SS
#define | SYS_GPD_MFPL_PD4MFP_USCI1_CTL1
#define | SYS_GPD_MFPL_PD4MFP_SC1_CLK
#define | SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST
#define | SYS_GPD_MFPL_PD5MFP_GPIO
#define | SYS_GPD_MFPL_PD5MFP_I2C1_SCL
#define | SYS_GPD_MFPL_PD5MFP_SPI1_CLK
#define | SYS_GPD_MFPL_PD5MFP_USCI1_DAT0
#define | SYS_GPD_MFPL_PD5MFP_SC1_DAT
#define | SYS_GPD_MFPL_PD6MFP_GPIO
#define | SYS_GPD_MFPL_PD6MFP_UART1_RXD
#define | SYS_GPD_MFPL_PD6MFP_I2C0_SDA
#define | SYS_GPD_MFPL_PD6MFP_SPI1_MOSI
#define | SYS_GPD_MFPL_PD6MFP_USCI1_DAT1
#define | SYS_GPD_MFPL_PD6MFP_SC1_RST
#define | SYS_GPD_MFPL_PD7MFP_GPIO
#define | SYS_GPD_MFPL_PD7MFP_UART1_TXD
#define | SYS_GPD_MFPL_PD7MFP_I2C0_SCL
#define | SYS_GPD_MFPL_PD7MFP_SPI1_MISO
#define | SYS_GPD_MFPL_PD7MFP_USCI1_CLK
#define | SYS_GPD_MFPL_PD7MFP_SC1_PWR
#define | SYS_GPD_MFPH_PD8MFP_GPIO
#define | SYS_GPD_MFPH_PD8MFP_EBI_AD6
#define | SYS_GPD_MFPH_PD8MFP_I2C2_SDA
#define | SYS_GPD_MFPH_PD8MFP_UART2_nRTS
#define | SYS_GPD_MFPH_PD8MFP_UART7_RXD
#define | SYS_GPD_MFPH_PD8MFP_CAN2_RXD
#define | SYS_GPD_MFPH_PD9MFP_GPIO
#define | SYS_GPD_MFPH_PD9MFP_EBI_AD7
#define | SYS_GPD_MFPH_PD9MFP_I2C2_SCL
#define | SYS_GPD_MFPH_PD9MFP_UART2_nCTS
#define | SYS_GPD_MFPH_PD9MFP_UART7_TXD
#define | SYS_GPD_MFPH_PD9MFP_CAN2_TXD
#define | SYS_GPD_MFPH_PD10MFP_GPIO
#define | SYS_GPD_MFPH_PD10MFP_OPA2_P
#define | SYS_GPD_MFPH_PD10MFP_EADC1_CH0
#define | SYS_GPD_MFPH_PD10MFP_EBI_nCS2
#define | SYS_GPD_MFPH_PD10MFP_UART1_RXD
#define | SYS_GPD_MFPH_PD10MFP_CAN0_RXD
#define | SYS_GPD_MFPH_PD10MFP_QEI0_B
#define | SYS_GPD_MFPH_PD10MFP_INT7
#define | SYS_GPD_MFPH_PD11MFP_GPIO
#define | SYS_GPD_MFPH_PD11MFP_EADC1_CH1
#define | SYS_GPD_MFPH_PD11MFP_OPA2_N
#define | SYS_GPD_MFPH_PD11MFP_EBI_nCS1
#define | SYS_GPD_MFPH_PD11MFP_UART1_TXD
#define | SYS_GPD_MFPH_PD11MFP_CAN0_TXD
#define | SYS_GPD_MFPH_PD11MFP_QEI0_A
#define | SYS_GPD_MFPH_PD11MFP_INT6
#define | SYS_GPD_MFPH_PD12MFP_GPIO
#define | SYS_GPD_MFPH_PD12MFP_OPA2_O
#define | SYS_GPD_MFPH_PD12MFP_EADC1_CH2
#define | SYS_GPD_MFPH_PD12MFP_EBI_nCS0
#define | SYS_GPD_MFPH_PD12MFP_CAN1_RXD
#define | SYS_GPD_MFPH_PD12MFP_UART2_RXD
#define | SYS_GPD_MFPH_PD12MFP_BPWM0_CH5
#define | SYS_GPD_MFPH_PD12MFP_QEI0_INDEX
#define | SYS_GPD_MFPH_PD12MFP_CLKO
#define | SYS_GPD_MFPH_PD12MFP_EADC0_ST
#define | SYS_GPD_MFPH_PD12MFP_INT5
#define | SYS_GPD_MFPH_PD13MFP_GPIO
#define | SYS_GPD_MFPH_PD13MFP_EBI_AD10
#define | SYS_GPD_MFPH_PD13MFP_SD0_nCD
#define | SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK
#define | SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK
#define | SYS_GPD_MFPH_PD13MFP_SC2_nCD
#define | SYS_GPD_MFPH_PD14MFP_GPIO
#define | SYS_GPD_MFPH_PD14MFP_EBI_nCS0
#define | SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK
#define | SYS_GPD_MFPH_PD14MFP_SC1_nCD
#define | SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK
#define | SYS_GPD_MFPH_PD14MFP_EPWM0_CH4
#define | SYS_GPE_MFPL_PE0MFP_GPIO
#define | SYS_GPE_MFPL_PE0MFP_EBI_AD11
#define | SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0
#define | SYS_GPE_MFPL_PE0MFP_SC2_CLK
#define | SYS_GPE_MFPL_PE0MFP_I2S0_MCLK
#define | SYS_GPE_MFPL_PE0MFP_SPI1_MOSI
#define | SYS_GPE_MFPL_PE0MFP_UART3_RXD
#define | SYS_GPE_MFPL_PE0MFP_I2C1_SDA
#define | SYS_GPE_MFPL_PE0MFP_UART4_nRTS
#define | SYS_GPE_MFPL_PE1MFP_GPIO
#define | SYS_GPE_MFPL_PE1MFP_EBI_AD10
#define | SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0
#define | SYS_GPE_MFPL_PE1MFP_SC2_DAT
#define | SYS_GPE_MFPL_PE1MFP_I2S0_BCLK
#define | SYS_GPE_MFPL_PE1MFP_SPI1_MISO
#define | SYS_GPE_MFPL_PE1MFP_UART3_TXD
#define | SYS_GPE_MFPL_PE1MFP_I2C1_SCL
#define | SYS_GPE_MFPL_PE1MFP_UART4_nCTS
#define | SYS_GPE_MFPL_PE2MFP_GPIO
#define | SYS_GPE_MFPL_PE2MFP_EBI_ALE
#define | SYS_GPE_MFPL_PE2MFP_SD0_DAT0
#define | SYS_GPE_MFPL_PE2MFP_SPIM_MOSI
#define | SYS_GPE_MFPL_PE2MFP_SPI3_MOSI
#define | SYS_GPE_MFPL_PE2MFP_SC0_CLK
#define | SYS_GPE_MFPL_PE2MFP_USCI0_CLK
#define | SYS_GPE_MFPL_PE2MFP_UART6_nCTS
#define | SYS_GPE_MFPL_PE2MFP_UART7_RXD
#define | SYS_GPE_MFPL_PE2MFP_QEI0_B
#define | SYS_GPE_MFPL_PE2MFP_EPWM0_CH5
#define | SYS_GPE_MFPL_PE2MFP_BPWM0_CH0
#define | SYS_GPE_MFPL_PE3MFP_GPIO
#define | SYS_GPE_MFPL_PE3MFP_EBI_MCLK
#define | SYS_GPE_MFPL_PE3MFP_SD0_DAT1
#define | SYS_GPE_MFPL_PE3MFP_SPIM_MISO
#define | SYS_GPE_MFPL_PE3MFP_SPI3_MISO
#define | SYS_GPE_MFPL_PE3MFP_SC0_DAT
#define | SYS_GPE_MFPL_PE3MFP_USCI0_DAT0
#define | SYS_GPE_MFPL_PE3MFP_UART6_nRTS
#define | SYS_GPE_MFPL_PE3MFP_UART7_TXD
#define | SYS_GPE_MFPL_PE3MFP_QEI0_A
#define | SYS_GPE_MFPL_PE3MFP_EPWM0_CH4
#define | SYS_GPE_MFPL_PE3MFP_BPWM0_CH1
#define | SYS_GPE_MFPL_PE4MFP_GPIO
#define | SYS_GPE_MFPL_PE4MFP_EBI_nWR
#define | SYS_GPE_MFPL_PE4MFP_SD0_DAT2
#define | SYS_GPE_MFPL_PE4MFP_SPIM_CLK
#define | SYS_GPE_MFPL_PE4MFP_SPI3_CLK
#define | SYS_GPE_MFPL_PE4MFP_SC0_RST
#define | SYS_GPE_MFPL_PE4MFP_USCI0_DAT1
#define | SYS_GPE_MFPL_PE4MFP_UART6_RXD
#define | SYS_GPE_MFPL_PE4MFP_UART7_nCTS
#define | SYS_GPE_MFPL_PE4MFP_QEI0_INDEX
#define | SYS_GPE_MFPL_PE4MFP_EPWM0_CH3
#define | SYS_GPE_MFPL_PE4MFP_BPWM0_CH2
#define | SYS_GPE_MFPL_PE5MFP_GPIO
#define | SYS_GPE_MFPL_PE5MFP_EBI_nRD
#define | SYS_GPE_MFPL_PE5MFP_SD0_DAT3
#define | SYS_GPE_MFPL_PE5MFP_SPIM_SS
#define | SYS_GPE_MFPL_PE5MFP_SPI3_SS
#define | SYS_GPE_MFPL_PE5MFP_SC0_PWR
#define | SYS_GPE_MFPL_PE5MFP_USCI0_CTL1
#define | SYS_GPE_MFPL_PE5MFP_UART6_TXD
#define | SYS_GPE_MFPL_PE5MFP_UART7_nRTS
#define | SYS_GPE_MFPL_PE5MFP_QEI1_B
#define | SYS_GPE_MFPL_PE5MFP_EPWM0_CH2
#define | SYS_GPE_MFPL_PE5MFP_BPWM0_CH3
#define | SYS_GPE_MFPL_PE6MFP_GPIO
#define | SYS_GPE_MFPL_PE6MFP_SD0_CLK
#define | SYS_GPE_MFPL_PE6MFP_SPIM_D3
#define | SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK
#define | SYS_GPE_MFPL_PE6MFP_SC0_nCD
#define | SYS_GPE_MFPL_PE6MFP_USCI0_CTL0
#define | SYS_GPE_MFPL_PE6MFP_UART5_RXD
#define | SYS_GPE_MFPL_PE6MFP_CAN1_RXD
#define | SYS_GPE_MFPL_PE6MFP_QEI1_A
#define | SYS_GPE_MFPL_PE6MFP_EPWM0_CH1
#define | SYS_GPE_MFPL_PE6MFP_BPWM0_CH4
#define | SYS_GPE_MFPL_PE7MFP_GPIO
#define | SYS_GPE_MFPL_PE7MFP_SD0_CMD
#define | SYS_GPE_MFPL_PE7MFP_SPIM_D2
#define | SYS_GPE_MFPL_PE7MFP_UART5_TXD
#define | SYS_GPE_MFPL_PE7MFP_CAN1_TXD
#define | SYS_GPE_MFPL_PE7MFP_QEI1_INDEX
#define | SYS_GPE_MFPL_PE7MFP_EPWM0_CH0
#define | SYS_GPE_MFPL_PE7MFP_BPWM0_CH5
#define | SYS_GPE_MFPH_PE8MFP_GPIO
#define | SYS_GPE_MFPH_PE8MFP_EBI_ADR10
#define | SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC
#define | SYS_GPE_MFPH_PE8MFP_I2S0_BCLK
#define | SYS_GPE_MFPH_PE8MFP_SPI2_CLK
#define | SYS_GPE_MFPH_PE8MFP_USCI1_CTL1
#define | SYS_GPE_MFPH_PE8MFP_UART2_TXD
#define | SYS_GPE_MFPH_PE8MFP_EPWM0_CH0
#define | SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0
#define | SYS_GPE_MFPH_PE8MFP_ECAP0_IC0
#define | SYS_GPE_MFPH_PE8MFP_TRACE_DATA3
#define | SYS_GPE_MFPH_PE9MFP_GPIO
#define | SYS_GPE_MFPH_PE9MFP_EBI_ADR11
#define | SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO
#define | SYS_GPE_MFPH_PE9MFP_I2S0_MCLK
#define | SYS_GPE_MFPH_PE9MFP_SPI2_MISO
#define | SYS_GPE_MFPH_PE9MFP_USCI1_CTL0
#define | SYS_GPE_MFPH_PE9MFP_UART2_RXD
#define | SYS_GPE_MFPH_PE9MFP_EPWM0_CH1
#define | SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1
#define | SYS_GPE_MFPH_PE9MFP_ECAP0_IC1
#define | SYS_GPE_MFPH_PE9MFP_TRACE_DATA2
#define | SYS_GPE_MFPH_PE10MFP_GPIO
#define | SYS_GPE_MFPH_PE10MFP_EBI_ADR12
#define | SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0
#define | SYS_GPE_MFPH_PE10MFP_I2S0_DI
#define | SYS_GPE_MFPH_PE10MFP_SPI2_MOSI
#define | SYS_GPE_MFPH_PE10MFP_USCI1_DAT0
#define | SYS_GPE_MFPH_PE10MFP_UART3_TXD
#define | SYS_GPE_MFPH_PE10MFP_EPWM0_CH2
#define | SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0
#define | SYS_GPE_MFPH_PE10MFP_ECAP0_IC2
#define | SYS_GPE_MFPH_PE10MFP_TRACE_DATA1
#define | SYS_GPE_MFPH_PE11MFP_GPIO
#define | SYS_GPE_MFPH_PE11MFP_EBI_ADR13
#define | SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1
#define | SYS_GPE_MFPH_PE11MFP_I2S0_DO
#define | SYS_GPE_MFPH_PE11MFP_SPI2_SS
#define | SYS_GPE_MFPH_PE11MFP_USCI1_DAT1
#define | SYS_GPE_MFPH_PE11MFP_UART3_RXD
#define | SYS_GPE_MFPH_PE11MFP_UART1_nCTS
#define | SYS_GPE_MFPH_PE11MFP_EPWM0_CH3
#define | SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1
#define | SYS_GPE_MFPH_PE11MFP_ECAP1_IC2
#define | SYS_GPE_MFPH_PE11MFP_TRACE_DATA0
#define | SYS_GPE_MFPH_PE12MFP_GPIO
#define | SYS_GPE_MFPH_PE12MFP_EBI_ADR14
#define | SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN
#define | SYS_GPE_MFPH_PE12MFP_I2S0_LRCK
#define | SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK
#define | SYS_GPE_MFPH_PE12MFP_USCI1_CLK
#define | SYS_GPE_MFPH_PE12MFP_UART1_nRTS
#define | SYS_GPE_MFPH_PE12MFP_EPWM0_CH4
#define | SYS_GPE_MFPH_PE12MFP_ECAP1_IC1
#define | SYS_GPE_MFPH_PE12MFP_TRACE_CLK
#define | SYS_GPE_MFPH_PE13MFP_GPIO
#define | SYS_GPE_MFPH_PE13MFP_EBI_ADR15
#define | SYS_GPE_MFPH_PE13MFP_EMAC_PPS
#define | SYS_GPE_MFPH_PE13MFP_I2C0_SCL
#define | SYS_GPE_MFPH_PE13MFP_UART4_nRTS
#define | SYS_GPE_MFPH_PE13MFP_UART1_TXD
#define | SYS_GPE_MFPH_PE13MFP_EPWM0_CH5
#define | SYS_GPE_MFPH_PE13MFP_EPWM1_CH0
#define | SYS_GPE_MFPH_PE13MFP_BPWM1_CH5
#define | SYS_GPE_MFPH_PE13MFP_ECAP1_IC0
#define | SYS_GPE_MFPH_PE14MFP_GPIO
#define | SYS_GPE_MFPH_PE14MFP_EBI_AD8
#define | SYS_GPE_MFPH_PE14MFP_UART2_TXD
#define | SYS_GPE_MFPH_PE14MFP_CAN0_TXD
#define | SYS_GPE_MFPH_PE14MFP_SD1_nCD
#define | SYS_GPE_MFPH_PE14MFP_UART6_TXD (0x06UL<<SYS_GPE_MFPH_PE14MFP_Pos)
#define | SYS_GPE_MFPH_PE15MFP_GPIO
#define | SYS_GPE_MFPH_PE15MFP_EBI_AD9
#define | SYS_GPE_MFPH_PE15MFP_UART2_RXD
#define | SYS_GPE_MFPH_PE15MFP_CAN0_RXD
#define | SYS_GPE_MFPH_PE15MFP_UART6_RXD
#define | SYS_GPF_MFPL_PF0MFP_GPIO
#define | SYS_GPF_MFPL_PF0MFP_UART1_TXD
#define | SYS_GPF_MFPL_PF0MFP_I2C1_SCL
#define | SYS_GPF_MFPL_PF0MFP_UART0_TXD
#define | SYS_GPF_MFPL_PF0MFP_BPWM1_CH0
#define | SYS_GPF_MFPL_PF0MFP_ICE_DAT
#define | SYS_GPF_MFPL_PF1MFP_GPIO
#define | SYS_GPF_MFPL_PF1MFP_UART1_RXD
#define | SYS_GPF_MFPL_PF1MFP_I2C1_SDA
#define | SYS_GPF_MFPL_PF1MFP_UART0_RXD
#define | SYS_GPF_MFPL_PF1MFP_BPWM1_CH1
#define | SYS_GPF_MFPL_PF1MFP_ICE_CLK
#define | SYS_GPF_MFPL_PF2MFP_GPIO
#define | SYS_GPF_MFPL_PF2MFP_EBI_nCS1
#define | SYS_GPF_MFPL_PF2MFP_UART0_RXD
#define | SYS_GPF_MFPL_PF2MFP_I2C0_SDA
#define | SYS_GPF_MFPL_PF2MFP_QSPI0_CLK
#define | SYS_GPF_MFPL_PF2MFP_XT1_OUT
#define | SYS_GPF_MFPL_PF2MFP_BPWM1_CH1
#define | SYS_GPF_MFPL_PF3MFP_GPIO
#define | SYS_GPF_MFPL_PF3MFP_EBI_nCS0
#define | SYS_GPF_MFPL_PF3MFP_UART0_TXD
#define | SYS_GPF_MFPL_PF3MFP_I2C0_SCL
#define | SYS_GPF_MFPL_PF3MFP_XT1_IN
#define | SYS_GPF_MFPL_PF3MFP_BPWM1_CH0
#define | SYS_GPF_MFPL_PF4MFP_GPIO
#define | SYS_GPF_MFPL_PF4MFP_UART2_TXD
#define | SYS_GPF_MFPL_PF4MFP_UART2_nRTS
#define | SYS_GPF_MFPL_PF4MFP_EPWM0_CH1
#define | SYS_GPF_MFPL_PF4MFP_BPWM0_CH5
#define | SYS_GPF_MFPL_PF4MFP_X32_OUT
#define | SYS_GPF_MFPL_PF4MFP_EADC1_ST
#define | SYS_GPF_MFPL_PF5MFP_GPIO
#define | SYS_GPF_MFPL_PF5MFP_UART2_RXD
#define | SYS_GPF_MFPL_PF5MFP_UART2_nCTS
#define | SYS_GPF_MFPL_PF5MFP_EPWM0_CH0
#define | SYS_GPF_MFPL_PF5MFP_BPWM0_CH4
#define | SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT
#define | SYS_GPF_MFPL_PF5MFP_X32_IN
#define | SYS_GPF_MFPL_PF5MFP_EADC0_ST
#define | SYS_GPF_MFPL_PF6MFP_GPIO
#define | SYS_GPF_MFPL_PF6MFP_EBI_ADR19
#define | SYS_GPF_MFPL_PF6MFP_SC0_CLK
#define | SYS_GPF_MFPL_PF6MFP_I2S0_LRCK
#define | SYS_GPF_MFPL_PF6MFP_SPI0_MOSI
#define | SYS_GPF_MFPL_PF6MFP_UART4_RXD
#define | SYS_GPF_MFPL_PF6MFP_EBI_nCS0
#define | SYS_GPF_MFPL_PF6MFP_CAN2_RXD
#define | SYS_GPF_MFPL_PF6MFP_TAMPER0
#define | SYS_GPF_MFPL_PF7MFP_GPIO
#define | SYS_GPF_MFPL_PF7MFP_EBI_ADR18
#define | SYS_GPF_MFPL_PF7MFP_SC0_DAT
#define | SYS_GPF_MFPL_PF7MFP_I2S0_DO
#define | SYS_GPF_MFPL_PF7MFP_SPI0_MISO
#define | SYS_GPF_MFPL_PF7MFP_UART4_TXD
#define | SYS_GPF_MFPL_PF7MFP_CCAP_DATA0 (0x07UL<<SYS_GPF_MFPL_PF7MFP_Pos)
#define | SYS_GPF_MFPL_PF7MFP_CAN2_TXD (0x08UL<<SYS_GPF_MFPL_PF7MFP_Pos)
#define | SYS_GPF_MFPL_PF7MFP_TAMPER1
#define | SYS_GPF_MFPH_PF8MFP_GPIO
#define | SYS_GPF_MFPH_PF8MFP_EBI_ADR17
#define | SYS_GPF_MFPH_PF8MFP_SC0_RST
#define | SYS_GPF_MFPH_PF8MFP_I2S0_DI
#define | SYS_GPF_MFPH_PF8MFP_SPI0_CLK
#define | SYS_GPF_MFPH_PF8MFP_UART5_nCTS
#define | SYS_GPF_MFPH_PF8MFP_CCAP_DATA1
#define | SYS_GPF_MFPH_PF8MFP_CAN1_RXD (0x08UL<<SYS_GPF_MFPH_PF8MFP_Pos)
#define | SYS_GPF_MFPH_PF8MFP_TAMPER2
#define | SYS_GPF_MFPH_PF9MFP_GPIO
#define | SYS_GPF_MFPH_PF9MFP_EBI_ADR16
#define | SYS_GPF_MFPH_PF9MFP_SC0_PWR
#define | SYS_GPF_MFPH_PF9MFP_I2S0_MCLK
#define | SYS_GPF_MFPH_PF9MFP_SPI0_SS
#define | SYS_GPF_MFPH_PF9MFP_UART5_nRTS
#define | SYS_GPF_MFPH_PF9MFP_CCAP_DATA2
#define | SYS_GPF_MFPH_PF9MFP_CAN1_TXD
#define | SYS_GPF_MFPH_PF9MFP_TAMPER3
#define | SYS_GPF_MFPH_PF10MFP_GPIO
#define | SYS_GPF_MFPH_PF10MFP_EBI_ADR15
#define | SYS_GPF_MFPH_PF10MFP_SC0_nCD
#define | SYS_GPF_MFPH_PF10MFP_I2S0_BCLK
#define | SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK
#define | SYS_GPF_MFPH_PF10MFP_UART5_RXD
#define | SYS_GPF_MFPH_PF10MFP_CCAP_DATA3
#define | SYS_GPF_MFPH_PF10MFP_TAMPER4
#define | SYS_GPF_MFPH_PF11MFP_GPIO
#define | SYS_GPF_MFPH_PF11MFP_EBI_ADR14
#define | SYS_GPF_MFPH_PF11MFP_SPI2_MOSI
#define | SYS_GPF_MFPH_PF11MFP_UART5_TXD
#define | SYS_GPF_MFPH_PF11MFP_CCAP_DATA4
#define | SYS_GPF_MFPH_PF11MFP_TAMPER5
#define | SYS_GPF_MFPH_PF11MFP_TM3
#define | SYS_GPG_MFPL_PG0MFP_GPIO
#define | SYS_GPG_MFPL_PG0MFP_EBI_ADR8
#define | SYS_GPG_MFPL_PG0MFP_I2C0_SCL
#define | SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL
#define | SYS_GPG_MFPL_PG0MFP_UART2_RXD
#define | SYS_GPG_MFPL_PG0MFP_CAN1_TXD
#define | SYS_GPG_MFPL_PG0MFP_UART1_TXD
#define | SYS_GPG_MFPL_PG1MFP_GPIO
#define | SYS_GPG_MFPL_PG1MFP_EBI_ADR9
#define | SYS_GPG_MFPL_PG1MFP_SPI2_I2SMCLK
#define | SYS_GPG_MFPL_PG1MFP_I2C0_SDA
#define | SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS
#define | SYS_GPG_MFPL_PG1MFP_UART2_TXD
#define | SYS_GPG_MFPL_PG1MFP_CAN1_RXD
#define | SYS_GPG_MFPL_PG1MFP_UART1_RXD
#define | SYS_GPG_MFPL_PG2MFP_GPIO
#define | SYS_GPG_MFPL_PG2MFP_EBI_ADR11
#define | SYS_GPG_MFPL_PG2MFP_SPI2_SS
#define | SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL
#define | SYS_GPG_MFPL_PG2MFP_I2C1_SCL
#define | SYS_GPG_MFPL_PG2MFP_CCAP_DATA7
#define | SYS_GPG_MFPL_PG2MFP_TM0
#define | SYS_GPG_MFPL_PG3MFP_GPIO
#define | SYS_GPG_MFPL_PG3MFP_EBI_ADR12
#define | SYS_GPG_MFPL_PG3MFP_SPI2_CLK
#define | SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS
#define | SYS_GPG_MFPL_PG3MFP_I2C1_SDA
#define | SYS_GPG_MFPL_PG3MFP_CCAP_DATA6
#define | SYS_GPG_MFPL_PG3MFP_TM1
#define | SYS_GPG_MFPL_PG4MFP_GPIO
#define | SYS_GPG_MFPL_PG4MFP_EBI_ADR13
#define | SYS_GPG_MFPL_PG4MFP_SPI2_MISO
#define | SYS_GPG_MFPL_PG4MFP_CCAP_DATA5
#define | SYS_GPG_MFPL_PG4MFP_TM2
#define | SYS_GPG_MFPL_PG5MFP_GPIO
#define | SYS_GPG_MFPL_PG5MFP_EBI_nCS1
#define | SYS_GPG_MFPL_PG5MFP_SPI3_SS
#define | SYS_GPG_MFPL_PG5MFP_SC1_PWR
#define | SYS_GPG_MFPL_PG5MFP_EPWM0_CH3
#define | SYS_GPG_MFPL_PG6MFP_GPIO
#define | SYS_GPG_MFPL_PG6MFP_EBI_nCS2
#define | SYS_GPG_MFPL_PG6MFP_SPI3_CLK
#define | SYS_GPG_MFPL_PG6MFP_SC1_RST
#define | SYS_GPG_MFPL_PG6MFP_EPWM0_CH2
#define | SYS_GPG_MFPL_PG7MFP_GPIO
#define | SYS_GPG_MFPL_PG7MFP_EBI_nWRL
#define | SYS_GPG_MFPL_PG7MFP_SPI3_MISO
#define | SYS_GPG_MFPL_PG7MFP_SC1_DAT
#define | SYS_GPG_MFPL_PG7MFP_EPWM0_CH1
#define | SYS_GPG_MFPH_PG8MFP_GPIO
#define | SYS_GPG_MFPH_PG8MFP_EBI_nWRH
#define | SYS_GPG_MFPH_PG8MFP_SPI3_MOSI
#define | SYS_GPG_MFPH_PG8MFP_SC1_CLK
#define | SYS_GPG_MFPH_PG8MFP_EPWM0_CH0
#define | SYS_GPG_MFPH_PG9MFP_GPIO
#define | SYS_GPG_MFPH_PG9MFP_EBI_AD0
#define | SYS_GPG_MFPH_PG9MFP_SD1_DAT3
#define | SYS_GPG_MFPH_PG9MFP_SPIM_D2
#define | SYS_GPG_MFPH_PG9MFP_QSPI1_MISO1
#define | SYS_GPG_MFPH_PG9MFP_CCAP_PIXCLK
#define | SYS_GPG_MFPH_PG9MFP_BPWM0_CH5
#define | SYS_GPG_MFPH_PG10MFP_GPIO
#define | SYS_GPG_MFPH_PG10MFP_EBI_AD1
#define | SYS_GPG_MFPH_PG10MFP_SD1_DAT2
#define | SYS_GPG_MFPH_PG10MFP_SPIM_D3
#define | SYS_GPG_MFPH_PG10MFP_QSPI1_MOSI1
#define | SYS_GPG_MFPH_PG10MFP_CCAP_SCLK
#define | SYS_GPG_MFPH_PG10MFP_BPWM0_CH4
#define | SYS_GPG_MFPH_PG11MFP_GPIO
#define | SYS_GPG_MFPH_PG11MFP_EBI_AD2
#define | SYS_GPG_MFPH_PG11MFP_SD1_DAT1
#define | SYS_GPG_MFPH_PG11MFP_SPIM_SS
#define | SYS_GPG_MFPH_PG11MFP_QSPI1_SS
#define | SYS_GPG_MFPH_PG11MFP_UART7_TXD
#define | SYS_GPG_MFPH_PG11MFP_CCAP_SFIELD
#define | SYS_GPG_MFPH_PG11MFP_BPWM0_CH3
#define | SYS_GPG_MFPH_PG12MFP_GPIO
#define | SYS_GPG_MFPH_PG12MFP_EBI_AD3
#define | SYS_GPG_MFPH_PG12MFP_SD1_DAT0
#define | SYS_GPG_MFPH_PG12MFP_SPIM_CLK
#define | SYS_GPG_MFPH_PG12MFP_QSPI1_CLK
#define | SYS_GPG_MFPH_PG12MFP_UART7_RXD
#define | SYS_GPG_MFPH_PG12MFP_CCAP_VSYNC
#define | SYS_GPG_MFPH_PG12MFP_BPWM0_CH2
#define | SYS_GPG_MFPH_PG13MFP_GPIO
#define | SYS_GPG_MFPH_PG13MFP_EBI_AD4
#define | SYS_GPG_MFPH_PG13MFP_SD1_CMD
#define | SYS_GPG_MFPH_PG13MFP_SPIM_MISO
#define | SYS_GPG_MFPH_PG13MFP_QSPI1_MISO0
#define | SYS_GPG_MFPH_PG13MFP_UART6_TXD
#define | SYS_GPG_MFPH_PG13MFP_CCAP_HSYNC
#define | SYS_GPG_MFPH_PG13MFP_BPWM0_CH1
#define | SYS_GPG_MFPH_PG14MFP_GPIO
#define | SYS_GPG_MFPH_PG14MFP_EBI_AD5
#define | SYS_GPG_MFPH_PG14MFP_SD1_CLK
#define | SYS_GPG_MFPH_PG14MFP_SPIM_MOSI
#define | SYS_GPG_MFPH_PG14MFP_QSPI1_MOSI0
#define | SYS_GPG_MFPH_PG14MFP_UART6_RXD
#define | SYS_GPG_MFPH_PG14MFP_BPWM0_CH0
#define | SYS_GPG_MFPH_PG15MFP_GPIO
#define | SYS_GPG_MFPH_PG15MFP_SD1_nCD
#define | SYS_GPG_MFPH_PG15MFP_CLKO
#define | SYS_GPG_MFPH_PG15MFP_EADC0_ST
#define | SYS_GPH_MFPL_PH0MFP_GPIO
#define | SYS_GPH_MFPL_PH0MFP_EBI_ADR7
#define | SYS_GPH_MFPL_PH0MFP_UART5_TXD
#define | SYS_GPH_MFPL_PH0MFP_TM0_EXT
#define | SYS_GPH_MFPL_PH1MFP_GPIO
#define | SYS_GPH_MFPL_PH1MFP_EBI_ADR6
#define | SYS_GPH_MFPL_PH1MFP_UART5_RXD
#define | SYS_GPH_MFPL_PH1MFP_TM1_EXT
#define | SYS_GPH_MFPL_PH2MFP_GPIO
#define | SYS_GPH_MFPL_PH2MFP_EBI_ADR5
#define | SYS_GPH_MFPL_PH2MFP_UART5_nRTS
#define | SYS_GPH_MFPL_PH2MFP_UART4_TXD
#define | SYS_GPH_MFPL_PH2MFP_I2C0_SCL
#define | SYS_GPH_MFPL_PH2MFP_TM2_EXT
#define | SYS_GPH_MFPL_PH3MFP_GPIO
#define | SYS_GPH_MFPL_PH3MFP_EBI_ADR4
#define | SYS_GPH_MFPL_PH3MFP_SPI1_I2SMCLK
#define | SYS_GPH_MFPL_PH3MFP_UART5_nCTS
#define | SYS_GPH_MFPL_PH3MFP_UART4_RXD
#define | SYS_GPH_MFPL_PH3MFP_I2C0_SDA
#define | SYS_GPH_MFPL_PH3MFP_TM3_EXT
#define | SYS_GPH_MFPL_PH4MFP_GPIO
#define | SYS_GPH_MFPL_PH4MFP_EBI_ADR3
#define | SYS_GPH_MFPL_PH4MFP_SPI1_MISO
#define | SYS_GPH_MFPL_PH4MFP_UART7_nRTS
#define | SYS_GPH_MFPL_PH4MFP_UART6_TXD
#define | SYS_GPH_MFPL_PH5MFP_GPIO
#define | SYS_GPH_MFPL_PH5MFP_EBI_ADR2
#define | SYS_GPH_MFPL_PH5MFP_SPI1_MOSI
#define | SYS_GPH_MFPL_PH5MFP_UART7_nCTS
#define | SYS_GPH_MFPL_PH5MFP_UART6_RXD
#define | SYS_GPH_MFPL_PH6MFP_GPIO
#define | SYS_GPH_MFPL_PH6MFP_EBI_ADR1
#define | SYS_GPH_MFPL_PH6MFP_SPI1_CLK
#define | SYS_GPH_MFPL_PH6MFP_UART7_TXD
#define | SYS_GPH_MFPL_PH7MFP_GPIO
#define | SYS_GPH_MFPL_PH7MFP_EBI_ADR0
#define | SYS_GPH_MFPL_PH7MFP_SPI1_SS
#define | SYS_GPH_MFPL_PH7MFP_UART7_RXD
#define | SYS_GPH_MFPH_PH8MFP_GPIO
#define | SYS_GPH_MFPH_PH8MFP_EBI_AD12
#define | SYS_GPH_MFPH_PH8MFP_QSPI0_CLK
#define | SYS_GPH_MFPH_PH8MFP_SC2_PWR
#define | SYS_GPH_MFPH_PH8MFP_I2S0_DI
#define | SYS_GPH_MFPH_PH8MFP_SPI1_CLK
#define | SYS_GPH_MFPH_PH8MFP_UART3_nRTS
#define | SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL
#define | SYS_GPH_MFPH_PH8MFP_I2C2_SCL
#define | SYS_GPH_MFPH_PH8MFP_UART1_TXD
#define | SYS_GPH_MFPH_PH9MFP_GPIO
#define | SYS_GPH_MFPH_PH9MFP_EBI_AD13
#define | SYS_GPH_MFPH_PH9MFP_QSPI0_SS
#define | SYS_GPH_MFPH_PH9MFP_SC2_RST
#define | SYS_GPH_MFPH_PH9MFP_I2S0_DO
#define | SYS_GPH_MFPH_PH9MFP_SPI1_SS
#define | SYS_GPH_MFPH_PH9MFP_UART3_nCTS
#define | SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS
#define | SYS_GPH_MFPH_PH9MFP_I2C2_SDA
#define | SYS_GPH_MFPH_PH9MFP_UART1_RXD
#define | SYS_GPH_MFPH_PH10MFP_GPIO
#define | SYS_GPH_MFPH_PH10MFP_EBI_AD14
#define | SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1
#define | SYS_GPH_MFPH_PH10MFP_SC2_nCD
#define | SYS_GPH_MFPH_PH10MFP_I2S0_LRCK
#define | SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK
#define | SYS_GPH_MFPH_PH10MFP_UART4_TXD
#define | SYS_GPH_MFPH_PH10MFP_UART0_TXD
#define | SYS_GPH_MFPH_PH11MFP_GPIO
#define | SYS_GPH_MFPH_PH11MFP_EBI_AD15
#define | SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1
#define | SYS_GPH_MFPH_PH11MFP_UART4_RXD
#define | SYS_GPH_MFPH_PH11MFP_UART0_RXD
#define | SYS_GPH_MFPH_PH11MFP_EPWM0_CH5

## Detailed Description

## Macro Definition Documentation

## ◆ ACMP01_RST

#define ACMP01_RST

Reset ACMP01

Definition at line 52 of file sys.h.

## ◆ BPWM0_RST

#define BPWM0_RST

Reset BPWM0

Definition at line 87 of file sys.h.

## ◆ BPWM1_RST

#define BPWM1_RST

Reset BPWM1

Definition at line 88 of file sys.h.

## ◆ CAN0_RST

#define CAN0_RST

Reset CAN0

Definition at line 68 of file sys.h.

## ◆ CAN1_RST

#define CAN1_RST

Reset CAN1

Definition at line 69 of file sys.h.

## ◆ CAN2_RST

#define CAN2_RST

Reset CAN2

Definition at line 93 of file sys.h.

## ◆ CCAP_RST

#define CCAP_RST

Reset ICAP

Definition at line 40 of file sys.h.

## ◆ CRC_RST

#define CRC_RST

Reset CRC

Definition at line 39 of file sys.h.

## ◆ CRPT_RST

#define CRPT_RST

Reset CRPT

Definition at line 42 of file sys.h.

## ◆ DAC_RST

#define DAC_RST

Reset DAC

Definition at line 84 of file sys.h.

## ◆ EADC1_RST

#define EADC1_RST

Reset EADC1

Definition at line 95 of file sys.h.

## ◆ EADC_RST

#define EADC_RST

Reset EADC

Definition at line 72 of file sys.h.

## ◆ EBI_RST

#define EBI_RST

Reset EBI

Definition at line 36 of file sys.h.

## ◆ ECAP0_RST

#define ECAP0_RST

Reset ECAP0

Definition at line 91 of file sys.h.

## ◆ ECAP1_RST

#define ECAP1_RST

Reset ECAP1

Definition at line 92 of file sys.h.

## ◆ EMAC_RST

#define EMAC_RST

Reset EMAC

Definition at line 37 of file sys.h.

## ◆ EPWM0_RST

#define EPWM0_RST

Reset EPWM0

Definition at line 85 of file sys.h.

## ◆ EPWM1_RST

#define EPWM1_RST

Reset EPWM1

Definition at line 86 of file sys.h.

## ◆ GPIO_RST

#define GPIO_RST

Reset GPIO

Definition at line 47 of file sys.h.

## ◆ HSOTG_RST

#define HSOTG_RST

Reset HSOTG

Definition at line 74 of file sys.h.

## ◆ HSUSBD_RST

#define HSUSBD_RST

Reset HSUSBD

Definition at line 41 of file sys.h.

## ◆ I2C0_RST

#define I2C0_RST

Reset I2C0

Definition at line 53 of file sys.h.

## ◆ I2C1_RST

#define I2C1_RST

Reset I2C1

Definition at line 54 of file sys.h.

## ◆ I2C2_RST

#define I2C2_RST

Reset I2C2

Definition at line 55 of file sys.h.

## ◆ I2S0_RST

#define I2S0_RST

Reset I2S0

Definition at line 73 of file sys.h.

## ◆ OPA_RST

#define OPA_RST

Reset OPA

Definition at line 94 of file sys.h.

## ◆ OTG_RST

#define OTG_RST

Reset OTG

Definition at line 70 of file sys.h.

## ◆ PDMA_RST

#define PDMA_RST

Reset PDMA

Definition at line 35 of file sys.h.

## ◆ QEI0_RST

#define QEI0_RST

Reset QEI0

Definition at line 89 of file sys.h.

## ◆ QEI1_RST

#define QEI1_RST

Reset QEI1

Definition at line 90 of file sys.h.

## ◆ QSPI0_RST

#define QSPI0_RST

Reset QSPI0

Definition at line 56 of file sys.h.

## ◆ QSPI1_RST

#define QSPI1_RST

Reset QSPI1

Definition at line 80 of file sys.h.

## ◆ SC0_RST

#define SC0_RST

Reset SC0

Definition at line 77 of file sys.h.

## ◆ SC1_RST

#define SC1_RST

Reset SC1

Definition at line 78 of file sys.h.

## ◆ SC2_RST

#define SC2_RST

Reset SC2

Definition at line 79 of file sys.h.

## ◆ SDH0_RST

#define SDH0_RST

Reset SDH0

Definition at line 38 of file sys.h.

## ◆ SDH1_RST

#define SDH1_RST

Reset SDH1

Definition at line 45 of file sys.h.

## ◆ SPI0_RST

#define SPI0_RST

Reset SPI0

Definition at line 57 of file sys.h.

## ◆ SPI1_RST

#define SPI1_RST

Reset SPI1

Definition at line 58 of file sys.h.

## ◆ SPI2_RST

#define SPI2_RST

Reset SPI2

Definition at line 59 of file sys.h.

## ◆ SPI3_RST

#define SPI3_RST

Reset SPI3

Definition at line 81 of file sys.h.

## ◆ SPIM_RST

#define SPIM_RST

Reset SPIM

Definition at line 43 of file sys.h.

## ◆ SYS_BODCTL_BOD_INTERRUPT_EN

#define SYS_BODCTL_BOD_INTERRUPT_EN

Brown-out Interrupt Enable

Definition at line 101 of file sys.h.

## ◆ SYS_BODCTL_BOD_RST_EN

#define SYS_BODCTL_BOD_RST_EN

Brown-out Reset Enable

Definition at line 100 of file sys.h.

## ◆ SYS_BODCTL_BODVL_1_6V

#define SYS_BODCTL_BODVL_1_6V

Setting Brown Out Detector Threshold Voltage as 1.6V

Definition at line 109 of file sys.h.

## ◆ SYS_BODCTL_BODVL_1_8V

#define SYS_BODCTL_BODVL_1_8V

Setting Brown Out Detector Threshold Voltage as 1.8V

Definition at line 108 of file sys.h.

## ◆ SYS_BODCTL_BODVL_2_0V

#define SYS_BODCTL_BODVL_2_0V

Setting Brown Out Detector Threshold Voltage as 2.0V

Definition at line 107 of file sys.h.

## ◆ SYS_BODCTL_BODVL_2_2V

#define SYS_BODCTL_BODVL_2_2V

Setting Brown Out Detector Threshold Voltage as 2.2V

Definition at line 106 of file sys.h.

## ◆ SYS_BODCTL_BODVL_2_4V

#define SYS_BODCTL_BODVL_2_4V

Setting Brown Out Detector Threshold Voltage as 2.4V

Definition at line 105 of file sys.h.

## ◆ SYS_BODCTL_BODVL_2_6V

#define SYS_BODCTL_BODVL_2_6V

Setting Brown Out Detector Threshold Voltage as 2.6V

Definition at line 104 of file sys.h.

## ◆ SYS_BODCTL_BODVL_2_8V

#define SYS_BODCTL_BODVL_2_8V

Setting Brown Out Detector Threshold Voltage as 2.8V

Definition at line 103 of file sys.h.

## ◆ SYS_BODCTL_BODVL_3_0V

#define SYS_BODCTL_BODVL_3_0V

Setting Brown Out Detector Threshold Voltage as 3.0V

Definition at line 102 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_ACMP1_P0

#define SYS_GPA_MFPH_PA10MFP_ACMP1_P0

Analog comparator1 positive input pin.

Definition at line 291 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_BPWM0_CH1

#define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1

BPWM0 channel1 output/capture input.

Definition at line 301 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_DAC0_ST

#define SYS_GPA_MFPH_PA10MFP_DAC0_ST

DAC0 external trigger input.

Definition at line 305 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_EADC1_CH6

#define SYS_GPA_MFPH_PA10MFP_EADC1_CH6

EADC1 channel6 analog input.

Definition at line 293 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_EBI_nWR

#define SYS_GPA_MFPH_PA10MFP_EBI_nWR

EBI write enable output pin.

Definition at line 294 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_ECAP0_IC0

#define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0

Input 0 of enhanced capture unit 0.

Definition at line 303 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_GPIO

#define SYS_GPA_MFPH_PA10MFP_GPIO

General purpose digital I/O pin.

Definition at line 290 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_I2C2_SDA

#define SYS_GPA_MFPH_PA10MFP_I2C2_SDA

I2C2 data input/output pin.

Definition at line 299 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_OPA1_O

#define SYS_GPA_MFPH_PA10MFP_OPA1_O

Operational amplifier output pin.

Definition at line 292 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_QEI1_INDEX

#define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX

Quadrature encoder index input of QEI Unit 1.

Definition at line 302 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_SC2_RST

#define SYS_GPA_MFPH_PA10MFP_SC2_RST

SmartCard2 reset pin.

Definition at line 295 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_SD1_DAT2

#define SYS_GPA_MFPH_PA10MFP_SD1_DAT2

SD/SDIO 1 data line bit 2.

Definition at line 297 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_SPI2_CLK

#define SYS_GPA_MFPH_PA10MFP_SPI2_CLK

SPI2 serial clock pin.

Definition at line 296 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_SWDH_CLK

#define SYS_GPA_MFPH_PA10MFP_SWDH_CLK

SWD Host interface clock output pin.

Definition at line 306 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_TM1_EXT

#define SYS_GPA_MFPH_PA10MFP_TM1_EXT

Timer1 event counter input / toggle output

Definition at line 304 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_UART6_RXD

#define SYS_GPA_MFPH_PA10MFP_UART6_RXD

Data receiver input pin for UART6.

Definition at line 300 of file sys.h.

## ◆ SYS_GPA_MFPH_PA10MFP_USCI0_DAT0

#define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0

USCI0 data0 pin.

Definition at line 298 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_ACMP0_P0

#define SYS_GPA_MFPH_PA11MFP_ACMP0_P0

Analog comparator0 positive input pin.

Definition at line 308 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_BPWM0_CH0

#define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0

BPWM0 channel0 output/capture input.

Definition at line 317 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_DAC1_ST

#define SYS_GPA_MFPH_PA11MFP_DAC1_ST

DAC1 external trigger input.

Definition at line 320 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_EADC1_CH7

#define SYS_GPA_MFPH_PA11MFP_EADC1_CH7

EADC1 channel7 analog input.

Definition at line 309 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_EBI_nRD

#define SYS_GPA_MFPH_PA11MFP_EBI_nRD

EBI read enable output pin.

Definition at line 310 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT

#define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT

EPWM0 counter synchronous trigger output pin.

Definition at line 318 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_GPIO

#define SYS_GPA_MFPH_PA11MFP_GPIO

General purpose digital I/O pin.

Definition at line 307 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_I2C2_SCL

#define SYS_GPA_MFPH_PA11MFP_I2C2_SCL

I2C2 clock pin.

Definition at line 315 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_SC2_PWR

#define SYS_GPA_MFPH_PA11MFP_SC2_PWR

SmartCard2 power pin.

Definition at line 311 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_SD1_DAT3

#define SYS_GPA_MFPH_PA11MFP_SD1_DAT3

SD/SDIO 1 data line bit 3.

Definition at line 313 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_SPI2_SS

#define SYS_GPA_MFPH_PA11MFP_SPI2_SS

1st SPI2 slave select pin.

Definition at line 312 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_TM0_EXT

#define SYS_GPA_MFPH_PA11MFP_TM0_EXT

Timer0 event counter input / toggle output

Definition at line 319 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_UART6_TXD

#define SYS_GPA_MFPH_PA11MFP_UART6_TXD

Data transmitter output pin for UART6.

Definition at line 316 of file sys.h.

## ◆ SYS_GPA_MFPH_PA11MFP_USCI0_CLK

#define SYS_GPA_MFPH_PA11MFP_USCI0_CLK

USCI0 clock pin.

Definition at line 314 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_BPWM1_CH2

#define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2

BPWM1 channel2 output/capture input.

Definition at line 328 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_CAN0_TXD

#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD

CAN0 bus transmitter output.

Definition at line 326 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_GPIO

#define SYS_GPA_MFPH_PA12MFP_GPIO

General purpose digital I/O pin.

Definition at line 321 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_I2C1_SCL

#define SYS_GPA_MFPH_PA12MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 324 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_I2S0_BCLK

#define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK

I2S0 bit clock pin.

Definition at line 322 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_QEI1_INDEX

#define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX

Quadrature encoder index input of QEI Unit 1.

Definition at line 329 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_SC2_PWR

#define SYS_GPA_MFPH_PA12MFP_SC2_PWR

SmartCard2 power pin.

Definition at line 327 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_SPI2_SS

#define SYS_GPA_MFPH_PA12MFP_SPI2_SS

1st SPI2 slave select pin.

Definition at line 325 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_UART4_TXD

#define SYS_GPA_MFPH_PA12MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 323 of file sys.h.

## ◆ SYS_GPA_MFPH_PA12MFP_USB_VBUS

#define SYS_GPA_MFPH_PA12MFP_USB_VBUS

Power supply from USB Full speed host or HUB.

Definition at line 330 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_BPWM1_CH3

#define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3

BPWM1 channel3 output/capture input.

Definition at line 338 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_CAN0_RXD

#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD

CAN0 bus receiver input.

Definition at line 336 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_GPIO

#define SYS_GPA_MFPH_PA13MFP_GPIO

General purpose digital I/O pin.

Definition at line 331 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_I2C1_SDA

#define SYS_GPA_MFPH_PA13MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 334 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_I2S0_MCLK

#define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK

I2S0 master clock output pin.

Definition at line 332 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_QEI1_A

#define SYS_GPA_MFPH_PA13MFP_QEI1_A

Quadrature encoder phase A input of QEI Unit 1.

Definition at line 339 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_SC2_RST

#define SYS_GPA_MFPH_PA13MFP_SC2_RST

SmartCard2 reset pin.

Definition at line 337 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_SPI2_CLK

#define SYS_GPA_MFPH_PA13MFP_SPI2_CLK

SPI2 serial clock pin.

Definition at line 335 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_UART4_RXD

#define SYS_GPA_MFPH_PA13MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 333 of file sys.h.

## ◆ SYS_GPA_MFPH_PA13MFP_USB_D_N

#define SYS_GPA_MFPH_PA13MFP_USB_D_N

USB Full speed differential signal D-.

Definition at line 340 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_BPWM1_CH4

#define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4

BPWM1 channel4 output/capture input.

Definition at line 347 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_GPIO

#define SYS_GPA_MFPH_PA14MFP_GPIO

General purpose digital I/O pin.

Definition at line 341 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_I2C2_SCL

#define SYS_GPA_MFPH_PA14MFP_I2C2_SCL

I2C2 clock pin.

Definition at line 345 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_I2S0_DI

#define SYS_GPA_MFPH_PA14MFP_I2S0_DI

I2S0 data input.

Definition at line 342 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_QEI1_B

#define SYS_GPA_MFPH_PA14MFP_QEI1_B

Quadrature encoder phase B input of QEI Unit 1.

Definition at line 348 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_SC2_DAT

#define SYS_GPA_MFPH_PA14MFP_SC2_DAT

SmartCard2 data pin.

Definition at line 346 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_SPI2_MISO

#define SYS_GPA_MFPH_PA14MFP_SPI2_MISO

1st SPI2 MISO (Master In, Slave Out) pin.

Definition at line 344 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_UART0_TXD

#define SYS_GPA_MFPH_PA14MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 343 of file sys.h.

## ◆ SYS_GPA_MFPH_PA14MFP_USB_D_P

#define SYS_GPA_MFPH_PA14MFP_USB_D_P

USB Full speed differential signal D+.

Definition at line 349 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_BPWM1_CH5

#define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5

BPWM1 channel5 output/capture input.

Definition at line 356 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN

#define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN

EPWM0 counter synchronous trigger input pin.

Definition at line 357 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_GPIO

#define SYS_GPA_MFPH_PA15MFP_GPIO

General purpose digital I/O pin.

Definition at line 350 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_I2C2_SDA

#define SYS_GPA_MFPH_PA15MFP_I2C2_SDA

I2C2 data input/output pin.

Definition at line 354 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_I2S0_DO

#define SYS_GPA_MFPH_PA15MFP_I2S0_DO

I2S0 data output.

Definition at line 351 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_SC2_CLK

#define SYS_GPA_MFPH_PA15MFP_SC2_CLK

SmartCard2 clock pin.

Definition at line 355 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_SPI2_MOSI

#define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI

1st SPI2 MOSI (Master Out, Slave In) pin.

Definition at line 353 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_UART0_RXD

#define SYS_GPA_MFPH_PA15MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 352 of file sys.h.

## ◆ SYS_GPA_MFPH_PA15MFP_USB_OTG_ID

#define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID

USB Full speed identification.

Definition at line 358 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_BPWM0_CH3

#define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3

BPWM0 channel3 output/capture input.

Definition at line 270 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_EADC1_CH4

#define SYS_GPA_MFPH_PA8MFP_EADC1_CH4

EADC1 channel4 analog input.

Definition at line 262 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_EBI_ALE

#define SYS_GPA_MFPH_PA8MFP_EBI_ALE

EBI address latch enable output pin.

Definition at line 263 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_ECAP0_IC2

#define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2

Input 0 of enhanced capture unit 2.

Definition at line 272 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_GPIO

#define SYS_GPA_MFPH_PA8MFP_GPIO

General purpose digital I/O pin.

Definition at line 260 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_INT4

#define SYS_GPA_MFPH_PA8MFP_INT4

External interrupt4 input pin.

Definition at line 274 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_OPA1_P

#define SYS_GPA_MFPH_PA8MFP_OPA1_P

Operational amplifier positive input pin.

Definition at line 261 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_QEI1_B

#define SYS_GPA_MFPH_PA8MFP_QEI1_B

Quadrature encoder phase B input of QEI Unit 1.

Definition at line 271 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_SC2_CLK

#define SYS_GPA_MFPH_PA8MFP_SC2_CLK

SmartCard2 clock pin.

Definition at line 264 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_SD1_DAT0

#define SYS_GPA_MFPH_PA8MFP_SD1_DAT0

SD/SDIO 1 data line bit 0.

Definition at line 266 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_SPI2_MOSI

#define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI

1st SPI2 MOSI (Master Out, Slave In) pin.

Definition at line 265 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_TM3_EXT

#define SYS_GPA_MFPH_PA8MFP_TM3_EXT

Timer3 event counter input / toggle output

Definition at line 273 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_UART1_RXD

#define SYS_GPA_MFPH_PA8MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 268 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_UART7_RXD

#define SYS_GPA_MFPH_PA8MFP_UART7_RXD

Data receiver input pin for UART7.

Definition at line 269 of file sys.h.

## ◆ SYS_GPA_MFPH_PA8MFP_USCI0_CTL1

#define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1

USCI0 control1 pin.

Definition at line 267 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_BPWM0_CH2

#define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2

BPWM0 channel2 output/capture input.

Definition at line 285 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_EADC1_CH5

#define SYS_GPA_MFPH_PA9MFP_EADC1_CH5

EADC1 channel5 analog input.

Definition at line 277 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_EBI_MCLK

#define SYS_GPA_MFPH_PA9MFP_EBI_MCLK

EBI external clock output pin.

Definition at line 278 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_ECAP0_IC1

#define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1

Input 1 of enhanced capture unit 0.

Definition at line 287 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_GPIO

#define SYS_GPA_MFPH_PA9MFP_GPIO

General purpose digital I/O pin.

Definition at line 275 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_OPA1_N

#define SYS_GPA_MFPH_PA9MFP_OPA1_N

Operational amplifier negative input pin.

Definition at line 276 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_QEI1_A

#define SYS_GPA_MFPH_PA9MFP_QEI1_A

Quadrature encoder phase A input of QEI Unit 1.

Definition at line 286 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_SC2_DAT

#define SYS_GPA_MFPH_PA9MFP_SC2_DAT

SmartCard2 data pin.

Definition at line 279 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_SD1_DAT1

#define SYS_GPA_MFPH_PA9MFP_SD1_DAT1

SD/SDIO 1 data line bit 1.

Definition at line 281 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_SPI2_MISO

#define SYS_GPA_MFPH_PA9MFP_SPI2_MISO

1st SPI2 MISO (Master In, Slave Out) pin.

Definition at line 280 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_SWDH_DAT

#define SYS_GPA_MFPH_PA9MFP_SWDH_DAT

SWD Host interface input/output bus bit.

Definition at line 289 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_TM2_EXT

#define SYS_GPA_MFPH_PA9MFP_TM2_EXT

Timer2 event counter input / toggle output

Definition at line 288 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_UART1_TXD

#define SYS_GPA_MFPH_PA9MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 283 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_UART7_TXD

#define SYS_GPA_MFPH_PA9MFP_UART7_TXD

Data transmitter output pin for UART7.

Definition at line 284 of file sys.h.

## ◆ SYS_GPA_MFPH_PA9MFP_USCI0_DAT1

#define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1

USCI0 data1 pin.

Definition at line 282 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_BPWM0_CH0

#define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0

BPWM0 channel0 output/capture input.

Definition at line 162 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_CCAP_DATA6

#define SYS_GPA_MFPL_PA0MFP_CCAP_DATA6

Sensor pixel data6 input pin.

Definition at line 161 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_DAC0_ST

#define SYS_GPA_MFPL_PA0MFP_DAC0_ST

DAC0 external trigger input.

Definition at line 164 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_EPWM0_CH5

#define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5

EPWM0 channel5 output/capture input.

Definition at line 163 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_GPIO

#define SYS_GPA_MFPL_PA0MFP_GPIO

General purpose digital I/O pin.

Definition at line 152 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_I2C2_SDA

#define SYS_GPA_MFPL_PA0MFP_I2C2_SDA

I2C2 data input/output pin.

Definition at line 160 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0

#define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0

1st QSPI0 MOSI (Master Out, Slave In) pin.

Definition at line 154 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_SC0_CLK

#define SYS_GPA_MFPL_PA0MFP_SC0_CLK

SmartCard0 clock pin.

Definition at line 157 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_SD1_DAT0

#define SYS_GPA_MFPL_PA0MFP_SD1_DAT0

SD/SDIO 1 data line bit 0.

Definition at line 156 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_SPI0_MOSI

#define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI

1st SPI0 MOSI (Master Out, Slave In) pin.

Definition at line 155 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_SPIM_MOSI

#define SYS_GPA_MFPL_PA0MFP_SPIM_MOSI

1st SPIM MOSI (Master Out, Slave In) pin.

Definition at line 153 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_UART0_RXD

#define SYS_GPA_MFPL_PA0MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 158 of file sys.h.

## ◆ SYS_GPA_MFPL_PA0MFP_UART1_nRTS

#define SYS_GPA_MFPL_PA0MFP_UART1_nRTS

Request to Send output pin for UART1.

Definition at line 159 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_BPWM0_CH1

#define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1

BPWM0 channel1 output/capture input.

Definition at line 175 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_CCAP_DATA7

#define SYS_GPA_MFPL_PA1MFP_CCAP_DATA7

Sensor pixel data7 input pin.

Definition at line 174 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_DAC1_ST

#define SYS_GPA_MFPL_PA1MFP_DAC1_ST

DAC1 external trigger input.

Definition at line 177 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_EPWM0_CH4

#define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4

EPWM0 channel4 output/capture input.

Definition at line 176 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_GPIO

#define SYS_GPA_MFPL_PA1MFP_GPIO

General purpose digital I/O pin.

Definition at line 165 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_I2C2_SCL

#define SYS_GPA_MFPL_PA1MFP_I2C2_SCL

I2C2 clock pin.

Definition at line 173 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0

#define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0

1st QSPI0 MISO (Master In, Slave Out) pin.

Definition at line 167 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_SC0_DAT

#define SYS_GPA_MFPL_PA1MFP_SC0_DAT

SmartCard0 data pin.

Definition at line 170 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_SD1_DAT1

#define SYS_GPA_MFPL_PA1MFP_SD1_DAT1

SD/SDIO 1 data line bit 1.

Definition at line 169 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_SPI0_MISO

#define SYS_GPA_MFPL_PA1MFP_SPI0_MISO

1st SPI0 MISO (Master In, Slave Out) pin.

Definition at line 168 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_SPIM_MISO

#define SYS_GPA_MFPL_PA1MFP_SPIM_MISO

1st SPIM MISO (Master In, Slave Out) pin.

Definition at line 166 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_UART0_TXD

#define SYS_GPA_MFPL_PA1MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 171 of file sys.h.

## ◆ SYS_GPA_MFPL_PA1MFP_UART1_nCTS

#define SYS_GPA_MFPL_PA1MFP_UART1_nCTS

Clear to Send input pin for UART1.

Definition at line 172 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_BPWM0_CH2

#define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2

BPWM0 channel2 output/capture input.

Definition at line 188 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_EPWM0_CH3

#define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3

EPWM0 channel3 output/capture input.

Definition at line 189 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_GPIO

#define SYS_GPA_MFPL_PA2MFP_GPIO

General purpose digital I/O pin.

Definition at line 178 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS

#define SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS

I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 187 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_I2C1_SDA

#define SYS_GPA_MFPL_PA2MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 186 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_QSPI0_CLK

#define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK

QSPI0 serial clock pin.

Definition at line 180 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_SC0_RST

#define SYS_GPA_MFPL_PA2MFP_SC0_RST

SmartCard0 reset pin.

Definition at line 183 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_SD1_DAT2

#define SYS_GPA_MFPL_PA2MFP_SD1_DAT2

SD/SDIO 1 data line bit 2.

Definition at line 182 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_SPI0_CLK

#define SYS_GPA_MFPL_PA2MFP_SPI0_CLK

SPI0 serial clock pin.

Definition at line 181 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_SPIM_CLK

#define SYS_GPA_MFPL_PA2MFP_SPIM_CLK

SPIM serial clock pin.

Definition at line 179 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_UART1_RXD

#define SYS_GPA_MFPL_PA2MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 185 of file sys.h.

## ◆ SYS_GPA_MFPL_PA2MFP_UART4_RXD

#define SYS_GPA_MFPL_PA2MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 184 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_BPWM0_CH3

#define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3

BPWM0 channel3 output/capture input.

Definition at line 200 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_EPWM0_CH2

#define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2

EPWM0 channel2 output/capture input.

Definition at line 201 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1

#define SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1

Brake input pin 1 of EPWM1.

Definition at line 203 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_GPIO

#define SYS_GPA_MFPL_PA3MFP_GPIO

General purpose digital I/O pin.

Definition at line 190 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL

#define SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL

I2C0 SMBus SMBALTER# pin.

Definition at line 199 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_I2C1_SCL

#define SYS_GPA_MFPL_PA3MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 198 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_QEI0_B

#define SYS_GPA_MFPL_PA3MFP_QEI0_B

Quadrature encoder phase B input of QEI Unit 0.

Definition at line 202 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_QSPI0_SS

#define SYS_GPA_MFPL_PA3MFP_QSPI0_SS

1st QSPI0 slave select pin.

Definition at line 192 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_SC0_PWR

#define SYS_GPA_MFPL_PA3MFP_SC0_PWR

SmartCard0 power pin.

Definition at line 195 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_SD1_DAT3

#define SYS_GPA_MFPL_PA3MFP_SD1_DAT3

SD/SDIO 1 data line bit 3.

Definition at line 194 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_SPI0_SS

#define SYS_GPA_MFPL_PA3MFP_SPI0_SS

1st SPI0 slave select pin.

Definition at line 193 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_SPIM_SS

#define SYS_GPA_MFPL_PA3MFP_SPIM_SS

1st SPIM slave select pin.

Definition at line 191 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_UART1_TXD

#define SYS_GPA_MFPL_PA3MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 197 of file sys.h.

## ◆ SYS_GPA_MFPL_PA3MFP_UART4_TXD

#define SYS_GPA_MFPL_PA3MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 196 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_BPWM0_CH4

#define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4

BPWM0 channel4 output/capture input.

Definition at line 215 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_CAN0_RXD

#define SYS_GPA_MFPL_PA4MFP_CAN0_RXD

CAN0 bus receiver input.

Definition at line 213 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_EPWM0_CH1

#define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1

EPWM0 channel1 output/capture input.

Definition at line 216 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_GPIO

#define SYS_GPA_MFPL_PA4MFP_GPIO

General purpose digital I/O pin.

Definition at line 204 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_I2C0_SDA

#define SYS_GPA_MFPL_PA4MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 212 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_QEI0_A

#define SYS_GPA_MFPL_PA4MFP_QEI0_A

Quadrature encoder phase A input of QEI Unit 0.

Definition at line 217 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1

#define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1

2nd QSPI0 MOSI (Master Out, Slave In) pin.

Definition at line 206 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_SC0_nCD

#define SYS_GPA_MFPL_PA4MFP_SC0_nCD

SmartCard0 card detect pin.

Definition at line 209 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_SD1_CLK

#define SYS_GPA_MFPL_PA4MFP_SD1_CLK

SD/SDIO 1 clock.

Definition at line 208 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK

#define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK

SPI0 I2S master clock output pin.

Definition at line 207 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_SPIM_D3

#define SYS_GPA_MFPL_PA4MFP_SPIM_D3

SPIM data 3 pin for Quad Mode I/O.

Definition at line 205 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_UART0_nRTS

#define SYS_GPA_MFPL_PA4MFP_UART0_nRTS

Request to Send output pin for UART0.

Definition at line 210 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_UART0_RXD

#define SYS_GPA_MFPL_PA4MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 214 of file sys.h.

## ◆ SYS_GPA_MFPL_PA4MFP_UART5_RXD

#define SYS_GPA_MFPL_PA4MFP_UART5_RXD

Data receiver input pin for UART5.

Definition at line 211 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_BPWM0_CH5

#define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5

BPWM0 channel5 output/capture input.

Definition at line 229 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_CAN0_TXD

#define SYS_GPA_MFPL_PA5MFP_CAN0_TXD

CAN0 bus transmitter output.

Definition at line 227 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_EPWM0_CH0

#define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0

EPWM0 channel0 output/capture input.

Definition at line 230 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_GPIO

#define SYS_GPA_MFPL_PA5MFP_GPIO

General purpose digital I/O pin.

Definition at line 218 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_I2C0_SCL

#define SYS_GPA_MFPL_PA5MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 226 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_QEI0_INDEX

#define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX

Quadrature encoder index input of QEI Unit 0.

Definition at line 231 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1

#define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1

2nd QSPI0 MISO (Master In, Slave Out) pin.

Definition at line 220 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_SC2_nCD

#define SYS_GPA_MFPL_PA5MFP_SC2_nCD

SmartCard2 card detect pin.

Definition at line 223 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_SD1_CMD

#define SYS_GPA_MFPL_PA5MFP_SD1_CMD

SD/SDIO 1 command/response.

Definition at line 222 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK

#define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK

SPI1 I2S master clock output pin.

Definition at line 221 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_SPIM_D2

#define SYS_GPA_MFPL_PA5MFP_SPIM_D2

SPIM data 2 pin for Quad Mode I/O.

Definition at line 219 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_UART0_nCTS

#define SYS_GPA_MFPL_PA5MFP_UART0_nCTS

Clear to Send input pin for UART0.

Definition at line 224 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_UART0_TXD

#define SYS_GPA_MFPL_PA5MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 228 of file sys.h.

## ◆ SYS_GPA_MFPL_PA5MFP_UART5_TXD

#define SYS_GPA_MFPL_PA5MFP_UART5_TXD

Data transmitter output pin for UART5.

Definition at line 225 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT

#define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT

Analog comparator1 window latch input pin.

Definition at line 243 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_BPWM1_CH3

#define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3

BPWM1 channel3 output/capture input.

Definition at line 242 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_EBI_AD6

#define SYS_GPA_MFPL_PA6MFP_EBI_AD6

EBI address/data bus bit6.

Definition at line 233 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR

#define SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR

RMII Receive Data error.

Definition at line 234 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_EPWM1_CH5

#define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5

EPWM1 channel5 output/capture input.

Definition at line 241 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_GPIO

#define SYS_GPA_MFPL_PA6MFP_GPIO

General purpose digital I/O pin.

Definition at line 232 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_I2C1_SDA

#define SYS_GPA_MFPL_PA6MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 239 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_INT0

#define SYS_GPA_MFPL_PA6MFP_INT0

External interrupt0 input pin.

Definition at line 245 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_QSPI1_MOSI1

#define SYS_GPA_MFPL_PA6MFP_QSPI1_MOSI1

2nd QSPI1 MOSI (Master Out, Slave In) pin.

Definition at line 240 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_SC2_CLK

#define SYS_GPA_MFPL_PA6MFP_SC2_CLK

SmartCard2 clock pin.

Definition at line 237 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_SD1_nCD

#define SYS_GPA_MFPL_PA6MFP_SD1_nCD

SD/SDIO 1 card detect

Definition at line 236 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_SPI1_SS

#define SYS_GPA_MFPL_PA6MFP_SPI1_SS

1st SPI1 slave select pin.

Definition at line 235 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_TM3

#define SYS_GPA_MFPL_PA6MFP_TM3

Timer3 event counter input / toggle output

Definition at line 244 of file sys.h.

## ◆ SYS_GPA_MFPL_PA6MFP_UART0_RXD

#define SYS_GPA_MFPL_PA6MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 238 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT

#define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT

Analog comparator0 window latch input pin.

Definition at line 256 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_BPWM1_CH2

#define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2

BPWM1 channel2 output/capture input.

Definition at line 255 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_EBI_AD7

#define SYS_GPA_MFPL_PA7MFP_EBI_AD7

EBI address/data bus bit7.

Definition at line 247 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV

#define SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV

MII Receive Data Valid / RMII CRS_DV input.

Definition at line 248 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_EPWM1_CH4

#define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4

EPWM1 channel4 output/capture input.

Definition at line 254 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_GPIO

#define SYS_GPA_MFPL_PA7MFP_GPIO

General purpose digital I/O pin.

Definition at line 246 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_I2C1_SCL

#define SYS_GPA_MFPL_PA7MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 252 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_INT1

#define SYS_GPA_MFPL_PA7MFP_INT1

External interrupt1 input pin.

Definition at line 258 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_QSPI1_MISO1

#define SYS_GPA_MFPL_PA7MFP_QSPI1_MISO1

2nd QSPI1 MISO (Master In, Slave Out) pin.

Definition at line 253 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_SC2_DAT

#define SYS_GPA_MFPL_PA7MFP_SC2_DAT

SmartCard2 data pin.

Definition at line 250 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_SPI1_CLK

#define SYS_GPA_MFPL_PA7MFP_SPI1_CLK

SPI1 serial clock pin.

Definition at line 249 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_TM2

#define SYS_GPA_MFPL_PA7MFP_TM2

Timer2 event counter input / toggle output

Definition at line 257 of file sys.h.

## ◆ SYS_GPA_MFPL_PA7MFP_UART0_TXD

#define SYS_GPA_MFPL_PA7MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 251 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_BPWM1_CH1

#define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1

BPWM1 channel1 output/capture input.

Definition at line 525 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_CAN0_RXD

#define SYS_GPB_MFPH_PB10MFP_CAN0_RXD

CAN0 bus receiver input.

Definition at line 524 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_CCAP_VSYNC

#define SYS_GPB_MFPH_PB10MFP_CCAP_VSYNC

Sensor vertical synchronization input pin.

Definition at line 527 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_EADC0_CH10

#define SYS_GPB_MFPH_PB10MFP_EADC0_CH10

EADC0 channel1 analog input.

Definition at line 517 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_EBI_ADR17

#define SYS_GPB_MFPH_PB10MFP_EBI_ADR17

EBI address/data bus bit*.

Definition at line 518 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO

#define SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO

RMII Management Data I/O.

Definition at line 519 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_GPIO

#define SYS_GPB_MFPH_PB10MFP_GPIO

General purpose digital I/O pin.

Definition at line 516 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN

#define SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN

Power supply from USB High speed host or HUB.

Definition at line 528 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_I2C1_SDA

#define SYS_GPB_MFPH_PB10MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 523 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_SPI3_SS

#define SYS_GPB_MFPH_PB10MFP_SPI3_SS

1st SPI3 slave select pin.

Definition at line 526 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_UART0_nRTS

#define SYS_GPB_MFPH_PB10MFP_UART0_nRTS

Request to Send output pin for UART0.

Definition at line 521 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_UART4_RXD

#define SYS_GPB_MFPH_PB10MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 522 of file sys.h.

## ◆ SYS_GPB_MFPH_PB10MFP_USCI1_CTL0

#define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0

USCI1 control0 pin.

Definition at line 520 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_BPWM1_CH0

#define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0

BPWM1 channel0 output/capture input.

Definition at line 538 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_CAN0_TXD

#define SYS_GPB_MFPH_PB11MFP_CAN0_TXD

CAN0 bus transmitter output.

Definition at line 536 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_CCAP_SFIELD

#define SYS_GPB_MFPH_PB11MFP_CCAP_SFIELD

Even/Odd Field Flag input pin.

Definition at line 540 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_EADC0_CH11

#define SYS_GPB_MFPH_PB11MFP_EADC0_CH11

EADC0 channel1 analog input.

Definition at line 530 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_EBI_ADR16

#define SYS_GPB_MFPH_PB11MFP_EBI_ADR16

EBI address/data bus bit*.

Definition at line 531 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC

#define SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC

RMII Management Data Clock.

Definition at line 532 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_GPIO

#define SYS_GPB_MFPH_PB11MFP_GPIO

General purpose digital I/O pin.

Definition at line 529 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST

#define SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST

Power supply from USB High speed host or HUB.

Definition at line 541 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_I2C1_SCL

#define SYS_GPB_MFPH_PB11MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 535 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK

#define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK

SPI0 I2S master clock output pin.

Definition at line 537 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_SPI3_CLK

#define SYS_GPB_MFPH_PB11MFP_SPI3_CLK

SPI3 serial clock pin.

Definition at line 539 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_UART0_nCTS

#define SYS_GPB_MFPH_PB11MFP_UART0_nCTS

Clear to Send input pin for UART0.

Definition at line 533 of file sys.h.

## ◆ SYS_GPB_MFPH_PB11MFP_UART4_TXD

#define SYS_GPB_MFPH_PB11MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 534 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_ACMP0_P2

#define SYS_GPB_MFPH_PB12MFP_ACMP0_P2

Analog comparator0 positive input pin.

Definition at line 543 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_ACMP1_P2

#define SYS_GPB_MFPH_PB12MFP_ACMP1_P2

Analog comparator1 positive input pin.

Definition at line 544 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_CCAP_SCLK

#define SYS_GPB_MFPH_PB12MFP_CCAP_SCLK

Sensor pixel clock(to sensor) output pin.

Definition at line 556 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_DAC0_OUT

#define SYS_GPB_MFPH_PB12MFP_DAC0_OUT

DAC0 channel analog output.

Definition at line 545 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_EADC0_CH12

#define SYS_GPB_MFPH_PB12MFP_EADC0_CH12

EADC0 channel1 analog input.

Definition at line 546 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_EADC1_CH12

#define SYS_GPB_MFPH_PB12MFP_EADC1_CH12

EADC1 channel1 analog input.

Definition at line 547 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_EBI_AD15

#define SYS_GPB_MFPH_PB12MFP_EBI_AD15

EBI address/data bus bit1.

Definition at line 548 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_EPWM1_CH3

#define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3

EPWM1 channel3 output/capture input.

Definition at line 557 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3

#define SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3

ETM Rx input bus bit3.

Definition at line 558 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_GPIO

#define SYS_GPB_MFPH_PB12MFP_GPIO

General purpose digital I/O pin.

Definition at line 542 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_I2C2_SDA

#define SYS_GPB_MFPH_PB12MFP_I2C2_SDA

I2C2 data input/output pin.

Definition at line 554 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_SC1_CLK

#define SYS_GPB_MFPH_PB12MFP_SC1_CLK

SmartCard1 clock pin.

Definition at line 549 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_SD0_nCD

#define SYS_GPB_MFPH_PB12MFP_SD0_nCD

SD/SDIO 0 card detect.

Definition at line 555 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_SPI0_MOSI

#define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI

1st SPI0 MOSI (Master Out, Slave In) pin.

Definition at line 550 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_TM3_EXT

#define SYS_GPB_MFPH_PB12MFP_TM3_EXT

Timer3 event counter input / toggle output

Definition at line 559 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_UART0_RXD

#define SYS_GPB_MFPH_PB12MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 552 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_UART3_nCTS

#define SYS_GPB_MFPH_PB12MFP_UART3_nCTS

Clear to Send input pin for UART3.

Definition at line 553 of file sys.h.

## ◆ SYS_GPB_MFPH_PB12MFP_USCI0_CLK

#define SYS_GPB_MFPH_PB12MFP_USCI0_CLK

USCI0 clock pin.

Definition at line 551 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_ACMP0_P3

#define SYS_GPB_MFPH_PB13MFP_ACMP0_P3

Analog comparator0 positive input pin.

Definition at line 561 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_ACMP1_P3

#define SYS_GPB_MFPH_PB13MFP_ACMP1_P3

Analog comparator1 positive input pin.

Definition at line 562 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_CCAP_PIXCLK

#define SYS_GPB_MFPH_PB13MFP_CCAP_PIXCLK

Sensor pixel clock(from sensor) input pin.

Definition at line 573 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_DAC1_OUT

#define SYS_GPB_MFPH_PB13MFP_DAC1_OUT

DAC1 channel analog output.

Definition at line 563 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_EADC0_CH13

#define SYS_GPB_MFPH_PB13MFP_EADC0_CH13

EADC0 channel1 analog input.

Definition at line 564 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_EADC1_CH13

#define SYS_GPB_MFPH_PB13MFP_EADC1_CH13

EADC1 channel1 analog input.

Definition at line 565 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_EBI_AD14

#define SYS_GPB_MFPH_PB13MFP_EBI_AD14

EBI address/data bus bit1.

Definition at line 566 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_EPWM1_CH2

#define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2

EPWM1 channel2 output/capture input.

Definition at line 574 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2

#define SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2

ETM Rx input bus bit2.

Definition at line 575 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_GPIO

#define SYS_GPB_MFPH_PB13MFP_GPIO

General purpose digital I/O pin.

Definition at line 560 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_I2C2_SCL

#define SYS_GPB_MFPH_PB13MFP_I2C2_SCL

I2C2 clock pin.

Definition at line 572 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_SC1_DAT

#define SYS_GPB_MFPH_PB13MFP_SC1_DAT

SmartCard1 data pin.

Definition at line 567 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_SPI0_MISO

#define SYS_GPB_MFPH_PB13MFP_SPI0_MISO

1st SPI0 MISO (Master In, Slave Out) pin.

Definition at line 568 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_TM2_EXT

#define SYS_GPB_MFPH_PB13MFP_TM2_EXT

Timer2 event counter input / toggle output

Definition at line 576 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_UART0_TXD

#define SYS_GPB_MFPH_PB13MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 570 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_UART3_nRTS

#define SYS_GPB_MFPH_PB13MFP_UART3_nRTS

Request to Send output pin for UART3.

Definition at line 571 of file sys.h.

## ◆ SYS_GPB_MFPH_PB13MFP_USCI0_DAT0

#define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0

USCI0 data0 pin.

Definition at line 569 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_CLKO

#define SYS_GPB_MFPH_PB14MFP_CLKO

Clock Output pin.

Definition at line 590 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_EADC0_CH14

#define SYS_GPB_MFPH_PB14MFP_EADC0_CH14

EADC0 channel1 analog input.

Definition at line 578 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_EADC1_CH14

#define SYS_GPB_MFPH_PB14MFP_EADC1_CH14

EADC1 channel1 analog input.

Definition at line 579 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_EBI_AD13

#define SYS_GPB_MFPH_PB14MFP_EBI_AD13

EBI address/data bus bit1.

Definition at line 580 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_EPWM1_CH1

#define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1

EPWM1 channel1 output/capture input.

Definition at line 587 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1

#define SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1

ETM Rx input bus bit1.

Definition at line 588 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_GPIO

#define SYS_GPB_MFPH_PB14MFP_GPIO

General purpose digital I/O pin.

Definition at line 577 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS

#define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS

I2C2 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 586 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_SC1_RST

#define SYS_GPB_MFPH_PB14MFP_SC1_RST

SmartCard1 reset pin.

Definition at line 581 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_SPI0_CLK

#define SYS_GPB_MFPH_PB14MFP_SPI0_CLK

SPI0 serial clock pin.

Definition at line 582 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_TM1_EXT

#define SYS_GPB_MFPH_PB14MFP_TM1_EXT

Timer1 event counter input / toggle output

Definition at line 589 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_UART0_nRTS

#define SYS_GPB_MFPH_PB14MFP_UART0_nRTS

Request to Send output pin for UART0.

Definition at line 584 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_UART3_RXD

#define SYS_GPB_MFPH_PB14MFP_UART3_RXD

Data receiver input pin for UART3.

Definition at line 585 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST

#define SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST (0x0FUL<<SYS_GPB_MFPH_PB14MFP_Pos)

Power supply from USB Full speed host or HUB.

Definition at line 591 of file sys.h.

## ◆ SYS_GPB_MFPH_PB14MFP_USCI0_DAT1

#define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1

USCI0 data1 pin.

Definition at line 583 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_EADC0_CH15

#define SYS_GPB_MFPH_PB15MFP_EADC0_CH15

EADC0 channel1 analog input.

Definition at line 593 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_EADC1_CH15

#define SYS_GPB_MFPH_PB15MFP_EADC1_CH15

EADC1 channel1 analog input.

Definition at line 594 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_EBI_AD12

#define SYS_GPB_MFPH_PB15MFP_EBI_AD12

EBI address/data bus bit1.

Definition at line 595 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_EPWM0_BRAKE1

#define SYS_GPB_MFPH_PB15MFP_EPWM0_BRAKE1

Brake input pin 1 of EPWM0.

Definition at line 602 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_EPWM1_CH0

#define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0

EPWM1 channel0 output/capture input.

Definition at line 603 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0

#define SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0

ETM Rx input bus bit0.

Definition at line 604 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_GPIO

#define SYS_GPB_MFPH_PB15MFP_GPIO

General purpose digital I/O pin.

Definition at line 592 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN

#define SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN

Power supply from USB High speed host or HUB.

Definition at line 607 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL

#define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL

I2C2 SMBus SMBALTER# pin.

Definition at line 601 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_SC1_PWR

#define SYS_GPB_MFPH_PB15MFP_SC1_PWR

SmartCard1 power pin.

Definition at line 596 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_SPI0_SS

#define SYS_GPB_MFPH_PB15MFP_SPI0_SS

1st SPI0 slave select pin.

Definition at line 597 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_TM0_EXT

#define SYS_GPB_MFPH_PB15MFP_TM0_EXT

Timer0 event counter input / toggle output

Definition at line 605 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_UART0_nCTS

#define SYS_GPB_MFPH_PB15MFP_UART0_nCTS

Clear to Send input pin for UART0.

Definition at line 599 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_UART3_TXD

#define SYS_GPB_MFPH_PB15MFP_UART3_TXD

Data transmitter output pin for UART3.

Definition at line 600 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN

#define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN

Power supply from USB Full speed host or HUB.

Definition at line 606 of file sys.h.

## ◆ SYS_GPB_MFPH_PB15MFP_USCI0_CTL1

#define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1

USCI0 control1 pin.

Definition at line 598 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_BPWM1_CH3

#define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3

BPWM1 channel3 output/capture input.

Definition at line 497 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_CAN2_RXD

#define SYS_GPB_MFPH_PB8MFP_CAN2_RXD

CAN2 bus receiver input.

Definition at line 499 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_EADC0_CH8

#define SYS_GPB_MFPH_PB8MFP_EADC0_CH8

EADC0 channel8 analog input.

Definition at line 488 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_EBI_ADR19

#define SYS_GPB_MFPH_PB8MFP_EBI_ADR19

EBI address/data bus bit*.

Definition at line 489 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1

#define SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1

RMII Transmit Data bus bit 1.

Definition at line 490 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_GPIO

#define SYS_GPB_MFPH_PB8MFP_GPIO

General purpose digital I/O pin.

Definition at line 487 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_I2C0_SDA

#define SYS_GPB_MFPH_PB8MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 496 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS

#define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS

I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 494 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_INT6

#define SYS_GPB_MFPH_PB8MFP_INT6

External interrupt6 input pin.

Definition at line 500 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_SPI3_MOSI

#define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI

1st SPI3 MOSI (Master Out, Slave In) pin.

Definition at line 498 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_UART0_RXD

#define SYS_GPB_MFPH_PB8MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 492 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_UART1_nRTS

#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS

Request to Send output pin for UART1.

Definition at line 493 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_UART7_RXD

#define SYS_GPB_MFPH_PB8MFP_UART7_RXD

Data receiver input pin for UART7.

Definition at line 495 of file sys.h.

## ◆ SYS_GPB_MFPH_PB8MFP_USCI1_CLK

#define SYS_GPB_MFPH_PB8MFP_USCI1_CLK

USCI1 clock pin.

Definition at line 491 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_BPWM1_CH2

#define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2

BPWM1 channel2 output/capture input.

Definition at line 511 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_CAN2_TXD

#define SYS_GPB_MFPH_PB9MFP_CAN2_TXD

CAN2 bus transmitter output.

Definition at line 513 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_CCAP_HSYNC

#define SYS_GPB_MFPH_PB9MFP_CCAP_HSYNC

Sensor horizontal synchronization input pin.

Definition at line 515 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_EADC0_CH9

#define SYS_GPB_MFPH_PB9MFP_EADC0_CH9

EADC0 channel9 analog input.

Definition at line 502 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_EBI_ADR18

#define SYS_GPB_MFPH_PB9MFP_EBI_ADR18

EBI address/data bus bit*.

Definition at line 503 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0

#define SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0

RMII Transmit Data bus bit 0.

Definition at line 504 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_GPIO

#define SYS_GPB_MFPH_PB9MFP_GPIO

General purpose digital I/O pin.

Definition at line 501 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_I2C0_SCL

#define SYS_GPB_MFPH_PB9MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 510 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL

#define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL

I2C1 SMBus SMBALTER# pin

Definition at line 508 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_INT7

#define SYS_GPB_MFPH_PB9MFP_INT7

External interrupt7 input pin.

Definition at line 514 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_SPI3_MISO

#define SYS_GPB_MFPH_PB9MFP_SPI3_MISO

1st SPI3 MISO (Master In, Slave Out) pin.

Definition at line 512 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_UART0_TXD

#define SYS_GPB_MFPH_PB9MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 506 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_UART1_nCTS

#define SYS_GPB_MFPH_PB9MFP_UART1_nCTS

Clear to Send input pin for UART1.

Definition at line 507 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_UART7_TXD

#define SYS_GPB_MFPH_PB9MFP_UART7_TXD

Data transmitter output pin for UART7.

Definition at line 509 of file sys.h.

## ◆ SYS_GPB_MFPH_PB9MFP_USCI1_CTL1

#define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1

USCI1 control1 pin.

Definition at line 505 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_EADC0_CH0

#define SYS_GPB_MFPL_PB0MFP_EADC0_CH0

EADC0 channel0 analog input.

Definition at line 361 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_EADC1_CH8

#define SYS_GPB_MFPL_PB0MFP_EADC1_CH8

EADC1 channel8 analog input.

Definition at line 362 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_EBI_ADR9

#define SYS_GPB_MFPL_PB0MFP_EBI_ADR9

EBI address/data bus bit*.

Definition at line 364 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1

#define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1

Brake input pin 1 of EPWM0.

Definition at line 372 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_EPWM0_CH5

#define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5

EPWM0 channel5 output/capture input.

Definition at line 370 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_EPWM1_CH5

#define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5

EPWM1 channel5 output/capture input.

Definition at line 371 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_GPIO

#define SYS_GPB_MFPL_PB0MFP_GPIO

General purpose digital I/O pin.

Definition at line 360 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_I2C1_SDA

#define SYS_GPB_MFPL_PB0MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 369 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_OPA0_P

#define SYS_GPB_MFPL_PB0MFP_OPA0_P

Operational amplifier positive input pin.

Definition at line 363 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_SD0_CMD

#define SYS_GPB_MFPL_PB0MFP_SD0_CMD

SD/SDIO 0 command/response.

Definition at line 365 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK

#define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK

SPI0 I2S master clock output pin.

Definition at line 368 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK

#define SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK

SPI2 I2S master clock output pin.

Definition at line 366 of file sys.h.

## ◆ SYS_GPB_MFPL_PB0MFP_UART2_RXD

#define SYS_GPB_MFPL_PB0MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 367 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_EADC0_CH1

#define SYS_GPB_MFPL_PB1MFP_EADC0_CH1

EADC0 channel1 analog input.

Definition at line 374 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_EADC1_CH9

#define SYS_GPB_MFPL_PB1MFP_EADC1_CH9

EADC1 channel9 analog input.

Definition at line 376 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_EBI_ADR8

#define SYS_GPB_MFPL_PB1MFP_EBI_ADR8

EBI address/data bus bit*.

Definition at line 377 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR

#define SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR

RMII Receive Data error.

Definition at line 379 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0

#define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0

Brake input pin 0 of EPWM0.

Definition at line 388 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_EPWM0_CH4

#define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4

EPWM0 channel4 output/capture input.

Definition at line 386 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_EPWM1_CH4

#define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4

EPWM1 channel4 output/capture input.

Definition at line 387 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_GPIO

#define SYS_GPB_MFPL_PB1MFP_GPIO

General purpose digital I/O pin.

Definition at line 373 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_I2C1_SCL

#define SYS_GPB_MFPL_PB1MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 384 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_I2S0_LRCK

#define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK

I2S0 left right channel clock.

Definition at line 385 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_OPA0_N

#define SYS_GPB_MFPL_PB1MFP_OPA0_N

Operational amplifier negative input pin.

Definition at line 375 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_SD0_CLK

#define SYS_GPB_MFPL_PB1MFP_SD0_CLK

SD/SDIO 0 clock.

Definition at line 378 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK

#define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK

SPI1 I2S master clock output pin.

Definition at line 380 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK

#define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK

SPI3 I2S master clock output pin.

Definition at line 381 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_UART2_TXD

#define SYS_GPB_MFPL_PB1MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 382 of file sys.h.

## ◆ SYS_GPB_MFPL_PB1MFP_USCI1_CLK

#define SYS_GPB_MFPL_PB1MFP_USCI1_CLK

USCI1 clock pin.

Definition at line 383 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_ACMP0_P1

#define SYS_GPB_MFPL_PB2MFP_ACMP0_P1

Analog comparator0 positive input pin.

Definition at line 390 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_EADC0_CH2

#define SYS_GPB_MFPL_PB2MFP_EADC0_CH2

EADC0 channel2 analog input.

Definition at line 391 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_EADC1_CH10

#define SYS_GPB_MFPL_PB2MFP_EADC1_CH10

EADC1 channel1 analog input.

Definition at line 393 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_EBI_ADR3

#define SYS_GPB_MFPL_PB2MFP_EBI_ADR3

EBI address/data bus bit*.

Definition at line 394 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV

#define SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV

MII Receive Data Valid / RMII CRS_DV input.

Definition at line 396 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_EPWM0_CH3

#define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3

EPWM0 channel3 output/capture input.

Definition at line 403 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_GPIO

#define SYS_GPB_MFPL_PB2MFP_GPIO

General purpose digital I/O pin.

Definition at line 389 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_I2C1_SDA

#define SYS_GPB_MFPL_PB2MFP_I2C1_SDA (0x0CUL<<SYS_GPB_MFPL_PB2MFP_Pos)

I2C1 data input/output pin.

Definition at line 404 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_I2S0_DO

#define SYS_GPB_MFPL_PB2MFP_I2S0_DO

I2S0 data output.

Definition at line 402 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_INT3

#define SYS_GPB_MFPL_PB2MFP_INT3

External interrupt3 input pin.

Definition at line 406 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_OPA0_O

#define SYS_GPB_MFPL_PB2MFP_OPA0_O

Operational amplifier output pin.

Definition at line 392 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_SC0_PWR

#define SYS_GPB_MFPL_PB2MFP_SC0_PWR

SmartCard0 power pin.

Definition at line 401 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_SD0_DAT0

#define SYS_GPB_MFPL_PB2MFP_SD0_DAT0

SD/SDIO 0 data line bit 0.

Definition at line 395 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_SPI1_SS

#define SYS_GPB_MFPL_PB2MFP_SPI1_SS

1st SPI1 slave select pin.

Definition at line 397 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_TM3

#define SYS_GPB_MFPL_PB2MFP_TM3

Timer3 event counter input / toggle output

Definition at line 405 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_UART1_RXD

#define SYS_GPB_MFPL_PB2MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 398 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_UART5_nCTS

#define SYS_GPB_MFPL_PB2MFP_UART5_nCTS

Clear to Send input pin for UART5.

Definition at line 399 of file sys.h.

## ◆ SYS_GPB_MFPL_PB2MFP_USCI1_DAT0

#define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0

USCI1 data0 pin.

Definition at line 400 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_ACMP0_N

#define SYS_GPB_MFPL_PB3MFP_ACMP0_N

Analog comparator0 negative input pin.

Definition at line 408 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_EADC0_CH3

#define SYS_GPB_MFPL_PB3MFP_EADC0_CH3

EADC0 channel3 analog input.

Definition at line 409 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_EADC1_CH11

#define SYS_GPB_MFPL_PB3MFP_EADC1_CH11

EADC1 channel1 analog input.

Definition at line 410 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_EBI_ADR2

#define SYS_GPB_MFPL_PB3MFP_EBI_ADR2

EBI address/data bus bit*.

Definition at line 411 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1

#define SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1

RMII Receive Data bus bit 1.

Definition at line 413 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_EPWM0_CH2

#define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2

EPWM0 channel2 output/capture input.

Definition at line 420 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_GPIO

#define SYS_GPB_MFPL_PB3MFP_GPIO

General purpose digital I/O pin.

Definition at line 407 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_I2C1_SCL

#define SYS_GPB_MFPL_PB3MFP_I2C1_SCL (0x0CUL<<SYS_GPB_MFPL_PB3MFP_Pos)

I2C1 clock pin.

Definition at line 421 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_I2S0_DI

#define SYS_GPB_MFPL_PB3MFP_I2S0_DI

I2S0 data input.

Definition at line 419 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_INT2

#define SYS_GPB_MFPL_PB3MFP_INT2

External interrupt2 input pin.

Definition at line 423 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_SC0_RST

#define SYS_GPB_MFPL_PB3MFP_SC0_RST

SmartCard0 reset pin.

Definition at line 418 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_SD0_DAT1

#define SYS_GPB_MFPL_PB3MFP_SD0_DAT1

SD/SDIO 0 data line bit 1.

Definition at line 412 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_SPI1_CLK

#define SYS_GPB_MFPL_PB3MFP_SPI1_CLK

SPI1 serial clock pin.

Definition at line 414 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_TM2

#define SYS_GPB_MFPL_PB3MFP_TM2

Timer2 event counter input / toggle output

Definition at line 422 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_UART1_TXD

#define SYS_GPB_MFPL_PB3MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 415 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_UART5_nRTS

#define SYS_GPB_MFPL_PB3MFP_UART5_nRTS

Request to Send output pin for UART5.

Definition at line 416 of file sys.h.

## ◆ SYS_GPB_MFPL_PB3MFP_USCI1_DAT1

#define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1

USCI1 data1 pin.

Definition at line 417 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_ACMP1_P1

#define SYS_GPB_MFPL_PB4MFP_ACMP1_P1

Analog comparator1 positive input pin.

Definition at line 425 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_EADC0_CH4

#define SYS_GPB_MFPL_PB4MFP_EADC0_CH4

EADC0 channel4 analog input.

Definition at line 426 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_EBI_ADR1

#define SYS_GPB_MFPL_PB4MFP_EBI_ADR1

EBI address/data bus bit*.

Definition at line 427 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0

#define SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0

RMII Receive Data bus bit 0.

Definition at line 429 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_EPWM0_CH1

#define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1

EPWM0 channel1 output/capture input.

Definition at line 436 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_GPIO

#define SYS_GPB_MFPL_PB4MFP_GPIO

General purpose digital I/O pin.

Definition at line 424 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_I2C0_SDA

#define SYS_GPB_MFPL_PB4MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 431 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_I2S0_MCLK

#define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK

I2S0 master clock output pin.

Definition at line 435 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_INT1

#define SYS_GPB_MFPL_PB4MFP_INT1

External interrupt1 input pin.

Definition at line 439 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_SC0_DAT

#define SYS_GPB_MFPL_PB4MFP_SC0_DAT

SmartCard0 data pin.

Definition at line 434 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_SD0_DAT2

#define SYS_GPB_MFPL_PB4MFP_SD0_DAT2

SD/SDIO 0 data line bit 2.

Definition at line 428 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_SPI1_MOSI

#define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI

1st SPI1 MOSI (Master Out, Slave In) pin.

Definition at line 430 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_TM1

#define SYS_GPB_MFPL_PB4MFP_TM1

Timer1 event counter input / toggle output

Definition at line 438 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_UART2_RXD

#define SYS_GPB_MFPL_PB4MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 437 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_UART5_RXD

#define SYS_GPB_MFPL_PB4MFP_UART5_RXD

Data receiver input pin for UART5.

Definition at line 432 of file sys.h.

## ◆ SYS_GPB_MFPL_PB4MFP_USCI1_CTL1

#define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1

USCI1 control1 pin.

Definition at line 433 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_ACMP1_N

#define SYS_GPB_MFPL_PB5MFP_ACMP1_N

Analog comparator1 negative input pin.

Definition at line 441 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_EADC0_CH5

#define SYS_GPB_MFPL_PB5MFP_EADC0_CH5

EADC0 channel5 analog input.

Definition at line 442 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_EBI_ADR0

#define SYS_GPB_MFPL_PB5MFP_EBI_ADR0

EBI address/data bus bit*.

Definition at line 443 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK

#define SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK

EMAC mode clock input.

Definition at line 445 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_EPWM0_CH0

#define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0

EPWM0 channel0 output/capture input.

Definition at line 452 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_GPIO

#define SYS_GPB_MFPL_PB5MFP_GPIO

General purpose digital I/O pin.

Definition at line 440 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_I2C0_SCL

#define SYS_GPB_MFPL_PB5MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 447 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_I2S0_BCLK

#define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK

I2S0 bit clock pin.

Definition at line 451 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_INT0

#define SYS_GPB_MFPL_PB5MFP_INT0

External interrupt0 input pin.

Definition at line 455 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_SC0_CLK

#define SYS_GPB_MFPL_PB5MFP_SC0_CLK

SmartCard0 clock pin.

Definition at line 450 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_SD0_DAT3

#define SYS_GPB_MFPL_PB5MFP_SD0_DAT3

SD/SDIO 0 data line bit 3.

Definition at line 444 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_SPI1_MISO

#define SYS_GPB_MFPL_PB5MFP_SPI1_MISO

1st SPI1 MISO (Master In, Slave Out) pin.

Definition at line 446 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_TM0

#define SYS_GPB_MFPL_PB5MFP_TM0

Timer0 event counter input / toggle output

Definition at line 454 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_UART2_TXD

#define SYS_GPB_MFPL_PB5MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 453 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_UART5_TXD

#define SYS_GPB_MFPL_PB5MFP_UART5_TXD

Data transmitter output pin for UART5.

Definition at line 448 of file sys.h.

## ◆ SYS_GPB_MFPL_PB5MFP_USCI1_CTL0

#define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0

USCI1 control0 pin.

Definition at line 449 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_ACMP1_O

#define SYS_GPB_MFPL_PB6MFP_ACMP1_O

Analog comparator1 output.

Definition at line 470 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_BPWM1_CH5

#define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5

BPWM1 channel5 output/capture input.

Definition at line 465 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_CAN1_RXD

#define SYS_GPB_MFPL_PB6MFP_CAN1_RXD

CAN1 bus receiver input.

Definition at line 461 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_EADC0_CH6

#define SYS_GPB_MFPL_PB6MFP_EADC0_CH6

EADC0 channel6 analog input.

Definition at line 457 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_EBI_nCS1

#define SYS_GPB_MFPL_PB6MFP_EBI_nCS1

EBI chip select enable output pin.

Definition at line 464 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_EBI_nWRH

#define SYS_GPB_MFPL_PB6MFP_EBI_nWRH

EBI write enable output pin.

Definition at line 458 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_EMAC_PPS

#define SYS_GPB_MFPL_PB6MFP_EMAC_PPS

EMAC Pulse Per Second output

Definition at line 459 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1

#define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1

Brake input pin 1 of EPWM1.

Definition at line 466 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_EPWM1_CH5

#define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5

EPWM1 channel5 output/capture input.

Definition at line 467 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_GPIO

#define SYS_GPB_MFPL_PB6MFP_GPIO

General purpose digital I/O pin.

Definition at line 456 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_INT4

#define SYS_GPB_MFPL_PB6MFP_INT4

External interrupt4 input pin.

Definition at line 468 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_SD1_CLK

#define SYS_GPB_MFPL_PB6MFP_SD1_CLK

SD/SDIO 1 clock.

Definition at line 463 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_UART1_RXD

#define SYS_GPB_MFPL_PB6MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 462 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN

#define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN

Power supply from USB Full speed host or HUB.

Definition at line 469 of file sys.h.

## ◆ SYS_GPB_MFPL_PB6MFP_USCI1_DAT1

#define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1

USCI1 data1 pin.

Definition at line 460 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_ACMP0_O

#define SYS_GPB_MFPL_PB7MFP_ACMP0_O

Analog comparator0 output.

Definition at line 485 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_BPWM1_CH4

#define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4

BPWM1 channel4 output/capture input.

Definition at line 480 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_CAN1_TXD

#define SYS_GPB_MFPL_PB7MFP_CAN1_TXD

CAN1 bus transmitter output.

Definition at line 476 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_EADC0_CH7

#define SYS_GPB_MFPL_PB7MFP_EADC0_CH7

EADC0 channel7 analog input.

Definition at line 472 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_EBI_nCS0

#define SYS_GPB_MFPL_PB7MFP_EBI_nCS0

EBI chip select enable output pin.

Definition at line 479 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_EBI_nWRL

#define SYS_GPB_MFPL_PB7MFP_EBI_nWRL

EBI write enable output pin.

Definition at line 473 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN

#define SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN

RMII Transmit Enable.

Definition at line 474 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0

#define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0

Brake input pin 0 of EPWM1.

Definition at line 481 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_EPWM1_CH4

#define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4

EPWM1 channel4 output/capture input.

Definition at line 482 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_GPIO

#define SYS_GPB_MFPL_PB7MFP_GPIO

General purpose digital I/O pin.

Definition at line 471 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_INT5

#define SYS_GPB_MFPL_PB7MFP_INT5

External interrupt5 input pin.

Definition at line 483 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_SD1_CMD

#define SYS_GPB_MFPL_PB7MFP_SD1_CMD

SD/SDIO 1 command/response.

Definition at line 478 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_UART1_TXD

#define SYS_GPB_MFPL_PB7MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 477 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST

#define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST

Power supply from USB Full speed host or HUB.

Definition at line 484 of file sys.h.

## ◆ SYS_GPB_MFPL_PB7MFP_USCI1_DAT0

#define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0

USCI1 data0 pin.

Definition at line 475 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_CAN1_TXD

#define SYS_GPC_MFPH_PC10MFP_CAN1_TXD

CAN1 bus transmitter output.

Definition at line 738 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_EADC1_ST

#define SYS_GPC_MFPH_PC10MFP_EADC1_ST

EADC external trigger input.

Definition at line 741 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_EBI_ADR6

#define SYS_GPC_MFPH_PC10MFP_EBI_ADR6

EBI address/data bus bit*.

Definition at line 734 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_ECAP1_IC0

#define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0

Input 0 of enhanced capture unit 1.

Definition at line 739 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_EPWM1_CH2

#define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2

EPWM1 channel2 output/capture input.

Definition at line 740 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_GPIO

#define SYS_GPC_MFPH_PC10MFP_GPIO

General purpose digital I/O pin.

Definition at line 733 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_SPI3_CLK

#define SYS_GPC_MFPH_PC10MFP_SPI3_CLK

SPI3 serial clock pin.

Definition at line 736 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_UART3_TXD

#define SYS_GPC_MFPH_PC10MFP_UART3_TXD

Data transmitter output pin for UART3.

Definition at line 737 of file sys.h.

## ◆ SYS_GPC_MFPH_PC10MFP_UART6_nRTS

#define SYS_GPC_MFPH_PC10MFP_UART6_nRTS

Request to Send output pin for UART6.

Definition at line 735 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_ACMP1_O

#define SYS_GPC_MFPH_PC11MFP_ACMP1_O

Analog comparator1 output.

Definition at line 750 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_EBI_ADR5

#define SYS_GPC_MFPH_PC11MFP_EBI_ADR5

EBI address/data bus bit*.

Definition at line 743 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_ECAP1_IC1

#define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1

Input 1 of enhanced capture unit 1.

Definition at line 748 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_EPWM1_CH1

#define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1

EPWM1 channel1 output/capture input.

Definition at line 749 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_GPIO

#define SYS_GPC_MFPH_PC11MFP_GPIO

General purpose digital I/O pin.

Definition at line 742 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_I2C0_SDA

#define SYS_GPC_MFPH_PC11MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 745 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_SPI3_MOSI

#define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI

1st SPI3 MOSI (Master Out, Slave In) pin.

Definition at line 747 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_UART0_RXD

#define SYS_GPC_MFPH_PC11MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 744 of file sys.h.

## ◆ SYS_GPC_MFPH_PC11MFP_UART6_RXD

#define SYS_GPC_MFPH_PC11MFP_UART6_RXD

Data receiver input pin for UART6.

Definition at line 746 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_ACMP0_O

#define SYS_GPC_MFPH_PC12MFP_ACMP0_O

Analog comparator0 output.

Definition at line 760 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_EBI_ADR4

#define SYS_GPC_MFPH_PC12MFP_EBI_ADR4

EBI address/data bus bit*.

Definition at line 752 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_ECAP1_IC2

#define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2

Input 1 of enhanced capture unit 2.

Definition at line 758 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_EPWM1_CH0

#define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0

EPWM1 channel0 output/capture input.

Definition at line 759 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_GPIO

#define SYS_GPC_MFPH_PC12MFP_GPIO

General purpose digital I/O pin.

Definition at line 751 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_I2C0_SCL

#define SYS_GPC_MFPH_PC12MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 754 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_SC0_nCD

#define SYS_GPC_MFPH_PC12MFP_SC0_nCD

SmartCard0 card detect pin.

Definition at line 757 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_SPI3_MISO

#define SYS_GPC_MFPH_PC12MFP_SPI3_MISO

1st SPI3 MISO (Master In, Slave Out) pin.

Definition at line 756 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_UART0_TXD

#define SYS_GPC_MFPH_PC12MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 753 of file sys.h.

## ◆ SYS_GPC_MFPH_PC12MFP_UART6_TXD

#define SYS_GPC_MFPH_PC12MFP_UART6_TXD

Data transmitter output pin for UART6.

Definition at line 755 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_BPWM0_CH4

#define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4

BPWM0 channel4 output/capture input.

Definition at line 769 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_CAN1_TXD

#define SYS_GPC_MFPH_PC13MFP_CAN1_TXD

CAN1 bus transmitter output.

Definition at line 766 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_CLKO

#define SYS_GPC_MFPH_PC13MFP_CLKO

Clock Output pin.

Definition at line 770 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_EADC0_ST

#define SYS_GPC_MFPH_PC13MFP_EADC0_ST

EADC external trigger input.

Definition at line 771 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_EADC1_CH3

#define SYS_GPC_MFPH_PC13MFP_EADC1_CH3

EADC1 channel3 analog input.

Definition at line 762 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_EBI_ADR10

#define SYS_GPC_MFPH_PC13MFP_EBI_ADR10

EBI address/data bus bit*.

Definition at line 763 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_GPIO

#define SYS_GPC_MFPH_PC13MFP_GPIO

General purpose digital I/O pin.

Definition at line 761 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_SC2_nCD

#define SYS_GPC_MFPH_PC13MFP_SC2_nCD

SmartCard2 card detect pin.

Definition at line 764 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK

#define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK

SPI2 I2S master clock output pin.

Definition at line 765 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_UART2_TXD

#define SYS_GPC_MFPH_PC13MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 768 of file sys.h.

## ◆ SYS_GPC_MFPH_PC13MFP_USCI0_CTL0

#define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0

USCI0 control0 pin.

Definition at line 767 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_EBI_AD11

#define SYS_GPC_MFPH_PC14MFP_EBI_AD11

EBI address/data bus bit1.

Definition at line 773 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN

#define SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN

EPWM0 counter synchronous trigger input pin.

Definition at line 778 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK

#define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK

ETM Rx clock input pin.

Definition at line 779 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_GPIO

#define SYS_GPC_MFPH_PC14MFP_GPIO

General purpose digital I/O pin.

Definition at line 772 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST

#define SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST

Power supply from USB High speed host or HUB.

Definition at line 782 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_QSPI0_CLK

#define SYS_GPC_MFPH_PC14MFP_QSPI0_CLK

QSPI0 serial clock pin.

Definition at line 777 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_SC1_nCD

#define SYS_GPC_MFPH_PC14MFP_SC1_nCD

SmartCard1 card detect pin.

Definition at line 774 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK

#define SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK

SPI0 I2S master clock output pin.

Definition at line 775 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_TM1

#define SYS_GPC_MFPH_PC14MFP_TM1

Timer1 event counter input / toggle output

Definition at line 780 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST

#define SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST

Power supply from USB Full speed host or HUB.

Definition at line 781 of file sys.h.

## ◆ SYS_GPC_MFPH_PC14MFP_USCI0_CTL0

#define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0

USCI0 control0 pin.

Definition at line 776 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_BPWM1_CH4

#define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4

BPWM1 channel4 output/capture input.

Definition at line 724 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_EBI_ADR16

#define SYS_GPC_MFPH_PC8MFP_EBI_ADR16

EBI address/data bus bit*.

Definition at line 718 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK

#define SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK

EMAC mode clock input.

Definition at line 719 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_EPWM1_CH1

#define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1

EPWM1 channel1 output/capture input.

Definition at line 723 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_GPIO

#define SYS_GPC_MFPH_PC8MFP_GPIO

General purpose digital I/O pin.

Definition at line 717 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_I2C0_SDA

#define SYS_GPC_MFPH_PC8MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 720 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_UART1_RXD

#define SYS_GPC_MFPH_PC8MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 722 of file sys.h.

## ◆ SYS_GPC_MFPH_PC8MFP_UART4_nCTS

#define SYS_GPC_MFPH_PC8MFP_UART4_nCTS

Clear to Send input pin for UART4.

Definition at line 721 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_CAN1_RXD

#define SYS_GPC_MFPH_PC9MFP_CAN1_RXD

CAN1 bus receiver input.

Definition at line 730 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_EADC1_ST

#define SYS_GPC_MFPH_PC9MFP_EADC1_ST

EADC external trigger input.

Definition at line 732 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_EBI_ADR7

#define SYS_GPC_MFPH_PC9MFP_EBI_ADR7

EBI address/data bus bit*.

Definition at line 726 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_EPWM1_CH3

#define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3

EPWM1 channel3 output/capture input.

Definition at line 731 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_GPIO

#define SYS_GPC_MFPH_PC9MFP_GPIO

General purpose digital I/O pin.

Definition at line 725 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_SPI3_SS

#define SYS_GPC_MFPH_PC9MFP_SPI3_SS

1st SPI3 slave select pin.

Definition at line 728 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_UART3_RXD

#define SYS_GPC_MFPH_PC9MFP_UART3_RXD

Data receiver input pin for UART3.

Definition at line 729 of file sys.h.

## ◆ SYS_GPC_MFPH_PC9MFP_UART6_nCTS

#define SYS_GPC_MFPH_PC9MFP_UART6_nCTS

Clear to Send input pin for UART6.

Definition at line 727 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_ACMP1_O

#define SYS_GPC_MFPL_PC0MFP_ACMP1_O

Analog comparator1 output.

Definition at line 621 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_CAN2_RXD

#define SYS_GPC_MFPL_PC0MFP_CAN2_RXD

CAN2 bus receiver input.

Definition at line 618 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_CCAP_DATA0

#define SYS_GPC_MFPL_PC0MFP_CCAP_DATA0

Sensor pixel data0 input pin.

Definition at line 620 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_EADC1_ST

#define SYS_GPC_MFPL_PC0MFP_EADC1_ST

EADC external trigger input.

Definition at line 622 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_EBI_AD0

#define SYS_GPC_MFPL_PC0MFP_EBI_AD0

EBI address/data bus bit0.

Definition at line 610 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_EPWM1_CH5

#define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5

EPWM1 channel5 output/capture input.

Definition at line 619 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_GPIO

#define SYS_GPC_MFPL_PC0MFP_GPIO

General purpose digital I/O pin.

Definition at line 609 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_I2C0_SDA

#define SYS_GPC_MFPL_PC0MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 617 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_I2S0_LRCK

#define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK

I2S0 left right channel clock.

Definition at line 614 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0

#define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0

1st QSPI0 MOSI (Master Out, Slave In) pin.

Definition at line 612 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_SC1_CLK

#define SYS_GPC_MFPL_PC0MFP_SC1_CLK

SmartCard1 clock pin.

Definition at line 613 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_SPI1_SS

#define SYS_GPC_MFPL_PC0MFP_SPI1_SS

1st SPI1 slave select pin.

Definition at line 615 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_SPIM_MOSI

#define SYS_GPC_MFPL_PC0MFP_SPIM_MOSI

1st SPIM MOSI (Master Out, Slave In) pin.

Definition at line 611 of file sys.h.

## ◆ SYS_GPC_MFPL_PC0MFP_UART2_RXD

#define SYS_GPC_MFPL_PC0MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 616 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_ACMP0_O

#define SYS_GPC_MFPL_PC1MFP_ACMP0_O

Analog comparator0 output.

Definition at line 635 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_CAN2_TXD

#define SYS_GPC_MFPL_PC1MFP_CAN2_TXD

CAN2 bus transmitter output.

Definition at line 632 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_CCAP_DATA1

#define SYS_GPC_MFPL_PC1MFP_CCAP_DATA1

Sensor pixel data1 input pin.

Definition at line 634 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_EADC0_ST

#define SYS_GPC_MFPL_PC1MFP_EADC0_ST

EADC external trigger input.

Definition at line 636 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_EBI_AD1

#define SYS_GPC_MFPL_PC1MFP_EBI_AD1

EBI address/data bus bit1.

Definition at line 624 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_EPWM1_CH4

#define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4

EPWM1 channel4 output/capture input.

Definition at line 633 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_GPIO

#define SYS_GPC_MFPL_PC1MFP_GPIO

General purpose digital I/O pin.

Definition at line 623 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_I2C0_SCL

#define SYS_GPC_MFPL_PC1MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 631 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_I2S0_DO

#define SYS_GPC_MFPL_PC1MFP_I2S0_DO

I2S0 data output.

Definition at line 628 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0

#define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0

1st QSPI0 MISO (Master In, Slave Out) pin.

Definition at line 626 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_SC1_DAT

#define SYS_GPC_MFPL_PC1MFP_SC1_DAT

SmartCard1 data pin.

Definition at line 627 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_SPI1_CLK

#define SYS_GPC_MFPL_PC1MFP_SPI1_CLK

SPI1 serial clock pin.

Definition at line 629 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_SPIM_MISO

#define SYS_GPC_MFPL_PC1MFP_SPIM_MISO

1st SPIM MISO (Master In, Slave Out) pin.

Definition at line 625 of file sys.h.

## ◆ SYS_GPC_MFPL_PC1MFP_UART2_TXD

#define SYS_GPC_MFPL_PC1MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 630 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_CAN1_RXD

#define SYS_GPC_MFPL_PC2MFP_CAN1_RXD

CAN1 bus receiver input.

Definition at line 646 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_CCAP_DATA2

#define SYS_GPC_MFPL_PC2MFP_CCAP_DATA2

Sensor pixel data2 input pin.

Definition at line 649 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_EBI_AD2

#define SYS_GPC_MFPL_PC2MFP_EBI_AD2

EBI address/data bus bit2.

Definition at line 638 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_EPWM1_CH3

#define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3

EPWM1 channel3 output/capture input.

Definition at line 648 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_GPIO

#define SYS_GPC_MFPL_PC2MFP_GPIO

General purpose digital I/O pin.

Definition at line 637 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS

#define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS

I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 645 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_I2S0_DI

#define SYS_GPC_MFPL_PC2MFP_I2S0_DI

I2S0 data input.

Definition at line 642 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_QSPI0_CLK

#define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK

QSPI0 serial clock pin.

Definition at line 640 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_QSPI1_MOSI0

#define SYS_GPC_MFPL_PC2MFP_QSPI1_MOSI0

1st QSPI1 MOSI (Master Out, Slave In) pin.

Definition at line 650 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_SC1_RST

#define SYS_GPC_MFPL_PC2MFP_SC1_RST

SmartCard1 reset pin.

Definition at line 641 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_SPI1_MOSI

#define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI

1st SPI1 MOSI (Master Out, Slave In) pin.

Definition at line 643 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_SPIM_CLK

#define SYS_GPC_MFPL_PC2MFP_SPIM_CLK

SPIM serial clock pin.

Definition at line 639 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_UART2_nCTS

#define SYS_GPC_MFPL_PC2MFP_UART2_nCTS

Clear to Send input pin for UART2.

Definition at line 644 of file sys.h.

## ◆ SYS_GPC_MFPL_PC2MFP_UART3_RXD

#define SYS_GPC_MFPL_PC2MFP_UART3_RXD

Data receiver input pin for UART3.

Definition at line 647 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_CAN1_TXD

#define SYS_GPC_MFPL_PC3MFP_CAN1_TXD

CAN1 bus transmitter output.

Definition at line 660 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_CCAP_DATA3

#define SYS_GPC_MFPL_PC3MFP_CCAP_DATA3

Sensor pixel data3 input pin.

Definition at line 663 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_EBI_AD3

#define SYS_GPC_MFPL_PC3MFP_EBI_AD3

EBI address/data bus bit3.

Definition at line 652 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_EPWM1_CH2

#define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2

EPWM1 channel2 output/capture input.

Definition at line 662 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_GPIO

#define SYS_GPC_MFPL_PC3MFP_GPIO

General purpose digital I/O pin.

Definition at line 651 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL

#define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL

I2C0 SMBus SMBALTER# pin

Definition at line 659 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_I2S0_MCLK

#define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK

I2S0 master clock output pin.

Definition at line 656 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_QSPI0_SS

#define SYS_GPC_MFPL_PC3MFP_QSPI0_SS

1st QSPI0 slave select pin.

Definition at line 654 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_QSPI1_MISO0

#define SYS_GPC_MFPL_PC3MFP_QSPI1_MISO0

1st QSPI1 MISO (Master In, Slave Out) pin.

Definition at line 664 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_SC1_PWR

#define SYS_GPC_MFPL_PC3MFP_SC1_PWR

SmartCard1 power pin.

Definition at line 655 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_SPI1_MISO

#define SYS_GPC_MFPL_PC3MFP_SPI1_MISO

1st SPI1 MISO (Master In, Slave Out) pin.

Definition at line 657 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_SPIM_SS

#define SYS_GPC_MFPL_PC3MFP_SPIM_SS

1st SPIM slave select pin.

Definition at line 653 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_UART2_nRTS

#define SYS_GPC_MFPL_PC3MFP_UART2_nRTS

Request to Send output pin for UART2.

Definition at line 658 of file sys.h.

## ◆ SYS_GPC_MFPL_PC3MFP_UART3_TXD

#define SYS_GPC_MFPL_PC3MFP_UART3_TXD

Data transmitter output pin for UART3.

Definition at line 661 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_CAN0_RXD

#define SYS_GPC_MFPL_PC4MFP_CAN0_RXD

CAN0 bus receiver input.

Definition at line 674 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_CCAP_DATA4

#define SYS_GPC_MFPL_PC4MFP_CCAP_DATA4

Sensor pixel data4 input pin.

Definition at line 677 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_EBI_AD4

#define SYS_GPC_MFPL_PC4MFP_EBI_AD4

EBI address/data bus bit4.

Definition at line 666 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_EPWM1_CH1

#define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1

EPWM1 channel1 output/capture input.

Definition at line 676 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_GPIO

#define SYS_GPC_MFPL_PC4MFP_GPIO

General purpose digital I/O pin.

Definition at line 665 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_I2C1_SDA

#define SYS_GPC_MFPL_PC4MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 673 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_I2S0_BCLK

#define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK

I2S0 bit clock pin.

Definition at line 670 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1

#define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1

2nd QSPI0 MOSI (Master Out, Slave In) pin.

Definition at line 668 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_QSPI1_CLK

#define SYS_GPC_MFPL_PC4MFP_QSPI1_CLK

QSPI1 serial clock pin.

Definition at line 678 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_SC1_nCD

#define SYS_GPC_MFPL_PC4MFP_SC1_nCD

SmartCard1 card detect pin.

Definition at line 669 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK

#define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK

SPI1 I2S master clock output pin.

Definition at line 671 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_SPIM_D3

#define SYS_GPC_MFPL_PC4MFP_SPIM_D3

SPIM data 3 pin for Quad Mode I/O.

Definition at line 667 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_UART2_RXD

#define SYS_GPC_MFPL_PC4MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 672 of file sys.h.

## ◆ SYS_GPC_MFPL_PC4MFP_UART4_RXD

#define SYS_GPC_MFPL_PC4MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 675 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_CAN0_TXD

#define SYS_GPC_MFPL_PC5MFP_CAN0_TXD

CAN0 bus transmitter output.

Definition at line 685 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_CCAP_DATA5

#define SYS_GPC_MFPL_PC5MFP_CCAP_DATA5

Sensor pixel data5 input pin.

Definition at line 688 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_EBI_AD5

#define SYS_GPC_MFPL_PC5MFP_EBI_AD5

EBI address/data bus bit5.

Definition at line 680 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_EPWM1_CH0

#define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0

EPWM1 channel0 output/capture input.

Definition at line 687 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_GPIO

#define SYS_GPC_MFPL_PC5MFP_GPIO

General purpose digital I/O pin.

Definition at line 679 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_I2C1_SCL

#define SYS_GPC_MFPL_PC5MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 684 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1

#define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1

2nd QSPI0 MISO (Master In, Slave Out) pin.

Definition at line 682 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_QSPI1_SS

#define SYS_GPC_MFPL_PC5MFP_QSPI1_SS

1st QSPI1 slave select pin.

Definition at line 689 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_SPIM_D2

#define SYS_GPC_MFPL_PC5MFP_SPIM_D2

SPIM data 2 pin for Quad Mode I/O.

Definition at line 681 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_UART2_TXD

#define SYS_GPC_MFPL_PC5MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 683 of file sys.h.

## ◆ SYS_GPC_MFPL_PC5MFP_UART4_TXD

#define SYS_GPC_MFPL_PC5MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 686 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_BPWM1_CH1

#define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1

BPWM1 channel1 output/capture input.

Definition at line 700 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_EBI_AD8

#define SYS_GPC_MFPL_PC6MFP_EBI_AD8

EBI address/data bus bit8.

Definition at line 691 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1

#define SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1

RMII Receive Data bus bit 1.

Definition at line 692 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_EPWM1_CH3

#define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3

EPWM1 channel3 output/capture input.

Definition at line 699 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_GPIO

#define SYS_GPC_MFPL_PC6MFP_GPIO

General purpose digital I/O pin.

Definition at line 690 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS

#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS

I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 697 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_INT2

#define SYS_GPC_MFPL_PC6MFP_INT2

External interrupt2 input pin.

Definition at line 702 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_SC2_RST

#define SYS_GPC_MFPL_PC6MFP_SC2_RST

SmartCard2 reset pin.

Definition at line 695 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_SPI1_MOSI

#define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI

1st SPI1 MOSI (Master Out, Slave In) pin.

Definition at line 693 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_TM1

#define SYS_GPC_MFPL_PC6MFP_TM1

Timer1 event counter input / toggle output

Definition at line 701 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_UART0_nRTS

#define SYS_GPC_MFPL_PC6MFP_UART0_nRTS

Request to Send output pin for UART0.

Definition at line 696 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_UART4_RXD

#define SYS_GPC_MFPL_PC6MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 694 of file sys.h.

## ◆ SYS_GPC_MFPL_PC6MFP_UART6_RXD

#define SYS_GPC_MFPL_PC6MFP_UART6_RXD

Data receiver input pin for UART6.

Definition at line 698 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_BPWM1_CH0

#define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0

BPWM1 channel0 output/capture input.

Definition at line 713 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_EBI_AD9

#define SYS_GPC_MFPL_PC7MFP_EBI_AD9

EBI address/data bus bit9.

Definition at line 704 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0

#define SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0

RMII Receive Data bus bit 0.

Definition at line 705 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_EPWM1_CH2

#define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2

EPWM1 channel2 output/capture input.

Definition at line 712 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_GPIO

#define SYS_GPC_MFPL_PC7MFP_GPIO

General purpose digital I/O pin.

Definition at line 703 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL

#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL

I2C1 SMBus SMBALTER# pin

Definition at line 710 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_INT3

#define SYS_GPC_MFPL_PC7MFP_INT3

External interrupt3 input pin.

Definition at line 715 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_SC2_PWR

#define SYS_GPC_MFPL_PC7MFP_SC2_PWR

SmartCard2 power pin.

Definition at line 708 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_SPI1_MISO

#define SYS_GPC_MFPL_PC7MFP_SPI1_MISO

1st SPI1 MISO (Master In, Slave Out) pin.

Definition at line 706 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_TM0

#define SYS_GPC_MFPL_PC7MFP_TM0

Timer0 event counter input / toggle output

Definition at line 714 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_UART0_nCTS

#define SYS_GPC_MFPL_PC7MFP_UART0_nCTS

Clear to Send input pin for UART0.

Definition at line 709 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_UART4_TXD

#define SYS_GPC_MFPL_PC7MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 707 of file sys.h.

## ◆ SYS_GPC_MFPL_PC7MFP_UART6_TXD

#define SYS_GPC_MFPL_PC7MFP_UART6_TXD

Data transmitter output pin for UART6.

Definition at line 711 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_CAN0_RXD

#define SYS_GPD_MFPH_PD10MFP_CAN0_RXD

CAN0 bus receiver input.

Definition at line 857 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_EADC1_CH0

#define SYS_GPD_MFPH_PD10MFP_EADC1_CH0

EADC1 channel0 analog input.

Definition at line 854 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_EBI_nCS2

#define SYS_GPD_MFPH_PD10MFP_EBI_nCS2

EBI chip select enable output pin.

Definition at line 855 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_GPIO

#define SYS_GPD_MFPH_PD10MFP_GPIO

General purpose digital I/O pin.

Definition at line 852 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_INT7

#define SYS_GPD_MFPH_PD10MFP_INT7

External interrupt7 input pin.

Definition at line 859 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_OPA2_P

#define SYS_GPD_MFPH_PD10MFP_OPA2_P

Operational amplifier positive input pin.

Definition at line 853 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_QEI0_B

#define SYS_GPD_MFPH_PD10MFP_QEI0_B

Quadrature encoder phase B input of QEI Unit 0.

Definition at line 858 of file sys.h.

## ◆ SYS_GPD_MFPH_PD10MFP_UART1_RXD

#define SYS_GPD_MFPH_PD10MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 856 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_CAN0_TXD

#define SYS_GPD_MFPH_PD11MFP_CAN0_TXD

CAN0 bus transmitter output.

Definition at line 865 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_EADC1_CH1

#define SYS_GPD_MFPH_PD11MFP_EADC1_CH1

EADC1 channel1 analog input.

Definition at line 861 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_EBI_nCS1

#define SYS_GPD_MFPH_PD11MFP_EBI_nCS1

EBI chip select enable output pin.

Definition at line 863 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_GPIO

#define SYS_GPD_MFPH_PD11MFP_GPIO

General purpose digital I/O pin.

Definition at line 860 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_INT6

#define SYS_GPD_MFPH_PD11MFP_INT6

External interrupt6 input pin.

Definition at line 867 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_OPA2_N

#define SYS_GPD_MFPH_PD11MFP_OPA2_N

Operational amplifier negative input pin.

Definition at line 862 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_QEI0_A

#define SYS_GPD_MFPH_PD11MFP_QEI0_A

Quadrature encoder phase A input of QEI Unit 0.

Definition at line 866 of file sys.h.

## ◆ SYS_GPD_MFPH_PD11MFP_UART1_TXD

#define SYS_GPD_MFPH_PD11MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 864 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_BPWM0_CH5

#define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5

BPWM0 channel5 output/capture input.

Definition at line 874 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_CAN1_RXD

#define SYS_GPD_MFPH_PD12MFP_CAN1_RXD

CAN1 bus receiver input.

Definition at line 872 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_CLKO

#define SYS_GPD_MFPH_PD12MFP_CLKO

Clock Output pin.

Definition at line 876 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_EADC0_ST

#define SYS_GPD_MFPH_PD12MFP_EADC0_ST

EADC external trigger input.

Definition at line 877 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_EADC1_CH2

#define SYS_GPD_MFPH_PD12MFP_EADC1_CH2

EADC1 channel2 analog input.

Definition at line 870 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_EBI_nCS0

#define SYS_GPD_MFPH_PD12MFP_EBI_nCS0

EBI chip select enable output pin.

Definition at line 871 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_GPIO

#define SYS_GPD_MFPH_PD12MFP_GPIO

General purpose digital I/O pin.

Definition at line 868 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_INT5

#define SYS_GPD_MFPH_PD12MFP_INT5

External interrupt5 input pin.

Definition at line 878 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_OPA2_O

#define SYS_GPD_MFPH_PD12MFP_OPA2_O

Operational amplifier output pin.

Definition at line 869 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_QEI0_INDEX

#define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX

Quadrature encoder index input of QEI Unit 0.

Definition at line 875 of file sys.h.

## ◆ SYS_GPD_MFPH_PD12MFP_UART2_RXD

#define SYS_GPD_MFPH_PD12MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 873 of file sys.h.

## ◆ SYS_GPD_MFPH_PD13MFP_EBI_AD10

#define SYS_GPD_MFPH_PD13MFP_EBI_AD10

EBI address/data bus bit1.

Definition at line 880 of file sys.h.

## ◆ SYS_GPD_MFPH_PD13MFP_GPIO

#define SYS_GPD_MFPH_PD13MFP_GPIO

General purpose digital I/O pin.

Definition at line 879 of file sys.h.

## ◆ SYS_GPD_MFPH_PD13MFP_SC2_nCD

#define SYS_GPD_MFPH_PD13MFP_SC2_nCD

SmartCard2 card detect pin.

Definition at line 884 of file sys.h.

## ◆ SYS_GPD_MFPH_PD13MFP_SD0_nCD

#define SYS_GPD_MFPH_PD13MFP_SD0_nCD

SD/SDIO 0 card detect

Definition at line 881 of file sys.h.

## ◆ SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK

#define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK

SPI0 I2S master clock output pin.

Definition at line 882 of file sys.h.

## ◆ SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK

#define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK

SPI1 I2S master clock output pin.

Definition at line 883 of file sys.h.

## ◆ SYS_GPD_MFPH_PD14MFP_EBI_nCS0

#define SYS_GPD_MFPH_PD14MFP_EBI_nCS0

EBI chip select enable output pin.

Definition at line 886 of file sys.h.

## ◆ SYS_GPD_MFPH_PD14MFP_EPWM0_CH4

#define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4

EPWM0 channel4 output/capture input.

Definition at line 890 of file sys.h.

## ◆ SYS_GPD_MFPH_PD14MFP_GPIO

#define SYS_GPD_MFPH_PD14MFP_GPIO

General purpose digital I/O pin.

Definition at line 885 of file sys.h.

## ◆ SYS_GPD_MFPH_PD14MFP_SC1_nCD

#define SYS_GPD_MFPH_PD14MFP_SC1_nCD

SmartCard1 card detect pin.

Definition at line 888 of file sys.h.

## ◆ SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK

#define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK

SPI0 I2S master clock output pin.

Definition at line 889 of file sys.h.

## ◆ SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK

#define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK

SPI3 I2S master clock output pin.

Definition at line 887 of file sys.h.

## ◆ SYS_GPD_MFPH_PD8MFP_CAN2_RXD

#define SYS_GPD_MFPH_PD8MFP_CAN2_RXD

CAN2 bus receiver input.

Definition at line 845 of file sys.h.

## ◆ SYS_GPD_MFPH_PD8MFP_EBI_AD6

#define SYS_GPD_MFPH_PD8MFP_EBI_AD6

EBI address/data bus bit6.

Definition at line 841 of file sys.h.

## ◆ SYS_GPD_MFPH_PD8MFP_GPIO

#define SYS_GPD_MFPH_PD8MFP_GPIO

General purpose digital I/O pin.

Definition at line 840 of file sys.h.

## ◆ SYS_GPD_MFPH_PD8MFP_I2C2_SDA

#define SYS_GPD_MFPH_PD8MFP_I2C2_SDA

I2C2 data input/output pin.

Definition at line 842 of file sys.h.

## ◆ SYS_GPD_MFPH_PD8MFP_UART2_nRTS

#define SYS_GPD_MFPH_PD8MFP_UART2_nRTS

Request to Send output pin for UART2.

Definition at line 843 of file sys.h.

## ◆ SYS_GPD_MFPH_PD8MFP_UART7_RXD

#define SYS_GPD_MFPH_PD8MFP_UART7_RXD

Data receiver input pin for UART7.

Definition at line 844 of file sys.h.

## ◆ SYS_GPD_MFPH_PD9MFP_CAN2_TXD

#define SYS_GPD_MFPH_PD9MFP_CAN2_TXD

CAN2 bus transmitter output.

Definition at line 851 of file sys.h.

## ◆ SYS_GPD_MFPH_PD9MFP_EBI_AD7

#define SYS_GPD_MFPH_PD9MFP_EBI_AD7

EBI address/data bus bit7.

Definition at line 847 of file sys.h.

## ◆ SYS_GPD_MFPH_PD9MFP_GPIO

#define SYS_GPD_MFPH_PD9MFP_GPIO

General purpose digital I/O pin.

Definition at line 846 of file sys.h.

## ◆ SYS_GPD_MFPH_PD9MFP_I2C2_SCL

#define SYS_GPD_MFPH_PD9MFP_I2C2_SCL

I2C2 clock pin.

Definition at line 848 of file sys.h.

## ◆ SYS_GPD_MFPH_PD9MFP_UART2_nCTS

#define SYS_GPD_MFPH_PD9MFP_UART2_nCTS

Clear to Send input pin for UART2.

Definition at line 849 of file sys.h.

## ◆ SYS_GPD_MFPH_PD9MFP_UART7_TXD

#define SYS_GPD_MFPH_PD9MFP_UART7_TXD

Data transmitter output pin for UART7.

Definition at line 850 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_EBI_AD13

#define SYS_GPD_MFPL_PD0MFP_EBI_AD13

EBI address/data bus bit1.

Definition at line 785 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_GPIO

#define SYS_GPD_MFPL_PD0MFP_GPIO

General purpose digital I/O pin.

Definition at line 784 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_I2C2_SDA

#define SYS_GPD_MFPL_PD0MFP_I2C2_SDA

I2C2 data input/output pin.

Definition at line 789 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_SC2_CLK

#define SYS_GPD_MFPL_PD0MFP_SC2_CLK

SmartCard2 clock pin.

Definition at line 790 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_SPI0_MOSI

#define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI

1st SPI0 MOSI (Master Out, Slave In) pin.

Definition at line 787 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_TM2

#define SYS_GPD_MFPL_PD0MFP_TM2

Timer2 event counter input / toggle output

Definition at line 791 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_UART3_RXD

#define SYS_GPD_MFPL_PD0MFP_UART3_RXD

Data receiver input pin for UART3.

Definition at line 788 of file sys.h.

## ◆ SYS_GPD_MFPL_PD0MFP_USCI0_CLK

#define SYS_GPD_MFPL_PD0MFP_USCI0_CLK

USCI0 clock pin.

Definition at line 786 of file sys.h.

## ◆ SYS_GPD_MFPL_PD1MFP_EBI_AD12

#define SYS_GPD_MFPL_PD1MFP_EBI_AD12

EBI address/data bus bit1.

Definition at line 793 of file sys.h.

## ◆ SYS_GPD_MFPL_PD1MFP_GPIO

#define SYS_GPD_MFPL_PD1MFP_GPIO

General purpose digital I/O pin.

Definition at line 792 of file sys.h.

## ◆ SYS_GPD_MFPL_PD1MFP_I2C2_SCL

#define SYS_GPD_MFPL_PD1MFP_I2C2_SCL

I2C2 clock pin.

Definition at line 797 of file sys.h.

## ◆ SYS_GPD_MFPL_PD1MFP_SC2_DAT

#define SYS_GPD_MFPL_PD1MFP_SC2_DAT

SmartCard2 data pin.

Definition at line 798 of file sys.h.

## ◆ SYS_GPD_MFPL_PD1MFP_SPI0_MISO

#define SYS_GPD_MFPL_PD1MFP_SPI0_MISO

1st SPI0 MISO (Master In, Slave Out) pin.

Definition at line 795 of file sys.h.

## ◆ SYS_GPD_MFPL_PD1MFP_UART3_TXD

#define SYS_GPD_MFPL_PD1MFP_UART3_TXD

Data transmitter output pin for UART3.

Definition at line 796 of file sys.h.

## ◆ SYS_GPD_MFPL_PD1MFP_USCI0_DAT0

#define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0

USCI0 data0 pin.

Definition at line 794 of file sys.h.

## ◆ SYS_GPD_MFPL_PD2MFP_EBI_AD11

#define SYS_GPD_MFPL_PD2MFP_EBI_AD11

EBI address/data bus bit1.

Definition at line 800 of file sys.h.

## ◆ SYS_GPD_MFPL_PD2MFP_GPIO

#define SYS_GPD_MFPL_PD2MFP_GPIO

General purpose digital I/O pin.

Definition at line 799 of file sys.h.

## ◆ SYS_GPD_MFPL_PD2MFP_SC2_RST

#define SYS_GPD_MFPL_PD2MFP_SC2_RST

SmartCard2 reset pin.

Definition at line 804 of file sys.h.

## ◆ SYS_GPD_MFPL_PD2MFP_SPI0_CLK

#define SYS_GPD_MFPL_PD2MFP_SPI0_CLK

SPI0 serial clock pin.

Definition at line 802 of file sys.h.

## ◆ SYS_GPD_MFPL_PD2MFP_UART0_RXD

#define SYS_GPD_MFPL_PD2MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 805 of file sys.h.

## ◆ SYS_GPD_MFPL_PD2MFP_UART3_nCTS

#define SYS_GPD_MFPL_PD2MFP_UART3_nCTS

Clear to Send input pin for UART3.

Definition at line 803 of file sys.h.

## ◆ SYS_GPD_MFPL_PD2MFP_USCI0_DAT1

#define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1

USCI0 data1 pin.

Definition at line 801 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_EBI_AD10

#define SYS_GPD_MFPL_PD3MFP_EBI_AD10

EBI address/data bus bit1.

Definition at line 807 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_GPIO

#define SYS_GPD_MFPL_PD3MFP_GPIO

General purpose digital I/O pin.

Definition at line 806 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_SC1_nCD

#define SYS_GPD_MFPL_PD3MFP_SC1_nCD

SmartCard1 card detect pin.

Definition at line 813 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_SC2_PWR

#define SYS_GPD_MFPL_PD3MFP_SC2_PWR

SmartCard2 power pin.

Definition at line 812 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_SPI0_SS

#define SYS_GPD_MFPL_PD3MFP_SPI0_SS

1st SPI0 slave select pin.

Definition at line 809 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_UART0_TXD

#define SYS_GPD_MFPL_PD3MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 814 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_UART3_nRTS

#define SYS_GPD_MFPL_PD3MFP_UART3_nRTS

Request to Send output pin for UART3.

Definition at line 810 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_USCI0_CTL1

#define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1

USCI0 control1 pin.

Definition at line 808 of file sys.h.

## ◆ SYS_GPD_MFPL_PD3MFP_USCI1_CTL0

#define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0

USCI1 control0 pin.

Definition at line 811 of file sys.h.

## ◆ SYS_GPD_MFPL_PD4MFP_GPIO

#define SYS_GPD_MFPL_PD4MFP_GPIO

General purpose digital I/O pin.

Definition at line 815 of file sys.h.

## ◆ SYS_GPD_MFPL_PD4MFP_I2C1_SDA

#define SYS_GPD_MFPL_PD4MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 817 of file sys.h.

## ◆ SYS_GPD_MFPL_PD4MFP_SC1_CLK

#define SYS_GPD_MFPL_PD4MFP_SC1_CLK

SmartCard1 clock pin.

Definition at line 820 of file sys.h.

## ◆ SYS_GPD_MFPL_PD4MFP_SPI1_SS

#define SYS_GPD_MFPL_PD4MFP_SPI1_SS

1st SPI1 slave select pin.

Definition at line 818 of file sys.h.

## ◆ SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST

#define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST

Power supply from USB Full speed host or HUB.

Definition at line 821 of file sys.h.

## ◆ SYS_GPD_MFPL_PD4MFP_USCI0_CTL0

#define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0

USCI0 control0 pin.

Definition at line 816 of file sys.h.

## ◆ SYS_GPD_MFPL_PD4MFP_USCI1_CTL1

#define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1

USCI1 control1 pin.

Definition at line 819 of file sys.h.

## ◆ SYS_GPD_MFPL_PD5MFP_GPIO

#define SYS_GPD_MFPL_PD5MFP_GPIO

General purpose digital I/O pin.

Definition at line 822 of file sys.h.

## ◆ SYS_GPD_MFPL_PD5MFP_I2C1_SCL

#define SYS_GPD_MFPL_PD5MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 823 of file sys.h.

## ◆ SYS_GPD_MFPL_PD5MFP_SC1_DAT

#define SYS_GPD_MFPL_PD5MFP_SC1_DAT

SmartCard1 data pin.

Definition at line 826 of file sys.h.

## ◆ SYS_GPD_MFPL_PD5MFP_SPI1_CLK

#define SYS_GPD_MFPL_PD5MFP_SPI1_CLK

SPI1 serial clock pin.

Definition at line 824 of file sys.h.

## ◆ SYS_GPD_MFPL_PD5MFP_USCI1_DAT0

#define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0

USCI1 data0 pin.

Definition at line 825 of file sys.h.

## ◆ SYS_GPD_MFPL_PD6MFP_GPIO

#define SYS_GPD_MFPL_PD6MFP_GPIO

General purpose digital I/O pin.

Definition at line 827 of file sys.h.

## ◆ SYS_GPD_MFPL_PD6MFP_I2C0_SDA

#define SYS_GPD_MFPL_PD6MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 829 of file sys.h.

## ◆ SYS_GPD_MFPL_PD6MFP_SC1_RST

#define SYS_GPD_MFPL_PD6MFP_SC1_RST

SmartCard1 reset pin.

Definition at line 832 of file sys.h.

## ◆ SYS_GPD_MFPL_PD6MFP_SPI1_MOSI

#define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI

1st SPI1 MOSI (Master Out, Slave In) pin.

Definition at line 830 of file sys.h.

## ◆ SYS_GPD_MFPL_PD6MFP_UART1_RXD

#define SYS_GPD_MFPL_PD6MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 828 of file sys.h.

## ◆ SYS_GPD_MFPL_PD6MFP_USCI1_DAT1

#define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1

USCI1 data1 pin.

Definition at line 831 of file sys.h.

## ◆ SYS_GPD_MFPL_PD7MFP_GPIO

#define SYS_GPD_MFPL_PD7MFP_GPIO

General purpose digital I/O pin.

Definition at line 833 of file sys.h.

## ◆ SYS_GPD_MFPL_PD7MFP_I2C0_SCL

#define SYS_GPD_MFPL_PD7MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 835 of file sys.h.

## ◆ SYS_GPD_MFPL_PD7MFP_SC1_PWR

#define SYS_GPD_MFPL_PD7MFP_SC1_PWR

SmartCard1 power pin.

Definition at line 838 of file sys.h.

## ◆ SYS_GPD_MFPL_PD7MFP_SPI1_MISO

#define SYS_GPD_MFPL_PD7MFP_SPI1_MISO

1st SPI1 MISO (Master In, Slave Out) pin.

Definition at line 836 of file sys.h.

## ◆ SYS_GPD_MFPL_PD7MFP_UART1_TXD

#define SYS_GPD_MFPL_PD7MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 834 of file sys.h.

## ◆ SYS_GPD_MFPL_PD7MFP_USCI1_CLK

#define SYS_GPD_MFPL_PD7MFP_USCI1_CLK

USCI1 clock pin.

Definition at line 837 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_EBI_ADR12

#define SYS_GPE_MFPH_PE10MFP_EBI_ADR12

EBI address/data bus bit*.

Definition at line 1001 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_ECAP0_IC2

#define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2

Input 0 of enhanced capture unit 2.

Definition at line 1009 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0

#define SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0

RMII Transmit Data bus bit 0.

Definition at line 1002 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_EPWM0_CH2

#define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2

EPWM0 channel2 output/capture input.

Definition at line 1007 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0

#define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0

Brake input pin 0 of EPWM1.

Definition at line 1008 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_GPIO

#define SYS_GPE_MFPH_PE10MFP_GPIO

General purpose digital I/O pin.

Definition at line 1000 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_I2S0_DI

#define SYS_GPE_MFPH_PE10MFP_I2S0_DI

I2S0 data input.

Definition at line 1003 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_SPI2_MOSI

#define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI

1st SPI2 MOSI (Master Out, Slave In) pin.

Definition at line 1004 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_TRACE_DATA1

#define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1

ETM Rx input bus bit1.

Definition at line 1010 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_UART3_TXD

#define SYS_GPE_MFPH_PE10MFP_UART3_TXD

Data transmitter output pin for UART3.

Definition at line 1006 of file sys.h.

## ◆ SYS_GPE_MFPH_PE10MFP_USCI1_DAT0

#define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0

USCI1 data0 pin.

Definition at line 1005 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_EBI_ADR13

#define SYS_GPE_MFPH_PE11MFP_EBI_ADR13

EBI address/data bus bit*.

Definition at line 1012 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_ECAP1_IC2

#define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2

Input 1 of enhanced capture unit 2.

Definition at line 1021 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1

#define SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1

RMII Transmit Data bus bit 1.

Definition at line 1013 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_EPWM0_CH3

#define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3

EPWM0 channel3 output/capture input.

Definition at line 1019 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1

#define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1

Brake input pin 1 of EPWM1.

Definition at line 1020 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_GPIO

#define SYS_GPE_MFPH_PE11MFP_GPIO

General purpose digital I/O pin.

Definition at line 1011 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_I2S0_DO

#define SYS_GPE_MFPH_PE11MFP_I2S0_DO

I2S0 data output.

Definition at line 1014 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_SPI2_SS

#define SYS_GPE_MFPH_PE11MFP_SPI2_SS

1st SPI2 slave select pin.

Definition at line 1015 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_TRACE_DATA0

#define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0

ETM Rx input bus bit0.

Definition at line 1022 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_UART1_nCTS

#define SYS_GPE_MFPH_PE11MFP_UART1_nCTS

Clear to Send input pin for UART1.

Definition at line 1018 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_UART3_RXD

#define SYS_GPE_MFPH_PE11MFP_UART3_RXD

Data receiver input pin for UART3.

Definition at line 1017 of file sys.h.

## ◆ SYS_GPE_MFPH_PE11MFP_USCI1_DAT1

#define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1

USCI1 data1 pin.

Definition at line 1016 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_EBI_ADR14

#define SYS_GPE_MFPH_PE12MFP_EBI_ADR14

EBI address/data bus bit*.

Definition at line 1024 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_ECAP1_IC1

#define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1

Input 1 of enhanced capture unit 1.

Definition at line 1031 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN

#define SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN

RMII? Transmit Enable.

Definition at line 1025 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_EPWM0_CH4

#define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4

EPWM0 channel4 output/capture input.

Definition at line 1030 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_GPIO

#define SYS_GPE_MFPH_PE12MFP_GPIO

General purpose digital I/O pin.

Definition at line 1023 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_I2S0_LRCK

#define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK

I2S0 left right channel clock.

Definition at line 1026 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK

#define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK

SPI2 I2S master clock output pin.

Definition at line 1027 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_TRACE_CLK

#define SYS_GPE_MFPH_PE12MFP_TRACE_CLK

ETM Rx clock input pin.

Definition at line 1032 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_UART1_nRTS

#define SYS_GPE_MFPH_PE12MFP_UART1_nRTS

Request to Send output pin for UART1.

Definition at line 1029 of file sys.h.

## ◆ SYS_GPE_MFPH_PE12MFP_USCI1_CLK

#define SYS_GPE_MFPH_PE12MFP_USCI1_CLK

USCI1 clock pin.

Definition at line 1028 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_BPWM1_CH5

#define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5

BPWM1 channel5 output/capture input.

Definition at line 1041 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_EBI_ADR15

#define SYS_GPE_MFPH_PE13MFP_EBI_ADR15

EBI address/data bus bit*.

Definition at line 1034 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_ECAP1_IC0

#define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0

Input 0 of enhanced capture unit 1.

Definition at line 1042 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_EMAC_PPS

#define SYS_GPE_MFPH_PE13MFP_EMAC_PPS

EMAC Pulse Per Second output

Definition at line 1035 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_EPWM0_CH5

#define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5

EPWM0 channel5 output/capture input.

Definition at line 1039 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_EPWM1_CH0

#define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0

EPWM1 channel0 output/capture input.

Definition at line 1040 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_GPIO

#define SYS_GPE_MFPH_PE13MFP_GPIO

General purpose digital I/O pin.

Definition at line 1033 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_I2C0_SCL

#define SYS_GPE_MFPH_PE13MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 1036 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_UART1_TXD

#define SYS_GPE_MFPH_PE13MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 1038 of file sys.h.

## ◆ SYS_GPE_MFPH_PE13MFP_UART4_nRTS

#define SYS_GPE_MFPH_PE13MFP_UART4_nRTS

Request to Send output pin for UART4.

Definition at line 1037 of file sys.h.

## ◆ SYS_GPE_MFPH_PE14MFP_CAN0_TXD

#define SYS_GPE_MFPH_PE14MFP_CAN0_TXD

CAN0 bus transmitter output.

Definition at line 1046 of file sys.h.

## ◆ SYS_GPE_MFPH_PE14MFP_EBI_AD8

#define SYS_GPE_MFPH_PE14MFP_EBI_AD8

EBI address/data bus bit8.

Definition at line 1044 of file sys.h.

## ◆ SYS_GPE_MFPH_PE14MFP_GPIO

#define SYS_GPE_MFPH_PE14MFP_GPIO

General purpose digital I/O pin.

Definition at line 1043 of file sys.h.

## ◆ SYS_GPE_MFPH_PE14MFP_SD1_nCD

#define SYS_GPE_MFPH_PE14MFP_SD1_nCD

SD/SDIO 1 card detect

Definition at line 1047 of file sys.h.

## ◆ SYS_GPE_MFPH_PE14MFP_UART2_TXD

#define SYS_GPE_MFPH_PE14MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 1045 of file sys.h.

## ◆ SYS_GPE_MFPH_PE14MFP_UART6_TXD

#define SYS_GPE_MFPH_PE14MFP_UART6_TXD (0x06UL<<SYS_GPE_MFPH_PE14MFP_Pos)

Data transmitter output pin for UART6.

Definition at line 1048 of file sys.h.

## ◆ SYS_GPE_MFPH_PE15MFP_CAN0_RXD

#define SYS_GPE_MFPH_PE15MFP_CAN0_RXD

CAN0 bus receiver input.

Definition at line 1052 of file sys.h.

## ◆ SYS_GPE_MFPH_PE15MFP_EBI_AD9

#define SYS_GPE_MFPH_PE15MFP_EBI_AD9

EBI address/data bus bit9.

Definition at line 1050 of file sys.h.

## ◆ SYS_GPE_MFPH_PE15MFP_GPIO

#define SYS_GPE_MFPH_PE15MFP_GPIO

General purpose digital I/O pin.

Definition at line 1049 of file sys.h.

## ◆ SYS_GPE_MFPH_PE15MFP_UART2_RXD

#define SYS_GPE_MFPH_PE15MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 1051 of file sys.h.

## ◆ SYS_GPE_MFPH_PE15MFP_UART6_RXD

#define SYS_GPE_MFPH_PE15MFP_UART6_RXD

Data receiver input pin for UART6.

Definition at line 1053 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_EBI_ADR10

#define SYS_GPE_MFPH_PE8MFP_EBI_ADR10

EBI address/data bus bit*.

Definition at line 979 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_ECAP0_IC0

#define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0

Input 0 of enhanced capture unit 0.

Definition at line 987 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC

#define SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC

RMII Management Data Clock.

Definition at line 980 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0

#define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0

Brake input pin 0 of EPWM0.

Definition at line 986 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_EPWM0_CH0

#define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0

EPWM0 channel0 output/capture input.

Definition at line 985 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_GPIO

#define SYS_GPE_MFPH_PE8MFP_GPIO

General purpose digital I/O pin.

Definition at line 978 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_I2S0_BCLK

#define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK

I2S0 bit clock pin.

Definition at line 981 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_SPI2_CLK

#define SYS_GPE_MFPH_PE8MFP_SPI2_CLK

SPI2 serial clock pin.

Definition at line 982 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_TRACE_DATA3

#define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3

ETM Rx input bus bit3.

Definition at line 988 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_UART2_TXD

#define SYS_GPE_MFPH_PE8MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 984 of file sys.h.

## ◆ SYS_GPE_MFPH_PE8MFP_USCI1_CTL1

#define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1

USCI1 control1 pin.

Definition at line 983 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_EBI_ADR11

#define SYS_GPE_MFPH_PE9MFP_EBI_ADR11

EBI address/data bus bit*.

Definition at line 990 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_ECAP0_IC1

#define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1

Input 1 of enhanced capture unit 0.

Definition at line 998 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO

#define SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO

RMII Management Data I/O.

Definition at line 991 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1

#define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1

Brake input pin 1 of EPWM0.

Definition at line 997 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_EPWM0_CH1

#define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1

EPWM0 channel1 output/capture input.

Definition at line 996 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_GPIO

#define SYS_GPE_MFPH_PE9MFP_GPIO

General purpose digital I/O pin.

Definition at line 989 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_I2S0_MCLK

#define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK

I2S0 master clock output pin.

Definition at line 992 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_SPI2_MISO

#define SYS_GPE_MFPH_PE9MFP_SPI2_MISO

1st SPI2 MISO (Master In, Slave Out) pin.

Definition at line 993 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_TRACE_DATA2

#define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2

ETM Rx input bus bit2.

Definition at line 999 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_UART2_RXD

#define SYS_GPE_MFPH_PE9MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 995 of file sys.h.

## ◆ SYS_GPE_MFPH_PE9MFP_USCI1_CTL0

#define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0

USCI1 control0 pin.

Definition at line 994 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_EBI_AD11

#define SYS_GPE_MFPL_PE0MFP_EBI_AD11

EBI address/data bus bit1.

Definition at line 893 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_GPIO

#define SYS_GPE_MFPL_PE0MFP_GPIO

General purpose digital I/O pin.

Definition at line 892 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_I2C1_SDA

#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 899 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_I2S0_MCLK

#define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK

I2S0 master clock output pin.

Definition at line 896 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0

#define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0

1st QSPI0 MOSI (Master Out, Slave In) pin.

Definition at line 894 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_SC2_CLK

#define SYS_GPE_MFPL_PE0MFP_SC2_CLK

SmartCard2 clock pin.

Definition at line 895 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_SPI1_MOSI

#define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI

1st SPI1 MOSI (Master Out, Slave In) pin.

Definition at line 897 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_UART3_RXD

#define SYS_GPE_MFPL_PE0MFP_UART3_RXD

Data receiver input pin for UART3.

Definition at line 898 of file sys.h.

## ◆ SYS_GPE_MFPL_PE0MFP_UART4_nRTS

#define SYS_GPE_MFPL_PE0MFP_UART4_nRTS

Request to Send output pin for UART4.

Definition at line 900 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_EBI_AD10

#define SYS_GPE_MFPL_PE1MFP_EBI_AD10

EBI address/data bus bit1.

Definition at line 902 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_GPIO

#define SYS_GPE_MFPL_PE1MFP_GPIO

General purpose digital I/O pin.

Definition at line 901 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_I2C1_SCL

#define SYS_GPE_MFPL_PE1MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 908 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_I2S0_BCLK

#define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK

I2S0 bit clock pin.

Definition at line 905 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0

#define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0

1st QSPI0 MISO (Master In, Slave Out) pin.

Definition at line 903 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_SC2_DAT

#define SYS_GPE_MFPL_PE1MFP_SC2_DAT

SmartCard2 data pin.

Definition at line 904 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_SPI1_MISO

#define SYS_GPE_MFPL_PE1MFP_SPI1_MISO

1st SPI1 MISO (Master In, Slave Out) pin.

Definition at line 906 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_UART3_TXD

#define SYS_GPE_MFPL_PE1MFP_UART3_TXD

Data transmitter output pin for UART3.

Definition at line 907 of file sys.h.

## ◆ SYS_GPE_MFPL_PE1MFP_UART4_nCTS

#define SYS_GPE_MFPL_PE1MFP_UART4_nCTS

Clear to Send input pin for UART4.

Definition at line 909 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_BPWM0_CH0

#define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0

BPWM0 channel0 output/capture input.

Definition at line 921 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_EBI_ALE

#define SYS_GPE_MFPL_PE2MFP_EBI_ALE

EBI address latch enable output pin.

Definition at line 911 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_EPWM0_CH5

#define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5

EPWM0 channel5 output/capture input.

Definition at line 920 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_GPIO

#define SYS_GPE_MFPL_PE2MFP_GPIO

General purpose digital I/O pin.

Definition at line 910 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_QEI0_B

#define SYS_GPE_MFPL_PE2MFP_QEI0_B

Quadrature encoder phase B input of QEI Unit 0.

Definition at line 919 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_SC0_CLK

#define SYS_GPE_MFPL_PE2MFP_SC0_CLK

SmartCard0 clock pin.

Definition at line 915 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_SD0_DAT0

#define SYS_GPE_MFPL_PE2MFP_SD0_DAT0

SD/SDIO 0 data line bit 0.

Definition at line 912 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_SPI3_MOSI

#define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI

1st SPI3 MOSI (Master Out, Slave In) pin.

Definition at line 914 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_SPIM_MOSI

#define SYS_GPE_MFPL_PE2MFP_SPIM_MOSI

1st SPIM MOSI (Master Out, Slave In) pin.

Definition at line 913 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_UART6_nCTS

#define SYS_GPE_MFPL_PE2MFP_UART6_nCTS

Clear to Send input pin for UART6.

Definition at line 917 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_UART7_RXD

#define SYS_GPE_MFPL_PE2MFP_UART7_RXD

Data receiver input pin for UART7.

Definition at line 918 of file sys.h.

## ◆ SYS_GPE_MFPL_PE2MFP_USCI0_CLK

#define SYS_GPE_MFPL_PE2MFP_USCI0_CLK

USCI0 clock pin.

Definition at line 916 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_BPWM0_CH1

#define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1

BPWM0 channel1 output/capture input.

Definition at line 933 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_EBI_MCLK

#define SYS_GPE_MFPL_PE3MFP_EBI_MCLK

EBI external clock output pin.

Definition at line 923 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_EPWM0_CH4

#define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4

EPWM0 channel4 output/capture input.

Definition at line 932 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_GPIO

#define SYS_GPE_MFPL_PE3MFP_GPIO

General purpose digital I/O pin.

Definition at line 922 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_QEI0_A

#define SYS_GPE_MFPL_PE3MFP_QEI0_A

Quadrature encoder phase A input of QEI Unit 0.

Definition at line 931 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_SC0_DAT

#define SYS_GPE_MFPL_PE3MFP_SC0_DAT

SmartCard0 data pin.

Definition at line 927 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_SD0_DAT1

#define SYS_GPE_MFPL_PE3MFP_SD0_DAT1

SD/SDIO 0 data line bit 1.

Definition at line 924 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_SPI3_MISO

#define SYS_GPE_MFPL_PE3MFP_SPI3_MISO

1st SPI3 MISO (Master In, Slave Out) pin.

Definition at line 926 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_SPIM_MISO

#define SYS_GPE_MFPL_PE3MFP_SPIM_MISO

1st SPIM MISO (Master In, Slave Out) pin.

Definition at line 925 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_UART6_nRTS

#define SYS_GPE_MFPL_PE3MFP_UART6_nRTS

Request to Send output pin for UART6.

Definition at line 929 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_UART7_TXD

#define SYS_GPE_MFPL_PE3MFP_UART7_TXD

Data transmitter output pin for UART7.

Definition at line 930 of file sys.h.

## ◆ SYS_GPE_MFPL_PE3MFP_USCI0_DAT0

#define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0

USCI0 data0 pin.

Definition at line 928 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_BPWM0_CH2

#define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2

BPWM0 channel2 output/capture input.

Definition at line 945 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_EBI_nWR

#define SYS_GPE_MFPL_PE4MFP_EBI_nWR

EBI write enable output pin.

Definition at line 935 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_EPWM0_CH3

#define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3

EPWM0 channel3 output/capture input.

Definition at line 944 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_GPIO

#define SYS_GPE_MFPL_PE4MFP_GPIO

General purpose digital I/O pin.

Definition at line 934 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_QEI0_INDEX

#define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX

Quadrature encoder index input of QEI Unit 0.

Definition at line 943 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_SC0_RST

#define SYS_GPE_MFPL_PE4MFP_SC0_RST

SmartCard0 reset pin.

Definition at line 939 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_SD0_DAT2

#define SYS_GPE_MFPL_PE4MFP_SD0_DAT2

SD/SDIO 0 data line bit 2.

Definition at line 936 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_SPI3_CLK

#define SYS_GPE_MFPL_PE4MFP_SPI3_CLK

SPI3 serial clock pin.

Definition at line 938 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_SPIM_CLK

#define SYS_GPE_MFPL_PE4MFP_SPIM_CLK

SPIM serial clock pin.

Definition at line 937 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_UART6_RXD

#define SYS_GPE_MFPL_PE4MFP_UART6_RXD

Data receiver input pin for UART6.

Definition at line 941 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_UART7_nCTS

#define SYS_GPE_MFPL_PE4MFP_UART7_nCTS

Clear to Send input pin for UART7.

Definition at line 942 of file sys.h.

## ◆ SYS_GPE_MFPL_PE4MFP_USCI0_DAT1

#define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1

USCI0 data1 pin.

Definition at line 940 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_BPWM0_CH3

#define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3

BPWM0 channel3 output/capture input.

Definition at line 957 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_EBI_nRD

#define SYS_GPE_MFPL_PE5MFP_EBI_nRD

EBI read enable output pin.

Definition at line 947 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_EPWM0_CH2

#define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2

EPWM0 channel2 output/capture input.

Definition at line 956 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_GPIO

#define SYS_GPE_MFPL_PE5MFP_GPIO

General purpose digital I/O pin.

Definition at line 946 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_QEI1_B

#define SYS_GPE_MFPL_PE5MFP_QEI1_B

Quadrature encoder phase B input of QEI Unit 1.

Definition at line 955 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_SC0_PWR

#define SYS_GPE_MFPL_PE5MFP_SC0_PWR

SmartCard0 power pin.

Definition at line 951 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_SD0_DAT3

#define SYS_GPE_MFPL_PE5MFP_SD0_DAT3

SD/SDIO 0 data line bit 3.

Definition at line 948 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_SPI3_SS

#define SYS_GPE_MFPL_PE5MFP_SPI3_SS

1st SPI3 slave select pin.

Definition at line 950 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_SPIM_SS

#define SYS_GPE_MFPL_PE5MFP_SPIM_SS

1st SPIM slave select pin.

Definition at line 949 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_UART6_TXD

#define SYS_GPE_MFPL_PE5MFP_UART6_TXD

Data transmitter output pin for UART6.

Definition at line 953 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_UART7_nRTS

#define SYS_GPE_MFPL_PE5MFP_UART7_nRTS

Request to Send output pin for UART7.

Definition at line 954 of file sys.h.

## ◆ SYS_GPE_MFPL_PE5MFP_USCI0_CTL1

#define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1

USCI0 control1 pin.

Definition at line 952 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_BPWM0_CH4

#define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4

BPWM0 channel4 output/capture input.

Definition at line 968 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_CAN1_RXD

#define SYS_GPE_MFPL_PE6MFP_CAN1_RXD

CAN1 bus receiver input.

Definition at line 965 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_EPWM0_CH1

#define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1

EPWM0 channel1 output/capture input.

Definition at line 967 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_GPIO

#define SYS_GPE_MFPL_PE6MFP_GPIO

General purpose digital I/O pin.

Definition at line 958 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_QEI1_A

#define SYS_GPE_MFPL_PE6MFP_QEI1_A

Quadrature encoder phase A input of QEI Unit 1.

Definition at line 966 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_SC0_nCD

#define SYS_GPE_MFPL_PE6MFP_SC0_nCD

SmartCard0 card detect pin.

Definition at line 962 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_SD0_CLK

#define SYS_GPE_MFPL_PE6MFP_SD0_CLK

SD/SDIO 0 clock.

Definition at line 959 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK

#define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK

SPI3 I2S master clock output pin.

Definition at line 961 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_SPIM_D3

#define SYS_GPE_MFPL_PE6MFP_SPIM_D3

SPIM data 3 pin for Quad Mode I/O.

Definition at line 960 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_UART5_RXD

#define SYS_GPE_MFPL_PE6MFP_UART5_RXD

Data receiver input pin for UART5.

Definition at line 964 of file sys.h.

## ◆ SYS_GPE_MFPL_PE6MFP_USCI0_CTL0

#define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0

USCI0 control0 pin.

Definition at line 963 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_BPWM0_CH5

#define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5

BPWM0 channel5 output/capture input.

Definition at line 976 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_CAN1_TXD

#define SYS_GPE_MFPL_PE7MFP_CAN1_TXD

CAN1 bus transmitter output.

Definition at line 973 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_EPWM0_CH0

#define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0

EPWM0 channel0 output/capture input.

Definition at line 975 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_GPIO

#define SYS_GPE_MFPL_PE7MFP_GPIO

General purpose digital I/O pin.

Definition at line 969 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_QEI1_INDEX

#define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX

Quadrature encoder index input of QEI Unit 1.

Definition at line 974 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_SD0_CMD

#define SYS_GPE_MFPL_PE7MFP_SD0_CMD

SD/SDIO 0 command/response.

Definition at line 970 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_SPIM_D2

#define SYS_GPE_MFPL_PE7MFP_SPIM_D2

SPIM data 2 pin for Quad Mode I/O.

Definition at line 971 of file sys.h.

## ◆ SYS_GPE_MFPL_PE7MFP_UART5_TXD

#define SYS_GPE_MFPL_PE7MFP_UART5_TXD

Data transmitter output pin for UART5.

Definition at line 972 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_CCAP_DATA3

#define SYS_GPF_MFPH_PF10MFP_CCAP_DATA3

Sensor pixel data3 input pin.

Definition at line 1138 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_EBI_ADR15

#define SYS_GPF_MFPH_PF10MFP_EBI_ADR15

EBI address/data bus bit*.

Definition at line 1133 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_GPIO

#define SYS_GPF_MFPH_PF10MFP_GPIO

General purpose digital I/O pin.

Definition at line 1132 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_I2S0_BCLK

#define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK

I2S0 bit clock pin.

Definition at line 1135 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_SC0_nCD

#define SYS_GPF_MFPH_PF10MFP_SC0_nCD

SmartCard0 card detect pin.

Definition at line 1134 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK

#define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK

SPI0 I2S master clock output pin.

Definition at line 1136 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_TAMPER4

#define SYS_GPF_MFPH_PF10MFP_TAMPER4

TAMPER detector loop pin4.

Definition at line 1139 of file sys.h.

## ◆ SYS_GPF_MFPH_PF10MFP_UART5_RXD

#define SYS_GPF_MFPH_PF10MFP_UART5_RXD

Data receiver input pin for UART5.

Definition at line 1137 of file sys.h.

## ◆ SYS_GPF_MFPH_PF11MFP_CCAP_DATA4

#define SYS_GPF_MFPH_PF11MFP_CCAP_DATA4

Sensor pixel data4 input pin.

Definition at line 1144 of file sys.h.

## ◆ SYS_GPF_MFPH_PF11MFP_EBI_ADR14

#define SYS_GPF_MFPH_PF11MFP_EBI_ADR14

EBI address/data bus bit*.

Definition at line 1141 of file sys.h.

## ◆ SYS_GPF_MFPH_PF11MFP_GPIO

#define SYS_GPF_MFPH_PF11MFP_GPIO

General purpose digital I/O pin.

Definition at line 1140 of file sys.h.

## ◆ SYS_GPF_MFPH_PF11MFP_SPI2_MOSI

#define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI

1st SPI2 MOSI (Master Out, Slave In) pin.

Definition at line 1142 of file sys.h.

## ◆ SYS_GPF_MFPH_PF11MFP_TAMPER5

#define SYS_GPF_MFPH_PF11MFP_TAMPER5

TAMPER detector loop pin5.

Definition at line 1145 of file sys.h.

## ◆ SYS_GPF_MFPH_PF11MFP_TM3

#define SYS_GPF_MFPH_PF11MFP_TM3

Timer3 event counter input / toggle output

Definition at line 1146 of file sys.h.

## ◆ SYS_GPF_MFPH_PF11MFP_UART5_TXD

#define SYS_GPF_MFPH_PF11MFP_UART5_TXD

Data transmitter output pin for UART5.

Definition at line 1143 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_CAN1_RXD

#define SYS_GPF_MFPH_PF8MFP_CAN1_RXD (0x08UL<<SYS_GPF_MFPH_PF8MFP_Pos)

CAN1 bus receiver input.

Definition at line 1121 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_CCAP_DATA1

#define SYS_GPF_MFPH_PF8MFP_CCAP_DATA1

Sensor pixel data1 input pin.

Definition at line 1120 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_EBI_ADR17

#define SYS_GPF_MFPH_PF8MFP_EBI_ADR17

EBI address/data bus bit*.

Definition at line 1115 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_GPIO

#define SYS_GPF_MFPH_PF8MFP_GPIO

General purpose digital I/O pin.

Definition at line 1114 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_I2S0_DI

#define SYS_GPF_MFPH_PF8MFP_I2S0_DI

I2S0 data input.

Definition at line 1117 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_SC0_RST

#define SYS_GPF_MFPH_PF8MFP_SC0_RST

SmartCard0 reset pin.

Definition at line 1116 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_SPI0_CLK

#define SYS_GPF_MFPH_PF8MFP_SPI0_CLK

SPI0 serial clock pin.

Definition at line 1118 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_TAMPER2

#define SYS_GPF_MFPH_PF8MFP_TAMPER2

TAMPER detector loop pin2.

Definition at line 1122 of file sys.h.

## ◆ SYS_GPF_MFPH_PF8MFP_UART5_nCTS

#define SYS_GPF_MFPH_PF8MFP_UART5_nCTS

Clear to Send input pin for UART5.

Definition at line 1119 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_CAN1_TXD

#define SYS_GPF_MFPH_PF9MFP_CAN1_TXD

CAN1 bus transmitter output.

Definition at line 1130 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_CCAP_DATA2

#define SYS_GPF_MFPH_PF9MFP_CCAP_DATA2

Sensor pixel data2 input pin.

Definition at line 1129 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_EBI_ADR16

#define SYS_GPF_MFPH_PF9MFP_EBI_ADR16

EBI address/data bus bit*.

Definition at line 1124 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_GPIO

#define SYS_GPF_MFPH_PF9MFP_GPIO

General purpose digital I/O pin.

Definition at line 1123 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_I2S0_MCLK

#define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK

I2S0 master clock output pin.

Definition at line 1126 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_SC0_PWR

#define SYS_GPF_MFPH_PF9MFP_SC0_PWR

SmartCard0 power pin.

Definition at line 1125 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_SPI0_SS

#define SYS_GPF_MFPH_PF9MFP_SPI0_SS

1st SPI0 slave select pin.

Definition at line 1127 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_TAMPER3

#define SYS_GPF_MFPH_PF9MFP_TAMPER3

TAMPER detector loop pin3.

Definition at line 1131 of file sys.h.

## ◆ SYS_GPF_MFPH_PF9MFP_UART5_nRTS

#define SYS_GPF_MFPH_PF9MFP_UART5_nRTS

Request to Send output pin for UART5.

Definition at line 1128 of file sys.h.

## ◆ SYS_GPF_MFPL_PF0MFP_BPWM1_CH0

#define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0

BPWM1 channel0 output/capture input.

Definition at line 1059 of file sys.h.

## ◆ SYS_GPF_MFPL_PF0MFP_GPIO

#define SYS_GPF_MFPL_PF0MFP_GPIO

General purpose digital I/O pin.

Definition at line 1055 of file sys.h.

## ◆ SYS_GPF_MFPL_PF0MFP_I2C1_SCL

#define SYS_GPF_MFPL_PF0MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 1057 of file sys.h.

## ◆ SYS_GPF_MFPL_PF0MFP_ICE_DAT

#define SYS_GPF_MFPL_PF0MFP_ICE_DAT

Serial wired debugger data pin.

Definition at line 1060 of file sys.h.

## ◆ SYS_GPF_MFPL_PF0MFP_UART0_TXD

#define SYS_GPF_MFPL_PF0MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 1058 of file sys.h.

## ◆ SYS_GPF_MFPL_PF0MFP_UART1_TXD

#define SYS_GPF_MFPL_PF0MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 1056 of file sys.h.

## ◆ SYS_GPF_MFPL_PF1MFP_BPWM1_CH1

#define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1

BPWM1 channel1 output/capture input.

Definition at line 1065 of file sys.h.

## ◆ SYS_GPF_MFPL_PF1MFP_GPIO

#define SYS_GPF_MFPL_PF1MFP_GPIO

General purpose digital I/O pin.

Definition at line 1061 of file sys.h.

## ◆ SYS_GPF_MFPL_PF1MFP_I2C1_SDA

#define SYS_GPF_MFPL_PF1MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 1063 of file sys.h.

## ◆ SYS_GPF_MFPL_PF1MFP_ICE_CLK

#define SYS_GPF_MFPL_PF1MFP_ICE_CLK

Serial wired debugger clock pin.

Definition at line 1066 of file sys.h.

## ◆ SYS_GPF_MFPL_PF1MFP_UART0_RXD

#define SYS_GPF_MFPL_PF1MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 1064 of file sys.h.

## ◆ SYS_GPF_MFPL_PF1MFP_UART1_RXD

#define SYS_GPF_MFPL_PF1MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 1062 of file sys.h.

## ◆ SYS_GPF_MFPL_PF2MFP_BPWM1_CH1

#define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1

BPWM1 channel1 output/capture input.

Definition at line 1073 of file sys.h.

## ◆ SYS_GPF_MFPL_PF2MFP_EBI_nCS1

#define SYS_GPF_MFPL_PF2MFP_EBI_nCS1

EBI chip select enable output pin.

Definition at line 1068 of file sys.h.

## ◆ SYS_GPF_MFPL_PF2MFP_GPIO

#define SYS_GPF_MFPL_PF2MFP_GPIO

General purpose digital I/O pin.

Definition at line 1067 of file sys.h.

## ◆ SYS_GPF_MFPL_PF2MFP_I2C0_SDA

#define SYS_GPF_MFPL_PF2MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 1070 of file sys.h.

## ◆ SYS_GPF_MFPL_PF2MFP_QSPI0_CLK

#define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK

QSPI0 serial clock pin.

Definition at line 1071 of file sys.h.

## ◆ SYS_GPF_MFPL_PF2MFP_UART0_RXD

#define SYS_GPF_MFPL_PF2MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 1069 of file sys.h.

## ◆ SYS_GPF_MFPL_PF2MFP_XT1_OUT

#define SYS_GPF_MFPL_PF2MFP_XT1_OUT

External 4~24 MHz (high speed) crystal output pin.

Definition at line 1072 of file sys.h.

## ◆ SYS_GPF_MFPL_PF3MFP_BPWM1_CH0

#define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0

BPWM1 channel0 output/capture input.

Definition at line 1079 of file sys.h.

## ◆ SYS_GPF_MFPL_PF3MFP_EBI_nCS0

#define SYS_GPF_MFPL_PF3MFP_EBI_nCS0

EBI chip select enable output pin.

Definition at line 1075 of file sys.h.

## ◆ SYS_GPF_MFPL_PF3MFP_GPIO

#define SYS_GPF_MFPL_PF3MFP_GPIO

General purpose digital I/O pin.

Definition at line 1074 of file sys.h.

## ◆ SYS_GPF_MFPL_PF3MFP_I2C0_SCL

#define SYS_GPF_MFPL_PF3MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 1077 of file sys.h.

## ◆ SYS_GPF_MFPL_PF3MFP_UART0_TXD

#define SYS_GPF_MFPL_PF3MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 1076 of file sys.h.

## ◆ SYS_GPF_MFPL_PF3MFP_XT1_IN

#define SYS_GPF_MFPL_PF3MFP_XT1_IN

External 4~24 MHz (high speed) crystal input pin.

Definition at line 1078 of file sys.h.

## ◆ SYS_GPF_MFPL_PF4MFP_BPWM0_CH5

#define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5

BPWM0 channel5 output/capture input.

Definition at line 1084 of file sys.h.

## ◆ SYS_GPF_MFPL_PF4MFP_EADC1_ST

#define SYS_GPF_MFPL_PF4MFP_EADC1_ST

EADC external trigger input.

Definition at line 1086 of file sys.h.

## ◆ SYS_GPF_MFPL_PF4MFP_EPWM0_CH1

#define SYS_GPF_MFPL_PF4MFP_EPWM0_CH1

EPWM0 channel1 output/capture input.

Definition at line 1083 of file sys.h.

## ◆ SYS_GPF_MFPL_PF4MFP_GPIO

#define SYS_GPF_MFPL_PF4MFP_GPIO

General purpose digital I/O pin.

Definition at line 1080 of file sys.h.

## ◆ SYS_GPF_MFPL_PF4MFP_UART2_nRTS

#define SYS_GPF_MFPL_PF4MFP_UART2_nRTS

Request to Send output pin for UART2.

Definition at line 1082 of file sys.h.

## ◆ SYS_GPF_MFPL_PF4MFP_UART2_TXD

#define SYS_GPF_MFPL_PF4MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 1081 of file sys.h.

## ◆ SYS_GPF_MFPL_PF4MFP_X32_OUT

#define SYS_GPF_MFPL_PF4MFP_X32_OUT

External 32.768 kHz (low speed) crystal output pin.

Definition at line 1085 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_BPWM0_CH4

#define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4

BPWM0 channel4 output/capture input.

Definition at line 1091 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_EADC0_ST

#define SYS_GPF_MFPL_PF5MFP_EADC0_ST

EADC external trigger input.

Definition at line 1094 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_EPWM0_CH0

#define SYS_GPF_MFPL_PF5MFP_EPWM0_CH0

EPWM0 channel0 output/capture input.

Definition at line 1090 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT

#define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT

EPWM0 counter synchronous trigger output pin.

Definition at line 1092 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_GPIO

#define SYS_GPF_MFPL_PF5MFP_GPIO

General purpose digital I/O pin.

Definition at line 1087 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_UART2_nCTS

#define SYS_GPF_MFPL_PF5MFP_UART2_nCTS

Clear to Send input pin for UART2.

Definition at line 1089 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_UART2_RXD

#define SYS_GPF_MFPL_PF5MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 1088 of file sys.h.

## ◆ SYS_GPF_MFPL_PF5MFP_X32_IN

#define SYS_GPF_MFPL_PF5MFP_X32_IN

External 32.768 kHz (low speed) crystal input pin.

Definition at line 1093 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_CAN2_RXD

#define SYS_GPF_MFPL_PF6MFP_CAN2_RXD

CAN2 bus receiver input.

Definition at line 1102 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_EBI_ADR19

#define SYS_GPF_MFPL_PF6MFP_EBI_ADR19

EBI address/data bus bit*.

Definition at line 1096 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_EBI_nCS0

#define SYS_GPF_MFPL_PF6MFP_EBI_nCS0

EBI chip select enable output pin.

Definition at line 1101 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_GPIO

#define SYS_GPF_MFPL_PF6MFP_GPIO

General purpose digital I/O pin.

Definition at line 1095 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_I2S0_LRCK

#define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK

I2S0 left right channel clock.

Definition at line 1098 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_SC0_CLK

#define SYS_GPF_MFPL_PF6MFP_SC0_CLK

SmartCard0 clock pin.

Definition at line 1097 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_SPI0_MOSI

#define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI

1st SPI0 MOSI (Master Out, Slave In) pin.

Definition at line 1099 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_TAMPER0

#define SYS_GPF_MFPL_PF6MFP_TAMPER0

TAMPER detector loop pin0.

Definition at line 1103 of file sys.h.

## ◆ SYS_GPF_MFPL_PF6MFP_UART4_RXD

#define SYS_GPF_MFPL_PF6MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 1100 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_CAN2_TXD

#define SYS_GPF_MFPL_PF7MFP_CAN2_TXD (0x08UL<<SYS_GPF_MFPL_PF7MFP_Pos)

CAN2 bus transmitter output.

Definition at line 1111 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_CCAP_DATA0

#define SYS_GPF_MFPL_PF7MFP_CCAP_DATA0 (0x07UL<<SYS_GPF_MFPL_PF7MFP_Pos)

Sensor pixel data0 input pin.

Definition at line 1110 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_EBI_ADR18

#define SYS_GPF_MFPL_PF7MFP_EBI_ADR18

EBI address/data bus bit*.

Definition at line 1105 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_GPIO

#define SYS_GPF_MFPL_PF7MFP_GPIO

General purpose digital I/O pin.

Definition at line 1104 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_I2S0_DO

#define SYS_GPF_MFPL_PF7MFP_I2S0_DO

I2S0 data output.

Definition at line 1107 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_SC0_DAT

#define SYS_GPF_MFPL_PF7MFP_SC0_DAT

SmartCard0 data pin.

Definition at line 1106 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_SPI0_MISO

#define SYS_GPF_MFPL_PF7MFP_SPI0_MISO

1st SPI0 MISO (Master In, Slave Out) pin.

Definition at line 1108 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_TAMPER1

#define SYS_GPF_MFPL_PF7MFP_TAMPER1

TAMPER detector loop pin1.

Definition at line 1112 of file sys.h.

## ◆ SYS_GPF_MFPL_PF7MFP_UART4_TXD

#define SYS_GPF_MFPL_PF7MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 1109 of file sys.h.

## ◆ SYS_GPG_MFPH_PG10MFP_BPWM0_CH4

#define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4

BPWM0 channel4 output/capture input.

Definition at line 1216 of file sys.h.

## ◆ SYS_GPG_MFPH_PG10MFP_CCAP_SCLK

#define SYS_GPG_MFPH_PG10MFP_CCAP_SCLK

Sensor pixel clock(to sensor) output pin.

Definition at line 1215 of file sys.h.

## ◆ SYS_GPG_MFPH_PG10MFP_EBI_AD1

#define SYS_GPG_MFPH_PG10MFP_EBI_AD1

EBI address/data bus bit1.

Definition at line 1211 of file sys.h.

## ◆ SYS_GPG_MFPH_PG10MFP_GPIO

#define SYS_GPG_MFPH_PG10MFP_GPIO

General purpose digital I/O pin.

Definition at line 1210 of file sys.h.

## ◆ SYS_GPG_MFPH_PG10MFP_QSPI1_MOSI1

#define SYS_GPG_MFPH_PG10MFP_QSPI1_MOSI1

2nd QSPI1 MOSI (Master Out, Slave In) pin.

Definition at line 1214 of file sys.h.

## ◆ SYS_GPG_MFPH_PG10MFP_SD1_DAT2

#define SYS_GPG_MFPH_PG10MFP_SD1_DAT2

SD/SDIO 1 data line bit 2.

Definition at line 1212 of file sys.h.

## ◆ SYS_GPG_MFPH_PG10MFP_SPIM_D3

#define SYS_GPG_MFPH_PG10MFP_SPIM_D3

SPIM data 3 pin for Quad Mode I/O.

Definition at line 1213 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_BPWM0_CH3

#define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3

BPWM0 channel3 output/capture input.

Definition at line 1224 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_CCAP_SFIELD

#define SYS_GPG_MFPH_PG11MFP_CCAP_SFIELD

Even/Odd Field Flag input pin.

Definition at line 1223 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_EBI_AD2

#define SYS_GPG_MFPH_PG11MFP_EBI_AD2

EBI address/data bus bit2.

Definition at line 1218 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_GPIO

#define SYS_GPG_MFPH_PG11MFP_GPIO

General purpose digital I/O pin.

Definition at line 1217 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_QSPI1_SS

#define SYS_GPG_MFPH_PG11MFP_QSPI1_SS

1st QSPI1 slave select pin.

Definition at line 1221 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_SD1_DAT1

#define SYS_GPG_MFPH_PG11MFP_SD1_DAT1

SD/SDIO 1 data line bit 1.

Definition at line 1219 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_SPIM_SS

#define SYS_GPG_MFPH_PG11MFP_SPIM_SS

1st SPIM slave select pin.

Definition at line 1220 of file sys.h.

## ◆ SYS_GPG_MFPH_PG11MFP_UART7_TXD

#define SYS_GPG_MFPH_PG11MFP_UART7_TXD

Data transmitter output pin for UART7.

Definition at line 1222 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_BPWM0_CH2

#define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2

BPWM0 channel2 output/capture input.

Definition at line 1232 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_CCAP_VSYNC

#define SYS_GPG_MFPH_PG12MFP_CCAP_VSYNC

Sensor vertical synchronization input pin.

Definition at line 1231 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_EBI_AD3

#define SYS_GPG_MFPH_PG12MFP_EBI_AD3

EBI address/data bus bit3.

Definition at line 1226 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_GPIO

#define SYS_GPG_MFPH_PG12MFP_GPIO

General purpose digital I/O pin.

Definition at line 1225 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_QSPI1_CLK

#define SYS_GPG_MFPH_PG12MFP_QSPI1_CLK

QSPI1 serial clock pin.

Definition at line 1229 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_SD1_DAT0

#define SYS_GPG_MFPH_PG12MFP_SD1_DAT0

SD/SDIO 1 data line bit 0.

Definition at line 1227 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_SPIM_CLK

#define SYS_GPG_MFPH_PG12MFP_SPIM_CLK

SPIM serial clock pin.

Definition at line 1228 of file sys.h.

## ◆ SYS_GPG_MFPH_PG12MFP_UART7_RXD

#define SYS_GPG_MFPH_PG12MFP_UART7_RXD

Data receiver input pin for UART7.

Definition at line 1230 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_BPWM0_CH1

#define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1

BPWM0 channel1 output/capture input.

Definition at line 1240 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_CCAP_HSYNC

#define SYS_GPG_MFPH_PG13MFP_CCAP_HSYNC

Sensor horizontal synchronization input pin.

Definition at line 1239 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_EBI_AD4

#define SYS_GPG_MFPH_PG13MFP_EBI_AD4

EBI address/data bus bit4.

Definition at line 1234 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_GPIO

#define SYS_GPG_MFPH_PG13MFP_GPIO

General purpose digital I/O pin.

Definition at line 1233 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_QSPI1_MISO0

#define SYS_GPG_MFPH_PG13MFP_QSPI1_MISO0

1st QSPI1 MISO (Master In, Slave Out) pin.

Definition at line 1237 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_SD1_CMD

#define SYS_GPG_MFPH_PG13MFP_SD1_CMD

SD/SDIO 1 command/response.

Definition at line 1235 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_SPIM_MISO

#define SYS_GPG_MFPH_PG13MFP_SPIM_MISO

1st SPIM MISO (Master In, Slave Out) pin.

Definition at line 1236 of file sys.h.

## ◆ SYS_GPG_MFPH_PG13MFP_UART6_TXD

#define SYS_GPG_MFPH_PG13MFP_UART6_TXD

Data transmitter output pin for UART6.

Definition at line 1238 of file sys.h.

## ◆ SYS_GPG_MFPH_PG14MFP_BPWM0_CH0

#define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0

BPWM0 channel0 output/capture input.

Definition at line 1247 of file sys.h.

## ◆ SYS_GPG_MFPH_PG14MFP_EBI_AD5

#define SYS_GPG_MFPH_PG14MFP_EBI_AD5

EBI address/data bus bit5.

Definition at line 1242 of file sys.h.

## ◆ SYS_GPG_MFPH_PG14MFP_GPIO

#define SYS_GPG_MFPH_PG14MFP_GPIO

General purpose digital I/O pin.

Definition at line 1241 of file sys.h.

## ◆ SYS_GPG_MFPH_PG14MFP_QSPI1_MOSI0

#define SYS_GPG_MFPH_PG14MFP_QSPI1_MOSI0

1st QSPI1 MOSI (Master Out, Slave In) pin.

Definition at line 1245 of file sys.h.

## ◆ SYS_GPG_MFPH_PG14MFP_SD1_CLK

#define SYS_GPG_MFPH_PG14MFP_SD1_CLK

SD/SDIO 1 clock.

Definition at line 1243 of file sys.h.

## ◆ SYS_GPG_MFPH_PG14MFP_SPIM_MOSI

#define SYS_GPG_MFPH_PG14MFP_SPIM_MOSI

1st SPIM MOSI (Master Out, Slave In) pin.

Definition at line 1244 of file sys.h.

## ◆ SYS_GPG_MFPH_PG14MFP_UART6_RXD

#define SYS_GPG_MFPH_PG14MFP_UART6_RXD

Data receiver input pin for UART6.

Definition at line 1246 of file sys.h.

## ◆ SYS_GPG_MFPH_PG15MFP_CLKO

#define SYS_GPG_MFPH_PG15MFP_CLKO

Clock Output pin.

Definition at line 1250 of file sys.h.

## ◆ SYS_GPG_MFPH_PG15MFP_EADC0_ST

#define SYS_GPG_MFPH_PG15MFP_EADC0_ST

EADC external trigger input.

Definition at line 1251 of file sys.h.

## ◆ SYS_GPG_MFPH_PG15MFP_GPIO

#define SYS_GPG_MFPH_PG15MFP_GPIO

General purpose digital I/O pin.

Definition at line 1248 of file sys.h.

## ◆ SYS_GPG_MFPH_PG15MFP_SD1_nCD

#define SYS_GPG_MFPH_PG15MFP_SD1_nCD

SD/SDIO 1 card detect

Definition at line 1249 of file sys.h.

## ◆ SYS_GPG_MFPH_PG8MFP_EBI_nWRH

#define SYS_GPG_MFPH_PG8MFP_EBI_nWRH

EBI write enable output pin.

Definition at line 1199 of file sys.h.

## ◆ SYS_GPG_MFPH_PG8MFP_EPWM0_CH0

#define SYS_GPG_MFPH_PG8MFP_EPWM0_CH0

EPWM0 channel0 output/capture input.

Definition at line 1202 of file sys.h.

## ◆ SYS_GPG_MFPH_PG8MFP_GPIO

#define SYS_GPG_MFPH_PG8MFP_GPIO

General purpose digital I/O pin.

Definition at line 1198 of file sys.h.

## ◆ SYS_GPG_MFPH_PG8MFP_SC1_CLK

#define SYS_GPG_MFPH_PG8MFP_SC1_CLK

SmartCard1 clock pin.

Definition at line 1201 of file sys.h.

## ◆ SYS_GPG_MFPH_PG8MFP_SPI3_MOSI

#define SYS_GPG_MFPH_PG8MFP_SPI3_MOSI

1st SPI3 MOSI (Master Out, Slave In) pin.

Definition at line 1200 of file sys.h.

## ◆ SYS_GPG_MFPH_PG9MFP_BPWM0_CH5

#define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5

BPWM0 channel5 output/capture input.

Definition at line 1209 of file sys.h.

## ◆ SYS_GPG_MFPH_PG9MFP_CCAP_PIXCLK

#define SYS_GPG_MFPH_PG9MFP_CCAP_PIXCLK

Sensor pixel clock(from sensor) input pin.

Definition at line 1208 of file sys.h.

## ◆ SYS_GPG_MFPH_PG9MFP_EBI_AD0

#define SYS_GPG_MFPH_PG9MFP_EBI_AD0

EBI address/data bus bit0.

Definition at line 1204 of file sys.h.

## ◆ SYS_GPG_MFPH_PG9MFP_GPIO

#define SYS_GPG_MFPH_PG9MFP_GPIO

General purpose digital I/O pin.

Definition at line 1203 of file sys.h.

## ◆ SYS_GPG_MFPH_PG9MFP_QSPI1_MISO1

#define SYS_GPG_MFPH_PG9MFP_QSPI1_MISO1

2nd QSPI1 MISO (Master In, Slave Out) pin.

Definition at line 1207 of file sys.h.

## ◆ SYS_GPG_MFPH_PG9MFP_SD1_DAT3

#define SYS_GPG_MFPH_PG9MFP_SD1_DAT3

SD/SDIO 1 data line bit 3.

Definition at line 1205 of file sys.h.

## ◆ SYS_GPG_MFPH_PG9MFP_SPIM_D2

#define SYS_GPG_MFPH_PG9MFP_SPIM_D2

SPIM data 2 pin for Quad Mode I/O.

Definition at line 1206 of file sys.h.

## ◆ SYS_GPG_MFPL_PG0MFP_CAN1_TXD

#define SYS_GPG_MFPL_PG0MFP_CAN1_TXD

CAN1 bus transmitter output.

Definition at line 1153 of file sys.h.

## ◆ SYS_GPG_MFPL_PG0MFP_EBI_ADR8

#define SYS_GPG_MFPL_PG0MFP_EBI_ADR8

EBI address/data bus bit*.

Definition at line 1149 of file sys.h.

## ◆ SYS_GPG_MFPL_PG0MFP_GPIO

#define SYS_GPG_MFPL_PG0MFP_GPIO

General purpose digital I/O pin.

Definition at line 1148 of file sys.h.

## ◆ SYS_GPG_MFPL_PG0MFP_I2C0_SCL

#define SYS_GPG_MFPL_PG0MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 1150 of file sys.h.

## ◆ SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL

#define SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL

I2C1 SMBus SMBALTER# pin

Definition at line 1151 of file sys.h.

## ◆ SYS_GPG_MFPL_PG0MFP_UART1_TXD

#define SYS_GPG_MFPL_PG0MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 1154 of file sys.h.

## ◆ SYS_GPG_MFPL_PG0MFP_UART2_RXD

#define SYS_GPG_MFPL_PG0MFP_UART2_RXD

Data receiver input pin for UART2.

Definition at line 1152 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_CAN1_RXD

#define SYS_GPG_MFPL_PG1MFP_CAN1_RXD

CAN1 bus receiver input.

Definition at line 1161 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_EBI_ADR9

#define SYS_GPG_MFPL_PG1MFP_EBI_ADR9

EBI address/data bus bit*.

Definition at line 1156 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_GPIO

#define SYS_GPG_MFPL_PG1MFP_GPIO

General purpose digital I/O pin.

Definition at line 1155 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_I2C0_SDA

#define SYS_GPG_MFPL_PG1MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 1158 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS

#define SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS

I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 1159 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_SPI2_I2SMCLK

#define SYS_GPG_MFPL_PG1MFP_SPI2_I2SMCLK

SPI2 I2S master clock output pin.

Definition at line 1157 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_UART1_RXD

#define SYS_GPG_MFPL_PG1MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 1162 of file sys.h.

## ◆ SYS_GPG_MFPL_PG1MFP_UART2_TXD

#define SYS_GPG_MFPL_PG1MFP_UART2_TXD

Data transmitter output pin for UART2.

Definition at line 1160 of file sys.h.

## ◆ SYS_GPG_MFPL_PG2MFP_CCAP_DATA7

#define SYS_GPG_MFPL_PG2MFP_CCAP_DATA7

Sensor pixel data7 input pin.

Definition at line 1168 of file sys.h.

## ◆ SYS_GPG_MFPL_PG2MFP_EBI_ADR11

#define SYS_GPG_MFPL_PG2MFP_EBI_ADR11

EBI address/data bus bit*.

Definition at line 1164 of file sys.h.

## ◆ SYS_GPG_MFPL_PG2MFP_GPIO

#define SYS_GPG_MFPL_PG2MFP_GPIO

General purpose digital I/O pin.

Definition at line 1163 of file sys.h.

## ◆ SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL

#define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL

I2C0 SMBus SMBALTER# pin

Definition at line 1166 of file sys.h.

## ◆ SYS_GPG_MFPL_PG2MFP_I2C1_SCL

#define SYS_GPG_MFPL_PG2MFP_I2C1_SCL

I2C1 clock pin.

Definition at line 1167 of file sys.h.

## ◆ SYS_GPG_MFPL_PG2MFP_SPI2_SS

#define SYS_GPG_MFPL_PG2MFP_SPI2_SS

1st SPI2 slave select pin.

Definition at line 1165 of file sys.h.

## ◆ SYS_GPG_MFPL_PG2MFP_TM0

#define SYS_GPG_MFPL_PG2MFP_TM0

Timer0 event counter input / toggle output

Definition at line 1169 of file sys.h.

## ◆ SYS_GPG_MFPL_PG3MFP_CCAP_DATA6

#define SYS_GPG_MFPL_PG3MFP_CCAP_DATA6

Sensor pixel data6 input pin.

Definition at line 1175 of file sys.h.

## ◆ SYS_GPG_MFPL_PG3MFP_EBI_ADR12

#define SYS_GPG_MFPL_PG3MFP_EBI_ADR12

EBI address/data bus bit*.

Definition at line 1171 of file sys.h.

## ◆ SYS_GPG_MFPL_PG3MFP_GPIO

#define SYS_GPG_MFPL_PG3MFP_GPIO

General purpose digital I/O pin.

Definition at line 1170 of file sys.h.

## ◆ SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS

#define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS

I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 1173 of file sys.h.

## ◆ SYS_GPG_MFPL_PG3MFP_I2C1_SDA

#define SYS_GPG_MFPL_PG3MFP_I2C1_SDA

I2C1 data input/output pin.

Definition at line 1174 of file sys.h.

## ◆ SYS_GPG_MFPL_PG3MFP_SPI2_CLK

#define SYS_GPG_MFPL_PG3MFP_SPI2_CLK

SPI2 serial clock pin.

Definition at line 1172 of file sys.h.

## ◆ SYS_GPG_MFPL_PG3MFP_TM1

#define SYS_GPG_MFPL_PG3MFP_TM1

Timer1 event counter input / toggle output

Definition at line 1176 of file sys.h.

## ◆ SYS_GPG_MFPL_PG4MFP_CCAP_DATA5

#define SYS_GPG_MFPL_PG4MFP_CCAP_DATA5

Sensor pixel data5 input pin.

Definition at line 1180 of file sys.h.

## ◆ SYS_GPG_MFPL_PG4MFP_EBI_ADR13

#define SYS_GPG_MFPL_PG4MFP_EBI_ADR13

EBI address/data bus bit*.

Definition at line 1178 of file sys.h.

## ◆ SYS_GPG_MFPL_PG4MFP_GPIO

#define SYS_GPG_MFPL_PG4MFP_GPIO

General purpose digital I/O pin.

Definition at line 1177 of file sys.h.

## ◆ SYS_GPG_MFPL_PG4MFP_SPI2_MISO

#define SYS_GPG_MFPL_PG4MFP_SPI2_MISO

1st SPI2 MISO (Master In, Slave Out) pin.

Definition at line 1179 of file sys.h.

## ◆ SYS_GPG_MFPL_PG4MFP_TM2

#define SYS_GPG_MFPL_PG4MFP_TM2

Timer2 event counter input / toggle output

Definition at line 1181 of file sys.h.

## ◆ SYS_GPG_MFPL_PG5MFP_EBI_nCS1

#define SYS_GPG_MFPL_PG5MFP_EBI_nCS1

EBI chip select enable output pin.

Definition at line 1183 of file sys.h.

## ◆ SYS_GPG_MFPL_PG5MFP_EPWM0_CH3

#define SYS_GPG_MFPL_PG5MFP_EPWM0_CH3

EPWM0 channel3 output/capture input.

Definition at line 1186 of file sys.h.

## ◆ SYS_GPG_MFPL_PG5MFP_GPIO

#define SYS_GPG_MFPL_PG5MFP_GPIO

General purpose digital I/O pin.

Definition at line 1182 of file sys.h.

## ◆ SYS_GPG_MFPL_PG5MFP_SC1_PWR

#define SYS_GPG_MFPL_PG5MFP_SC1_PWR

SmartCard1 power pin.

Definition at line 1185 of file sys.h.

## ◆ SYS_GPG_MFPL_PG5MFP_SPI3_SS

#define SYS_GPG_MFPL_PG5MFP_SPI3_SS

1st SPI3 slave select pin.

Definition at line 1184 of file sys.h.

## ◆ SYS_GPG_MFPL_PG6MFP_EBI_nCS2

#define SYS_GPG_MFPL_PG6MFP_EBI_nCS2

EBI chip select enable output pin.

Definition at line 1188 of file sys.h.

## ◆ SYS_GPG_MFPL_PG6MFP_EPWM0_CH2

#define SYS_GPG_MFPL_PG6MFP_EPWM0_CH2

EPWM0 channel2 output/capture input.

Definition at line 1191 of file sys.h.

## ◆ SYS_GPG_MFPL_PG6MFP_GPIO

#define SYS_GPG_MFPL_PG6MFP_GPIO

General purpose digital I/O pin.

Definition at line 1187 of file sys.h.

## ◆ SYS_GPG_MFPL_PG6MFP_SC1_RST

#define SYS_GPG_MFPL_PG6MFP_SC1_RST

SmartCard1 reset pin.

Definition at line 1190 of file sys.h.

## ◆ SYS_GPG_MFPL_PG6MFP_SPI3_CLK

#define SYS_GPG_MFPL_PG6MFP_SPI3_CLK

SPI3 serial clock pin.

Definition at line 1189 of file sys.h.

## ◆ SYS_GPG_MFPL_PG7MFP_EBI_nWRL

#define SYS_GPG_MFPL_PG7MFP_EBI_nWRL

EBI write enable output pin.

Definition at line 1193 of file sys.h.

## ◆ SYS_GPG_MFPL_PG7MFP_EPWM0_CH1

#define SYS_GPG_MFPL_PG7MFP_EPWM0_CH1

EPWM0 channel1 output/capture input.

Definition at line 1196 of file sys.h.

## ◆ SYS_GPG_MFPL_PG7MFP_GPIO

#define SYS_GPG_MFPL_PG7MFP_GPIO

General purpose digital I/O pin.

Definition at line 1192 of file sys.h.

## ◆ SYS_GPG_MFPL_PG7MFP_SC1_DAT

#define SYS_GPG_MFPL_PG7MFP_SC1_DAT

SmartCard1 data pin.

Definition at line 1195 of file sys.h.

## ◆ SYS_GPG_MFPL_PG7MFP_SPI3_MISO

#define SYS_GPG_MFPL_PG7MFP_SPI3_MISO

1st SPI3 MISO (Master In, Slave Out) pin.

Definition at line 1194 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_EBI_AD14

#define SYS_GPH_MFPH_PH10MFP_EBI_AD14

EBI address/data bus bit1.

Definition at line 1314 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_GPIO

#define SYS_GPH_MFPH_PH10MFP_GPIO

General purpose digital I/O pin.

Definition at line 1313 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_I2S0_LRCK

#define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK

I2S0 left right channel clock.

Definition at line 1317 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1

#define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1

2nd QSPI0 MISO (Master In, Slave Out) pin.

Definition at line 1315 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_SC2_nCD

#define SYS_GPH_MFPH_PH10MFP_SC2_nCD

SmartCard2 card detect pin.

Definition at line 1316 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK

#define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK

SPI1 I2S master clock output pin.

Definition at line 1318 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_UART0_TXD

#define SYS_GPH_MFPH_PH10MFP_UART0_TXD

Data transmitter output pin for UART0.

Definition at line 1320 of file sys.h.

## ◆ SYS_GPH_MFPH_PH10MFP_UART4_TXD

#define SYS_GPH_MFPH_PH10MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 1319 of file sys.h.

## ◆ SYS_GPH_MFPH_PH11MFP_EBI_AD15

#define SYS_GPH_MFPH_PH11MFP_EBI_AD15

EBI address/data bus bit1.

Definition at line 1322 of file sys.h.

## ◆ SYS_GPH_MFPH_PH11MFP_EPWM0_CH5

#define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5

EPWM0 channel5 output/capture input.

Definition at line 1326 of file sys.h.

## ◆ SYS_GPH_MFPH_PH11MFP_GPIO

#define SYS_GPH_MFPH_PH11MFP_GPIO

General purpose digital I/O pin.

Definition at line 1321 of file sys.h.

## ◆ SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1

#define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1

2nd QSPI0 MOSI (Master Out, Slave In) pin.

Definition at line 1323 of file sys.h.

## ◆ SYS_GPH_MFPH_PH11MFP_UART0_RXD

#define SYS_GPH_MFPH_PH11MFP_UART0_RXD

Data receiver input pin for UART0.

Definition at line 1325 of file sys.h.

## ◆ SYS_GPH_MFPH_PH11MFP_UART4_RXD

#define SYS_GPH_MFPH_PH11MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 1324 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_EBI_AD12

#define SYS_GPH_MFPH_PH8MFP_EBI_AD12

EBI address/data bus bit1.

Definition at line 1294 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_GPIO

#define SYS_GPH_MFPH_PH8MFP_GPIO

General purpose digital I/O pin.

Definition at line 1293 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL

#define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL

I2C1 SMBus SMBALTER# pin

Definition at line 1300 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_I2C2_SCL

#define SYS_GPH_MFPH_PH8MFP_I2C2_SCL

I2C2 clock pin.

Definition at line 1301 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_I2S0_DI

#define SYS_GPH_MFPH_PH8MFP_I2S0_DI

I2S0 data input.

Definition at line 1297 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_QSPI0_CLK

#define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK

QSPI0 serial clock pin.

Definition at line 1295 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_SC2_PWR

#define SYS_GPH_MFPH_PH8MFP_SC2_PWR

SmartCard2 power pin.

Definition at line 1296 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_SPI1_CLK

#define SYS_GPH_MFPH_PH8MFP_SPI1_CLK

SPI1 serial clock pin.

Definition at line 1298 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_UART1_TXD

#define SYS_GPH_MFPH_PH8MFP_UART1_TXD

Data transmitter output pin for UART1.

Definition at line 1302 of file sys.h.

## ◆ SYS_GPH_MFPH_PH8MFP_UART3_nRTS

#define SYS_GPH_MFPH_PH8MFP_UART3_nRTS

Request to Send output pin for UART3.

Definition at line 1299 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_EBI_AD13

#define SYS_GPH_MFPH_PH9MFP_EBI_AD13

EBI address/data bus bit1.

Definition at line 1304 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_GPIO

#define SYS_GPH_MFPH_PH9MFP_GPIO

General purpose digital I/O pin.

Definition at line 1303 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS

#define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS

I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)

Definition at line 1310 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_I2C2_SDA

#define SYS_GPH_MFPH_PH9MFP_I2C2_SDA

I2C2 data input/output pin.

Definition at line 1311 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_I2S0_DO

#define SYS_GPH_MFPH_PH9MFP_I2S0_DO

I2S0 data output.

Definition at line 1307 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_QSPI0_SS

#define SYS_GPH_MFPH_PH9MFP_QSPI0_SS

1st QSPI0 slave select pin.

Definition at line 1305 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_SC2_RST

#define SYS_GPH_MFPH_PH9MFP_SC2_RST

SmartCard2 reset pin.

Definition at line 1306 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_SPI1_SS

#define SYS_GPH_MFPH_PH9MFP_SPI1_SS

1st SPI1 slave select pin.

Definition at line 1308 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_UART1_RXD

#define SYS_GPH_MFPH_PH9MFP_UART1_RXD

Data receiver input pin for UART1.

Definition at line 1312 of file sys.h.

## ◆ SYS_GPH_MFPH_PH9MFP_UART3_nCTS

#define SYS_GPH_MFPH_PH9MFP_UART3_nCTS

Clear to Send input pin for UART3.

Definition at line 1309 of file sys.h.

## ◆ SYS_GPH_MFPL_PH0MFP_EBI_ADR7

#define SYS_GPH_MFPL_PH0MFP_EBI_ADR7

EBI address/data bus bit*.

Definition at line 1254 of file sys.h.

## ◆ SYS_GPH_MFPL_PH0MFP_GPIO

#define SYS_GPH_MFPL_PH0MFP_GPIO

General purpose digital I/O pin.

Definition at line 1253 of file sys.h.

## ◆ SYS_GPH_MFPL_PH0MFP_TM0_EXT

#define SYS_GPH_MFPL_PH0MFP_TM0_EXT

Timer0 event counter input / toggle output

Definition at line 1256 of file sys.h.

## ◆ SYS_GPH_MFPL_PH0MFP_UART5_TXD

#define SYS_GPH_MFPL_PH0MFP_UART5_TXD

Data transmitter output pin for UART5.

Definition at line 1255 of file sys.h.

## ◆ SYS_GPH_MFPL_PH1MFP_EBI_ADR6

#define SYS_GPH_MFPL_PH1MFP_EBI_ADR6

EBI address/data bus bit*.

Definition at line 1258 of file sys.h.

## ◆ SYS_GPH_MFPL_PH1MFP_GPIO

#define SYS_GPH_MFPL_PH1MFP_GPIO

General purpose digital I/O pin.

Definition at line 1257 of file sys.h.

## ◆ SYS_GPH_MFPL_PH1MFP_TM1_EXT

#define SYS_GPH_MFPL_PH1MFP_TM1_EXT

Timer1 event counter input / toggle output

Definition at line 1260 of file sys.h.

## ◆ SYS_GPH_MFPL_PH1MFP_UART5_RXD

#define SYS_GPH_MFPL_PH1MFP_UART5_RXD

Data receiver input pin for UART5.

Definition at line 1259 of file sys.h.

## ◆ SYS_GPH_MFPL_PH2MFP_EBI_ADR5

#define SYS_GPH_MFPL_PH2MFP_EBI_ADR5

EBI address/data bus bit*.

Definition at line 1262 of file sys.h.

## ◆ SYS_GPH_MFPL_PH2MFP_GPIO

#define SYS_GPH_MFPL_PH2MFP_GPIO

General purpose digital I/O pin.

Definition at line 1261 of file sys.h.

## ◆ SYS_GPH_MFPL_PH2MFP_I2C0_SCL

#define SYS_GPH_MFPL_PH2MFP_I2C0_SCL

I2C0 clock pin.

Definition at line 1265 of file sys.h.

## ◆ SYS_GPH_MFPL_PH2MFP_TM2_EXT

#define SYS_GPH_MFPL_PH2MFP_TM2_EXT

Timer2 event counter input / toggle output

Definition at line 1266 of file sys.h.

## ◆ SYS_GPH_MFPL_PH2MFP_UART4_TXD

#define SYS_GPH_MFPL_PH2MFP_UART4_TXD

Data transmitter output pin for UART4.

Definition at line 1264 of file sys.h.

## ◆ SYS_GPH_MFPL_PH2MFP_UART5_nRTS

#define SYS_GPH_MFPL_PH2MFP_UART5_nRTS

Request to Send output pin for UART5.

Definition at line 1263 of file sys.h.

## ◆ SYS_GPH_MFPL_PH3MFP_EBI_ADR4

#define SYS_GPH_MFPL_PH3MFP_EBI_ADR4

EBI address/data bus bit*.

Definition at line 1268 of file sys.h.

## ◆ SYS_GPH_MFPL_PH3MFP_GPIO

#define SYS_GPH_MFPL_PH3MFP_GPIO

General purpose digital I/O pin.

Definition at line 1267 of file sys.h.

## ◆ SYS_GPH_MFPL_PH3MFP_I2C0_SDA

#define SYS_GPH_MFPL_PH3MFP_I2C0_SDA

I2C0 data input/output pin.

Definition at line 1272 of file sys.h.

## ◆ SYS_GPH_MFPL_PH3MFP_SPI1_I2SMCLK

#define SYS_GPH_MFPL_PH3MFP_SPI1_I2SMCLK

SPI1 I2S master clock output pin.

Definition at line 1269 of file sys.h.

## ◆ SYS_GPH_MFPL_PH3MFP_TM3_EXT

#define SYS_GPH_MFPL_PH3MFP_TM3_EXT

Timer3 event counter input / toggle output

Definition at line 1273 of file sys.h.

## ◆ SYS_GPH_MFPL_PH3MFP_UART4_RXD

#define SYS_GPH_MFPL_PH3MFP_UART4_RXD

Data receiver input pin for UART4.

Definition at line 1271 of file sys.h.

## ◆ SYS_GPH_MFPL_PH3MFP_UART5_nCTS

#define SYS_GPH_MFPL_PH3MFP_UART5_nCTS

Clear to Send input pin for UART5.

Definition at line 1270 of file sys.h.

## ◆ SYS_GPH_MFPL_PH4MFP_EBI_ADR3

#define SYS_GPH_MFPL_PH4MFP_EBI_ADR3

EBI address/data bus bit*.

Definition at line 1275 of file sys.h.

## ◆ SYS_GPH_MFPL_PH4MFP_GPIO

#define SYS_GPH_MFPL_PH4MFP_GPIO

General purpose digital I/O pin.

Definition at line 1274 of file sys.h.

## ◆ SYS_GPH_MFPL_PH4MFP_SPI1_MISO

#define SYS_GPH_MFPL_PH4MFP_SPI1_MISO

1st SPI1 MISO (Master In, Slave Out) pin.

Definition at line 1276 of file sys.h.

## ◆ SYS_GPH_MFPL_PH4MFP_UART6_TXD

#define SYS_GPH_MFPL_PH4MFP_UART6_TXD

Data transmitter output pin for UART6.

Definition at line 1278 of file sys.h.

## ◆ SYS_GPH_MFPL_PH4MFP_UART7_nRTS

#define SYS_GPH_MFPL_PH4MFP_UART7_nRTS

Request to Send output pin for UART7.

Definition at line 1277 of file sys.h.

## ◆ SYS_GPH_MFPL_PH5MFP_EBI_ADR2

#define SYS_GPH_MFPL_PH5MFP_EBI_ADR2

EBI address/data bus bit*.

Definition at line 1280 of file sys.h.

## ◆ SYS_GPH_MFPL_PH5MFP_GPIO

#define SYS_GPH_MFPL_PH5MFP_GPIO

General purpose digital I/O pin.

Definition at line 1279 of file sys.h.

## ◆ SYS_GPH_MFPL_PH5MFP_SPI1_MOSI

#define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI

1st SPI1 MOSI (Master Out, Slave In) pin.

Definition at line 1281 of file sys.h.

## ◆ SYS_GPH_MFPL_PH5MFP_UART6_RXD

#define SYS_GPH_MFPL_PH5MFP_UART6_RXD

Data receiver input pin for UART6.

Definition at line 1283 of file sys.h.

## ◆ SYS_GPH_MFPL_PH5MFP_UART7_nCTS

#define SYS_GPH_MFPL_PH5MFP_UART7_nCTS

Clear to Send input pin for UART7.

Definition at line 1282 of file sys.h.

## ◆ SYS_GPH_MFPL_PH6MFP_EBI_ADR1

#define SYS_GPH_MFPL_PH6MFP_EBI_ADR1

EBI address/data bus bit*.

Definition at line 1285 of file sys.h.

## ◆ SYS_GPH_MFPL_PH6MFP_GPIO

#define SYS_GPH_MFPL_PH6MFP_GPIO

General purpose digital I/O pin.

Definition at line 1284 of file sys.h.

## ◆ SYS_GPH_MFPL_PH6MFP_SPI1_CLK

#define SYS_GPH_MFPL_PH6MFP_SPI1_CLK

SPI1 serial clock pin.

Definition at line 1286 of file sys.h.

## ◆ SYS_GPH_MFPL_PH6MFP_UART7_TXD

#define SYS_GPH_MFPL_PH6MFP_UART7_TXD

Data transmitter output pin for UART7.

Definition at line 1287 of file sys.h.

## ◆ SYS_GPH_MFPL_PH7MFP_EBI_ADR0

#define SYS_GPH_MFPL_PH7MFP_EBI_ADR0

EBI address/data bus bit*.

Definition at line 1289 of file sys.h.

## ◆ SYS_GPH_MFPL_PH7MFP_GPIO

#define SYS_GPH_MFPL_PH7MFP_GPIO

General purpose digital I/O pin.

Definition at line 1288 of file sys.h.

## ◆ SYS_GPH_MFPL_PH7MFP_SPI1_SS

#define SYS_GPH_MFPL_PH7MFP_SPI1_SS

1st SPI1 slave select pin.

Definition at line 1290 of file sys.h.

## ◆ SYS_GPH_MFPL_PH7MFP_UART7_RXD

#define SYS_GPH_MFPL_PH7MFP_UART7_RXD

Data receiver input pin for UART7.

Definition at line 1291 of file sys.h.

## ◆ SYS_PLCTL_PLSEL_PL0

#define SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos)

Set power level to power level 0

Definition at line 137 of file sys.h.

## ◆ SYS_PLCTL_PLSEL_PL1

#define SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos)

Set power level to power level 1

Definition at line 138 of file sys.h.

## ◆ SYS_USBPHY_HSUSBROLE_ID_DEPH

#define SYS_USBPHY_HSUSBROLE_ID_DEPH

ID dependent device

Definition at line 132 of file sys.h.

## ◆ SYS_USBPHY_HSUSBROLE_STD_USBD

#define SYS_USBPHY_HSUSBROLE_STD_USBD

Standard HSUSB device

Definition at line 130 of file sys.h.

## ◆ SYS_USBPHY_HSUSBROLE_STD_USBH

#define SYS_USBPHY_HSUSBROLE_STD_USBH

Standard HSUSB host

Definition at line 131 of file sys.h.

## ◆ SYS_USBPHY_USBROLE_ID_DEPH

#define SYS_USBPHY_USBROLE_ID_DEPH

ID dependent device

Definition at line 128 of file sys.h.

## ◆ SYS_USBPHY_USBROLE_ON_THE_GO

#define SYS_USBPHY_USBROLE_ON_THE_GO

On-The-Go device

Definition at line 129 of file sys.h.

## ◆ SYS_USBPHY_USBROLE_STD_USBD

#define SYS_USBPHY_USBROLE_STD_USBD

Standard USB device

Definition at line 126 of file sys.h.

## ◆ SYS_USBPHY_USBROLE_STD_USBH

#define SYS_USBPHY_USBROLE_STD_USBH

Standard USB host

Definition at line 127 of file sys.h.

## ◆ SYS_VREFCTL_VREF_1_6V

#define SYS_VREFCTL_VREF_1_6V

Vref = 1.6V

Definition at line 116 of file sys.h.

## ◆ SYS_VREFCTL_VREF_2_0V

#define SYS_VREFCTL_VREF_2_0V

Vref = 2.0V

Definition at line 117 of file sys.h.

## ◆ SYS_VREFCTL_VREF_2_5V

#define SYS_VREFCTL_VREF_2_5V

Vref = 2.5V

Definition at line 118 of file sys.h.

## ◆ SYS_VREFCTL_VREF_3_0V

#define SYS_VREFCTL_VREF_3_0V

Vref = 3.0V

Definition at line 119 of file sys.h.

## ◆ SYS_VREFCTL_VREF_AVDD

#define SYS_VREFCTL_VREF_AVDD

Vref = AVDD

Definition at line 120 of file sys.h.

## ◆ SYS_VREFCTL_VREF_PIN

#define SYS_VREFCTL_VREF_PIN

Vref = Vref pin

Definition at line 115 of file sys.h.

## ◆ TMR0_RST

#define TMR0_RST

Reset TMR0

Definition at line 48 of file sys.h.

## ◆ TMR1_RST

#define TMR1_RST

Reset TMR1

Definition at line 49 of file sys.h.

## ◆ TMR2_RST

#define TMR2_RST

Reset TMR2

Definition at line 50 of file sys.h.

## ◆ TMR3_RST

#define TMR3_RST

Reset TMR3

Definition at line 51 of file sys.h.

## ◆ TRNG_RST

#define TRNG_RST

Reset TRNG

Definition at line 75 of file sys.h.

## ◆ UART0_RST

#define UART0_RST

Reset UART0

Definition at line 60 of file sys.h.

## ◆ UART1_RST

#define UART1_RST

Reset UART1

Definition at line 61 of file sys.h.

## ◆ UART2_RST

#define UART2_RST

Reset UART2

Definition at line 62 of file sys.h.

## ◆ UART3_RST

#define UART3_RST

Reset UART3

Definition at line 63 of file sys.h.

## ◆ UART4_RST

#define UART4_RST

Reset UART4

Definition at line 64 of file sys.h.

## ◆ UART5_RST

#define UART5_RST

Reset UART5

Definition at line 65 of file sys.h.

## ◆ UART6_RST

#define UART6_RST

Reset UART6

Definition at line 66 of file sys.h.

## ◆ UART7_RST

#define UART7_RST

Reset UART7

Definition at line 67 of file sys.h.

## ◆ USBD_RST

#define USBD_RST

Reset USBD

Definition at line 71 of file sys.h.

## ◆ USBH_RST

#define USBH_RST

Reset USBH

Definition at line 44 of file sys.h.

## ◆ USCI0_RST

#define USCI0_RST

Reset USCI0

Definition at line 82 of file sys.h.

## ◆ USCI1_RST

#define USCI1_RST

Reset USCI1

Definition at line 83 of file sys.h.