| M480 BSP V3.05.001 The Board Support Package for M480 Series

spi_reg.h
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1 /**************************************************************************/
9 #ifndef __SPI_REG_H__
10 #define __SPI_REG_H__
11
12 #if defined ( __CC_ARM )
13 #pragma anon_unions
14 #endif
15
26 typedef struct
27 {
28
29
1069 __IO uint32_t CTL;
1070 __IO uint32_t CLKDIV;
1071 __IO uint32_t SSCTL;
1072 __IO uint32_t PDMACTL;
1073 __IO uint32_t FIFOCTL;
1074 __IO uint32_t STATUS;
1075 __I uint32_t RESERVE0[2];
1078 __O uint32_t TX;
1079 __I uint32_t RESERVE1[3];
1082 __I uint32_t RX;
1083 __I uint32_t RESERVE2[11];
1086 __IO uint32_t I2SCTL;
1087 __IO uint32_t I2SCLK;
1088 __IO uint32_t I2SSTS;
1090 } SPI_T;
1091
1097 #define SPI_CTL_SPIEN_Pos (0)
1098 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos)
1100 #define SPI_CTL_RXNEG_Pos (1)
1101 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos)
1103 #define SPI_CTL_TXNEG_Pos (2)
1104 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos)
1106 #define SPI_CTL_CLKPOL_Pos (3)
1107 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos)
1109 #define SPI_CTL_SUSPITV_Pos (4)
1110 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos)
1112 #define SPI_CTL_DWIDTH_Pos (8)
1113 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos)
1115 #define SPI_CTL_LSB_Pos (13)
1116 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
1118 #define SPI_CTL_HALFDPX_Pos (14)
1119 #define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos)
1121 #define SPI_CTL_RXONLY_Pos (15)
1122 #define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos)
1124 #define SPI_CTL_UNITIEN_Pos (17)
1125 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos)
1127 #define SPI_CTL_SLAVE_Pos (18)
1128 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
1130 #define SPI_CTL_REORDER_Pos (19)
1131 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
1133 #define SPI_CTL_DATDIR_Pos (20)
1134 #define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos)
1136 #define SPI_CLKDIV_DIVIDER_Pos (0)
1137 #define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos)
1139 #define SPI_SSCTL_SS_Pos (0)
1140 #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos)
1142 #define SPI_SSCTL_SSACTPOL_Pos (2)
1143 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos)
1145 #define SPI_SSCTL_AUTOSS_Pos (3)
1146 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos)
1148 #define SPI_SSCTL_SLVBEIEN_Pos (8)
1149 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos)
1151 #define SPI_SSCTL_SLVURIEN_Pos (9)
1152 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos)
1154 #define SPI_SSCTL_SSACTIEN_Pos (12)
1155 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos)
1157 #define SPI_SSCTL_SSINAIEN_Pos (13)
1158 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos)
1160 #define SPI_SSCTL_SLVTOCNT_Pos (16)
1161 #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos)
1163 #define SPI_PDMACTL_TXPDMAEN_Pos (0)
1164 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)
1166 #define SPI_PDMACTL_RXPDMAEN_Pos (1)
1167 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)
1169 #define SPI_PDMACTL_PDMARST_Pos (2)
1170 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos)
1172 #define SPI_FIFOCTL_RXRST_Pos (0)
1173 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos)
1175 #define SPI_FIFOCTL_TXRST_Pos (1)
1176 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos)
1178 #define SPI_FIFOCTL_RXTHIEN_Pos (2)
1179 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)
1181 #define SPI_FIFOCTL_TXTHIEN_Pos (3)
1182 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)
1184 #define SPI_FIFOCTL_RXTOIEN_Pos (4)
1185 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)
1187 #define SPI_FIFOCTL_RXOVIEN_Pos (5)
1188 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)
1190 #define SPI_FIFOCTL_TXUFPOL_Pos (6)
1191 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos)
1193 #define SPI_FIFOCTL_TXUFIEN_Pos (7)
1194 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos)
1196 #define SPI_FIFOCTL_RXFBCLR_Pos (8)
1197 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)
1199 #define SPI_FIFOCTL_TXFBCLR_Pos (9)
1200 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)
1202 #define SPI_FIFOCTL_RXTH_Pos (24)
1203 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos)
1205 #define SPI_FIFOCTL_TXTH_Pos (28)
1206 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos)
1208 #define SPI_STATUS_BUSY_Pos (0)
1209 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos)
1211 #define SPI_STATUS_UNITIF_Pos (1)
1212 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos)
1214 #define SPI_STATUS_SSACTIF_Pos (2)
1215 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos)
1217 #define SPI_STATUS_SSINAIF_Pos (3)
1218 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos)
1220 #define SPI_STATUS_SSLINE_Pos (4)
1221 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos)
1223 #define SPI_STATUS_SLVBEIF_Pos (6)
1224 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos)
1226 #define SPI_STATUS_SLVURIF_Pos (7)
1227 #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos)
1229 #define SPI_STATUS_RXEMPTY_Pos (8)
1230 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos)
1232 #define SPI_STATUS_RXFULL_Pos (9)
1233 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos)
1235 #define SPI_STATUS_RXTHIF_Pos (10)
1236 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos)
1238 #define SPI_STATUS_RXOVIF_Pos (11)
1239 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos)
1241 #define SPI_STATUS_RXTOIF_Pos (12)
1242 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos)
1244 #define SPI_STATUS_SPIENSTS_Pos (15)
1245 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos)
1247 #define SPI_STATUS_TXEMPTY_Pos (16)
1248 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos)
1250 #define SPI_STATUS_TXFULL_Pos (17)
1251 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos)
1253 #define SPI_STATUS_TXTHIF_Pos (18)
1254 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos)
1256 #define SPI_STATUS_TXUFIF_Pos (19)
1257 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos)
1259 #define SPI_STATUS_TXRXRST_Pos (23)
1260 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos)
1262 #define SPI_STATUS_RXCNT_Pos (24)
1263 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos)
1265 #define SPI_STATUS_TXCNT_Pos (28)
1266 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos)
1268 #define SPI_TX_TX_Pos (0)
1269 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos)
1271 #define SPI_RX_RX_Pos (0)
1272 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos)
1274 #define SPI_I2SCTL_I2SEN_Pos (0)
1275 #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos)
1277 #define SPI_I2SCTL_TXEN_Pos (1)
1278 #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos)
1280 #define SPI_I2SCTL_RXEN_Pos (2)
1281 #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos)
1283 #define SPI_I2SCTL_MUTE_Pos (3)
1284 #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos)
1286 #define SPI_I2SCTL_WDWIDTH_Pos (4)
1287 #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos)
1289 #define SPI_I2SCTL_MONO_Pos (6)
1290 #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos)
1292 #define SPI_I2SCTL_ORDER_Pos (7)
1293 #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos)
1295 #define SPI_I2SCTL_SLAVE_Pos (8)
1296 #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos)
1298 #define SPI_I2SCTL_MCLKEN_Pos (15)
1299 #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos)
1301 #define SPI_I2SCTL_RZCEN_Pos (16)
1302 #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos)
1304 #define SPI_I2SCTL_LZCEN_Pos (17)
1305 #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos)
1307 #define SPI_I2SCTL_RXLCH_Pos (23)
1308 #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos)
1310 #define SPI_I2SCTL_RZCIEN_Pos (24)
1311 #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos)
1313 #define SPI_I2SCTL_LZCIEN_Pos (25)
1314 #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos)
1316 #define SPI_I2SCTL_FORMAT_Pos (28)
1317 #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos)
1319 #define SPI_I2SCLK_MCLKDIV_Pos (0)
1320 #define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos)
1322 #define SPI_I2SCLK_BCLKDIV_Pos (8)
1323 #define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos)
1325 #define SPI_I2SSTS_RIGHT_Pos (4)
1326 #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos)
1328 #define SPI_I2SSTS_RXEMPTY_Pos (8)
1329 #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos)
1331 #define SPI_I2SSTS_RXFULL_Pos (9)
1332 #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos)
1334 #define SPI_I2SSTS_RXTHIF_Pos (10)
1335 #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos)
1337 #define SPI_I2SSTS_RXOVIF_Pos (11)
1338 #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos)
1340 #define SPI_I2SSTS_RXTOIF_Pos (12)
1341 #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos)
1343 #define SPI_I2SSTS_I2SENSTS_Pos (15)
1344 #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos)
1346 #define SPI_I2SSTS_TXEMPTY_Pos (16)
1347 #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos)
1349 #define SPI_I2SSTS_TXFULL_Pos (17)
1350 #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos)
1352 #define SPI_I2SSTS_TXTHIF_Pos (18)
1353 #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos)
1355 #define SPI_I2SSTS_TXUFIF_Pos (19)
1356 #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos)
1358 #define SPI_I2SSTS_RZCIF_Pos (20)
1359 #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos)
1361 #define SPI_I2SSTS_LZCIF_Pos (21)
1362 #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos)
1364 #define SPI_I2SSTS_TXRXRST_Pos (23)
1365 #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos)
1367 #define SPI_I2SSTS_RXCNT_Pos (24)
1368 #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos)
1370 #define SPI_I2SSTS_TXCNT_Pos (28)
1371 #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /* SPI_CONST */
1374 /* end of SPI register group */ /* end of REGISTER group */
1376
1377 #if defined ( __CC_ARM )
1378 #pragma no_anon_unions
1379 #endif
1380
1381 #endif /* __SPI_REG_H__ */
SPI_T::TX
__O uint32_t TX
Definition: spi_reg.h:1078
SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: spi_reg.h:1071
SPI_T::RX
__I uint32_t RX
Definition: spi_reg.h:1082
SPI_T::PDMACTL
__IO uint32_t PDMACTL
Definition: spi_reg.h:1072
SPI_T::I2SCLK
__IO uint32_t I2SCLK
Definition: spi_reg.h:1087
SPI_T
Definition: spi_reg.h:26
SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: spi_reg.h:1073
SPI_T::I2SSTS
__IO uint32_t I2SSTS
Definition: spi_reg.h:1088
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: spi_reg.h:1070
SPI_T::I2SCTL
__IO uint32_t I2SCTL
Definition: spi_reg.h:1086
SPI_T::STATUS
__IO uint32_t STATUS
Definition: spi_reg.h:1074
SPI_T::CTL
__IO uint32_t CTL
Definition: spi_reg.h:1069