| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
FMC_T Struct Reference
Control Register

`#include <fmc_reg.h>`

## Data Fields
__IO uint32_t | ISPCTL
__IO uint32_t | ISPADDR
__IO uint32_t | ISPDAT
__IO uint32_t | ISPCMD
__IO uint32_t | ISPTRG
__I uint32_t | DFBA
__IO uint32_t | ISPSTS
__IO uint32_t | CYCCTL
__O uint32_t | KPKEY0
__O uint32_t | KPKEY1
__O uint32_t | KPKEY2
__IO uint32_t | KPKEYTRG
__IO uint32_t | KPKEYSTS
__I uint32_t | KPKEYCNT
__I uint32_t | KPCNT
__IO uint32_t | MPDAT0
__IO uint32_t | MPDAT1
__IO uint32_t | MPDAT2
__IO uint32_t | MPDAT3
__I uint32_t | MPSTS
__I uint32_t | MPADDR
__I uint32_t | XOMR0STS
__I uint32_t | XOMR1STS
__I uint32_t | XOMR2STS
__I uint32_t | XOMR3STS
__I uint32_t | XOMSTS

## Detailed Description

    @addtogroup FMC Flash Memory Controller(FMC)
    Memory Mapped Structure for FMC Controller

Definition at line 26 of file fmc_reg.h.

## Field Documentation

## ◆ CYCCTL

FMC_T::CYCCTL

[0x004c] Flash Access Cycle Control Register

CYCCTL

Offset: 0x4C Flash Access Cycle Control Register

Bits | Field | Descriptions
[3:0] | CYCLE | Flash Access Cycle Control (Write Protect) 0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. The HCLK working frequency range range is<27MHz 0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. The optimized HCLK working frequency range is 27~54 MHz 0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. The optimized HCLK working frequency range is 54~81MHz 0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. The optimized HCLK working frequency range is81~108MHz 0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. The optimized HCLK working frequency range is 108~135MHz 0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. The optimized HCLK working frequency range is 135~162MHz 0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. The optimized HCLK working frequency range is 162~192MHz 1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. The optimized HCLK working frequency range is >192MHz Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 976 of file fmc_reg.h.

## ◆ DFBA

FMC_T::DFBA

[0x0014] Data Flash Base Address

DFBA

Offset: 0x14 Data Flash Base Address

Bits | Field | Descriptions
[31:0] | DFBA | Data Flash Base Address This register indicates Data Flash start address. It is a read only register. The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 This register is valid when DFEN (CONFIG0[0]) =0 .

Definition at line 968 of file fmc_reg.h.

## ◆ ISPADDR

FMC_T::ISPADDR

[0x0004] ISP Address Register

ISPADDR

Offset: 0x04 ISP Address Register

Bits | Field | Descriptions
[31:0] | ISPADDR | ISP Address The NuMicro M480 series is equipped with embedded flash ISPADDR[1:0] must be kept 00 for ISP 32-bit operation ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. For FLASH 32-bit Program, ISP address needs word alignment (4-byte) For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).

Definition at line 964 of file fmc_reg.h.

## ◆ ISPCMD

FMC_T::ISPCMD

[0x000c] ISP Command Register

ISPCMD

Offset: 0x0C ISP Command Register

Bits | Field | Descriptions
[6:0] | CMD | ISP Command ISP command table is shown below: 0x00= FLASH Read. 0x04= Read Unique ID. 0x08= Read Flash All-One Result. 0x0B= Read Company ID. 0x0C= Read Device ID. 0x0D= Read Checksum. 0x21= FLASH 32-bit Program. 0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. 0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. 0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1.. 0x27= FLASH Multi-Word Program. 0x28= Run Flash All-One Verification. 0x2D= Run Checksum Calculation. 0x2E= Vector Remap. 0x40= FLASH 64-bit Read. 0x61= FLASH 64-bit Program. The other commands are invalid.

Definition at line 966 of file fmc_reg.h.

## ◆ ISPCTL

FMC_T::ISPCTL

[0x0000] ISP Control Register

ISPCTL

Offset: 0x00 ISP Control Register

Bits | Field | Descriptions
[0] | ISPEN | ISP Enable Bit (Write Protect) ISP function enable bit. Set this bit to enable ISP function. 0 = ISP function Disabled. 1 = ISP function Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] | BS | Boot Select (Write Protect) When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively This bit also functions as chip booting status flag, which can be used to check where chip booted from This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 0 = Booting from APROM when MBS (CONFIG0[5]) is 1. 1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] | SPUEN | SPROM Update Enable Bit (Write Protect) 0 = SPROM cannot be updated. 1 = SPROM can be updated. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | APUEN | APROM Update Enable Bit (Write Protect) 0 = APROM cannot be updated when the chip runs in APROM. 1 = APROM can be updated when the chip runs in APROM. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | CFGUEN | CONFIG Update Enable Bit (Write Protect) 0 = CONFIG cannot be updated. 1 = CONFIG can be updated. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5] | LDUEN | LDROM Update Enable Bit (Write Protect) LDROM update enable bit. 0 = LDROM cannot be updated. 1 = LDROM can be updated. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] | ISPFF | ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) SPROM is erased/programmed if SPUEN is set to 0 (5) SPROM is programmed at SPROM secured mode. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) Vector address is mapping to SPROM region (11) KPROM is erased/programmed if KEYLOCK is set to 1 (12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 (13) LDROM is erased/programmed if KEYLOCK is set to 1 (14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. (15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 (16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A (17) Read any content of boot loader with ICE connection Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[16] | BL | Boot Loader Booting (Write Protect) This bit is initiated with the inversed value of MBS (CONFIG0[5]) Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded This bit is used to check chip boot from Boot Loader or not User should keep original value of this bit when updating FMC_ISPCTL register. 0 = Booting from APROM or LDROM. 1 = Booting from Boot Loader. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 963 of file fmc_reg.h.

## ◆ ISPDAT

FMC_T::ISPDAT

[0x0008] ISP Data Register

ISPDAT

Offset: 0x08 ISP Data Register

Bits | Field | Descriptions
[31:0] | ISPDAT | ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment For ISP Read CRC32 Checksum command, ISPDAT is the checksum result If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect

Definition at line 965 of file fmc_reg.h.

## ◆ ISPSTS

FMC_T::ISPSTS

[0x0040] ISP Status Register

ISPSTS

Offset: 0x40 ISP Status Register

Bits | Field | Descriptions
[0] | ISPBUSY | ISP Busy Flag (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 = ISP operation is finished. 1 = ISP is progressed.
[2:1] | CBS | Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. The following function is valid when MBS (FMC_ISPSTS[3])= 1. 00 = LDROM with IAP mode. 01 = LDROM without IAP mode. 10 = APROM with IAP mode. 11 = APROM without IAP mode.
[3] | MBS | Boot From Boot Loader Selection Flag (Read Only) This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 0 = Booting from Boot Loader. 1 = Booting from LDROM/APROM.(.see CBS bit setting)
[4] | FCYCDIS | Flash Access Cycle Auto-tuning Disabled Flag (Read Only) This bit is set if flash access cycle auto-tuning function is disabled The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. 0 = Flash access cycle auto-tuning is enabled. 1 = Flash access cycle auto-tuning is disabled.
[5] | PGFF | Flash Program with Fast Verification Flag (Read Only) This bit is set if data is mismatched at ISP programming verification This bit is clear by performing ISP flash erase or ISP read CID operation 0 = Flash Program is success. 1 = Flash Program is fail. Program data is different with data in the flash memory
[6] | ISPFF | ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) SPROM is erased/programmed if SPUEN is set to 0 (5) SPROM is programmed at SPROM secured mode. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) Vector address is mapping to SPROM region. (11) KPROM is erased/programmed if KEYLOCK is set to 1 (12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 (13) LDROM is erased/programmed if KEYLOCK is set to 1 (14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. (15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. (16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A (17) Read any content of boot loader with ICE connection Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] | ALLONE | Flash All-one Verification Flag This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. 1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
[23:9] | VECMAP | Vector Page Mapping Address (Read Only) All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF}
[31] | SCODE | Security Code Active Flag This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation. 0 = Secured code is inactive. 1 = Secured code is active.

Definition at line 972 of file fmc_reg.h.

## ◆ ISPTRG

FMC_T::ISPTRG

[0x0010] ISP Trigger Control Register

ISPTRG

Offset: 0x10 ISP Trigger Control Register

Bits | Field | Descriptions
[0] | ISPGO | ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 = ISP operation is finished. 1 = ISP is progressed. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 967 of file fmc_reg.h.

## ◆ KPCNT

FMC_T::KPCNT

[0x0068] KPROM KEY-Unmatched Power-On Counting Register

KPCNT

Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register

Bits | Field | Descriptions
[3:0] | KPCNT | Power-on Counter for Error Key Entry(Read Only) KPCNT is the power-on counting for error key entry in Security Key protection KPCNT is cleared to 0 if key comparison is matched.
[11:8] | KPMAX | Power-on Maximum Number for Error Key Entry (Read Only) KPMAX is the power-on maximum number for error key entry When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX

Definition at line 983 of file fmc_reg.h.

## ◆ KPKEY0

FMC_T::KPKEY0

[0x0050] KPROM KEY0 Data Register

KPKEY0

Offset: 0x50 KPROM KEY0 Data Register

Bits | Field | Descriptions
[31:0] | KPKEY0 | KPROM KEY0 Data (Write Only) Write KPKEY0 data to this register before KEY Comparison operation.

Definition at line 977 of file fmc_reg.h.

## ◆ KPKEY1

FMC_T::KPKEY1

[0x0054] KPROM KEY1 Data Register

KPKEY1

Offset: 0x54 KPROM KEY1 Data Register

Bits | Field | Descriptions
[31:0] | KPKEY1 | KPROM KEY1 Data (Write Only) Write KPKEY1 data to this register before KEY Comparison operation.

Definition at line 978 of file fmc_reg.h.

## ◆ KPKEY2

FMC_T::KPKEY2

[0x0058] KPROM KEY2 Data Register

KPKEY2

Offset: 0x58 KPROM KEY2 Data Register

Bits | Field | Descriptions
[31:0] | KPKEY2 | KPROM KEY2 Data (Write Only) Write KPKEY2 data to this register before KEY Comparison operation.

Definition at line 979 of file fmc_reg.h.

## ◆ KPKEYCNT

FMC_T::KPKEYCNT

[0x0064] KPROM KEY-Unmatched Counting Register

KPKEYCNT

Offset: 0x64 KPROM KEY-Unmatched Counting Register

Bits | Field | Descriptions
[5:0] | KPKECNT | Error Key Entry Counter at Each Power-on (Read Only) KPKECNT is increased when entry keys is wrong in Security Key protection KPKECNT is cleared to 0 if key comparison is matched or system power-on.
[13:8] | KPKEMAX | Maximum Number for Error Key Entry at Each Power-on (Read Only) KPKEMAX is the maximum error key entry number at each power-on When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.

Definition at line 982 of file fmc_reg.h.

## ◆ KPKEYSTS

FMC_T::KPKEYSTS

[0x0060] KPROM KEY Comparison Status Register

KPKEYSTS

Offset: 0x60 KPROM KEY Comparison Status Register

Bits | Field | Descriptions
[0] | KEYBUSY | KEY Comparison Busy (Read Only) 0 = KEY comparison is finished. 1 = KEY comparison is busy.
[1] | KEYLOCK | KEY LOCK Flag This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection After Mass Erase operation, users must reset or power on /off to clear this bit to 0 This bit also can be set to 1 while - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or - KEYENROM is programmed a non-0xFF value or - Timeout event or - FORBID(FMC_KPKEYSTS[3]) is 1 0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. 1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. SPROM write protect is depended on SPFLAG. CONFIG write protect is depended on CFGFLAG
[2] | KEYMATCH | KEY Match Flag (Read Only) This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched This bit is also cleared to 0 while - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or - Timeout event or - KPROM is erased or - KEYENROM is programmed to a non-0xFF value. - Chip is in power down mode. 0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. 1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
[3] | FORBID | KEY Comparison Forbidden Flag (Read Only) This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). 0 = KEY comparison is not forbidden. 1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
[4] | KEYFLAG | KEY Protection Enabled Flag (Read Only) This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset This bit is cleared to 0 by hardware while KPROM is erased This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. 0 = Security Key protection is disabled. 1 = Security Key protection is enabled.
[5] | CFGFLAG | CONFIG Write-protection Enabled Flag (Read Only) This bit is set while the KEYENROM [0] is 0 at power-on or reset This bit is cleared to 0 by hardware while KPROM is erased This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. 0 = CONFIG write-protection is disabled. 1 = CONFIG write-protection is enabled.
[6] | SPFLAG | SPROM Write-protection Enabled Flag (Read Only) This bit is set while the KEYENROM [1] is 0 at power-on or reset This bit is cleared to 0 by hardware while KPROM is erased This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0. 0 = SPROM write-protection is disabled. 1 = SPROM write-protection is enabled.

Definition at line 981 of file fmc_reg.h.

## ◆ KPKEYTRG

FMC_T::KPKEYTRG

[0x005c] KPROM KEY Comparison Trigger Control Register

KPKEYTRG

Offset: 0x5C KPROM KEY Comparison Trigger Control Register

Bits | Field | Descriptions
[0] | KPKEYGO | KPROM KEY Comparison Start Trigger (Write Protection) Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. 0 = KEY comparison operation is finished. 1 = KEY comparison is progressed. Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
[1] | TCEN | Timeout Counting Enable (Write Protection) 0 = Timeout counting is disabled. 1 = Timeout counting is enabled if input key is matched after key comparison finish. 10 minutes is at least for timeout, and average is about 20 minutes. Note: This bit is write-protected. Refer to the SYS_REGLCTL register.

Definition at line 980 of file fmc_reg.h.

## ◆ MPADDR

FMC_T::MPADDR

[0x00c4] ISP Multi-Program Address Register

MPADDR

Offset: 0xC4 ISP Multi-Program Address Register

Bits | Field | Descriptions
[31:0] | MPADDR | ISP Multi-word Program Address MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. MPADDR will keep the final ISP address when ISP multi-word program is complete.

Definition at line 995 of file fmc_reg.h.

## ◆ MPDAT0

FMC_T::MPDAT0

[0x0080] ISP Data0 Register

MPDAT0

Offset: 0x80 ISP Data0 Register

Bits | Field | Descriptions
[31:0] | ISPDAT0 | ISP Data 0 This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data

Definition at line 987 of file fmc_reg.h.

## ◆ MPDAT1

FMC_T::MPDAT1

[0x0084] ISP Data1 Register

MPDAT1

Offset: 0x84 ISP Data1 Register

Bits | Field | Descriptions
[31:0] | ISPDAT1 | ISP Data 1 This register is the second 32-bit data for 64-bit/multi-word programming.

Definition at line 988 of file fmc_reg.h.

## ◆ MPDAT2

FMC_T::MPDAT2

[0x0088] ISP Data2 Register

MPDAT2

Offset: 0x88 ISP Data2 Register

Bits | Field | Descriptions
[31:0] | ISPDAT2 | ISP Data 2 This register is the third 32-bit data for multi-word programming.

Definition at line 989 of file fmc_reg.h.

## ◆ MPDAT3

FMC_T::MPDAT3

[0x008c] ISP Data3 Register

MPDAT3

Offset: 0x8C ISP Data3 Register

Bits | Field | Descriptions
[31:0] | ISPDAT3 | ISP Data 3 This register is the fourth 32-bit data for multi-word programming.

Definition at line 990 of file fmc_reg.h.

## ◆ MPSTS

FMC_T::MPSTS

[0x00c0] ISP Multi-Program Status Register

MPSTS

Offset: 0xC0 ISP Multi-Program Status Register

Bits | Field | Descriptions
[0] | MPBUSY | ISP Multi-word Program Busy Flag (Read Only) Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 = ISP Multi-Word program operation is finished. 1 = ISP Multi-Word program operation is progressed.
[1] | PPGO | ISP Multi-program Status (Read Only) 0 = ISP multi-word program operation is not active. 1 = ISP multi-word program operation is in progress.
[2] | ISPFF | ISP Fail Flag (Read Only) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) SPROM is erased/programmed if SPUEN is set to 0 (5) SPROM is programmed at SPROM secured mode. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) Vector address is mapping to SPROM region.
[4] | D0 | ISP DATA 0 Flag (Read Only) This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. 0 = FMC_MPDAT0 register is empty, or program to flash complete. 1 = FMC_MPDAT0 register has been written, and not program to flash complete.
[5] | D1 | ISP DATA 1 Flag (Read Only) This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. 0 = FMC_MPDAT1 register is empty, or program to flash complete. 1 = FMC_MPDAT1 register has been written, and not program to flash complete.
[6] | D2 | ISP DATA 2 Flag (Read Only) This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. 0 = FMC_MPDAT2 register is empty, or program to flash complete. 1 = FMC_MPDAT2 register has been written, and not program to flash complete.
[7] | D3 | ISP DATA 3 Flag (Read Only) This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. 0 = FMC_MPDAT3 register is empty, or program to flash complete. 1 = FMC_MPDAT3 register has been written, and not program to flash complete.

Definition at line 994 of file fmc_reg.h.

## ◆ XOMR0STS

__I uint32_t FMC_T::XOMR0STS

[0x00d0] XOM Region 0 Status Register

Definition at line 999 of file fmc_reg.h.

## ◆ XOMR1STS

__I uint32_t FMC_T::XOMR1STS

[0x00d4] XOM Region 1 Status Register

Definition at line 1000 of file fmc_reg.h.

## ◆ XOMR2STS

__I uint32_t FMC_T::XOMR2STS

[0x00d8] XOM Region 2 Status Register

Definition at line 1001 of file fmc_reg.h.

## ◆ XOMR3STS

__I uint32_t FMC_T::XOMR3STS

[0x00dc] XOM Region 3 Status Register

Definition at line 1002 of file fmc_reg.h.

## ◆ XOMSTS

__I uint32_t FMC_T::XOMSTS

[0x00e0] XOM Status Register

Definition at line 1003 of file fmc_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/fmc_reg.h