| M480 BSP V3.05.001 The Board Support Package for M480 Series

clk.c
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1 /**************************************************************************/
10 #include "NuMicro.h"
11
30 void CLK_DisableCKO(void)
31 {
32 /* Disable CKO clock source */
33 CLK_DisableModuleClock(CLKO_MODULE);
34 }
35
53 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
54 {
55 /* CKO = clock source / 2^(u32ClkDiv + 1) */
56 CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
57
58 /* Enable CKO clock source */
59 CLK_EnableModuleClock(CLKO_MODULE);
60
61 /* Select CKO clock source */
62 CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL);
63 }
64
72 void CLK_PowerDown(void)
73 {
74 uint32_t u32HIRCTRIMCTL;
75
76 /* Set the processor uses deep sleep as its low power mode */
77 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
78
79 /* Set system Power-down enabled */
80 CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk);
81
82 /* Store HIRC control register */
83 u32HIRCTRIMCTL = SYS->IRCTCTL;
84
85 /* Disable HIRC auto trim */
86 SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk);
87
88 /* Chip enter Power-down mode after CPU run WFI instruction */
89 __WFI();
90
91 /* Restore HIRC control register */
92 SYS->IRCTCTL = u32HIRCTRIMCTL;
93 }
94
102 void CLK_Idle(void)
103 {
104 /* Set the processor uses sleep as its low power mode */
105 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
106
107 /* Set chip in idle mode because of WFI command */
108 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
109
110 /* Chip enter idle mode after CPU run WFI instruction */
111 __WFI();
112 }
113
120 uint32_t CLK_GetHXTFreq(void)
121 {
122 uint32_t u32Freq;
123
124 if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk)
125 {
126 u32Freq = __HXT;
127 }
128 else
129 {
130 u32Freq = 0UL;
131 }
132
133 return u32Freq;
134 }
135
136
143 uint32_t CLK_GetLXTFreq(void)
144 {
145 uint32_t u32Freq;
146 if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk)
147 {
148 u32Freq = __LXT;
149 }
150 else
151 {
152 u32Freq = 0UL;
153 }
154
155 return u32Freq;
156 }
157
164 uint32_t CLK_GetPCLK0Freq(void)
165 {
166 uint32_t u32Freq;
167 SystemCoreClockUpdate();
168
169 if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1)
170 {
171 u32Freq = SystemCoreClock;
172 }
173 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2)
174 {
175 u32Freq = SystemCoreClock / 2UL;
176 }
177 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV4)
178 {
179 u32Freq = SystemCoreClock / 4UL;
180 }
181 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV8)
182 {
183 u32Freq = SystemCoreClock / 8UL;
184 }
185 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV16)
186 {
187 u32Freq = SystemCoreClock / 16UL;
188 }
189 else
190 {
191 u32Freq = SystemCoreClock;
192 }
193
194 return u32Freq;
195 }
196
197
204 uint32_t CLK_GetPCLK1Freq(void)
205 {
206 uint32_t u32Freq;
207 SystemCoreClockUpdate();
208
209 if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV1)
210 {
211 u32Freq = SystemCoreClock;
212 }
213 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV2)
214 {
215 u32Freq = SystemCoreClock / 2UL;
216 }
217 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV4)
218 {
219 u32Freq = SystemCoreClock / 4UL;
220 }
221 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV8)
222 {
223 u32Freq = SystemCoreClock / 8UL;
224 }
225 else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV16)
226 {
227 u32Freq = SystemCoreClock / 16UL;
228 }
229 else
230 {
231 u32Freq = SystemCoreClock;
232 }
233
234 return u32Freq;
235 }
236
237
244 uint32_t CLK_GetHCLKFreq(void)
245 {
246 SystemCoreClockUpdate();
247 return SystemCoreClock;
248 }
249
250
257 uint32_t CLK_GetCPUFreq(void)
258 {
259 SystemCoreClockUpdate();
260 return SystemCoreClock;
261 }
262
263
271 uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
272 {
273 uint32_t u32HIRCSTB;
274
275 /* Read HIRC clock source stable flag */
276 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
277
278 /* The range of u32Hclk is running up to 192 MHz */
279 if(u32Hclk > FREQ_192MHZ)
280 {
281 u32Hclk = FREQ_192MHZ;
282 }
283
284 /* Switch HCLK clock source to HIRC clock for safe */
285 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
286 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
287 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
288 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
289
290 /* Configure PLL setting if HXT clock is enabled */
291 if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk)
292 {
293 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
294 }
295 /* Configure PLL setting if HXT clock is not enabled */
296 else
297 {
298 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
299
300 /* Read HIRC clock source stable flag */
301 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
302 }
303
304 /* Select HCLK clock source to PLL,
305 and update system core clock
306 */
307 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
308
309 /* Disable HIRC if HIRC is disabled before setting core clock */
310 if(u32HIRCSTB == 0UL)
311 {
312 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
313 }
314
315 /* Return actually HCLK frequency is PLL frequency divide 1 */
316 return u32Hclk;
317 }
318
333 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
334 {
335 uint32_t u32HIRCSTB;
336
337 /* Read HIRC clock source stable flag */
338 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
339
340 /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
341 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
342 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
343 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
344
345 /* Apply new Divider */
346 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
347
348 /* Switch HCLK to new HCLK source */
349 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
350
351 /* Update System Core Clock */
352 SystemCoreClockUpdate();
353
354 /* Disable HIRC if HIRC is disabled before switching HCLK source */
355 if(u32HIRCSTB == 0UL)
356 {
357 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
358 }
359 }
360
503 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
504 {
505 uint32_t u32sel = 0U, u32div = 0U;
506
507 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
508 {
509 /* Get clock divider control register address */
510 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
511 {
512 if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1
513 {
514 u32div = (uint32_t)&CLK->CLKDIV2;
515 }
516 else if(MODULE_CLKDIV(u32ModuleIdx) == 2U && MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0
517 {
518 u32div = (uint32_t)&CLK->CLKDIV2;
519 }
520 else if (MODULE_CLKDIV(u32ModuleIdx) == 2U)
521 {
522 u32div = (uint32_t)&CLK->CLKDIV3;
523 }
524 else if (MODULE_CLKDIV(u32ModuleIdx) == 3U)
525 {
526 u32div = (uint32_t)&CLK->CLKDIV4;
527 }
528 else
529 {
530 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
531 }
532 }
533 else
534 {
535 /* Get clock divider control register address */
536 if(MODULE_CLKDIV(u32ModuleIdx) == 2U)
537 {
538 u32div = (uint32_t)&CLK->CLKDIV3;
539 }
540 else if (MODULE_CLKDIV(u32ModuleIdx) == 3U)
541 {
542 u32div = (uint32_t)&CLK->CLKDIV4;
543 }
544 else
545 {
546 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
547 }
548 }
549
550 /* Apply new divider */
551 M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
552 }
553
554 if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
555 {
556 /* Get clock select control register address */
557 u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U);
558 /* Set new clock selection setting */
559 M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
560 }
561 }
562
575 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
576 {
577 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
578
579 }
580
592 void CLK_EnableXtalRC(uint32_t u32ClkMask)
593 {
594 CLK->PWRCTL |= u32ClkMask;
595 }
596
608 void CLK_DisableXtalRC(uint32_t u32ClkMask)
609 {
610 CLK->PWRCTL &= ~u32ClkMask;
611 }
612
685 void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
686 {
687 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
688
689 u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
690 u32tmpAddr = (uint32_t)&CLK->AHBCLK;
691 u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
692
693 *(volatile uint32_t *)u32tmpAddr |= u32tmpVal;
694 }
695
768 void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
769 {
770 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
771
772 u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
773 u32tmpAddr = (uint32_t)&CLK->AHBCLK;
774 u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
775
776 *(uint32_t *)u32tmpAddr &= u32tmpVal;
777 }
778
779
790 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
791 {
792 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk;
793 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq;
794
795 /* Disable PLL first to avoid unstable when setting PLL */
796 CLK_DisablePLL();
797
798 /* PLL source clock is from HXT */
799 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
800 {
801 /* Enable HXT clock */
802 CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
803
804 /* Wait for HXT clock ready */
805 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
806
807 /* Select PLL source clock from HXT */
808 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
809 u32PllSrcClk = __HXT;
810
811 /* u32NR start from 2 */
812 u32NR = 2UL;
813 }
814
815 /* PLL source clock is from HIRC */
816 else
817 {
818 /* Enable HIRC clock */
819 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
820
821 /* Wait for HIRC clock ready */
822 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
823
824 /* Select PLL source clock from HIRC */
825 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
826 u32PllSrcClk = __HIRC;
827
828 /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
829 u32NR = 4UL;
830 }
831
832 if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ))
833 {
834
835 /* Find best solution */
836 u32Min = (uint32_t) - 1;
837 u32MinNR = 0UL;
838 u32MinNF = 0UL;
839 u32MinNO = 0UL;
840 u32basFreq = u32PllFreq;
841
842 for(u32NO = 1UL; u32NO <= 4UL; u32NO++)
843 {
844 /* Break when get good results */
845 if (u32Min == 0UL)
846 {
847 break;
848 }
849
850 if (u32NO != 3UL)
851 {
852
853 if(u32NO == 4UL)
854 {
855 u32PllFreq = u32basFreq << 2;
856 }
857 else if(u32NO == 2UL)
858 {
859 u32PllFreq = u32basFreq << 1;
860 }
861 else
862 {
863 }
864
865 for(u32NR = 2UL; u32NR <= 32UL; u32NR++)
866 {
867 /* Break when get good results */
868 if (u32Min == 0UL)
869 {
870 break;
871 }
872
873 u32Tmp = u32PllSrcClk / u32NR;
874 if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL))
875 {
876 for(u32NF = 2UL; u32NF <= 513UL; u32NF++)
877 {
878 /* u32Tmp2 is shifted 2 bits to avoid overflow */
879 u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF);
880
881 if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ))
882 {
883 u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2;
884 if(u32Tmp3 < u32Min)
885 {
886 u32Min = u32Tmp3;
887 u32MinNR = u32NR;
888 u32MinNF = u32NF;
889 u32MinNO = u32NO;
890
891 /* Break when get good results */
892 if(u32Min == 0UL)
893 {
894 break;
895 }
896 }
897 }
898 }
899 }
900 }
901 }
902 }
903
904 /* Enable and apply new PLL setting. */
905 CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);
906
907 /* Wait for PLL clock stable */
908 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
909
910 /* Actual PLL output clock frequency */
911 u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL;
912 }
913 else
914 {
915 /* Wrong frequency request. Just return default setting. */
916 /* Apply default PLL setting and return */
917 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
918 {
919 CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT;
920 }
921 else
922 {
923 CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC;
924 }
925
926 /* Wait for PLL clock stable */
927 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
928
929 /* Actual PLL output clock frequency */
930 u32PllClk = CLK_GetPLLClockFreq();
931 }
932
933 return u32PllClk;
934 }
935
943 void CLK_DisablePLL(void)
944 {
945 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
946 }
947
948
961 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
962 {
963 int32_t i32TimeOutCnt = 2160000;
964 uint32_t u32Ret = 1U;
965
966 while((CLK->STATUS & u32ClkMask) != u32ClkMask)
967 {
968 if(i32TimeOutCnt-- <= 0)
969 {
970 u32Ret = 0U;
971 break;
972 }
973 }
974 return u32Ret;
975 }
976
991 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
992 {
993 /* Set System Tick counter disabled */
994 SysTick->CTRL = 0UL;
995
996 /* Set System Tick clock source */
997 if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
998 {
999 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
1000 }
1001 else
1002 {
1003 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
1004 }
1005
1006 /* Set System Tick reload value */
1007 SysTick->LOAD = u32Count;
1008
1009 /* Clear System Tick current value and counter flag */
1010 SysTick->VAL = 0UL;
1011
1012 /* Set System Tick interrupt enabled and counter enabled */
1013 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
1014 }
1015
1022 void CLK_DisableSysTick(void)
1023 {
1024 /* Set System Tick counter disabled */
1025 SysTick->CTRL = 0UL;
1026 }
1027
1028
1043 void CLK_SetPowerDownMode(uint32_t u32PDMode)
1044 {
1045 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
1046 {
1047 if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD0)
1048 {
1049 u32PDMode = CLK_PMUCTL_PDMSEL_SPD0;
1050 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_16K;
1051 }
1052 else if(u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)
1053 {
1054 u32PDMode = CLK_PMUCTL_PDMSEL_SPD0;
1055 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_SRETSEL_Msk)) | CLK_SPDSRETSEL_NO;
1056 }
1057 }
1058 else
1059 {
1060 /* Enable LIRC clock before entering to Standby Power-down Mode */
1061 if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1))
1062 {
1063 /* Enable LIRC clock */
1064 CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk;
1065
1066 /* Wait for LIRC clock stable */
1067 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
1068 }
1069 }
1070
1071 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode;
1072 }
1073
1074
1099 void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
1100 {
1101 uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4;
1102
1103 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
1104 {
1105 u32Pin1 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN1_Pos);
1106 u32Pin2 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN2_Pos);
1107 u32Pin3 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN3_Pos);
1108 u32Pin4 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN4_Pos);
1109
1110 if(u32Pin1)
1111 {
1112 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType;
1113 }
1114 else if(u32Pin2)
1115 {
1116 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType;
1117 }
1118 else if(u32Pin3)
1119 {
1120 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType;
1121 }
1122 else if(u32Pin4)
1123 {
1124 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType;
1125 }
1126 else
1127 {
1128 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
1129 }
1130 }
1131 else
1132 {
1133 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
1134 }
1135 }
1136
1146 uint32_t CLK_GetPMUWKSrc(void)
1147 {
1148 return (CLK->PMUSTS);
1149 }
1150
1167 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
1168 {
1169 uint32_t u32tmpAddr = 0UL;
1170 uint32_t u32tmpVal = 0UL;
1171
1172 /* GPx Stand-by Power-down Wake-up Pin Select */
1173 u32tmpAddr = (uint32_t)&CLK->PASWKCTL;
1174 u32tmpAddr += (0x4UL * u32Port);
1175
1176 u32tmpVal = inpw((uint32_t *)u32tmpAddr);
1177 u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
1178 (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
1179 outpw((uint32_t *)u32tmpAddr, u32tmpVal);
1180 }
1181
1188 uint32_t CLK_GetPLLClockFreq(void)
1189 {
1190 uint32_t u32PllFreq = 0UL, u32PllReg;
1191 uint32_t u32FIN, u32NF, u32NR, u32NO;
1192 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
1193
1194 u32PllReg = CLK->PLLCTL;
1195
1196 if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
1197 {
1198 u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
1199 }
1200 else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk)
1201 {
1202 if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC)
1203 {
1204 u32FIN = __HIRC; /* PLL source clock from HIRC */
1205 }
1206 else
1207 {
1208 u32FIN = __HXT; /* PLL source clock from HXT */
1209 }
1210
1211 u32PllFreq = u32FIN;
1212 }
1213 else
1214 {
1215 if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC)
1216 {
1217 u32FIN = __HIRC; /* PLL source clock from HIRC */
1218 }
1219 else
1220 {
1221 u32FIN = __HXT; /* PLL source clock from HXT */
1222 }
1223 /* PLL is output enabled in normal work mode */
1224 u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
1225 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
1226 u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
1227
1228 /* u32FIN is shifted 2 bits to avoid overflow */
1229 u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL;
1230 }
1231
1232 return u32PllFreq;
1233 }
1234
1274 uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
1275 {
1276 uint32_t u32sel = 0;
1277 uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC};
1278
1279 /* Get clock source selection setting */
1280 if(u32ModuleIdx == EPWM0_MODULE)
1281 return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);
1282 else if(u32ModuleIdx == EPWM1_MODULE)
1283 return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);
1284 else if(u32ModuleIdx == BPWM0_MODULE)
1285 return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);
1286 else if(u32ModuleIdx == BPWM1_MODULE)
1287 return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);
1288 else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
1289 {
1290 /* Get clock select control register address */
1291 u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
1292 /* Get clock source selection setting */
1293 return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
1294 }
1295 else
1296 return 0;
1297 }
1298
1323 uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
1324 {
1325 uint32_t u32div = 0;
1326 uint32_t u32DivTbl[4] = {0x0, 0x4, 0xc, 0x10};
1327
1328 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
1329 {
1330 /* Get clock divider control register address */
1331 u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
1332 if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) // M480LD
1333 {
1334 if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 31U) //EADC1
1335 u32div = (uint32_t)&CLK->CLKDIV2;
1336 else if(MODULE_IP_EN_Pos_ENC(u32ModuleIdx) == 29U) //I2S0
1337 u32div = (uint32_t)&CLK->CLKDIV2;
1338 }
1339 /* Get clock divider number setting */
1340 return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
1341 }
1342 else
1343 return 0;
1344 }
1345
1346 /* end of group CLK_EXPORTED_FUNCTIONS */
1348 /* end of group CLK_Driver */
1350 /* end of group Standard_Driver */
1352
1353 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
CLK_PASWKCTL_WKPSEL_Msk
#define CLK_PASWKCTL_WKPSEL_Msk
Definition: clk_reg.h:2871
CLK_PASWKCTL_DBEN_Msk
#define CLK_PASWKCTL_DBEN_Msk
Definition: clk_reg.h:2874
CLK_PCLKDIV_APB1DIV_Msk
#define CLK_PCLKDIV_APB1DIV_Msk
Definition: clk_reg.h:2682
CLK_CLKSEL2_BPWM1SEL_Msk
#define CLK_CLKSEL2_BPWM1SEL_Msk
Definition: clk_reg.h:2571
M32
#define M32(addr)
Get a 32-bit unsigned value from specified address.
Definition: M480.h:492
CLK
#define CLK
Definition: M480.h:368
CLK_PLLCTL_192MHz_HXT
#define CLK_PLLCTL_192MHz_HXT
Definition: clk.h:330
FREQ_192MHZ
#define FREQ_192MHZ
Definition: clk.h:38
CLK_CLKOCTL_CLKOEN_Msk
#define CLK_CLKOCTL_CLKOEN_Msk
Definition: clk_reg.h:2733
CLK_CLKSEL0_HCLKSEL_PLL
#define CLK_CLKSEL0_HCLKSEL_PLL
Definition: clk.h:48
CLK_EnableCKO
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable clock divider output module clock, enable clock divider output function and set ...
Definition: clk.c:53
CLK_PMUCTL_PDMSEL_Msk
#define CLK_PMUCTL_PDMSEL_Msk
Definition: clk_reg.h:2775
CLK_PMUCTL_SRETSEL_Msk
#define CLK_PMUCTL_SRETSEL_Msk
Definition: clk_reg.h:2781
CLK_CLKSEL0_STCLKSEL_Msk
#define CLK_CLKSEL0_STCLKSEL_Msk
Definition: clk_reg.h:2511
BPWM0_MODULE
#define BPWM0_MODULE
Definition: clk.h:420
CLK_CLKSEL2_BPWM0SEL_Pos
#define CLK_CLKSEL2_BPWM0SEL_Pos
Definition: clk_reg.h:2567
CLK_CLKSEL0_HCLKSEL_HIRC
#define CLK_CLKSEL0_HCLKSEL_HIRC
Definition: clk.h:50
CLK_PCLKDIV_APB0DIV_DIV4
#define CLK_PCLKDIV_APB0DIV_DIV4
Definition: clk.h:304
CLK_PMUCTL_WKPINEN4_Pos
#define CLK_PMUCTL_WKPINEN4_Pos
Definition: clk_reg.h:2807
BPWM1_MODULE
#define BPWM1_MODULE
Definition: clk.h:421
CLK_SPDSRETSEL_16K
#define CLK_SPDSRETSEL_16K
Definition: clk.h:519
CLK_PMUCTL_WKPINEN4_Msk
#define CLK_PMUCTL_WKPINEN4_Msk
Definition: clk_reg.h:2808
CLK_CLKOCTL_DIV1EN_Pos
#define CLK_CLKOCTL_DIV1EN_Pos
Definition: clk_reg.h:2735
CLK_GetModuleClockSource
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
Get selected module clock source.
Definition: clk.c:1274
CLK_CLKSEL2_BPWM0SEL_Msk
#define CLK_CLKSEL2_BPWM0SEL_Msk
Definition: clk_reg.h:2568
MODULE_CLKSEL_Msk
#define MODULE_CLKSEL_Msk(x)
Definition: clk.h:346
CLK_PCLKDIV_APB0DIV_Msk
#define CLK_PCLKDIV_APB0DIV_Msk
Definition: clk_reg.h:2679
CLK_CLKSEL2_EPWM1SEL_Msk
#define CLK_CLKSEL2_EPWM1SEL_Msk
Definition: clk_reg.h:2556
SYS_IRCTCTL_FREQSEL_Msk
#define SYS_IRCTCTL_FREQSEL_Msk
Definition: sys_reg.h:5998
CLK_PCLKDIV_APB0DIV_DIV16
#define CLK_PCLKDIV_APB0DIV_DIV16
Definition: clk.h:306
CLK_PLLCTL_OUTDIV_Msk
#define CLK_PLLCTL_OUTDIV_Msk
Definition: clk_reg.h:2691
NuMicro.h
NuMicro peripheral access layer header file.
SYS
#define SYS
Definition: M480.h:367
CLK_PLLCTL_INDIV_Msk
#define CLK_PLLCTL_INDIV_Msk
Definition: clk_reg.h:2688
CLK_PLLCTL_OUTDIV_Pos
#define CLK_PLLCTL_OUTDIV_Pos
Definition: clk_reg.h:2690
SYS_CSERVER_VERSION_Msk
#define SYS_CSERVER_VERSION_Msk
Definition: sys_reg.h:6034
CLK_SPDWKPIN_ENABLE
#define CLK_SPDWKPIN_ENABLE
Definition: clk.h:512
CLK_PLLCTL_FBDIV_Msk
#define CLK_PLLCTL_FBDIV_Msk
Definition: clk_reg.h:2685
CLK_DisableCKO
void CLK_DisableCKO(void)
Disable clock divider output function.
Definition: clk.c:30
CLK_PMUCTL_WKPINEN_Msk
#define CLK_PMUCTL_WKPINEN_Msk
Definition: clk_reg.h:2790
FREQ_125MHZ
#define FREQ_125MHZ
Definition: clk.h:36
CLK_PLLCTL_INDIV_Pos
#define CLK_PLLCTL_INDIV_Pos
Definition: clk_reg.h:2687
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_M480.c:21
CLK_STATUS_HIRCSTB_Msk
#define CLK_STATUS_HIRCSTB_Msk
Definition: clk_reg.h:2721
CLK_PCLKDIV_APB0DIV_DIV1
#define CLK_PCLKDIV_APB0DIV_DIV1
Definition: clk.h:302
CLK_Idle
void CLK_Idle(void)
Enter to Idle mode.
Definition: clk.c:102
CLK_EnableSPDWKPin
void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
Set specified GPIO as wake up source at Stand-by Power down mode.
Definition: clk.c:1167
CLKO_MODULE
#define CLKO_MODULE
Definition: clk.h:384
CLK_PCLKDIV_APB1DIV_DIV4
#define CLK_PCLKDIV_APB1DIV_DIV4
Definition: clk.h:309
CLK_PCLKDIV_APB1DIV_DIV1
#define CLK_PCLKDIV_APB1DIV_DIV1
Definition: clk.h:307
CLK_PWRCTL_HIRCEN_Msk
#define CLK_PWRCTL_HIRCEN_Msk
Definition: clk_reg.h:2283
CLK_SetCoreClock
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
Definition: clk.c:271
CLK_PMUCTL_WKPINEN1_Msk
#define CLK_PMUCTL_WKPINEN1_Msk
Definition: clk_reg.h:2799
CLK_GetPCLK1Freq
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:204
CLK_PLLCTL_PLLSRC_HXT
#define CLK_PLLCTL_PLLSRC_HXT
Definition: clk.h:316
CLK_DisableXtalRC
void CLK_DisableXtalRC(uint32_t u32ClkMask)
Disable clock source.
Definition: clk.c:608
CLK_PMUCTL_WKPINEN3_Pos
#define CLK_PMUCTL_WKPINEN3_Pos
Definition: clk_reg.h:2804
CLK_CLKSEL0_STCLKSEL_HCLK
#define CLK_CLKSEL0_STCLKSEL_HCLK
Definition: clk.h:57
CLK_GetPCLK0Freq
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:164
CLK_GetModuleClockDivider
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
Get selected module clock divider number.
Definition: clk.c:1323
CLK_PLLCTL_FBDIV_Pos
#define CLK_PLLCTL_FBDIV_Pos
Definition: clk_reg.h:2684
CLK_STATUS_LIRCSTB_Msk
#define CLK_STATUS_LIRCSTB_Msk
Definition: clk_reg.h:2718
CLK_PWRCTL_LXTEN_Msk
#define CLK_PWRCTL_LXTEN_Msk
Definition: clk_reg.h:2280
CLK_SPDSRETSEL_NO
#define CLK_SPDSRETSEL_NO
Definition: clk.h:518
CLK_CLKSEL0_HCLKSEL_Msk
#define CLK_CLKSEL0_HCLKSEL_Msk
Definition: clk_reg.h:2508
CLK_PCLKDIV_APB1DIV_DIV8
#define CLK_PCLKDIV_APB1DIV_DIV8
Definition: clk.h:310
CLK_GetPMUWKSrc
uint32_t CLK_GetPMUWKSrc(void)
Get power manager wake up source.
Definition: clk.c:1146
CLK_CLKSEL2_EPWM1SEL_Pos
#define CLK_CLKSEL2_EPWM1SEL_Pos
Definition: clk_reg.h:2555
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1188
CLK_PLLCTL_PD_Msk
#define CLK_PLLCTL_PD_Msk
Definition: clk_reg.h:2694
CLK_CLKSEL2_BPWM1SEL_Pos
#define CLK_CLKSEL2_BPWM1SEL_Pos
Definition: clk_reg.h:2570
CLK_EnableDPDWKPin
void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
Set Wake-up pin trigger type at Deep Power down mode.
Definition: clk.c:1099
CLK_SetModuleClock
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:503
CLK_PowerDown
void CLK_PowerDown(void)
Enter to Power-down mode.
Definition: clk.c:72
CLK_PLLCTL_PLLSRC_HIRC
#define CLK_PLLCTL_PLLSRC_HIRC
Definition: clk.h:317
CLK_GetCPUFreq
uint32_t CLK_GetCPUFreq(void)
Get CPU frequency.
Definition: clk.c:257
CLK_PCLKDIV_APB0DIV_DIV8
#define CLK_PCLKDIV_APB0DIV_DIV8
Definition: clk.h:305
CLK_PMUCTL_PDMSEL_SPD1
#define CLK_PMUCTL_PDMSEL_SPD1
Definition: clk.h:437
CLK_PLLCTL_OE_Msk
#define CLK_PLLCTL_OE_Msk
Definition: clk_reg.h:2700
MODULE_IP_EN_Pos
#define MODULE_IP_EN_Pos(x)
Definition: clk.h:351
CLK_DisableModuleClock
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
Disable module clock.
Definition: clk.c:768
CLK_SetPowerDownMode
void CLK_SetPowerDownMode(uint32_t u32PDMode)
Power-down mode selected.
Definition: clk.c:1043
inpw
#define inpw(port)
Get a 32-bit unsigned value from specified I/O port.
Definition: M480.h:509
CLK_SetHCLK
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:333
CLK_EnableSysTick
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:991
MODULE_CLKDIV
#define MODULE_CLKDIV(x)
Definition: clk.h:348
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
Definition: system_M480.c:29
MODULE_CLKDIV_Pos
#define MODULE_CLKDIV_Pos(x)
Definition: clk.h:350
FREQ_500MHZ
#define FREQ_500MHZ
Definition: clk.h:41
CLK_CLKDIV0_HCLK
#define CLK_CLKDIV0_HCLK(x)
Definition: clk.h:250
CLK_EnableModuleClock
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
Enable module clock.
Definition: clk.c:685
MODULE_APBCLK
#define MODULE_APBCLK(x)
Definition: clk.h:344
CLK_PCLKDIV_APB0DIV_DIV2
#define CLK_PCLKDIV_APB0DIV_DIV2
Definition: clk.h:303
FREQ_50MHZ
#define FREQ_50MHZ
Definition: clk.h:32
MODULE_CLKDIV_Msk
#define MODULE_CLKDIV_Msk(x)
Definition: clk.h:349
CLK_PCLKDIV_APB1DIV_DIV2
#define CLK_PCLKDIV_APB1DIV_DIV2
Definition: clk.h:308
CLK_PWRCTL_PDEN_Msk
#define CLK_PWRCTL_PDEN_Msk
Definition: clk_reg.h:2298
CLK_PMUCTL_WKPINEN3_Msk
#define CLK_PMUCTL_WKPINEN3_Msk
Definition: clk_reg.h:2805
CLK_PMUCTL_PDMSEL_SPD0
#define CLK_PMUCTL_PDMSEL_SPD0
Definition: clk.h:436
CLK_PLLCTL_192MHz_HIRC
#define CLK_PLLCTL_192MHz_HIRC
Definition: clk.h:336
CLK_STATUS_HXTSTB_Msk
#define CLK_STATUS_HXTSTB_Msk
Definition: clk_reg.h:2709
CLK_PASWKCTL_PFWKEN_Msk
#define CLK_PASWKCTL_PFWKEN_Msk
Definition: clk_reg.h:2868
EPWM0_MODULE
#define EPWM0_MODULE
Definition: clk.h:418
CLK_CLKSEL2_EPWM0SEL_Msk
#define CLK_CLKSEL2_EPWM0SEL_Msk
Definition: clk_reg.h:2553
__LXT
#define __LXT
Definition: system_M480.h:33
CLK_DisablePLL
void CLK_DisablePLL(void)
Disable PLL.
Definition: clk.c:943
__HIRC
#define __HIRC
Definition: system_M480.h:36
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
Definition: clk.c:244
CLK_DisableSysTick
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:1022
EPWM1_MODULE
#define EPWM1_MODULE
Definition: clk.h:419
MODULE_IP_EN_Pos_ENC
#define MODULE_IP_EN_Pos_ENC(x)
Definition: clk.h:362
CLK_CLKSEL2_EPWM0SEL_Pos
#define CLK_CLKSEL2_EPWM0SEL_Pos
Definition: clk_reg.h:2552
outpw
#define outpw(port, value)
Set a 32-bit unsigned value to specified I/O port.
Definition: M480.h:501
CLK_PASWKCTL_PRWKEN_Msk
#define CLK_PASWKCTL_PRWKEN_Msk
Definition: clk_reg.h:2865
CLK_PLLCTL_BP_Msk
#define CLK_PLLCTL_BP_Msk
Definition: clk_reg.h:2697
CLK_PMUCTL_WKPINEN2_Pos
#define CLK_PMUCTL_WKPINEN2_Pos
Definition: clk_reg.h:2801
MODULE_CLKSEL_Pos
#define MODULE_CLKSEL_Pos(x)
Definition: clk.h:347
CLK_PMUCTL_WKPINEN2_Msk
#define CLK_PMUCTL_WKPINEN2_Msk
Definition: clk_reg.h:2802
MODULE_NoMsk
#define MODULE_NoMsk
Definition: clk.h:352
CLK_PASWKCTL_WKEN_Msk
#define CLK_PASWKCTL_WKEN_Msk
Definition: clk_reg.h:2862
CLK_GetLXTFreq
uint32_t CLK_GetLXTFreq(void)
Get external low speed crystal clock frequency.
Definition: clk.c:143
CLK_PWRCTL_HXTEN_Msk
#define CLK_PWRCTL_HXTEN_Msk
Definition: clk_reg.h:2277
CLK_EnableXtalRC
void CLK_EnableXtalRC(uint32_t u32ClkMask)
Enable clock source.
Definition: clk.c:592
CLK_CLKDIV0_HCLKDIV_Msk
#define CLK_CLKDIV0_HCLKDIV_Msk
Definition: clk_reg.h:2616
__HXT
#define __HXT
Definition: system_M480.h:29
MODULE_CLKSEL
#define MODULE_CLKSEL(x)
Definition: clk.h:345
CLK_SetSysTickClockSrc
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
Set SysTick clock source.
Definition: clk.c:575
CLK_PCLKDIV_APB1DIV_DIV16
#define CLK_PCLKDIV_APB1DIV_DIV16
Definition: clk.h:311
CLK_WaitClockReady
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:961
CLK_EnablePLL
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
Set PLL frequency.
Definition: clk.c:790
CLK_PWRCTL_LIRCEN_Msk
#define CLK_PWRCTL_LIRCEN_Msk
Definition: clk_reg.h:2286
CLK_PMUCTL_WKPINEN1_Pos
#define CLK_PMUCTL_WKPINEN1_Pos
Definition: clk_reg.h:2798
CLK_PASWKCTL_WKPSEL_Pos
#define CLK_PASWKCTL_WKPSEL_Pos
Definition: clk_reg.h:2870
CLK_GetHXTFreq
uint32_t CLK_GetHXTFreq(void)
Get external high speed crystal clock frequency.
Definition: clk.c:120
CLK_STATUS_PLLSTB_Msk
#define CLK_STATUS_PLLSTB_Msk
Definition: clk_reg.h:2715