| M480 BSP V3.05.001 The Board Support Package for M480 Series

Macros | Functions
CLK Exported Functions
Standard Driver » CLK Driver

## Macros
#define | CLK_SET_WKTMR_INTERVAL(u32Interval)
| Set Wake-up Timer Time-out Interval. More...
#define | CLK_SET_SPDDEBOUNCETIME(u32CycleSel)
| Set De-bounce Sampling Cycle Time. More...

## Functions
__STATIC_INLINE void | CLK_SysTickDelay (uint32_t us)
| This function execute delay function. More...
__STATIC_INLINE void | CLK_SysTickLongDelay (uint32_t us)
| This function execute long delay function. More...
void | CLK_DisableCKO (void)
| Disable clock divider output function. More...
void | CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
| This function enable clock divider output module clock, enable clock divider output function and set frequency selection. More...
void | CLK_PowerDown (void)
| Enter to Power-down mode. More...
void | CLK_Idle (void)
| Enter to Idle mode. More...
uint32_t | CLK_GetHXTFreq (void)
| Get external high speed crystal clock frequency. More...
uint32_t | CLK_GetLXTFreq (void)
| Get external low speed crystal clock frequency. More...
uint32_t | CLK_GetHCLKFreq (void)
| Get HCLK frequency. More...
uint32_t | CLK_GetPCLK0Freq (void)
| Get PCLK0 frequency. More...
uint32_t | CLK_GetPCLK1Freq (void)
| Get PCLK1 frequency. More...
uint32_t | CLK_GetCPUFreq (void)
| Get CPU frequency. More...
uint32_t | CLK_SetCoreClock (uint32_t u32Hclk)
| Set HCLK frequency. More...
void | CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
| This function set HCLK clock source and HCLK clock divider. More...
void | CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
| This function set selected module clock source and module clock divider. More...
void | CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
| Set SysTick clock source. More...
void | CLK_EnableXtalRC (uint32_t u32ClkMask)
| Enable clock source. More...
void | CLK_DisableXtalRC (uint32_t u32ClkMask)
| Disable clock source. More...
void | CLK_EnableModuleClock (uint32_t u32ModuleIdx)
| Enable module clock. More...
void | CLK_DisableModuleClock (uint32_t u32ModuleIdx)
| Disable module clock. More...
uint32_t | CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
| Set PLL frequency. More...
void | CLK_DisablePLL (void)
| Disable PLL. More...
uint32_t | CLK_WaitClockReady (uint32_t u32ClkMask)
| This function check selected clock source status. More...
void | CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
| Enable System Tick counter. More...
void | CLK_DisableSysTick (void)
| Disable System Tick counter. More...
void | CLK_SetPowerDownMode (uint32_t u32PDMode)
| Power-down mode selected. More...
void | CLK_EnableDPDWKPin (uint32_t u32TriggerType)
| Set Wake-up pin trigger type at Deep Power down mode. More...
uint32_t | CLK_GetPMUWKSrc (void)
| Get power manager wake up source. More...
void | CLK_EnableSPDWKPin (uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
| Set specified GPIO as wake up source at Stand-by Power down mode. More...
uint32_t | CLK_GetPLLClockFreq (void)
| Get PLL clock frequency. More...
uint32_t | CLK_GetModuleClockSource (uint32_t u32ModuleIdx)
| Get selected module clock source. More...
uint32_t | CLK_GetModuleClockDivider (uint32_t u32ModuleIdx)
| Get selected module clock divider number. More...

## Detailed Description

## Macro Definition Documentation

## ◆ CLK_SET_SPDDEBOUNCETIME

#define CLK_SET_SPDDEBOUNCETIME | ( |  | u32CycleSel | ) |

Set De-bounce Sampling Cycle Time.

Parameters

  [in] | u32CycleSel | The de-bounce sampling cycle selection. It could be CLK_SWKDBCTL_SWKDBCLKSEL_1 CLK_SWKDBCTL_SWKDBCLKSEL_2 CLK_SWKDBCTL_SWKDBCLKSEL_4 CLK_SWKDBCTL_SWKDBCLKSEL_8 CLK_SWKDBCTL_SWKDBCLKSEL_16 CLK_SWKDBCTL_SWKDBCLKSEL_32 CLK_SWKDBCTL_SWKDBCLKSEL_64 CLK_SWKDBCTL_SWKDBCLKSEL_128 CLK_SWKDBCTL_SWKDBCLKSEL_256 CLK_SWKDBCTL_SWKDBCLKSEL_2x256 CLK_SWKDBCTL_SWKDBCLKSEL_4x256 CLK_SWKDBCTL_SWKDBCLKSEL_8x256 CLK_SWKDBCTL_SWKDBCLKSEL_16x256 CLK_SWKDBCTL_SWKDBCLKSEL_32x256 CLK_SWKDBCTL_SWKDBCLKSEL_64x256 CLK_SWKDBCTL_SWKDBCLKSEL_128x256

Returns
  None

This function set Set De-bounce Sampling Cycle Time.

Definition at line 595 of file clk.h.

## ◆ CLK_SET_WKTMR_INTERVAL

#define CLK_SET_WKTMR_INTERVAL | ( |  | u32Interval | ) |

Set Wake-up Timer Time-out Interval.

Parameters

  [in] | u32Interval | The Wake-up Timer Time-out Interval selection. It could be CLK_PMUCTL_WKTMRIS_128 CLK_PMUCTL_WKTMRIS_256 CLK_PMUCTL_WKTMRIS_512 CLK_PMUCTL_WKTMRIS_1024 CLK_PMUCTL_WKTMRIS_4096 CLK_PMUCTL_WKTMRIS_8192 CLK_PMUCTL_WKTMRIS_16384 CLK_PMUCTL_WKTMRIS_65536 CLK_PMUCTL_WKTMRIS_131072 CLK_PMUCTL_WKTMRIS_262144 CLK_PMUCTL_WKTMRIS_524288 CLK_PMUCTL_WKTMRIS_1048576

Returns
  None

This function set Wake-up Timer Time-out Interval.

Definition at line 566 of file clk.h.

## Function Documentation

## ◆ CLK_DisableCKO()

void CLK_DisableCKO | ( | void |  | ) |

Disable clock divider output function.

Parameters

  None |

Returns
  None

This function disable clock divider output function.

Definition at line 30 of file clk.c.

## ◆ CLK_DisableModuleClock()

void CLK_DisableModuleClock | ( | uint32_t | u32ModuleIdx | ) |

Disable module clock.

Parameters

  [in] | u32ModuleIdx | is module index. Including : PDMA_MODULE ISP_MODULE EBI_MODULE EMAC_MODULE SDH0_MODULE CRC_MODULE CCAP_MODULE SEN_MODULE HSUSBD_MODULE CRPT_MODULE SPIM_MODULE FMCIDLE_MODULE USBH_MODULE SDH1_MODULE WDT_MODULE RTC_MODULE TMR0_MODULE TMR1_MODULE TMR2_MODULE TMR3_MODULE CLKO_MODULE WWDT_MODULE ACMP01_MODULE I2C0_MODULE I2C1_MODULE I2C2_MODULE QSPI0_MODULE SPI0_MODULE SPI1_MODULE SPI2_MODULE UART0_MODULE UART1_MODULE UART2_MODULE UART3_MODULE UART4_MODULE UART5_MODULE UART6_MODULE UART7_MODULE CAN0_MODULE CAN1_MODULE OTG_MODULE USBD_MODULE EADC_MODULE I2S0_MODULE HSOTG_MODULE SC0_MODULE SC1_MODULE SC2_MODULE QSPI1_MODULE SPI3_MODULE USCI0_MODULE USCI1_MODULE DAC_MODULE CAN2_MODULE EPWM0_MODULE EPWM1_MODULE BPWM0_MODULE BPWM1_MODULE QEI0_MODULE QEI1_MODULE TRNG_MODULE ECAP0_MODULE ECAP1_MODULE CAN2_MODULE OPA_MODULE EADC1_MODULE

Returns
  None

This function is used to disable module clock.

Definition at line 768 of file clk.c.

## ◆ CLK_DisablePLL()

void CLK_DisablePLL | ( | void |  | ) |

Disable PLL.

Parameters

  None |

Returns
  None

This function set PLL in Power-down mode.
The register write-protection function should be disabled before using this function.

Definition at line 943 of file clk.c.

## ◆ CLK_DisableSysTick()

void CLK_DisableSysTick | ( | void |  | ) |

Disable System Tick counter.

Parameters

  None |

Returns
  None

This function disable System Tick counter.

Definition at line 1022 of file clk.c.

## ◆ CLK_DisableXtalRC()

void CLK_DisableXtalRC | ( | uint32_t | u32ClkMask | ) |

Disable clock source.

Parameters

  [in] | u32ClkMask | is clock source mask. Including : CLK_PWRCTL_HXTEN_Msk CLK_PWRCTL_LXTEN_Msk CLK_PWRCTL_HIRCEN_Msk CLK_PWRCTL_LIRCEN_Msk

Returns
  None

This function disable clock source.
The register write-protection function should be disabled before using this function.

Definition at line 608 of file clk.c.

## ◆ CLK_EnableCKO()

void CLK_EnableCKO | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv,
|  | uint32_t | u32ClkDivBy1En
| ) |  |

This function enable clock divider output module clock, enable clock divider output function and set frequency selection.

Parameters

  [in] | u32ClkSrc | is frequency divider function clock source. Including : CLK_CLKSEL1_CLKOSEL_HXT CLK_CLKSEL1_CLKOSEL_LXT CLK_CLKSEL1_CLKOSEL_HCLK CLK_CLKSEL1_CLKOSEL_HIRC
  [in] | u32ClkDiv | is divider output frequency selection. It could be 0~15.
  [in] | u32ClkDivBy1En | is clock divided by one enabled.

Returns
  None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
The formula is:
CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 53 of file clk.c.

## ◆ CLK_EnableDPDWKPin()

void CLK_EnableDPDWKPin | ( | uint32_t | u32TriggerType | ) |

Set Wake-up pin trigger type at Deep Power down mode.

Parameters

  [in] | u32TriggerType | CLK_DPDWKPIN_RISING CLK_DPDWKPIN_FALLING CLK_DPDWKPIN_BOTHEDGE CLK_DPDWKPIN1_RISING CLK_DPDWKPIN1_FALLING CLK_DPDWKPIN1_BOTHEDGE CLK_DPDWKPIN2_RISING CLK_DPDWKPIN2_FALLING CLK_DPDWKPIN2_BOTHEDGE CLK_DPDWKPIN3_RISING CLK_DPDWKPIN3_FALLING CLK_DPDWKPIN3_BOTHEDGE CLK_DPDWKPIN4_RISING CLK_DPDWKPIN4_FALLING CLK_DPDWKPIN4_BOTHEDGE

Returns
  None

This function is used to enable Wake-up pin trigger type.

Definition at line 1099 of file clk.c.

## ◆ CLK_EnableModuleClock()

void CLK_EnableModuleClock | ( | uint32_t | u32ModuleIdx | ) |

Enable module clock.

Parameters

  [in] | u32ModuleIdx | is module index. Including : PDMA_MODULE ISP_MODULE EBI_MODULE EMAC_MODULE SDH0_MODULE CRC_MODULE CCAP_MODULE SEN_MODULE HSUSBD_MODULE CRPT_MODULE SPIM_MODULE FMCIDLE_MODULE USBH_MODULE SDH1_MODULE WDT_MODULE RTC_MODULE TMR0_MODULE TMR1_MODULE TMR2_MODULE TMR3_MODULE CLKO_MODULE WWDT_MODULE ACMP01_MODULE I2C0_MODULE I2C1_MODULE I2C2_MODULE QSPI0_MODULE SPI0_MODULE SPI1_MODULE SPI2_MODULE UART0_MODULE UART1_MODULE UART2_MODULE UART3_MODULE UART4_MODULE UART5_MODULE UART6_MODULE UART7_MODULE CAN0_MODULE CAN1_MODULE OTG_MODULE USBD_MODULE EADC_MODULE I2S0_MODULE HSOTG_MODULE SC0_MODULE SC1_MODULE SC2_MODULE QSPI1_MODULE SPI3_MODULE USCI0_MODULE USCI1_MODULE DAC_MODULE CAN2_MODULE EPWM0_MODULE EPWM1_MODULE BPWM0_MODULE BPWM1_MODULE QEI0_MODULE QEI1_MODULE TRNG_MODULE ECAP0_MODULE ECAP1_MODULE CAN2_MODULE OPA_MODULE EADC1_MODULE

Returns
  None

This function is used to enable module clock.

Definition at line 685 of file clk.c.

## ◆ CLK_EnablePLL()

uint32_t CLK_EnablePLL | ( | uint32_t | u32PllClkSrc,
|  | uint32_t | u32PllFreq
| ) |  |

Set PLL frequency.

Parameters

  [in] | u32PllClkSrc | is PLL clock source. Including : CLK_PLLCTL_PLLSRC_HXT CLK_PLLCTL_PLLSRC_HIRC
  [in] | u32PllFreq | is PLL frequency.

Returns
  PLL frequency

This function is used to configure PLLCTL register to set specified PLL frequency.
The register write-protection function should be disabled before using this function.

Definition at line 790 of file clk.c.

## ◆ CLK_EnableSPDWKPin()

void CLK_EnableSPDWKPin | ( | uint32_t | u32Port,
|  | uint32_t | u32Pin,
|  | uint32_t | u32TriggerType,
|  | uint32_t | u32DebounceEn
| ) |  |

Set specified GPIO as wake up source at Stand-by Power down mode.

Parameters

  [in] | u32Port | GPIO port. It could be 0~3.
  [in] | u32Pin | The pin of specified GPIO port. It could be 0 ~ 15.
  [in] | u32TriggerType | CLK_SPDWKPIN_RISING CLK_SPDWKPIN_FALLING
  [in] | u32DebounceEn | CLK_SPDWKPIN_DEBOUNCEEN CLK_SPDWKPIN_DEBOUNCEDIS

Returns
  None

This function is used to set specified GPIO as wake up source at Stand-by Power down mode.

Definition at line 1167 of file clk.c.

## ◆ CLK_EnableSysTick()

void CLK_EnableSysTick | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32Count
| ) |  |

Enable System Tick counter.

Parameters

  [in] | u32ClkSrc | is System Tick clock source. Including: CLK_CLKSEL0_STCLKSEL_HXT CLK_CLKSEL0_STCLKSEL_LXT CLK_CLKSEL0_STCLKSEL_HXT_DIV2 CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 CLK_CLKSEL0_STCLKSEL_HCLK
  [in] | u32Count | is System Tick reload value. It could be 0~0xFFFFFF.

Returns
  None

This function set System Tick clock source, reload value, enable System Tick counter and interrupt.
The register write-protection function should be disabled before using this function.

Definition at line 991 of file clk.c.

## ◆ CLK_EnableXtalRC()

void CLK_EnableXtalRC | ( | uint32_t | u32ClkMask | ) |

Enable clock source.

Parameters

  [in] | u32ClkMask | is clock source mask. Including : CLK_PWRCTL_HXTEN_Msk CLK_PWRCTL_LXTEN_Msk CLK_PWRCTL_HIRCEN_Msk CLK_PWRCTL_LIRCEN_Msk

Returns
  None

This function enable clock source.
The register write-protection function should be disabled before using this function.

Definition at line 592 of file clk.c.

## ◆ CLK_GetCPUFreq()

uint32_t CLK_GetCPUFreq | ( | void |  | ) |

Get CPU frequency.

Parameters

  None |

Returns
  CPU frequency

This function get CPU frequency. The frequency unit is Hz.

Definition at line 257 of file clk.c.

## ◆ CLK_GetHCLKFreq()

uint32_t CLK_GetHCLKFreq | ( | void |  | ) |

Get HCLK frequency.

Parameters

  None |

Returns
  HCLK frequency

This function get HCLK frequency. The frequency unit is Hz.

Definition at line 244 of file clk.c.

## ◆ CLK_GetHXTFreq()

uint32_t CLK_GetHXTFreq | ( | void |  | ) |

Get external high speed crystal clock frequency.

Parameters

  None |

Returns
  External high frequency crystal frequency

This function get external high frequency crystal frequency. The frequency unit is Hz.

Definition at line 120 of file clk.c.

## ◆ CLK_GetLXTFreq()

uint32_t CLK_GetLXTFreq | ( | void |  | ) |

Get external low speed crystal clock frequency.

Parameters

  None |

Returns
  External low speed crystal clock frequency

This function get external low frequency crystal frequency. The frequency unit is Hz.

Definition at line 143 of file clk.c.

## ◆ CLK_GetModuleClockDivider()

uint32_t CLK_GetModuleClockDivider | ( | uint32_t | u32ModuleIdx | ) |

Get selected module clock divider number.

Parameters

  [in] | u32ModuleIdx | is module index. CCAP_MODULE SDH0_MODULE SDH1_MODULE UART0_MODULE UART1_MODULE UART2_MODULE UART3_MODULE UART4_MODULE UART5_MODULE UART6_MODULE UART7_MODULE SC0_MODULE SC1_MODULE SC2_MODULE I2S0_MODULE EADC_MODULE EADC1_MODULE EMAC_MODULE

Returns
  Selected module clock divider number setting

This function get selected module clock divider number.

Definition at line 1323 of file clk.c.

## ◆ CLK_GetModuleClockSource()

uint32_t CLK_GetModuleClockSource | ( | uint32_t | u32ModuleIdx | ) |

Get selected module clock source.

Parameters

  [in] | u32ModuleIdx | is module index. CCAP_MODULE SDH0_MODULE SDH1_MODULE WDT_MODULE UART0_MODULE UART1_MODULE CLKO_MODULE WWDT_MODULE TMR0_MODULE TMR1_MODULE TMR2_MODULE TMR3_MODULE EPWM0_MODULE EPWM1_MODULE BPWM0_MODULE BPWM1_MODULE QSPI0_MODULE QSPI1_MODULE SPI0_MODULE SPI1_MODULE SPI2_MODULE SPI3_MODULE SC0_MODULE SC1_MODULE SC2_MODULE RTC_MODULE I2S0_MODULE UART2_MODULE UART3_MODULE UART4_MODULE UART5_MODULE UART6_MODULE UART7_MODULE

Returns
  Selected module clock source setting

This function get selected module clock source.

Definition at line 1274 of file clk.c.

## ◆ CLK_GetPCLK0Freq()

uint32_t CLK_GetPCLK0Freq | ( | void |  | ) |

Get PCLK0 frequency.

Parameters

  None |

Returns
  PCLK0 frequency

This function get PCLK0 frequency. The frequency unit is Hz.

Definition at line 164 of file clk.c.

## ◆ CLK_GetPCLK1Freq()

uint32_t CLK_GetPCLK1Freq | ( | void |  | ) |

Get PCLK1 frequency.

Parameters

  None |

Returns
  PCLK1 frequency

This function get PCLK1 frequency. The frequency unit is Hz.

Definition at line 204 of file clk.c.

## ◆ CLK_GetPLLClockFreq()

uint32_t CLK_GetPLLClockFreq | ( | void |  | ) |

Get PLL clock frequency.

Parameters

  None |

Returns
  PLL frequency

This function get PLL frequency. The frequency unit is Hz.

Definition at line 1188 of file clk.c.

## ◆ CLK_GetPMUWKSrc()

uint32_t CLK_GetPMUWKSrc | ( | void |  | ) |

Get power manager wake up source.

Parameters

  [in] | None |

Returns
  None

This function get power manager wake up source.

Definition at line 1146 of file clk.c.

## ◆ CLK_Idle()

void CLK_Idle | ( | void |  | ) |

Enter to Idle mode.

Parameters

  None |

Returns
  None

This function let system enter to Idle mode.
The register write-protection function should be disabled before using this function.

Definition at line 102 of file clk.c.

## ◆ CLK_PowerDown()

void CLK_PowerDown | ( | void |  | ) |

Enter to Power-down mode.

Parameters

  None |

Returns
  None

This function is used to let system enter to Power-down mode.
The register write-protection function should be disabled before using this function.

Definition at line 72 of file clk.c.

## ◆ CLK_SetCoreClock()

uint32_t CLK_SetCoreClock | ( | uint32_t | u32Hclk | ) |

Set HCLK frequency.

Parameters

  [in] | u32Hclk | is HCLK frequency. The range of u32Hclk is running up to 192MHz.

Returns
  HCLK frequency

This function is used to set HCLK frequency. The frequency unit is Hz.
The register write-protection function should be disabled before using this function.

Definition at line 271 of file clk.c.

## ◆ CLK_SetHCLK()

void CLK_SetHCLK | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv
| ) |  |

This function set HCLK clock source and HCLK clock divider.

Parameters

  [in] | u32ClkSrc | is HCLK clock source. Including : CLK_CLKSEL0_HCLKSEL_HXT CLK_CLKSEL0_HCLKSEL_LXT CLK_CLKSEL0_HCLKSEL_PLL CLK_CLKSEL0_HCLKSEL_LIRC CLK_CLKSEL0_HCLKSEL_HIRC
  [in] | u32ClkDiv | is HCLK clock divider. Including : CLK_CLKDIV0_HCLK(x)

Returns
  None

This function set HCLK clock source and HCLK clock divider.
The register write-protection function should be disabled before using this function.

Definition at line 333 of file clk.c.

## ◆ CLK_SetModuleClock()

void CLK_SetModuleClock | ( | uint32_t | u32ModuleIdx,
|  | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv
| ) |  |

This function set selected module clock source and module clock divider.

Parameters

  [in] | u32ModuleIdx | is module index.
  [in] | u32ClkSrc | is module clock source.
  [in] | u32ClkDiv | is module clock divider.

Returns
  None

Valid parameter combinations listed in following table:

Module index | Clock source | Divider
--- | --- | ---
CCAP_MODULE | CLK_CLKSEL0_CCAPSEL_HXT | CLK_CLKDIV3_CCAP(x)
CCAP_MODULE | CLK_CLKSEL0_CCAPSEL_PLL | CLK_CLKDIV3_CCAP(x)
CCAP_MODULE | CLK_CLKSEL0_CCAPSEL_HIRC | CLK_CLKDIV3_CCAP(x)
CCAP_MODULE | CLK_CLKSEL0_CCAPSEL_HCLK | CLK_CLKDIV3_CCAP(x)
SDH0_MODULE | CLK_CLKSEL0_SDH0SEL_HXT | CLK_CLKDIV0_SDH0(x)
SDH0_MODULE | CLK_CLKSEL0_SDH0SEL_PLL | CLK_CLKDIV0_SDH0(x)
SDH0_MODULE | CLK_CLKSEL0_SDH0SEL_HIRC | CLK_CLKDIV0_SDH0(x)
SDH0_MODULE | CLK_CLKSEL0_SDH0SEL_HCLK | CLK_CLKDIV0_SDH0(x)
SDH1_MODULE | CLK_CLKSEL0_SDH1SEL_HXT | CLK_CLKDIV3_SDH1(x)
SDH1_MODULE | CLK_CLKSEL0_SDH1SEL_PLL | CLK_CLKDIV3_SDH1(x)
SDH1_MODULE | CLK_CLKSEL0_SDH1SEL_HIRC | CLK_CLKDIV3_SDH1(x)
SDH1_MODULE | CLK_CLKSEL0_SDH1SEL_HCLK | CLK_CLKDIV3_SDH1(x)
WDT_MODULE | CLK_CLKSEL1_WDTSEL_LXT | x
WDT_MODULE | CLK_CLKSEL1_WDTSEL_LIRC | x
WDT_MODULE | CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x
TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_HXT | x
TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_LXT | x
TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_LIRC | x
TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_HIRC | x
TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_PCLK0 | x
TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_EXT | x
TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_HXT | x
TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_LXT | x
TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_LIRC | x
TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_HIRC | x
TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_PCLK0 | x
TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_EXT | x
TMR2_MODULE | CLK_CLKSEL1_TMR2SEL_HXT | x
TMR2_MODULE | CLK_CLKSEL1_TMR2SEL_LXT | x
TMR2_MODULE | CLK_CLKSEL1_TMR2SEL_LIRC | x
TMR2_MODULE | CLK_CLKSEL1_TMR2SEL_HIRC | x
TMR2_MODULE | CLK_CLKSEL1_TMR2SEL_PCLK1 | x
TMR2_MODULE | CLK_CLKSEL1_TMR2SEL_EXT | x
TMR3_MODULE | CLK_CLKSEL1_TMR3SEL_HXT | x
TMR3_MODULE | CLK_CLKSEL1_TMR3SEL_LXT | x
TMR3_MODULE | CLK_CLKSEL1_TMR3SEL_LIRC | x
TMR3_MODULE | CLK_CLKSEL1_TMR3SEL_HIRC | x
TMR3_MODULE | CLK_CLKSEL1_TMR3SEL_PCLK1 | x
TMR3_MODULE | CLK_CLKSEL1_TMR3SEL_EXT | x
UART0_MODULE | CLK_CLKSEL1_UART0SEL_HXT | CLK_CLKDIV0_UART0(x)
UART0_MODULE | CLK_CLKSEL1_UART0SEL_LXT | CLK_CLKDIV0_UART0(x)
UART0_MODULE | CLK_CLKSEL1_UART0SEL_PLL | CLK_CLKDIV0_UART0(x)
UART0_MODULE | CLK_CLKSEL1_UART0SEL_HIRC | CLK_CLKDIV0_UART0(x)
UART1_MODULE | CLK_CLKSEL1_UART1SEL_HXT | CLK_CLKDIV0_UART1(x)
UART1_MODULE | CLK_CLKSEL1_UART1SEL_LXT | CLK_CLKDIV0_UART1(x)
UART1_MODULE | CLK_CLKSEL1_UART1SEL_PLL | CLK_CLKDIV0_UART1(x)
UART1_MODULE | CLK_CLKSEL1_UART1SEL_HIRC | CLK_CLKDIV0_UART1(x)
CLKO_MODULE | CLK_CLKSEL1_CLKOSEL_HXT | x
CLKO_MODULE | CLK_CLKSEL1_CLKOSEL_LXT | x
CLKO_MODULE | CLK_CLKSEL1_CLKOSEL_HIRC | x
CLKO_MODULE | CLK_CLKSEL1_CLKOSEL_HCLK | x
WWDT_MODULE | CLK_CLKSEL1_WWDTSEL_LIRC | x
WWDT_MODULE | CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x
EPWM0_MODULE | CLK_CLKSEL2_EPWM0SEL_PLL | x
EPWM0_MODULE | CLK_CLKSEL2_EPWM0SEL_PCLK0 | x
EPWM1_MODULE | CLK_CLKSEL2_EPWM1SEL_PLL | x
EPWM1_MODULE | CLK_CLKSEL2_EPWM1SEL_PCLK1 | x
QSPI0_MODULE | CLK_CLKSEL2_QSPI0SEL_HXT | x
QSPI0_MODULE | CLK_CLKSEL2_QSPI0SEL_PLL | x
QSPI0_MODULE | CLK_CLKSEL2_QSPI0SEL_HIRC | x
QSPI0_MODULE | CLK_CLKSEL2_QSPI0SEL_PCLK0 | x
SPI0_MODULE | CLK_CLKSEL2_SPI0SEL_HXT | x
SPI0_MODULE | CLK_CLKSEL2_SPI0SEL_PLL | x
SPI0_MODULE | CLK_CLKSEL2_SPI0SEL_HIRC | x
SPI0_MODULE | CLK_CLKSEL2_SPI0SEL_PCLK1 | x
BPWM0_MODULE | CLK_CLKSEL2_BPWM0SEL_PLL | x
BPWM0_MODULE | CLK_CLKSEL2_BPWM0SEL_PCLK0 | x
BPWM1_MODULE | CLK_CLKSEL2_BPWM1SEL_PLL | x
BPWM1_MODULE | CLK_CLKSEL2_BPWM1SEL_PCLK1 | x
SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_HXT | x
SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_PLL | x
SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_HIRC | x
SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_PCLK0 | x
SPI2_MODULE | CLK_CLKSEL2_SPI2SEL_HXT | x
SPI2_MODULE | CLK_CLKSEL2_SPI2SEL_PLL | x
SPI2_MODULE | CLK_CLKSEL2_SPI2SEL_HIRC | x
SPI2_MODULE | CLK_CLKSEL2_SPI2SEL_PCLK1 | x
SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_HXT | x
SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_PLL | x
SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_HIRC | x
SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_PCLK0 | x
SC0_MODULE | CLK_CLKSEL3_SC0SEL_HXT | CLK_CLKDIV1_SC0(x)
SC0_MODULE | CLK_CLKSEL3_SC0SEL_PLL | CLK_CLKDIV1_SC0(x)
SC0_MODULE | CLK_CLKSEL3_SC0SEL_HIRC | CLK_CLKDIV1_SC0(x)
SC0_MODULE | CLK_CLKSEL3_SC0SEL_PCLK0 | CLK_CLKDIV1_SC0(x)
SC1_MODULE | CLK_CLKSEL3_SC1SEL_HXT | CLK_CLKDIV1_SC1(x)
SC1_MODULE | CLK_CLKSEL3_SC1SEL_PLL | CLK_CLKDIV1_SC1(x)
SC1_MODULE | CLK_CLKSEL3_SC1SEL_HIRC | CLK_CLKDIV1_SC1(x)
SC1_MODULE | CLK_CLKSEL3_SC1SEL_PCLK1 | CLK_CLKDIV1_SC1(x)
SC2_MODULE | CLK_CLKSEL3_SC2SEL_HXT | CLK_CLKDIV1_SC2(x)
SC2_MODULE | CLK_CLKSEL3_SC2SEL_PLL | CLK_CLKDIV1_SC2(x)
SC2_MODULE | CLK_CLKSEL3_SC2SEL_HIRC | CLK_CLKDIV1_SC2(x)
SC2_MODULE | CLK_CLKSEL3_SC2SEL_PCLK0 | CLK_CLKDIV1_SC2(x)
RTC_MODULE | CLK_CLKSEL3_RTCSEL_LXT | x
RTC_MODULE | CLK_CLKSEL3_RTCSEL_LIRC | x
QSPI1_MODULE | CLK_CLKSEL3_QSPI1SEL_HXT | x
QSPI1_MODULE | CLK_CLKSEL3_QSPI1SEL_PLL | x
QSPI1_MODULE | CLK_CLKSEL3_QSPI1SEL_HIRC | x
QSPI1_MODULE | CLK_CLKSEL3_QSPI1SEL_PCLK1 | x
I2S0_MODULE | CLK_CLKSEL3_I2S0SEL_HXT | CLK_CLKDIV2_I2S0(x)
I2S0_MODULE | CLK_CLKSEL3_I2S0SEL_PLL | CLK_CLKDIV2_I2S0(x)
I2S0_MODULE | CLK_CLKSEL3_I2S0SEL_HIRC | CLK_CLKDIV2_I2S0(x)
I2S0_MODULE | CLK_CLKSEL3_I2S0SEL_PCLK0 | CLK_CLKDIV2_I2S0(x)
UART6_MODULE | CLK_CLKSEL3_UART6SEL_HXT | CLK_CLKDIV4_UART6(x)
UART6_MODULE | CLK_CLKSEL3_UART6SEL_LXT | CLK_CLKDIV4_UART6(x)
UART6_MODULE | CLK_CLKSEL3_UART6SEL_PLL | CLK_CLKDIV4_UART6(x)
UART6_MODULE | CLK_CLKSEL3_UART6SEL_HIRC | CLK_CLKDIV4_UART6(x)
UART7_MODULE | CLK_CLKSEL3_UART7SEL_HXT | CLK_CLKDIV4_UART7(x)
UART7_MODULE | CLK_CLKSEL3_UART7SEL_LXT | CLK_CLKDIV4_UART7(x)
UART7_MODULE | CLK_CLKSEL3_UART7SEL_PLL | CLK_CLKDIV4_UART7(x)
UART7_MODULE | CLK_CLKSEL3_UART7SEL_HIRC | CLK_CLKDIV4_UART7(x)
UART2_MODULE | CLK_CLKSEL3_UART2SEL_HXT | CLK_CLKDIV4_UART2(x)
UART2_MODULE | CLK_CLKSEL3_UART2SEL_LXT | CLK_CLKDIV4_UART2(x)
UART2_MODULE | CLK_CLKSEL3_UART2SEL_PLL | CLK_CLKDIV4_UART2(x)
UART2_MODULE | CLK_CLKSEL3_UART2SEL_HIRC | CLK_CLKDIV4_UART2(x)
UART3_MODULE | CLK_CLKSEL3_UART3SEL_HXT | CLK_CLKDIV4_UART3(x)
UART3_MODULE | CLK_CLKSEL3_UART3SEL_LXT | CLK_CLKDIV4_UART3(x)
UART3_MODULE | CLK_CLKSEL3_UART3SEL_PLL | CLK_CLKDIV4_UART3(x)
UART3_MODULE | CLK_CLKSEL3_UART3SEL_HIRC | CLK_CLKDIV4_UART3(x)
UART4_MODULE | CLK_CLKSEL3_UART4SEL_HXT | CLK_CLKDIV4_UART4(x)
UART4_MODULE | CLK_CLKSEL3_UART4SEL_LXT | CLK_CLKDIV4_UART4(x)
UART4_MODULE | CLK_CLKSEL3_UART4SEL_PLL | CLK_CLKDIV4_UART4(x)
UART4_MODULE | CLK_CLKSEL3_UART4SEL_HIRC | CLK_CLKDIV4_UART4(x)
UART5_MODULE | CLK_CLKSEL3_UART5SEL_HXT | CLK_CLKDIV4_UART5(x)
UART5_MODULE | CLK_CLKSEL3_UART5SEL_LXT | CLK_CLKDIV4_UART5(x)
UART5_MODULE | CLK_CLKSEL3_UART5SEL_PLL | CLK_CLKDIV4_UART5(x)
UART5_MODULE | CLK_CLKSEL3_UART5SEL_HIRC | CLK_CLKDIV4_UART5(x)
EADC_MODULE | x | CLK_CLKDIV0_EADC(x)
EADC1_MODULE | x | CLK_CLKDIV2_EADC1(x)
EMAC_MODULE | x | CLK_CLKDIV3_EMAC(x)

Definition at line 503 of file clk.c.

## ◆ CLK_SetPowerDownMode()

void CLK_SetPowerDownMode | ( | uint32_t | u32PDMode | ) |

Power-down mode selected.

Parameters

  [in] | u32PDMode | is power down mode index. Including : CLK_PMUCTL_PDMSEL_PD CLK_PMUCTL_PDMSEL_LLPD CLK_PMUCTL_PDMSEL_FWPD CLK_PMUCTL_PDMSEL_SPD0 CLK_PMUCTL_PDMSEL_SPD1 CLK_PMUCTL_PDMSEL_DPD

Returns
  None

This function is used to set power-down mode.

Note
  Must enable LIRC clock before entering to Standby Power-down Mode

Definition at line 1043 of file clk.c.

## ◆ CLK_SetSysTickClockSrc()

void CLK_SetSysTickClockSrc | ( | uint32_t | u32ClkSrc | ) |

Set SysTick clock source.

Parameters

  [in] | u32ClkSrc | is module clock source. Including: CLK_CLKSEL0_STCLKSEL_HXT CLK_CLKSEL0_STCLKSEL_LXT CLK_CLKSEL0_STCLKSEL_HXT_DIV2 CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

Returns
  None

This function set SysTick clock source.
The register write-protection function should be disabled before using this function.

Definition at line 575 of file clk.c.

## ◆ CLK_SysTickDelay()

__STATIC_INLINE void CLK_SysTickDelay | ( | uint32_t | us | ) |

This function execute delay function.

Parameters

  [in] | us | Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: 72MHz => 233016us, 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...

Returns
  None

Use the SysTick to generate the delay time and the unit is in us. The SysTick clock source is from HCLK, i.e the same as system core clock.

Definition at line 613 of file clk.h.

## ◆ CLK_SysTickLongDelay()

__STATIC_INLINE void CLK_SysTickLongDelay | ( | uint32_t | us | ) |

This function execute long delay function.

Parameters

  [in] | us | Delay time.

Returns
  None

Use the SysTick to generate the long delay time and the UNIT is in us. The SysTick clock source is from HCLK, i.e the same as system core clock. User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.

Definition at line 636 of file clk.h.

## ◆ CLK_WaitClockReady()

uint32_t CLK_WaitClockReady | ( | uint32_t | u32ClkMask | ) |

This function check selected clock source status.

Parameters

  [in] | u32ClkMask | is selected clock source. Including : CLK_STATUS_HXTSTB_Msk CLK_STATUS_LXTSTB_Msk CLK_STATUS_HIRCSTB_Msk CLK_STATUS_LIRCSTB_Msk CLK_STATUS_PLLSTB_Msk

Return values

  0 | clock is not stable
  1 | clock is stable

To wait for clock ready by specified clock source stable flag or timeout (~300ms)

Definition at line 961 of file clk.c.