| M480 BSP V3.05.001 The Board Support Package for M480 Series

hsusbh_reg.h
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1 /**************************************************************************/
9 #ifndef __HSUSBH_REG_H__
10 #define __HSUSBH_REG_H__
11
12 #if defined ( __CC_ARM )
13 #pragma anon_unions
14 #endif
15
26 typedef struct
27 {
28
29
958 __I uint32_t EHCVNR;
959 __I uint32_t EHCSPR;
960 __I uint32_t EHCCPR;
961 __I uint32_t RESERVE0[5];
964 __IO uint32_t UCMDR;
965 __IO uint32_t USTSR;
966 __IO uint32_t UIENR;
967 __IO uint32_t UFINDR;
968 __I uint32_t RESERVE1[1];
971 __IO uint32_t UPFLBAR;
972 __IO uint32_t UCALAR;
973 __IO uint32_t UASSTR;
974 __I uint32_t RESERVE2[8];
977 __IO uint32_t UCFGR;
978 __IO uint32_t UPSCR[2];
979 __I uint32_t RESERVE3[22];
982 __IO uint32_t USBPCR0;
983 __IO uint32_t USBPCR1;
985 } HSUSBH_T;
986
992 #define HSUSBH_EHCVNR_CRLEN_Pos (0)
993 #define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos)
995 #define HSUSBH_EHCVNR_VERSION_Pos (16)
996 #define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos)
998 #define HSUSBH_EHCSPR_N_PORTS_Pos (0)
999 #define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos)
1001 #define HSUSBH_EHCSPR_PPC_Pos (4)
1002 #define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos)
1004 #define HSUSBH_EHCSPR_N_PCC_Pos (8)
1005 #define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos)
1007 #define HSUSBH_EHCSPR_N_CC_Pos (12)
1008 #define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos)
1010 #define HSUSBH_EHCCPR_AC64_Pos (0)
1011 #define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos)
1013 #define HSUSBH_EHCCPR_PFLF_Pos (1)
1014 #define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos)
1016 #define HSUSBH_EHCCPR_ASPC_Pos (2)
1017 #define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos)
1019 #define HSUSBH_EHCCPR_IST_Pos (4)
1020 #define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos)
1022 #define HSUSBH_EHCCPR_EECP_Pos (8)
1023 #define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos)
1025 #define HSUSBH_UCMDR_RUN_Pos (0)
1026 #define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos)
1028 #define HSUSBH_UCMDR_HCRST_Pos (1)
1029 #define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos)
1031 #define HSUSBH_UCMDR_FLSZ_Pos (2)
1032 #define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos)
1034 #define HSUSBH_UCMDR_PSEN_Pos (4)
1035 #define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos)
1037 #define HSUSBH_UCMDR_ASEN_Pos (5)
1038 #define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos)
1040 #define HSUSBH_UCMDR_IAAD_Pos (6)
1041 #define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos)
1043 #define HSUSBH_UCMDR_ITC_Pos (16)
1044 #define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos)
1046 #define HSUSBH_USTSR_USBINT_Pos (0)
1047 #define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos)
1049 #define HSUSBH_USTSR_UERRINT_Pos (1)
1050 #define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos)
1052 #define HSUSBH_USTSR_PCD_Pos (2)
1053 #define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos)
1055 #define HSUSBH_USTSR_FLR_Pos (3)
1056 #define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos)
1058 #define HSUSBH_USTSR_HSERR_Pos (4)
1059 #define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos)
1061 #define HSUSBH_USTSR_IAA_Pos (5)
1062 #define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos)
1064 #define HSUSBH_USTSR_HCHalted_Pos (12)
1065 #define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos)
1067 #define HSUSBH_USTSR_RECLA_Pos (13)
1068 #define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos)
1070 #define HSUSBH_USTSR_PSS_Pos (14)
1071 #define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos)
1073 #define HSUSBH_USTSR_ASS_Pos (15)
1074 #define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos)
1076 #define HSUSBH_UIENR_USBIEN_Pos (0)
1077 #define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos)
1079 #define HSUSBH_UIENR_UERRIEN_Pos (1)
1080 #define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos)
1082 #define HSUSBH_UIENR_PCIEN_Pos (2)
1083 #define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos)
1085 #define HSUSBH_UIENR_FLREN_Pos (3)
1086 #define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos)
1088 #define HSUSBH_UIENR_HSERREN_Pos (4)
1089 #define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos)
1091 #define HSUSBH_UIENR_IAAEN_Pos (5)
1092 #define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos)
1094 #define HSUSBH_UFINDR_FI_Pos (0)
1095 #define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos)
1097 #define HSUSBH_UPFLBAR_BADDR_Pos (12)
1098 #define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos)
1100 #define HSUSBH_UCALAR_LPL_Pos (5)
1101 #define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos)
1103 #define HSUSBH_UASSTR_ASSTMR_Pos (0)
1104 #define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos)
1106 #define HSUSBH_UCFGR_CF_Pos (0)
1107 #define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos)
1109 #define HSUSBH_UPSCR_CCS_Pos (0)
1110 #define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos)
1112 #define HSUSBH_UPSCR_CSC_Pos (1)
1113 #define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos)
1115 #define HSUSBH_UPSCR_PE_Pos (2)
1116 #define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos)
1118 #define HSUSBH_UPSCR_PEC_Pos (3)
1119 #define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos)
1121 #define HSUSBH_UPSCR_OCA_Pos (4)
1122 #define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos)
1124 #define HSUSBH_UPSCR_OCC_Pos (5)
1125 #define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos)
1127 #define HSUSBH_UPSCR_FPR_Pos (6)
1128 #define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos)
1130 #define HSUSBH_UPSCR_SUSPEND_Pos (7)
1131 #define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos)
1133 #define HSUSBH_UPSCR_PRST_Pos (8)
1134 #define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos)
1136 #define HSUSBH_UPSCR_LSTS_Pos (10)
1137 #define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos)
1139 #define HSUSBH_UPSCR_PP_Pos (12)
1140 #define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos)
1142 #define HSUSBH_UPSCR_PO_Pos (13)
1143 #define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos)
1145 #define HSUSBH_UPSCR_PTC_Pos (16)
1146 #define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos)
1148 #define HSUSBH_USBPCR0_SUSPEND_Pos (8)
1149 #define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos)
1151 #define HSUSBH_USBPCR0_CLKVALID_Pos (11)
1152 #define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos)
1154 #define HSUSBH_USBPCR1_SUSPEND_Pos (8)
1155 #define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /* HSUSBH_CONST */
1158 /* end of HSUSBH register group */ /* end of REGISTER group */
1160
1161 #if defined ( __CC_ARM )
1162 #pragma no_anon_unions
1163 #endif
1164
1165 #endif /* __HSUSBH_REG_H__ */
HSUSBH_T::EHCVNR
__I uint32_t EHCVNR
Definition: hsusbh_reg.h:958
HSUSBH_T::UIENR
__IO uint32_t UIENR
Definition: hsusbh_reg.h:966
HSUSBH_T::UCMDR
__IO uint32_t UCMDR
Definition: hsusbh_reg.h:964
HSUSBH_T::UASSTR
__IO uint32_t UASSTR
Definition: hsusbh_reg.h:973
HSUSBH_T::UCFGR
__IO uint32_t UCFGR
Definition: hsusbh_reg.h:977
HSUSBH_T
Definition: hsusbh_reg.h:26
HSUSBH_T::USBPCR0
__IO uint32_t USBPCR0
Definition: hsusbh_reg.h:982
HSUSBH_T::UFINDR
__IO uint32_t UFINDR
Definition: hsusbh_reg.h:967
HSUSBH_T::UCALAR
__IO uint32_t UCALAR
Definition: hsusbh_reg.h:972
HSUSBH_T::EHCCPR
__I uint32_t EHCCPR
Definition: hsusbh_reg.h:960
HSUSBH_T::EHCSPR
__I uint32_t EHCSPR
Definition: hsusbh_reg.h:959
HSUSBH_T::USTSR
__IO uint32_t USTSR
Definition: hsusbh_reg.h:965
HSUSBH_T::USBPCR1
__IO uint32_t USBPCR1
Definition: hsusbh_reg.h:983
HSUSBH_T::UPFLBAR
__IO uint32_t UPFLBAR
Definition: hsusbh_reg.h:971