| M480 BSP V3.05.001 The Board Support Package for M480 Series

usci_uart.c
Go to the documentation of this file.
1 /**************************************************************************/
10 #include <stdio.h>
11 #include "NuMicro.h"
12
45 void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask)
46 {
47
48 if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */
49 {
50 uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk;
51 }
52
53 if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */
54 {
55 uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk);
56 }
57
58 if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */
59 {
60 uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk;
61 }
62
63 if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */
64 {
65 uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk;
66 }
67
68 if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */
69 {
70 uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk;
71 }
72
73 if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */
74 {
75 uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk;
76 }
77
78 if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */
79 {
80 uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk;
81 }
82
83 }
84
105 uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask)
106 {
107 uint32_t u32IntFlag = 0ul;
108 uint32_t u32Tmp1, u32Tmp2;
109
110 /* Check Auto-baud Rate Interrupt Flag */
111 u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK);
112 u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk);
113 if(u32Tmp1 && u32Tmp2)
114 {
115 u32IntFlag |= UUART_ABR_INT_MASK;
116 }
117
118 /* Check Receive Line Status Interrupt Flag */
119 u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK);
120 u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk));
121 if(u32Tmp1 && u32Tmp2)
122 {
123 u32IntFlag |= UUART_RLS_INT_MASK;
124 }
125
126 /* Check Receive Buffer Over-run Error Interrupt Flag */
127 u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK);
128 u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk);
129 if(u32Tmp1 && u32Tmp2)
130 {
131 u32IntFlag |= UUART_BUF_RXOV_INT_MASK;
132 }
133
134 /* Check Transmit Start Interrupt Flag */
135 u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK);
136 u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk);
137 if(u32Tmp1 && u32Tmp2)
138 {
139 u32IntFlag |= UUART_TXST_INT_MASK;
140 }
141
142 /* Check Transmit End Interrupt Flag */
143 u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK);
144 u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk);
145 if(u32Tmp1 && u32Tmp2)
146 {
147 u32IntFlag |= UUART_TXEND_INT_MASK;
148 }
149
150 /* Check Receive Start Interrupt Flag */
151 u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK);
152 u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk);
153 if(u32Tmp1 && u32Tmp2)
154 {
155 u32IntFlag |= UUART_RXST_INT_MASK;
156 }
157
158 /* Check Receive End Interrupt Flag */
159 u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK);
160 u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk);
161 if(u32Tmp1 && u32Tmp2)
162 {
163 u32IntFlag |= UUART_RXEND_INT_MASK;
164 }
165
166 return u32IntFlag;
167
168 }
169
170
180 void UUART_Close(UUART_T* uuart)
181 {
182 uuart->CTL = 0ul;
183 }
184
185
205 void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask)
206 {
207
208 /* Disable Auto-baud rate interrupt flag */
209 if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
210 {
211 uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk;
212 }
213
214 /* Disable receive line status interrupt flag */
215 if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
216 {
217 uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk;
218 }
219
220 /* Disable RX overrun interrupt flag */
221 if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
222 {
223 uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk;
224 }
225
226 /* Disable TX start interrupt flag */
227 if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
228 {
229 uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk;
230 }
231
232 /* Disable TX end interrupt flag */
233 if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
234 {
235 uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk;
236 }
237
238 /* Disable RX start interrupt flag */
239 if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
240 {
241 uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk;
242 }
243
244 /* Disable RX end interrupt flag */
245 if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
246 {
247 uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk;
248 }
249 }
250
251
271 void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask)
272 {
273 /* Enable Auto-baud rate interrupt flag */
274 if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
275 {
276 uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk;
277 }
278
279 /* Enable receive line status interrupt flag */
280 if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
281 {
282 uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk;
283 }
284
285 /* Enable RX overrun interrupt flag */
286 if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
287 {
288 uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk;
289 }
290
291 /* Enable TX start interrupt flag */
292 if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
293 {
294 uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk;
295 }
296
297 /* Enable TX end interrupt flag */
298 if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
299 {
300 uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk;
301 }
302
303 /* Enable RX start interrupt flag */
304 if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
305 {
306 uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk;
307 }
308
309 /* Enable RX end interrupt flag */
310 if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
311 {
312 uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk;
313 }
314 }
315
316
327 uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate)
328 {
329 uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;
330 uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
331 uint32_t u32Div;
332
333 /* Get PCLK frequency */
334 if( uuart == UUART0)
335 {
336 u32PCLKFreq = CLK_GetPCLK0Freq();
337 }
338 else
339 {
340 u32PCLKFreq = CLK_GetPCLK1Freq();
341 }
342
343 u32Div = u32PCLKFreq / u32baudrate;
344 u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;
345 u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul));
346
347 if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;
348
349 u32Tmp = 0x400ul * 0x10ul;
350 for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)
351 {
352 if(u32Div <= (u32Tmp * u32PDSCnt)) break;
353 }
354
355 if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;
356
357 u32Div = u32Div / u32PDSCnt;
358
359 /* Find best solution */
360 u32Min = (uint32_t) - 1;
361 u32MinDSCnt = 0ul;
362 u32MinClkDiv = 0ul;
363 u32Tmp = 0ul;
364
365 for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */
366 {
367
368 u32ClkDiv = u32Div / u32DSCnt;
369
370 if(u32ClkDiv > 0x400ul)
371 {
372 u32ClkDiv = 0x400ul;
373 u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
374 u32Tmp2 = u32Tmp + 1ul;
375 }
376 else
377 {
378 u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
379 u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div;
380 }
381
382 if(u32Tmp >= u32Tmp2)
383 {
384 u32ClkDiv = u32ClkDiv + 1ul;
385 }
386 else u32Tmp2 = u32Tmp;
387
388 if(u32Tmp2 < u32Min)
389 {
390 u32Min = u32Tmp2;
391 u32MinDSCnt = u32DSCnt;
392 u32MinClkDiv = u32ClkDiv;
393
394 /* Break when get good results */
395 if(u32Min == 0ul)
396 {
397 break;
398 }
399 }
400 }
401
402 /* Enable USCI_UART protocol */
403 uuart->CTL &= ~UUART_CTL_FUNMODE_Msk;
404 uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos;
405
406 /* Set USCI_UART line configuration */
407 uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk;
408 uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */
409
410 /* Set USCI_UART baud rate */
411 uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) |
412 ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) |
413 ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos);
414
415 uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk;
416
417 return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv);
418 }
419
420
432 uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
433 {
434 uint32_t u32Count, u32delayno;
435
436 for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
437 {
438 u32delayno = 0ul;
439
440 while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */
441 {
442 u32delayno++;
443 if(u32delayno >= 0x40000000ul)
444 {
445 break;
446 }
447 }
448
449 if(u32delayno >= 0x40000000ul)
450 {
451 break;
452 }
453
454 pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */
455 }
456
457 return u32Count;
458
459 }
460
461
485 uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
486 {
487 uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;
488 uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
489 uint32_t u32Div;
490
491 /* Get PCLK frequency */
492 if(uuart == UUART0)
493 {
494 u32PCLKFreq = CLK_GetPCLK0Freq();
495 }
496 else /* UUART1 */
497 {
498 u32PCLKFreq = CLK_GetPCLK1Freq();
499 }
500
501 if(u32baudrate != 0ul)
502 {
503 u32Div = u32PCLKFreq / u32baudrate;
504 u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;
505 u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul));
506
507 if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;
508
509 u32Tmp = 0x400ul * 0x10ul;
510 for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)
511 {
512 if(u32Div <= (u32Tmp * u32PDSCnt)) break;
513 }
514
515 if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;
516
517 u32Div = u32Div / u32PDSCnt;
518
519 /* Find best solution */
520 u32Min = (uint32_t) - 1;
521 u32MinDSCnt = 0ul;
522 u32MinClkDiv = 0ul;
523
524 for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */
525 {
526 u32ClkDiv = u32Div / u32DSCnt;
527
528 if(u32ClkDiv > 0x400ul)
529 {
530 u32ClkDiv = 0x400ul;
531 u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
532 u32Tmp2 = u32Tmp + 1ul;
533 }
534 else
535 {
536 u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
537 u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div;
538 }
539
540 if(u32Tmp >= u32Tmp2)
541 {
542 u32ClkDiv = u32ClkDiv + 1ul;
543 }
544 else u32Tmp2 = u32Tmp;
545
546 if(u32Tmp2 < u32Min)
547 {
548 u32Min = u32Tmp2;
549 u32MinDSCnt = u32DSCnt;
550 u32MinClkDiv = u32ClkDiv;
551
552 /* Break when get good results */
553 if(u32Min == 0ul)
554 {
555 break;
556 }
557 }
558 }
559
560 /* Set USCI_UART baud rate */
561 uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) |
562 ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) |
563 ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos);
564 }
565 else
566 {
567 u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul;
568 u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul;
569 u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul;
570 }
571
572 /* Set USCI_UART line configuration */
573 uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width;
574 uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk |
575 UUART_PROTCTL_PARITYEN_Msk)) | u32parity;
576 uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk ) | u32stop_bits;
577
578 return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv);
579 }
580
581
593 uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
594 {
595 uint32_t u32Count, u32delayno;
596
597 for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
598 {
599 u32delayno = 0ul;
600 while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */
601 {
602 u32delayno++;
603 if(u32delayno >= 0x40000000ul)
604 {
605 break;
606 }
607 }
608
609 if(u32delayno >= 0x40000000ul)
610 {
611 break;
612 }
613
614 uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */
615 }
616
617 return u32Count;
618
619 }
620
621
634 void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode)
635 {
636 uuart->PROTCTL |= u32WakeupMode;
637 uuart->WKCTL |= UUART_WKCTL_WKEN_Msk;
638 }
639
640
650 void UUART_DisableWakeup(UUART_T* uuart)
651 {
652 uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk|UUART_PROTCTL_CTSWKEN_Msk);
653 uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk;
654 }
655
665 void UUART_EnableFlowCtrl(UUART_T* uuart)
666 {
667 /* Set RTS signal is low level active */
668 uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk;
669
670 /* Set CTS signal is low level active */
671 uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk;
672
673 /* Enable CTS and RTS auto flow control function */
674 uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk;
675 }
676
686 void UUART_DisableFlowCtrl(UUART_T* uuart)
687 {
688 /* Disable CTS and RTS auto flow control function */
689 uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk);
690 }
691
692
693
694 /* end of group USCI_UART_EXPORTED_FUNCTIONS */
696 /* end of group USCI_UART_Driver */
698 /* end of group Standard_Driver */
700
701 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
702
UUART_T::WKCTL
__IO uint32_t WKCTL
Definition: uuart_reg.h:962
UUART_PROTCTL_STOPB_Msk
#define UUART_PROTCTL_STOPB_Msk
Definition: uuart_reg.h:1102
UUART_INTEN_RXSTIEN_Msk
#define UUART_INTEN_RXSTIEN_Msk
Definition: uuart_reg.h:985
UUART_BUFSTS_RXEMPTY_Msk
#define UUART_BUFSTS_RXEMPTY_Msk
Definition: uuart_reg.h:1066
UUART_PROTSTS_TXENDIF_Msk
#define UUART_PROTSTS_TXENDIF_Msk
Definition: uuart_reg.h:1153
UUART_T::BUFCTL
__IO uint32_t BUFCTL
Definition: uuart_reg.h:956
UUART_WORD_LEN_8
#define UUART_WORD_LEN_8
Definition: usci_uart.h:36
UUART_Read
uint32_t UUART_Read(UUART_T *uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
Read USCI_UART data.
Definition: usci_uart.c:432
UUART_RLS_INT_MASK
#define UUART_RLS_INT_MASK
Definition: usci_uart.h:53
UUART_BRGEN_DSCNT_Pos
#define UUART_BRGEN_DSCNT_Pos
Definition: uuart_reg.h:1008
UUART_TXST_INT_MASK
#define UUART_TXST_INT_MASK
Definition: usci_uart.h:55
UUART_LINECTL_CTLOINV_Msk
#define UUART_LINECTL_CTLOINV_Msk
Definition: uuart_reg.h:1039
UUART_DisableFlowCtrl
void UUART_DisableFlowCtrl(UUART_T *uuart)
Disable USCI_UART auto flow control.
Definition: usci_uart.c:686
UUART_T
Definition: uuart_reg.h:26
UUART_DisableInt
void UUART_DisableInt(UUART_T *uuart, uint32_t u32Mask)
Disable interrupt function.
Definition: usci_uart.c:205
UUART_PROTSTS_FRMERR_Msk
#define UUART_PROTSTS_FRMERR_Msk
Definition: uuart_reg.h:1165
UUART_T::LINECTL
__IO uint32_t LINECTL
Definition: uuart_reg.h:953
UUART_BUFCTL_RXOVIEN_Msk
#define UUART_BUFCTL_RXOVIEN_Msk
Definition: uuart_reg.h:1054
UUART_TXEND_INT_MASK
#define UUART_TXEND_INT_MASK
Definition: usci_uart.h:56
UUART_Close
void UUART_Close(UUART_T *uuart)
Disable USCI_UART function mode.
Definition: usci_uart.c:180
UUART_EnableWakeup
void UUART_EnableWakeup(UUART_T *uuart, uint32_t u32WakeupMode)
Enable USCI_UART Wake-up Function.
Definition: usci_uart.c:634
UUART_T::BRGEN
__IO uint32_t BRGEN
Definition: uuart_reg.h:940
UUART_RXEND_INT_MASK
#define UUART_RXEND_INT_MASK
Definition: usci_uart.h:58
UUART_Open
uint32_t UUART_Open(UUART_T *uuart, uint32_t u32baudrate)
Open and set USCI_UART function.
Definition: usci_uart.c:327
UUART_PROTCTL_PARITYEN_Msk
#define UUART_PROTCTL_PARITYEN_Msk
Definition: uuart_reg.h:1105
NuMicro.h
NuMicro peripheral access layer header file.
UUART_T::PROTCTL
__IO uint32_t PROTCTL
Definition: uuart_reg.h:964
UUART0
#define UUART0
Definition: M480.h:456
UUART_PROTIEN_ABRIEN_Msk
#define UUART_PROTIEN_ABRIEN_Msk
Definition: uuart_reg.h:1144
UUART_BUFSTS_TXEMPTY_Msk
#define UUART_BUFSTS_TXEMPTY_Msk
Definition: uuart_reg.h:1075
UUART_PROTSTS_PARITYERR_Msk
#define UUART_PROTSTS_PARITYERR_Msk
Definition: uuart_reg.h:1162
UUART_PROTSTS_BREAK_Msk
#define UUART_PROTSTS_BREAK_Msk
Definition: uuart_reg.h:1168
UUART_PROTCTL_PROTEN_Msk
#define UUART_PROTCTL_PROTEN_Msk
Definition: uuart_reg.h:1141
UUART_T::PROTSTS
__IO uint32_t PROTSTS
Definition: uuart_reg.h:966
UUART_BUF_RXOV_INT_MASK
#define UUART_BUF_RXOV_INT_MASK
Definition: usci_uart.h:54
UUART_PROTCTL_RTSAUTOEN_Msk
#define UUART_PROTCTL_RTSAUTOEN_Msk
Definition: uuart_reg.h:1111
CLK_GetPCLK1Freq
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:204
UUART_BRGEN_PDSCNT_Pos
#define UUART_BRGEN_PDSCNT_Pos
Definition: uuart_reg.h:1005
CLK_GetPCLK0Freq
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:164
UUART_PROTCTL_CTSAUTOEN_Msk
#define UUART_PROTCTL_CTSAUTOEN_Msk
Definition: uuart_reg.h:1114
UUART_T::DATIN0
__IO uint32_t DATIN0
Definition: uuart_reg.h:944
UUART_WKCTL_WKEN_Msk
#define UUART_WKCTL_WKEN_Msk
Definition: uuart_reg.h:1093
UUART_ABR_INT_MASK
#define UUART_ABR_INT_MASK
Definition: usci_uart.h:52
UUART_DATIN0_EDGEDET_Pos
#define UUART_DATIN0_EDGEDET_Pos
Definition: uuart_reg.h:1020
UUART_BRGEN_DSCNT_Msk
#define UUART_BRGEN_DSCNT_Msk
Definition: uuart_reg.h:1009
UUART_PROTIEN_RLSIEN_Msk
#define UUART_PROTIEN_RLSIEN_Msk
Definition: uuart_reg.h:1147
UUART_EnableInt
void UUART_EnableInt(UUART_T *uuart, uint32_t u32Mask)
Enable interrupt function.
Definition: usci_uart.c:271
UUART_GetIntFlag
uint32_t UUART_GetIntFlag(UUART_T *uuart, uint32_t u32Mask)
Get USCI_UART specified interrupt flag.
Definition: usci_uart.c:105
UUART_BUFSTS_RXOVIF_Msk
#define UUART_BUFSTS_RXOVIF_Msk
Definition: uuart_reg.h:1072
UUART_CTLIN0_ININV_Msk
#define UUART_CTLIN0_ININV_Msk
Definition: uuart_reg.h:1027
UUART_PROTCTL_STICKEN_Msk
#define UUART_PROTCTL_STICKEN_Msk
Definition: uuart_reg.h:1135
UUART_BRGEN_CLKDIV_Pos
#define UUART_BRGEN_CLKDIV_Pos
Definition: uuart_reg.h:1011
UUART_CTL_FUNMODE_Pos
#define UUART_CTL_FUNMODE_Pos
Definition: uuart_reg.h:975
UUART_PROTSTS_TXSTIF_Msk
#define UUART_PROTSTS_TXSTIF_Msk
Definition: uuart_reg.h:1150
UUART_T::CTLIN0
__IO uint32_t CTLIN0
Definition: uuart_reg.h:948
UUART_PROTSTS_ABRDETIF_Msk
#define UUART_PROTSTS_ABRDETIF_Msk
Definition: uuart_reg.h:1171
UUART_DisableWakeup
void UUART_DisableWakeup(UUART_T *uuart)
Disable USCI_UART Wake-up Function.
Definition: usci_uart.c:650
UUART_SetLine_Config
uint32_t UUART_SetLine_Config(UUART_T *uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
Set USCI_UART line configuration.
Definition: usci_uart.c:485
UUART_BRGEN_PDSCNT_Msk
#define UUART_BRGEN_PDSCNT_Msk
Definition: uuart_reg.h:1006
UUART_Write
uint32_t UUART_Write(UUART_T *uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
Write USCI_UART data.
Definition: usci_uart.c:593
UUART_T::TXDAT
__IO uint32_t TXDAT
Definition: uuart_reg.h:954
UUART_INTEN_RXENDIEN_Msk
#define UUART_INTEN_RXENDIEN_Msk
Definition: uuart_reg.h:988
UUART_BRGEN_CLKDIV_Msk
#define UUART_BRGEN_CLKDIV_Msk
Definition: uuart_reg.h:1012
UUART_PROTCTL_EVENPARITY_Msk
#define UUART_PROTCTL_EVENPARITY_Msk
Definition: uuart_reg.h:1108
UUART_PROTCTL_CTSWKEN_Msk
#define UUART_PROTCTL_CTSWKEN_Msk
Definition: uuart_reg.h:1126
UUART_ClearIntFlag
void UUART_ClearIntFlag(UUART_T *uuart, uint32_t u32Mask)
Clear USCI_UART specified interrupt flag.
Definition: usci_uart.c:45
UUART_T::CTL
__IO uint32_t CTL
Definition: uuart_reg.h:938
UUART_T::BUFSTS
__IO uint32_t BUFSTS
Definition: uuart_reg.h:957
UUART_INTEN_TXSTIEN_Msk
#define UUART_INTEN_TXSTIEN_Msk
Definition: uuart_reg.h:979
UUART_PROTCTL_DATWKEN_Msk
#define UUART_PROTCTL_DATWKEN_Msk
Definition: uuart_reg.h:1123
UUART_INTEN_TXENDIEN_Msk
#define UUART_INTEN_TXENDIEN_Msk
Definition: uuart_reg.h:982
UUART_PROTSTS_RXENDIF_Msk
#define UUART_PROTSTS_RXENDIF_Msk
Definition: uuart_reg.h:1159
UUART_T::INTEN
__IO uint32_t INTEN
Definition: uuart_reg.h:939
UUART_T::RXDAT
__IO uint32_t RXDAT
Definition: uuart_reg.h:955
UUART_T::PROTIEN
__IO uint32_t PROTIEN
Definition: uuart_reg.h:965
UUART_PROTSTS_RXSTIF_Msk
#define UUART_PROTSTS_RXSTIF_Msk
Definition: uuart_reg.h:1156
UUART_LINECTL_DWIDTH_Msk
#define UUART_LINECTL_DWIDTH_Msk
Definition: uuart_reg.h:1042
UUART_EnableFlowCtrl
void UUART_EnableFlowCtrl(UUART_T *uuart)
Enable USCI_UART auto flow control.
Definition: usci_uart.c:665
UUART_RXST_INT_MASK
#define UUART_RXST_INT_MASK
Definition: usci_uart.h:57
UUART_CTL_FUNMODE_Msk
#define UUART_CTL_FUNMODE_Msk
Definition: uuart_reg.h:976
UUART_LINECTL_LSB_Msk
#define UUART_LINECTL_LSB_Msk
Definition: uuart_reg.h:1033