| M480 BSP V3.05.001 The Board Support Package for M480 Series

spim_reg.h
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1 /**************************************************************************/
9 #ifndef __SPIM_REG_H__
10 #define __SPIM_REG_H__
11
12 #if defined ( __CC_ARM )
13 #pragma anon_unions
14 #endif
15
26 typedef struct
27 {
28
29
862 __IO uint32_t CTL0;
863 __IO uint32_t CTL1;
864 __I uint32_t RESERVE0[1];
867 __IO uint32_t RXCLKDLY;
868 __I uint32_t RX[4];
869 __IO uint32_t TX[4];
870 __IO uint32_t SRAMADDR;
871 __IO uint32_t DMACNT;
872 __IO uint32_t FADDR;
873 __O uint32_t KEY1;
874 __O uint32_t KEY2;
875 __IO uint32_t DMMCTL;
876 __IO uint32_t CTL2;
878 } SPIM_T;
879
885 #define SPIM_CTL0_CIPHOFF_Pos (0)
886 #define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos)
888 #define SPIM_CTL0_BALEN_Pos (2)
889 #define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos)
891 #define SPIM_CTL0_B4ADDREN_Pos (5)
892 #define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos)
894 #define SPIM_CTL0_IEN_Pos (6)
895 #define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos)
897 #define SPIM_CTL0_IF_Pos (7)
898 #define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos)
900 #define SPIM_CTL0_DWIDTH_Pos (8)
901 #define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos)
903 #define SPIM_CTL0_BURSTNUM_Pos (13)
904 #define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos)
906 #define SPIM_CTL0_QDIODIR_Pos (15)
907 #define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos)
909 #define SPIM_CTL0_SUSPITV_Pos (16)
910 #define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos)
912 #define SPIM_CTL0_BITMODE_Pos (20)
913 #define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos)
915 #define SPIM_CTL0_OPMODE_Pos (22)
916 #define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos)
918 #define SPIM_CTL0_CMDCODE_Pos (24)
919 #define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos)
921 #define SPIM_CTL1_SPIMEN_Pos (0)
922 #define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos)
924 #define SPIM_CTL1_CACHEOFF_Pos (1)
925 #define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos)
927 #define SPIM_CTL1_CCMEN_Pos (2)
928 #define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos)
930 #define SPIM_CTL1_CDINVAL_Pos (3)
931 #define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos)
933 #define SPIM_CTL1_SS_Pos (4)
934 #define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos)
936 #define SPIM_CTL1_SSACTPOL_Pos (5)
937 #define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos)
939 #define SPIM_CTL1_IDLETIME_Pos (8)
940 #define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos)
942 #define SPIM_CTL1_DIVIDER_Pos (16)
943 #define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos)
945 #define SPIM_RXCLKDLY_DWDELSEL_Pos (0)
946 #define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos)
948 #define SPIM_RXCLKDLY_RDDLYSEL_Pos (16)
949 #define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos)
951 #define SPIM_RXCLKDLY_RDEDGE_Pos (20)
952 #define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos)
954 #define SPIM_RX_RXDAT_Pos (0)
955 #define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos)
957 #define SPIM_TX_TXDAT_Pos (0)
958 #define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos)
960 #define SPIM_SRAMADDR_ADDR_Pos (0)
961 #define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos)
963 #define SPIM_DMACNT_DMACNT_Pos (0)
964 #define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos)
966 #define SPIM_FADDR_ADDR_Pos (0)
967 #define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos)
969 #define SPIM_KEY1_KEY1_Pos (0)
970 #define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos)
972 #define SPIM_KEY2_KEY2_Pos (0)
973 #define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos)
975 #define SPIM_DMMCTL_CRMDAT_Pos (8)
976 #define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos)
978 #define SPIM_DMMCTL_DESELTIM_Pos (16)
979 #define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos)
981 #define SPIM_DMMCTL_BWEN_Pos (24)
982 #define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos)
984 #define SPIM_DMMCTL_CREN_Pos (25)
985 #define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos)
987 #define SPIM_DMMCTL_UACTSCLK_Pos (26)
988 #define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos)
990 #define SPIM_DMMCTL_ACTSCLKT_Pos (28)
991 #define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos)
993 #define SPIM_CTL2_USETEN_Pos (16)
994 #define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos)
996 #define SPIM_CTL2_DTRMPOFF_Pos (20)
997 #define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos)
999 #define SPIM_CTL2_DCNUM_Pos (24)
1000 #define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /* SPIM_CONST */
1003 /* end of SPIM register group */ /* end of REGISTER group */
1005
1006 #if defined ( __CC_ARM )
1007 #pragma no_anon_unions
1008 #endif
1009
1010 #endif /* __SPIM_REG_H__ */
SPIM_T
Definition: spim_reg.h:26
SPIM_T::CTL0
__IO uint32_t CTL0
Definition: spim_reg.h:862
SPIM_T::CTL2
__IO uint32_t CTL2
Definition: spim_reg.h:876
SPIM_T::SRAMADDR
__IO uint32_t SRAMADDR
Definition: spim_reg.h:870
SPIM_T::DMACNT
__IO uint32_t DMACNT
Definition: spim_reg.h:871
SPIM_T::RXCLKDLY
__IO uint32_t RXCLKDLY
Definition: spim_reg.h:867
SPIM_T::CTL1
__IO uint32_t CTL1
Definition: spim_reg.h:863
SPIM_T::FADDR
__IO uint32_t FADDR
Definition: spim_reg.h:872
SPIM_T::KEY1
__O uint32_t KEY1
Definition: spim_reg.h:873
SPIM_T::KEY2
__O uint32_t KEY2
Definition: spim_reg.h:874
SPIM_T::DMMCTL
__IO uint32_t DMMCTL
Definition: spim_reg.h:875