| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
SYS_T Struct Reference
Control Register

`#include <sys_reg.h>`

## Data Fields
__I uint32_t | PDID
__IO uint32_t | RSTSTS
__IO uint32_t | IPRST0
__IO uint32_t | IPRST1
__IO uint32_t | IPRST2
__IO uint32_t | BODCTL
__IO uint32_t | IVSCTL
__IO uint32_t | PORCTL
__IO uint32_t | VREFCTL
__IO uint32_t | USBPHY
__IO uint32_t | GPA_MFPL
__IO uint32_t | GPA_MFPH
__IO uint32_t | GPB_MFPL
__IO uint32_t | GPB_MFPH
__IO uint32_t | GPC_MFPL
__IO uint32_t | GPC_MFPH
__IO uint32_t | GPD_MFPL
__IO uint32_t | GPD_MFPH
__IO uint32_t | GPE_MFPL
__IO uint32_t | GPE_MFPH
__IO uint32_t | GPF_MFPL
__IO uint32_t | GPF_MFPH
__IO uint32_t | GPG_MFPL
__IO uint32_t | GPG_MFPH
__IO uint32_t | GPH_MFPL
__IO uint32_t | GPH_MFPH
__IO uint32_t | GPA_MFOS
__IO uint32_t | GPB_MFOS
__IO uint32_t | GPC_MFOS
__IO uint32_t | GPD_MFOS
__IO uint32_t | GPE_MFOS
__IO uint32_t | GPF_MFOS
__IO uint32_t | GPG_MFOS
__IO uint32_t | GPH_MFOS
__IO uint32_t | SRAM_INTCTL
__IO uint32_t | SRAM_STATUS
__I uint32_t | SRAM_ERRADDR
__IO uint32_t | SRAM_BISTCTL
__I uint32_t | SRAM_BISTSTS
__IO uint32_t | HIRCTCTL
__IO uint32_t | HIRCTIEN
__IO uint32_t | HIRCTISTS
__IO uint32_t | IRCTCTL
__IO uint32_t | IRCTIEN
__IO uint32_t | IRCTISTS
__IO uint32_t | REGLCTL
__IO uint32_t | PORDISAN
__I uint32_t | CSERVER
__IO uint32_t | PLCTL
__I uint32_t | PLSTS
__IO uint32_t | AHBMCTL

## Detailed Description

    @addtogroup SYS System Manger Controller(SYS)
    Memory Mapped Structure for SYS Controller

Definition at line 26 of file sys_reg.h.

## Field Documentation

## ◆ AHBMCTL

SYS_T::AHBMCTL

[0x0400] AHB Bus Matrix Priority Control Register

AHBMCTL

Offset: 0x400 AHB Bus Matrix Priority Control Register

Bits | Field | Descriptions
[0] | INTACTEN | Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect) Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix 0 = Run robin mode. 1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 4818 of file sys_reg.h.

## ◆ BODCTL

SYS_T::BODCTL

[0x0018] Brown-Out Detector Control Register

BODCTL

Offset: 0x18 Brown-Out Detector Control Register

Bits | Field | Descriptions
[0] | BODEN | Brown-out Detector Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]). 0 = Brown-out Detector function Disabled. 1 = Brown-out Detector function Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | BODRSTEN | Brown-out Reset Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . 0 = Brown-out INTERRUPT function Enabled. 1 = Brown-out RESET function Enabled. Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high BOD interrupt will keep till to the BODEN set to 0 BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | BODIF | Brown-out Detector Interrupt Flag 0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. 1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. Note: Write 1 to clear this bit to 0.
[5] | BODLPM | Brown-out Detector Low Power Mode (Write Protect) 0 = BOD operate in normal mode (default). 1 = BOD Low Power mode Enabled. Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] | BODOUT | Brown-out Detector Output Status 0 = Brown-out Detector output status is 0. It means the detected voltage is higher than BODVL setting or BODEN is 0. 1 = Brown-out Detector output status is 1. It means the detected voltage is lower than BODVL setting If the BODEN is 0, BOD function disabled , this bit always responds 0000.
[7] | LVREN | Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting LVR function is enabled by default. 0 = Low Voltage Reset function Disabled. 1 = Low Voltage Reset function Enabled. Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[10:8] | BODDGSEL | Brown-out Detector Output De-glitch Time Select (Write Protect) 000 = BOD output is sampled by RC10K clock. 001 = 4 system clock (HCLK). 010 = 8 system clock (HCLK). 011 = 16 system clock (HCLK). 100 = 32 system clock (HCLK). 101 = 64 system clock (HCLK). 110 = 128 system clock (HCLK). 111 = 256 system clock (HCLK). Note: These bits are write protected. Refer to the SYS_REGLCTL register.
[14:12] | LVRDGSEL | LVR Output De-glitch Time Select (Write Protect) 000 = Without de-glitch function. 001 = 4 system clock (HCLK). 010 = 8 system clock (HCLK). 011 = 16 system clock (HCLK). 100 = 32 system clock (HCLK). 101 = 64 system clock (HCLK). 110 = 128 system clock (HCLK). 111 = 256 system clock (HCLK). Note: These bits are write protected. Refer to the SYS_REGLCTL register.
[18:16] | BODVL | Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). 000 = Brown-Out Detector threshold voltage is 1.6V. 001 = Brown-Out Detector threshold voltage is 1.8V. 010 = Brown-Out Detector threshold voltage is 2.0V. 011 = Brown-Out Detector threshold voltage is 2.2V. 100 = Brown-Out Detector threshold voltage is 2.4V. 101 = Brown-Out Detector threshold voltage is 2.6V. 110 = Brown-Out Detector threshold voltage is 2.8V. 111 = Brown-Out Detector threshold voltage is 3.0V. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 4746 of file sys_reg.h.

## ◆ CSERVER

__I uint32_t SYS_T::CSERVER

[0x01f4] Chip Series Version Register

Definition at line 4812 of file sys_reg.h.

## ◆ GPA_MFOS

SYS_T::GPA_MFOS

[0x0080] GPIOA Multiple Function Output Select Register

GPA_MFOS

Offset: 0x80 GPIOA Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4773 of file sys_reg.h.

## ◆ GPA_MFPH

SYS_T::GPA_MFPH

[0x0034] GPIOA High Byte Multiple Function Control Register

GPA_MFPH

Offset: 0x34 GPIOA High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PA8MFP | PA.8 Multi-function Pin Selection
[7:4] | PA9MFP | PA.9 Multi-function Pin Selection
[11:8] | PA10MFP | PA.10 Multi-function Pin Selection
[15:12] | PA11MFP | PA.11 Multi-function Pin Selection
[19:16] | PA12MFP | PA.12 Multi-function Pin Selection
[23:20] | PA13MFP | PA.13 Multi-function Pin Selection
[27:24] | PA14MFP | PA.14 Multi-function Pin Selection
[31:28] | PA15MFP | PA.15 Multi-function Pin Selection

Definition at line 4755 of file sys_reg.h.

## ◆ GPA_MFPL

SYS_T::GPA_MFPL

[0x0030] GPIOA Low Byte Multiple Function Control Register

GPA_MFPL

Offset: 0x30 GPIOA Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PA0MFP | PA.0 Multi-function Pin Selection
[7:4] | PA1MFP | PA.1 Multi-function Pin Selection
[11:8] | PA2MFP | PA.2 Multi-function Pin Selection
[15:12] | PA3MFP | PA.3 Multi-function Pin Selection
[19:16] | PA4MFP | PA.4 Multi-function Pin Selection
[23:20] | PA5MFP | PA.5 Multi-function Pin Selection
[27:24] | PA6MFP | PA.6 Multi-function Pin Selection
[31:28] | PA7MFP | PA.7 Multi-function Pin Selection

Definition at line 4754 of file sys_reg.h.

## ◆ GPB_MFOS

SYS_T::GPB_MFOS

[0x0084] GPIOB Multiple Function Output Select Register

GPB_MFOS

Offset: 0x84 GPIOB Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4774 of file sys_reg.h.

## ◆ GPB_MFPH

SYS_T::GPB_MFPH

[0x003c] GPIOB High Byte Multiple Function Control Register

GPB_MFPH

Offset: 0x3C GPIOB High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PB8MFP | PB.8 Multi-function Pin Selection
[7:4] | PB9MFP | PB.9 Multi-function Pin Selection
[11:8] | PB10MFP | PB.10 Multi-function Pin Selection
[15:12] | PB11MFP | PB.11 Multi-function Pin Selection
[19:16] | PB12MFP | PB.12 Multi-function Pin Selection
[23:20] | PB13MFP | PB.13 Multi-function Pin Selection
[27:24] | PB14MFP | PB.14 Multi-function Pin Selection
[31:28] | PB15MFP | PB.15 Multi-function Pin Selection

Definition at line 4757 of file sys_reg.h.

## ◆ GPB_MFPL

SYS_T::GPB_MFPL

[0x0038] GPIOB Low Byte Multiple Function Control Register

GPB_MFPL

Offset: 0x38 GPIOB Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PB0MFP | PB.0 Multi-function Pin Selection
[7:4] | PB1MFP | PB.1 Multi-function Pin Selection
[11:8] | PB2MFP | PB.2 Multi-function Pin Selection
[15:12] | PB3MFP | PB.3 Multi-function Pin Selection
[19:16] | PB4MFP | PB.4 Multi-function Pin Selection
[23:20] | PB5MFP | PB.5 Multi-function Pin Selection
[27:24] | PB6MFP | PB.6 Multi-function Pin Selection
[31:28] | PB7MFP | PB.7 Multi-function Pin Selection

Definition at line 4756 of file sys_reg.h.

## ◆ GPC_MFOS

SYS_T::GPC_MFOS

[0x0088] GPIOC Multiple Function Output Select Register

GPC_MFOS

Offset: 0x88 GPIOC Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4775 of file sys_reg.h.

## ◆ GPC_MFPH

SYS_T::GPC_MFPH

[0x0044] GPIOC High Byte Multiple Function Control Register

GPC_MFPH

Offset: 0x44 GPIOC High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PC8MFP | PC.8 Multi-function Pin Selection
[7:4] | PC9MFP | PC.9 Multi-function Pin Selection
[11:8] | PC10MFP | PC.10 Multi-function Pin Selection
[15:12] | PC11MFP | PC.11 Multi-function Pin Selection
[19:16] | PC12MFP | PC.12 Multi-function Pin Selection
[23:20] | PC13MFP | PC.13 Multi-function Pin Selection
[27:24] | PC14MFP | PC.14 Multi-function Pin Selection
[31:28] | PC15MFP | PC.15 Multi-function Pin Selection

Definition at line 4759 of file sys_reg.h.

## ◆ GPC_MFPL

SYS_T::GPC_MFPL

[0x0040] GPIOC Low Byte Multiple Function Control Register

GPC_MFPL

Offset: 0x40 GPIOC Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PC0MFP | PC.0 Multi-function Pin Selection
[7:4] | PC1MFP | PC.1 Multi-function Pin Selection
[11:8] | PC2MFP | PC.2 Multi-function Pin Selection
[15:12] | PC3MFP | PC.3 Multi-function Pin Selection
[19:16] | PC4MFP | PC.4 Multi-function Pin Selection
[23:20] | PC5MFP | PC.5 Multi-function Pin Selection
[27:24] | PC6MFP | PC.6 Multi-function Pin Selection
[31:28] | PC7MFP | PC.7 Multi-function Pin Selection

Definition at line 4758 of file sys_reg.h.

## ◆ GPD_MFOS

SYS_T::GPD_MFOS

[0x008c] GPIOD Multiple Function Output Select Register

GPD_MFOS

Offset: 0x8C GPIOD Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4776 of file sys_reg.h.

## ◆ GPD_MFPH

SYS_T::GPD_MFPH

[0x004c] GPIOD High Byte Multiple Function Control Register

GPD_MFPH

Offset: 0x4C GPIOD High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PD8MFP | PD.8 Multi-function Pin Selection
[7:4] | PD9MFP | PD.9 Multi-function Pin Selection
[11:8] | PD10MFP | PD.10 Multi-function Pin Selection
[15:12] | PD11MFP | PD.11 Multi-function Pin Selection
[19:16] | PD12MFP | PD.12 Multi-function Pin Selection
[23:20] | PD13MFP | PD.13 Multi-function Pin Selection
[27:24] | PD14MFP | PD.14 Multi-function Pin Selection
[31:28] | PD15MFP | PD.15 Multi-function Pin Selection

Definition at line 4761 of file sys_reg.h.

## ◆ GPD_MFPL

SYS_T::GPD_MFPL

[0x0048] GPIOD Low Byte Multiple Function Control Register

GPD_MFPL

Offset: 0x48 GPIOD Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PD0MFP | PD.0 Multi-function Pin Selection
[7:4] | PD1MFP | PD.1 Multi-function Pin Selection
[11:8] | PD2MFP | PD.2 Multi-function Pin Selection
[15:12] | PD3MFP | PD.3 Multi-function Pin Selection
[19:16] | PD4MFP | PD.4 Multi-function Pin Selection
[23:20] | PD5MFP | PD.5 Multi-function Pin Selection
[27:24] | PD6MFP | PD.6 Multi-function Pin Selection
[31:28] | PD7MFP | PD.7 Multi-function Pin Selection

Definition at line 4760 of file sys_reg.h.

## ◆ GPE_MFOS

SYS_T::GPE_MFOS

[0x0090] GPIOE Multiple Function Output Select Register

GPE_MFOS

Offset: 0x90 GPIOE Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4777 of file sys_reg.h.

## ◆ GPE_MFPH

SYS_T::GPE_MFPH

[0x0054] GPIOE High Byte Multiple Function Control Register

GPE_MFPH

Offset: 0x54 GPIOE High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PE8MFP | PE.8 Multi-function Pin Selection
[7:4] | PE9MFP | PE.9 Multi-function Pin Selection
[11:8] | PE10MFP | PE.10 Multi-function Pin Selection
[15:12] | PE11MFP | PE.11 Multi-function Pin Selection
[19:16] | PE12MFP | PE.12 Multi-function Pin Selection
[23:20] | PE13MFP | PE.13 Multi-function Pin Selection
[27:24] | PE14MFP | PE.14 Multi-function Pin Selection
[31:28] | PE15MFP | PE.15 Multi-function Pin Selection

Definition at line 4763 of file sys_reg.h.

## ◆ GPE_MFPL

SYS_T::GPE_MFPL

[0x0050] GPIOE Low Byte Multiple Function Control Register

GPE_MFPL

Offset: 0x50 GPIOE Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PE0MFP | PE.0 Multi-function Pin Selection
[7:4] | PE1MFP | PE.1 Multi-function Pin Selection
[11:8] | PE2MFP | PE.2 Multi-function Pin Selection
[15:12] | PE3MFP | PE.3 Multi-function Pin Selection
[19:16] | PE4MFP | PE.4 Multi-function Pin Selection
[23:20] | PE5MFP | PE.5 Multi-function Pin Selection
[27:24] | PE6MFP | PE.6 Multi-function Pin Selection
[31:28] | PE7MFP | PE.7 Multi-function Pin Selection

Definition at line 4762 of file sys_reg.h.

## ◆ GPF_MFOS

SYS_T::GPF_MFOS

[0x0094] GPIOF Multiple Function Output Select Register

GPF_MFOS

Offset: 0x94 GPIOF Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4778 of file sys_reg.h.

## ◆ GPF_MFPH

SYS_T::GPF_MFPH

[0x005c] GPIOF High Byte Multiple Function Control Register

GPF_MFPH

Offset: 0x5C GPIOF High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PF8MFP | PF.8 Multi-function Pin Selection
[7:4] | PF9MFP | PF.9 Multi-function Pin Selection
[11:8] | PF10MFP | PF.10 Multi-function Pin Selection
[15:12] | PF11MFP | PF.11 Multi-function Pin Selection
[19:16] | PF12MFP | PF.12 Multi-function Pin Selection
[23:20] | PF13MFP | PF.13 Multi-function Pin Selection
[27:24] | PF14MFP | PF.14 Multi-function Pin Selection
[31:28] | PF15MFP | PF.15 Multi-function Pin Selection

Definition at line 4765 of file sys_reg.h.

## ◆ GPF_MFPL

SYS_T::GPF_MFPL

[0x0058] GPIOF Low Byte Multiple Function Control Register

GPF_MFPL

Offset: 0x58 GPIOF Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PF0MFP | PF.0 Multi-function Pin Selection
[7:4] | PF1MFP | PF.1 Multi-function Pin Selection
[11:8] | PF2MFP | PF.2 Multi-function Pin Selection
[15:12] | PF3MFP | PF.3 Multi-function Pin Selection
[19:16] | PF4MFP | PF.4 Multi-function Pin Selection
[23:20] | PF5MFP | PF.5 Multi-function Pin Selection
[27:24] | PF6MFP | PF.6 Multi-function Pin Selection
[31:28] | PF7MFP | PF.7 Multi-function Pin Selection

Definition at line 4764 of file sys_reg.h.

## ◆ GPG_MFOS

SYS_T::GPG_MFOS

[0x0098] GPIOG Multiple Function Output Select Register

GPG_MFOS

Offset: 0x98 GPIOG Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4779 of file sys_reg.h.

## ◆ GPG_MFPH

SYS_T::GPG_MFPH

[0x0064] GPIOG High Byte Multiple Function Control Register

GPG_MFPH

Offset: 0x64 GPIOG High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PG8MFP | PG.8 Multi-function Pin Selection
[7:4] | PG9MFP | PG.9 Multi-function Pin Selection
[11:8] | PG10MFP | PG.10 Multi-function Pin Selection
[15:12] | PG11MFP | PG.11 Multi-function Pin Selection
[19:16] | PG12MFP | PG.12 Multi-function Pin Selection
[23:20] | PG13MFP | PG.13 Multi-function Pin Selection
[27:24] | PG14MFP | PG.14 Multi-function Pin Selection
[31:28] | PG15MFP | PG.15 Multi-function Pin Selection

Definition at line 4767 of file sys_reg.h.

## ◆ GPG_MFPL

SYS_T::GPG_MFPL

[0x0060] GPIOG Low Byte Multiple Function Control Register

GPG_MFPL

Offset: 0x60 GPIOG Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PG0MFP | PG.0 Multi-function Pin Selection
[7:4] | PG1MFP | PG.1 Multi-function Pin Selection
[11:8] | PG2MFP | PG.2 Multi-function Pin Selection
[15:12] | PG3MFP | PG.3 Multi-function Pin Selection
[19:16] | PG4MFP | PG.4 Multi-function Pin Selection
[23:20] | PG5MFP | PG.5 Multi-function Pin Selection
[27:24] | PG6MFP | PG.6 Multi-function Pin Selection
[31:28] | PG7MFP | PG.7 Multi-function Pin Selection

Definition at line 4766 of file sys_reg.h.

## ◆ GPH_MFOS

SYS_T::GPH_MFOS

[0x009c] GPIOH Multiple Function Output Select Register

GPH_MFOS

Offset: 0x9C GPIOH Multiple Function Output Select Register

Bits | Field | Descriptions
[0] | MFOS0 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[1] | MFOS1 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[2] | MFOS2 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[3] | MFOS3 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[4] | MFOS4 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[5] | MFOS5 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[6] | MFOS6 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[7] | MFOS7 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[8] | MFOS8 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[9] | MFOS9 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[10] | MFOS10 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[11] | MFOS11 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[12] | MFOS12 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[13] | MFOS13 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[14] | MFOS14 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.
[15] | MFOS15 | GPIOA-H Pin[n] Multiple Function Pin Output Mode Select This bit used to select multiple function pin output mode type for Px.n pin 0 = Multiple function pin output mode type is Push-pull mode. 1 = Multiple function pin output mode type is Open-drain mode. Note: Max. n=15 for port A/B/E/G. Max. n=14 for port C/D. Max. n=11 for port F/H.

Definition at line 4780 of file sys_reg.h.

## ◆ GPH_MFPH

SYS_T::GPH_MFPH

[0x006c] GPIOH High Byte Multiple Function Control Register

GPH_MFPH

Offset: 0x6C GPIOH High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PH8MFP | PH.8 Multi-function Pin Selection
[7:4] | PH9MFP | PH.9 Multi-function Pin Selection
[11:8] | PH10MFP | PH.10 Multi-function Pin Selection
[15:12] | PH11MFP | PH.11 Multi-function Pin Selection
[19:16] | PH12MFP | PH.12 Multi-function Pin Selection
[23:20] | PH13MFP | PH.13 Multi-function Pin Selection
[27:24] | PH14MFP | PH.14 Multi-function Pin Selection
[31:28] | PH15MFP | PH.15 Multi-function Pin Selection

Definition at line 4769 of file sys_reg.h.

## ◆ GPH_MFPL

SYS_T::GPH_MFPL

[0x0068] GPIOH Low Byte Multiple Function Control Register

GPH_MFPL

Offset: 0x68 GPIOH Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PH0MFP | PH.0 Multi-function Pin Selection
[7:4] | PH1MFP | PH.1 Multi-function Pin Selection
[11:8] | PH2MFP | PH.2 Multi-function Pin Selection
[15:12] | PH3MFP | PH.3 Multi-function Pin Selection
[19:16] | PH4MFP | PH.4 Multi-function Pin Selection
[23:20] | PH5MFP | PH.5 Multi-function Pin Selection
[27:24] | PH6MFP | PH.6 Multi-function Pin Selection
[31:28] | PH7MFP | PH.7 Multi-function Pin Selection

Definition at line 4768 of file sys_reg.h.

## ◆ HIRCTCTL

SYS_T::HIRCTCTL

[0x00e4] HIRC48M Trim Control Register

HIRCTCTL

Offset: 0xE4 HIRC48M Trim Control Register

Bits | Field | Descriptions
[1:0] | FREQSEL | Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 00 = Disable HIRC auto trim function. 01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. 10 = Reserved.. 11 = Reserved.
[5:4] | LOOPSEL | Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. 00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 11 = Trim value calculation is based on average difference in 32 clocks of reference clock. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
[7:6] | RETRYCNT | Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 00 = Trim retry count limitation is 64 loops. 01 = Trim retry count limitation is 128 loops. 10 = Trim retry count limitation is 256 loops. 11 = Trim retry count limitation is 512 loops.
[8] | CESTOPEN | Clock Error Stop Enable Bit 0 = The trim operation is keep going if clock is inaccuracy. 1 = The trim operation is stopped if clock is inaccuracy.
[9] | BOUNDEN | Boundary Enable Bit 0 = Boundary function is disable. 1 = Boundary function is enable.
[10] | REFCKSEL | Reference Clock Selection 0 = HIRC trim reference from external 32.768 kHz crystal oscillator. 1 = HIRC trim reference from internal USB synchronous mode. Note: HIRC trim reference clock is 20Khz in test mode.
|  | [20:16 |BOUNDARY |Boundary Selection Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. Note1: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable.

Definition at line 4795 of file sys_reg.h.

## ◆ HIRCTIEN

SYS_T::HIRCTIEN

[0x00e8] HIRC48M Trim Interrupt Enable Register

HIRCTIEN

Offset: 0xE8 HIRC48M Trim Interrupt Enable Register

Bits | Field | Descriptions
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]). If this bit is high and TFAILIF(SYS_HIRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 0 = Disable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. 1 = Enable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU.
[2] | CLKEIEN | Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_HIRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 0 = Disable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. 1 = Enable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU.

Definition at line 4796 of file sys_reg.h.

## ◆ HIRCTISTS

SYS_T::HIRCTISTS

[0x00ec] HIRC48M Trim Interrupt Status Register

HIRCTISTS

Offset: 0xEC HIRC48M Trim Interrupt Status Register

Bits | Field | Descriptions
[0] | FREQLOCK | HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0 This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. 1 = The internal high-speed oscillator frequency locked at 48 MHz.
[1] | TFAILIF | Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_HIRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached Write 1 to clear this to 0. 0 = Trim value update limitation count does not reach. 1 = Trim value update limitation count reached and HIRC frequency still not locked.
[2] | CLKERRIF | Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 0 = Clock frequency is accurate. 1 = Clock frequency is inaccurate.
[3] | OVBDIF | Over Boundary Status When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. Note1: Write 1 to clear this flag. Note2: This function is only supported in M48xGC/M48xG8. 0 = Over boundary condition did not occur. 1 = Over boundary condition occurred.

Definition at line 4797 of file sys_reg.h.

## ◆ IPRST0

SYS_T::IPRST0

[0x0008] Peripheral Reset Control Register 0

IPRST0

Offset: 0x08 Peripheral Reset Control Register 0

Bits | Field | Descriptions
[0] | CHIPRST | Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 0 = Chip normal operation. 1 = Chip one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] | CPURST | Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. 0 = Processor core normal operation. 1 = Processor core one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] | PDMARST | PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA User needs to set this bit to 0 to release from reset state. 0 = PDMA controller normal operation. 1 = PDMA controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | EBIRST | EBI Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the EBI User needs to set this bit to 0 to release from the reset state. 0 = EBI controller normal operation. 1 = EBI controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5] | EMACRST | EMAC Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the EMAC controller User needs to set this bit to 0 to release from the reset state. 0 = EMAC controller normal operation. 1 = EMAC controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] | SDH0RST | SDHOST0 Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the SDHOST0 controller User needs to set this bit to 0 to release from the reset state. 0 = SDHOST0 controller normal operation. 1 = SDHOST0 controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] | CRCRST | CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller User needs to set this bit to 0 to release from the reset state. 0 = CRC calculation controller normal operation. 1 = CRC calculation controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8] | CCAPRST | CCAP Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CCAP controller. User needs to set this bit to 0 to release from the reset state. 0 = CCAP controller normal operation. 1 = CCAP controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[10] | HSUSBDRST | HSUSBD Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the HSUSBD controller User needs to set this bit to 0 to release from the reset state. 0 = HSUSBD controller normal operation. 1 = HSUSBD controller reset.
[12] | CRPTRST | CRYPTO Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the CRYPTO controller User needs to set this bit to 0 to release from the reset state. 0 = CRYPTO controller normal operation. 1 = CRYPTO controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[14] | SPIMRST | SPIM Controller Reset Setting this bit to 1 will generate a reset signal to the SPIM controller User needs to set this bit to 0 to release from the reset state. 0 = SPIM controller normal operation. 1 = SPIM controller reset.
[16] | USBHRST | USBH Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the USBH controller User needs to set this bit to 0 to release from the reset state. 0 = USBH controller normal operation. 1 = USBH controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[17] | SDH1RST | SDHOST1 Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the SDHOST1 controller User needs to set this bit to 0 to release from the reset state. 0 = SDHOST1 controller normal operation. 1 = SDHOST1 controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 4740 of file sys_reg.h.

## ◆ IPRST1

SYS_T::IPRST1

[0x000c] Peripheral Reset Control Register 1

IPRST1

Offset: 0x0C Peripheral Reset Control Register 1

Bits | Field | Descriptions
[1] | GPIORST | GPIO Controller Reset 0 = GPIO controller normal operation. 1 = GPIO controller reset.
[2] | TMR0RST | Timer0 Controller Reset 0 = Timer0 controller normal operation. 1 = Timer0 controller reset.
[3] | TMR1RST | Timer1 Controller Reset 0 = Timer1 controller normal operation. 1 = Timer1 controller reset.
[4] | TMR2RST | Timer2 Controller Reset 0 = Timer2 controller normal operation. 1 = Timer2 controller reset.
[5] | TMR3RST | Timer3 Controller Reset 0 = Timer3 controller normal operation. 1 = Timer3 controller reset.
[7] | ACMP01RST | Analog Comparator 0/1 Controller Reset 0 = Analog Comparator 0/1 controller normal operation. 1 = Analog Comparator 0/1 controller reset.
[8] | I2C0RST | I2C0 Controller Reset 0 = I2C0 controller normal operation. 1 = I2C0 controller reset.
[9] | I2C1RST | I2C1 Controller Reset 0 = I2C1 controller normal operation. 1 = I2C1 controller reset.
[10] | I2C2RST | I2C2 Controller Reset 0 = I2C2 controller normal operation. 1 = I2C2 controller reset.
[12] | QSPI0RST | QSPI0 Controller Reset 0 = QSPI0 controller normal operation. 1 = QSPI0 controller reset.
[13] | SPI0RST | SPI0 Controller Reset 0 = SPI0 controller normal operation. 1 = SPI0 controller reset.
[14] | SPI1RST | SPI1 Controller Reset 0 = SPI1 controller normal operation. 1 = SPI1 controller reset.
[15] | SPI2RST | SPI2 Controller Reset 0 = SPI2 controller normal operation. 1 = SPI2 controller reset.
[16] | UART0RST | UART0 Controller Reset 0 = UART0 controller normal operation. 1 = UART0 controller reset.
[17] | UART1RST | UART1 Controller Reset 0 = UART1 controller normal operation. 1 = UART1 controller reset.
[18] | UART2RST | UART2 Controller Reset 0 = UART2 controller normal operation. 1 = UART2 controller reset.
[19] | UART3RST | UART3 Controller Reset 0 = UART3 controller normal operation. 1 = UART3 controller reset.
[20] | UART4RST | UART4 Controller Reset 0 = UART4 controller normal operation. 1 = UART4 controller reset.
[21] | UART5RST | UART5 Controller Reset 0 = UART5 controller normal operation. 1 = UART5 controller reset.
[24] | CAN0RST | CAN0 Controller Reset 0 = CAN0 controller normal operation. 1 = CAN0 controller reset.
[25] | CAN1RST | CAN1 Controller Reset 0 = CAN1 controller normal operation. 1 = CAN1 controller reset.
[27] | USBDRST | USBD Controller Reset 0 = USBD controller normal operation. 1 = USBD controller reset.
[28] | EADCRST | EADC Controller Reset 0 = EADC controller normal operation. 1 = EADC controller reset.
[29] | I2S0RST | I2S0 Controller Reset 0 = I2S0 controller normal operation. 1 = I2S0 controller reset.

Definition at line 4741 of file sys_reg.h.

## ◆ IPRST2

SYS_T::IPRST2

[0x0010] Peripheral Reset Control Register 2

IPRST2

Offset: 0x10 Peripheral Reset Control Register 2

Bits | Field | Descriptions
[0] | SC0RST | SC0 Controller Reset 0 = SC0 controller normal operation. 1 = SC0 controller reset.
[1] | SC1RST | SC1 Controller Reset 0 = SC1 controller normal operation. 1 = SC1 controller reset.
[2] | SC2RST | SC2 Controller Reset 0 = SC2 controller normal operation. 1 = SC2 controller reset.
[6] | SPI3RST | SPI3 Controller Reset 0 = SPI3 controller normal operation. 1 = SPI3 controller reset.
[8] | USCI0RST | USCI0 Controller Reset 0 = USCI0 controller normal operation. 1 = USCI0 controller reset.
[9] | USCI1RST | USCI1 Controller Reset 0 = USCI1 controller normal operation. 1 = USCI1 controller reset.
[12] | DACRST | DAC Controller Reset 0 = DAC controller normal operation. 1 = DAC controller reset.
[16] | EPWM0RST | EPWM0 Controller Reset 0 = EPWM0 controller normal operation. 1 = EPWM0 controller reset.
[17] | EPWM1RST | EPWM1 Controller Reset 0 = EPWM1 controller normal operation. 1 = EPWM1 controller reset.
[18] | BPWM0RST | BPWM0 Controller Reset 0 = BPWM0 controller normal operation. 1 = BPWM0 controller reset.
[19] | BPWM1RST | BPWM1 Controller Reset 0 = BPWM1 controller normal operation. 1 = BPWM1 controller reset.
[22] | QEI0RST | QEI0 Controller Reset 0 = QEI0 controller normal operation. 1 = QEI0 controller reset.
[23] | QEI1RST | QEI1 Controller Reset 0 = QEI1 controller normal operation. 1 = QEI1 controller reset.
[26] | ECAP0RST | ECAP0 Controller Reset 0 = ECAP0 controller normal operation. 1 = ECAP0 controller reset.
[27] | ECAP1RST | ECAP1 Controller Reset 0 = ECAP1 controller normal operation. 1 = ECAP1 controller reset.
[28] | CAN2RST | CAN2 Controller Reset 0 = CAN2 controller normal operation. 1 = CAN2 controller reset.
[30] | OPARST | OP Amplifier (OPA) Controller Reset 0 = OPA controller normal operation. 1 = OPA controller reset.

Definition at line 4742 of file sys_reg.h.

## ◆ IRCTCTL

SYS_T::IRCTCTL

[0x00f0] HIRC Trim Control Register

IRCTCTL

Offset: 0xF0 HIRC Trim Control Register

Bits | Field | Descriptions
[1:0] | FREQSEL | Trim Frequency Selection This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 00 = Disable HIRC auto trim function. 01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. 10 = Reserved.. 11 = Reserved.
[5:4] | LOOPSEL | Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. 00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 11 = Trim value calculation is based on average difference in 32 clocks of reference clock. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
[7:6] | RETRYCNT | Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 00 = Trim retry count limitation is 64 loops. 01 = Trim retry count limitation is 128 loops. 10 = Trim retry count limitation is 256 loops. 11 = Trim retry count limitation is 512 loops.
[8] | CESTOPEN | Clock Error Stop Enable Bit 0 = The trim operation is keep going if clock is inaccuracy. 1 = The trim operation is stopped if clock is inaccuracy.
[10] | REFCKSEL | Reference Clock Selection 0 = HIRC trim reference from external 32.768 kHz crystal oscillator. 1 = HIRC trim reference from internal USB synchronous mode. Note: HIRC trim reference clock is 20Khz in test mode.

Definition at line 4798 of file sys_reg.h.

## ◆ IRCTIEN

SYS_T::IRCTIEN

[0x00f4] HIRC Trim Interrupt Enable Register

IRCTIEN

Offset: 0xF4 HIRC Trim Interrupt Enable Register

Bits | Field | Descriptions
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
[2] | CLKEIEN | Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.

Definition at line 4799 of file sys_reg.h.

## ◆ IRCTISTS

SYS_T::IRCTISTS

[0x00f8] HIRC Trim Interrupt Status Register

IRCTISTS

Offset: 0xF8 HIRC Trim Interrupt Status Register

Bits | Field | Descriptions
[0] | FREQLOCK | HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0 This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. 1 = The internal high-speed oscillator frequency locked at 12 MHz.
[1] | TFAILIF | Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached Write 1 to clear this to 0. 0 = Trim value update limitation count does not reach. 1 = Trim value update limitation count reached and HIRC frequency still not locked.
[2] | CLKERRIF | Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 0 = Clock frequency is accurate. 1 = Clock frequency is inaccurate.

Definition at line 4800 of file sys_reg.h.

## ◆ IVSCTL

SYS_T::IVSCTL

[0x001c] Internal Voltage Source Control Register

IVSCTL

Offset: 0x1C Internal Voltage Source Control Register

Bits | Field | Descriptions
[0] | VTEMPEN | Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. 0 = Temperature sensor function Disabled (default). 1 = Temperature sensor function Enabled. Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9.
[1] | VBATUGEN | VBAT Unity Gain Buffer Enable Bit This bit is used to enable/disable VBAT unity gain buffer function. 0 = VBAT unity gain buffer function Disabled (default). 1 = VBAT unity gain buffer function Enabled. Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result

Definition at line 4747 of file sys_reg.h.

## ◆ PDID

SYS_T::PDID

[0x0000] Part Device Identification Number Register

PDID

Offset: 0x00 Part Device Identification Number Register

Bits | Field | Descriptions
[31:0] | PDID | Part Device Identification Number (Read Only) This register reflects device part number code Software can read this register to identify which device is used.

Definition at line 4738 of file sys_reg.h.

## ◆ PLCTL

SYS_T::PLCTL

[0x01f8] Power Level Control Register

PLCTL

Offset: 0x1F8 Power Level Control Register

Bits | Field | Descriptions
[1:0] | PLSEL | Power Level Select(Write Protect) 00 = Power level is PL0. 01 = Power level is PL1. Others = Reserved.
[21:16] | LVSSTEP | LDO Voltage Scaling Step(Write Protect) The LVSSTEP value is LDO voltage rising step. Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV.
[31:24] | LVSPRD | LDO Voltage Scaling Period(Write Protect) The LVSPRD value is the period of each LDO voltage rising step. LDO voltage scaling period = (LVSPRD + 1) * 1us.

Definition at line 4813 of file sys_reg.h.

## ◆ PLSTS

SYS_T::PLSTS

[0x01fc] Power Level Status Register

PLSTS

Offset: 0x1FC Power Level Status Register

Bits | Field | Descriptions
[0] | PLCBUSY | Power Level Change Busy Bit (Read Only) This bit is set by hardware when core voltage is changing After core voltage change is completed, this bit will be cleared automatically by hardware. 0 = Core voltage change is completed. 1 = Core voltage change is ongoing.
[9:8] | PLSTATUS | Power Level Status (Read Only) 00 = Power level is PL0. 01 = Power level is PL1. Others = Reserved.

Definition at line 4814 of file sys_reg.h.

## ◆ PORCTL

SYS_T::PORCTL

[0x0024] Power-On-Reset Controller Register

PORCTL

Offset: 0x24 Power-On-Reset Controller Register

Bits | Field | Descriptions
[15:0] | POROFF | Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 4751 of file sys_reg.h.

## ◆ PORDISAN

SYS_T::PORDISAN

[0x01ec] Analog POR Disable Control Register

PORDISAN

Offset: 0x1EC Analog POR Disable Control Register

Bits | Field | Descriptions
[15:0] | POROFFAN | Power-on Reset Enable Bit (Write Protect) After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 4808 of file sys_reg.h.

## ◆ REGLCTL

SYS_T::REGLCTL

[0x0100] Register Lock Control Register

REGLCTL

Offset: 0x100 Register Lock Control Register

Bits | Field | Descriptions
[7:0] | REGLCTL | Register Lock Control Code Some registers have write-protection function Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Register Lock Control Code 0 = Write-protection Enabled for writing protected registers Any write to the protected register is ignored. 1 = Write-protection Disabled for writing protected registers.

Definition at line 4804 of file sys_reg.h.

## ◆ RSTSTS

SYS_T::RSTSTS

[0x0004] System Reset Status Register

RSTSTS

Offset: 0x04 System Reset Status Register

Bits | Field | Descriptions
[0] | PORF | POR Reset Flag The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 0 = No reset from POR or CHIPRST. 1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[1] | PINRF | NRESET Pin Reset Flag The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. 0 = No reset from nRESET pin. 1 = Pin nRESET had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[2] | WDTRF | WDT Reset Flag The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. 0 = No reset from watchdog timer or window watchdog timer. 1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. Note1: Write 1 to clear this bit to 0. Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
[3] | LVRF | LVR Reset Flag The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. 0 = No reset from LVR. 1 = LVR controller had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[4] | BODRF | BOD Reset Flag The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. 0 = No reset from BOD. 1 = The BOD had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[5] | SYSRF | System Reset Flag The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. 0 = No reset from Cortex-M4. 1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. Note: Write 1 to clear this bit to 0.
[7] | CPURF | CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). 0 = No reset from CPU. 1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. Note: Write to clear this bit to 0.
[8] | CPULKRF | CPU Lock-up Reset Flag 0 = No reset from CPU lock-up happened. 1 = The Cortex-M4 lock-up happened and chip is reset. Note: Write 1 to clear this bit to 0. Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset.

Definition at line 4739 of file sys_reg.h.

## ◆ SRAM_BISTCTL

SYS_T::SRAM_BISTCTL

[0x00d0] System SRAM BIST Test Control Register

SRAM_BISTCTL

Offset: 0xD0 System SRAM BIST Test Control Register

Bits | Field | Descriptions
[0] | SRBIST0 | SRAM Bank0 BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM bank0. 0 = system SRAM bank0 BIST Disabled. 1 = system SRAM bank0 BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] | SRBIST1 | SRAM Bank1 BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM bank1. 0 = system SRAM bank1 BIST Disabled. 1 = system SRAM bank1 BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] | CRBIST | CACHE BIST Enable Bit (Write Protect) This bit enables BIST test for CACHE RAM 0 = system CACHE BIST Disabled. 1 = system CACHE BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | CANBIST | CAN BIST Enable Bit (Write Protect) This bit enables BIST test for CAN RAM 0 = system CAN BIST Disabled. 1 = system CAN BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | USBBIST | USB BIST Enable Bit (Write Protect) This bit enables BIST test for USB RAM 0 = system USB BIST Disabled. 1 = system USB BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5] | SPIMBIST | SPIM BIST Enable Bit (Write Protect) This bit enables BIST test for SPIM RAM 0 = system SPIM BIST Disabled. 1 = system SPIM BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] | EMCBIST | EMC BIST Enable Bit (Write Protect) This bit enables BIST test for EMC RAM 0 = system EMC BIST Disabled. 1 = system EMC BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] | PDMABIST | PDMA BIST Enable Bit (Write Protect) This bit enables BIST test for PDMA RAM 0 = system PDMA BIST Disabled. 1 = system PDMA BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8] | HSUSBDBIST | HSUSBD BIST Enable Bit (Write Protect) This bit enables BIST test for HSUSBD RAM 0 = system HSUSBD BIST Disabled. 1 = system HSUSBD BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[9] | HSUSBHBIST | HSUSBH BIST Enable Bit (Write Protect) This bit enables BIST test for HSUSBH RAM 0 = system HSUSBH BIST Disabled. 1 = system HSUSBH BIST Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[16] | SRB0S0 | SRAM Bank0 Section 0 BIST Select (Write Protect) This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test. 0 = SRAM bank0 section 0 is deselected when doing bist test. 1 = SRAM bank0 section 0 is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
[17] | SRB0S1 | SRAM Bank0 Section 1 BIST Select (Write Protect) This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test. 0 = SRAM bank0 section 1 is deselected when doing bist test. 1 = SRAM bank0 section 1 is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test.
[18] | SRB1S0 | SRAM Bank1 Section 0 BIST Select (Write Protect) This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test. 0 = SRAM bank1 first 16KB section is deselected when doing bist test. 1 = SRAM bank1 first 16KB section is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
[19] | SRB1S1 | SRAM Bank1 Section 1 BIST Select (Write Protect) This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test. 0 = SRAM bank1 second 16KB section is deselected when doing bist test. 1 = SRAM bank1 second 16KB section is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
[20] | SRB1S2 | SRAM Bank1 Section 0 BIST Select (Write Protect) This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test. 0 = SRAM bank1 third 16KB section is deselected when doing bist test. 1 = SRAM bank1 third 16KB section is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
[21] | SRB1S3 | SRAM Bank1 Section 1 BIST Select (Write Protect) This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test. 0 = SRAM bank1 fourth 16KB section is deselected when doing bist test. 1 = SRAM bank1 fourth 16KB section is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
[22] | SRB1S4 | SRAM Bank1 Section 0 BIST Select (Write Protect) This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test. 0 = SRAM bank1 fifth 16KB section is deselected when doing bist test. 1 = SRAM bank1 fifth 16KB section is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.
[23] | SRB1S5 | SRAM Bank1 Section 1 BIST Select (Write Protect) This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test. 0 = SRAM bank1 sixth 16KB section is deselected when doing bist test. 1 = SRAM bank1 sixth 16KB section is selected when doing bist test. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test.

Definition at line 4790 of file sys_reg.h.

## ◆ SRAM_BISTSTS

SYS_T::SRAM_BISTSTS

[0x00d4] System SRAM BIST Test Status Register

SRAM_BISTSTS

Offset: 0xD4 System SRAM BIST Test Status Register

Bits | Field | Descriptions
[0] | SRBISTEF0 | 1st System SRAM BIST Fail Flag 0 = 1st system SRAM BIST test pass. 1 = 1st system SRAM BIST test fail.
[1] | SRBISTEF1 | 2nd System SRAM BIST Fail Flag 0 = 2nd system SRAM BIST test pass. 1 = 2nd system SRAM BIST test fail.
[2] | CRBISTEF | CACHE SRAM BIST Fail Flag 0 = System CACHE RAM BIST test pass. 1 = System CACHE RAM BIST test fail.
[3] | CANBEF | CAN SRAM BIST Fail Flag 0 = CAN SRAM BIST test pass. 1 = CAN SRAM BIST test fail.
[4] | USBBEF | USB SRAM BIST Fail Flag 0 = USB SRAM BIST test pass. 1 = USB SRAM BIST test fail.
[16] | SRBEND0 | 1st SRAM BIST Test Finish 0 = 1st system SRAM BIST active. 1 =1st system SRAM BIST finish.
[17] | SRBEND1 | 2nd SRAM BIST Test Finish 0 = 2nd system SRAM BIST is active. 1 = 2nd system SRAM BIST finish.
[18] | CRBEND | CACHE SRAM BIST Test Finish 0 = System CACHE RAM BIST is active. 1 = System CACHE RAM BIST test finish.
[19] | CANBEND | CAN SRAM BIST Test Finish 0 = CAN SRAM BIST is active. 1 = CAN SRAM BIST test finish.
[20] | USBBEND | USB SRAM BIST Test Finish 0 = USB SRAM BIST is active. 1 = USB SRAM BIST test finish.

Definition at line 4791 of file sys_reg.h.

## ◆ SRAM_ERRADDR

SYS_T::SRAM_ERRADDR

[0x00c8] System SRAM Parity Check Error Address Register

SRAM_ERRADDR

Offset: 0xC8 System SRAM Parity Check Error Address Register

Bits | Field | Descriptions
[31:0] | ERRADDR | System SRAM Parity Error Address This register shows system SRAM parity error byte address.

Definition at line 4786 of file sys_reg.h.

## ◆ SRAM_INTCTL

SYS_T::SRAM_INTCTL

[0x00c0] System SRAM Interrupt Enable Control Register

SRAM_INTCTL

Offset: 0xC0 System SRAM Interrupt Enable Control Register

Bits | Field | Descriptions
[0] | PERRIEN | SRAM Parity Check Error Interrupt Enable Bit 0 = SRAM parity check error interrupt Disabled. 1 = SRAM parity check error interrupt Enabled.

Definition at line 4784 of file sys_reg.h.

## ◆ SRAM_STATUS

SYS_T::SRAM_STATUS

[0x00c4] System SRAM Parity Error Status Register

SRAM_STATUS

Offset: 0xC4 System SRAM Parity Error Status Register

Bits | Field | Descriptions
[0] | PERRIF | SRAM Parity Check Error Flag This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 0 = No System SRAM parity error. 1 = System SRAM parity error occur.

Definition at line 4785 of file sys_reg.h.

## ◆ USBPHY

SYS_T::USBPHY

[0x002c] USB PHY Control Register

USBPHY

Offset: 0x2C USB PHY Control Register

Bits | Field | Descriptions
[1:0] | USBROLE | USB Role Option (Write Protect) These two bits are used to select the role of USB. 00 = Standard USB Device mode. 01 = Standard USB Host mode. 10 = ID dependent mode. 11 = Reserved. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] | SBO | Note: This bit must always be kept 1. If set to 0, the result is unpredictable
[8] | USBEN | USB PHY Enable (Write Protect) This bit is used to enable/disable USB PHY. 0 = USB PHY Disabled. 1 = USB PHY Enabled.
[17:16] | HSUSBROLE | HSUSB Role Option (Write Protect) These two bits are used to select the role of HSUSB 00 = Standard HSUSB Device mode. 01 = Standard HSUSB Host mode. 10 = ID dependent mode. 11 = Reserved. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[24] | HSUSBEN | HSUSB PHY Enable (Write Protect) This bit is used to enable/disable HSUSB PHY. 0 = HSUSB PHY Disabled. 1 = HSUSB PHY Enabled.
[25] | HSUSBACT | HSUSB PHY Active Control This bit is used to control HSUSB PHY at reset state or active state. 0 = HSUSB PHY at reset state. 1 = HSUSB PHY at active state. Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode.

Definition at line 4753 of file sys_reg.h.

## ◆ VREFCTL

SYS_T::VREFCTL

[0x0028] VREF Control Register

VREFCTL

Offset: 0x28 VREF Control Register

Bits | Field | Descriptions
[4:0] | VREFCTL | VREF Control Bits (Write Protect) 00000 = VREF is from external pin. 00011 = VREF is internal 1.6V. 00111 = VREF is internal 2.0V. 01011 = VREF is internal 2.5V. 01111 = VREF is internal 3.0V. Others = Reserved. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7:6] | PRELOAD_SEL | Pre-load Timing Selection. 00 = pre-load time is 60us for 0.1uF Capacitor. 01 = pre-load time is 310us for 1uF Capacitor. 10 = pre-load time is 1270us for 4.7uF Capacitor. 11 = pre-load time is 2650us for 10uF Capacitor.

Definition at line 4752 of file sys_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/sys_reg.h