| M480 BSP V3.05.001 The Board Support Package for M480 Series

pdma_reg.h
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1 /**************************************************************************/
9 #ifndef __PDMA_REG_H__
10 #define __PDMA_REG_H__
11
12 #if defined ( __CC_ARM )
13 #pragma anon_unions
14 #endif
15
27 typedef struct
28 {
29
229 __IO uint32_t CTL;
230 __IO uint32_t SA;
231 __IO uint32_t DA;
232 __IO uint32_t NEXT;
233 } DSCT_T;
234
235
236 typedef struct
237 {
282 __IO uint32_t STCR;
283 __IO uint32_t ASOCR;
284 } STRIDE_T;
285
286 typedef struct
287 {
332 __IO uint32_t AICTL;
333 __IO uint32_t RCNT;
334 } REPEAT_T;
335
336 typedef struct
337 {
338
339
1211 DSCT_T DSCT[16];
1212 __I uint32_t CURSCAT[16];
1213 __I uint32_t RESERVE1[176];
1216 __IO uint32_t CHCTL;
1217 __O uint32_t PAUSE;
1218 __O uint32_t SWREQ;
1219 __I uint32_t TRGSTS;
1220 __IO uint32_t PRISET;
1221 __O uint32_t PRICLR;
1222 __IO uint32_t INTEN;
1223 __IO uint32_t INTSTS;
1224 __IO uint32_t ABTSTS;
1225 __IO uint32_t TDSTS;
1226 __IO uint32_t ALIGN;
1227 __I uint32_t TACTSTS;
1228 __IO uint32_t TOUTPSC;
1229 __IO uint32_t TOUTEN;
1230 __IO uint32_t TOUTIEN;
1231 __IO uint32_t SCATBA;
1232 __IO uint32_t TOC0_1;
1233 __I uint32_t RESERVE2[7];
1236 __IO uint32_t CHRST;
1237 __I uint32_t RESERVE3[7];
1240 __IO uint32_t REQSEL0_3;
1241 __IO uint32_t REQSEL4_7;
1242 __IO uint32_t REQSEL8_11;
1243 __IO uint32_t REQSEL12_15;
1244 __I uint32_t RESERVE4[28];
1247 STRIDE_T STRIDE[6];
1249 __IO uint32_t RESERVE5[52];
1251 REPEAT_T REPEAT[2];
1252 } PDMA_T;
1253
1259 #define PDMA_DSCT_CTL_OPMODE_Pos (0)
1260 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos)
1262 #define PDMA_DSCT_CTL_TXTYPE_Pos (2)
1263 #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos)
1265 #define PDMA_DSCT_CTL_BURSIZE_Pos (4)
1266 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos)
1268 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7)
1269 #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos)
1271 #define PDMA_DSCT_CTL_SAINC_Pos (8)
1272 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos)
1274 #define PDMA_DSCT_CTL_DAINC_Pos (10)
1275 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos)
1277 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12)
1278 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos)
1280 #define PDMA_DSCT_CTL_TXACK_Pos (14)
1281 #define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos)
1283 #define PDMA_DSCT_CTL_STRIDEEN_Pos (15)
1284 #define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos)
1286 #define PDMA_DSCT_CTL_TXCNT_Pos (16)
1287 #define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos)
1289 #define PDMA_DSCT_SA_SA_Pos (0)
1290 #define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos)
1292 #define PDMA_DSCT_DA_DA_Pos (0)
1293 #define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos)
1295 #define PDMA_DSCT_NEXT_NEXT_Pos (0)
1296 #define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos)
1298 #define PDMA_DSCT_NEXT_EXENEXT_Pos (16)
1299 #define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos)
1301 #define PDMA_CURSCAT_CURADDR_Pos (0)
1302 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos)
1304 #define PDMA_CHCTL_CHENn_Pos (0)
1305 #define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos)
1307 #define PDMA_PAUSE_PAUSEn_Pos (0)
1308 #define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos)
1310 #define PDMA_SWREQ_SWREQn_Pos (0)
1311 #define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos)
1313 #define PDMA_TRGSTS_REQSTSn_Pos (0)
1314 #define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos)
1316 #define PDMA_PRISET_FPRISETn_Pos (0)
1317 #define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos)
1319 #define PDMA_PRICLR_FPRICLRn_Pos (0)
1320 #define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos)
1322 #define PDMA_INTEN_INTENn_Pos (0)
1323 #define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos)
1325 #define PDMA_INTSTS_ABTIF_Pos (0)
1326 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos)
1328 #define PDMA_INTSTS_TDIF_Pos (1)
1329 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos)
1331 #define PDMA_INTSTS_ALIGNF_Pos (2)
1332 #define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos)
1334 #define PDMA_INTSTS_REQTOF0_Pos (8)
1335 #define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos)
1337 #define PDMA_INTSTS_REQTOF1_Pos (9)
1338 #define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos)
1340 #define PDMA_ABTSTS_ABTIF0_Pos (0)
1341 #define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos)
1343 #define PDMA_ABTSTS_ABTIF1_Pos (1)
1344 #define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos)
1346 #define PDMA_ABTSTS_ABTIF2_Pos (2)
1347 #define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos)
1349 #define PDMA_ABTSTS_ABTIF3_Pos (3)
1350 #define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos)
1352 #define PDMA_ABTSTS_ABTIF4_Pos (4)
1353 #define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos)
1355 #define PDMA_ABTSTS_ABTIF5_Pos (5)
1356 #define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos)
1358 #define PDMA_ABTSTS_ABTIF6_Pos (6)
1359 #define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos)
1361 #define PDMA_ABTSTS_ABTIF7_Pos (7)
1362 #define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos)
1364 #define PDMA_ABTSTS_ABTIF8_Pos (8)
1365 #define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos)
1367 #define PDMA_ABTSTS_ABTIF9_Pos (9)
1368 #define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos)
1370 #define PDMA_ABTSTS_ABTIF10_Pos (10)
1371 #define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos)
1373 #define PDMA_ABTSTS_ABTIF11_Pos (11)
1374 #define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos)
1376 #define PDMA_ABTSTS_ABTIF12_Pos (12)
1377 #define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos)
1379 #define PDMA_ABTSTS_ABTIF13_Pos (13)
1380 #define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos)
1382 #define PDMA_ABTSTS_ABTIF14_Pos (14)
1383 #define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos)
1385 #define PDMA_ABTSTS_ABTIF15_Pos (15)
1386 #define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos)
1388 #define PDMA_TDSTS_TDIF0_Pos (0)
1389 #define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos)
1391 #define PDMA_TDSTS_TDIF1_Pos (1)
1392 #define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos)
1394 #define PDMA_TDSTS_TDIF2_Pos (2)
1395 #define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos)
1397 #define PDMA_TDSTS_TDIF3_Pos (3)
1398 #define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos)
1400 #define PDMA_TDSTS_TDIF4_Pos (4)
1401 #define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos)
1403 #define PDMA_TDSTS_TDIF5_Pos (5)
1404 #define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos)
1406 #define PDMA_TDSTS_TDIF6_Pos (6)
1407 #define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos)
1409 #define PDMA_TDSTS_TDIF7_Pos (7)
1410 #define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos)
1412 #define PDMA_TDSTS_TDIF8_Pos (8)
1413 #define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos)
1415 #define PDMA_TDSTS_TDIF9_Pos (9)
1416 #define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos)
1418 #define PDMA_TDSTS_TDIF10_Pos (10)
1419 #define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos)
1421 #define PDMA_TDSTS_TDIF11_Pos (11)
1422 #define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos)
1424 #define PDMA_TDSTS_TDIF12_Pos (12)
1425 #define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos)
1427 #define PDMA_TDSTS_TDIF13_Pos (13)
1428 #define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos)
1430 #define PDMA_TDSTS_TDIF14_Pos (14)
1431 #define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos)
1433 #define PDMA_TDSTS_TDIF15_Pos (15)
1434 #define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos)
1436 #define PDMA_ALIGN_ALIGNn_Pos (0)
1437 #define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos)
1439 #define PDMA_TACTSTS_TXACTFn_Pos (0)
1440 #define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos)
1442 #define PDMA_TOUTPSC_TOUTPSC0_Pos (0)
1443 #define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos)
1445 #define PDMA_TOUTPSC_TOUTPSC1_Pos (4)
1446 #define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos)
1448 #define PDMA_TOUTEN_TOUTENn_Pos (0)
1449 #define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos)
1451 #define PDMA_TOUTIEN_TOUTIENn_Pos (0)
1452 #define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos)
1454 #define PDMA_SCATBA_SCATBA_Pos (16)
1455 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos)
1457 #define PDMA_TOC0_1_TOC0_Pos (0)
1458 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos)
1460 #define PDMA_TOC0_1_TOC1_Pos (16)
1461 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos)
1463 #define PDMA_CHRST_CHnRST_Pos (0)
1464 #define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos)
1466 #define PDMA_REQSEL0_3_REQSRC0_Pos (0)
1467 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos)
1469 #define PDMA_REQSEL0_3_REQSRC1_Pos (8)
1470 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos)
1472 #define PDMA_REQSEL0_3_REQSRC2_Pos (16)
1473 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos)
1475 #define PDMA_REQSEL0_3_REQSRC3_Pos (24)
1476 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos)
1478 #define PDMA_REQSEL4_7_REQSRC4_Pos (0)
1479 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos)
1481 #define PDMA_REQSEL4_7_REQSRC5_Pos (8)
1482 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos)
1484 #define PDMA_REQSEL4_7_REQSRC6_Pos (16)
1485 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos)
1487 #define PDMA_REQSEL4_7_REQSRC7_Pos (24)
1488 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos)
1490 #define PDMA_REQSEL8_11_REQSRC8_Pos (0)
1491 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos)
1493 #define PDMA_REQSEL8_11_REQSRC9_Pos (8)
1494 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos)
1496 #define PDMA_REQSEL8_11_REQSRC10_Pos (16)
1497 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos)
1499 #define PDMA_REQSEL8_11_REQSRC11_Pos (24)
1500 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos)
1502 #define PDMA_REQSEL12_15_REQSRC12_Pos (0)
1503 #define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos)
1505 #define PDMA_REQSEL12_15_REQSRC13_Pos (8)
1506 #define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos)
1508 #define PDMA_REQSEL12_15_REQSRC14_Pos (16)
1509 #define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos)
1511 #define PDMA_REQSEL12_15_REQSRC15_Pos (24)
1512 #define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos)
1514 #define PDMA_STCRn_STC_Pos (0)
1515 #define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos)
1517 #define PDMA_ASOCRn_SASOL_Pos (0)
1518 #define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos)
1520 #define PDMA_ASOCRn_DASOL_Pos (16)
1521 #define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos)
1523 #define PDMA_RCNTn_RCNT_Pos (0)
1524 #define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos)
1526 #define PDMA_AICTLn_SAICNT_Pos (0)
1527 #define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos)
1529 #define PDMA_AICTLn_DAICNT_Pos (16)
1530 #define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /* PDMA_CONST */
1533 /* end of PDMA register group */ /* end of REGISTER group */
1535
1536 #if defined ( __CC_ARM )
1537 #pragma no_anon_unions
1538 #endif
1539
1540 #endif /* __PDMA_REG_H__ */
DSCT_T::DA
__IO uint32_t DA
Definition: pdma_reg.h:231
PDMA_T::TDSTS
__IO uint32_t TDSTS
Definition: pdma_reg.h:1225
PDMA_T::PRICLR
__O uint32_t PRICLR
Definition: pdma_reg.h:1221
PDMA_T::ABTSTS
__IO uint32_t ABTSTS
Definition: pdma_reg.h:1224
DSCT_T::NEXT
__IO uint32_t NEXT
Definition: pdma_reg.h:232
PDMA_T::SCATBA
__IO uint32_t SCATBA
Definition: pdma_reg.h:1231
DSCT_T::CTL
__IO uint32_t CTL
Definition: pdma_reg.h:229
PDMA_T::CHCTL
__IO uint32_t CHCTL
Definition: pdma_reg.h:1216
REPEAT_T::AICTL
__IO uint32_t AICTL
Definition: pdma_reg.h:332
PDMA_T::TOUTEN
__IO uint32_t TOUTEN
Definition: pdma_reg.h:1229
STRIDE_T::STCR
__IO uint32_t STCR
Definition: pdma_reg.h:282
PDMA_T::PRISET
__IO uint32_t PRISET
Definition: pdma_reg.h:1220
STRIDE_T
Definition: pdma_reg.h:236
PDMA_T::TRGSTS
__I uint32_t TRGSTS
Definition: pdma_reg.h:1219
PDMA_T::REQSEL8_11
__IO uint32_t REQSEL8_11
Definition: pdma_reg.h:1242
PDMA_T::ALIGN
__IO uint32_t ALIGN
Definition: pdma_reg.h:1226
PDMA_T::TACTSTS
__I uint32_t TACTSTS
Definition: pdma_reg.h:1227
PDMA_T
Definition: pdma_reg.h:336
PDMA_T::TOC0_1
__IO uint32_t TOC0_1
Definition: pdma_reg.h:1232
PDMA_T::PAUSE
__O uint32_t PAUSE
Definition: pdma_reg.h:1217
PDMA_T::TOUTPSC
__IO uint32_t TOUTPSC
Definition: pdma_reg.h:1228
PDMA_T::REQSEL0_3
__IO uint32_t REQSEL0_3
Definition: pdma_reg.h:1240
PDMA_T::INTEN
__IO uint32_t INTEN
Definition: pdma_reg.h:1222
PDMA_T::CHRST
__IO uint32_t CHRST
Definition: pdma_reg.h:1236
PDMA_T::TOUTIEN
__IO uint32_t TOUTIEN
Definition: pdma_reg.h:1230
PDMA_T::SWREQ
__O uint32_t SWREQ
Definition: pdma_reg.h:1218
REPEAT_T
Definition: pdma_reg.h:286
REPEAT_T::RCNT
__IO uint32_t RCNT
Definition: pdma_reg.h:333
DSCT_T::SA
__IO uint32_t SA
Definition: pdma_reg.h:230
PDMA_T::REQSEL12_15
__IO uint32_t REQSEL12_15
Definition: pdma_reg.h:1243
PDMA_T::INTSTS
__IO uint32_t INTSTS
Definition: pdma_reg.h:1223
STRIDE_T::ASOCR
__IO uint32_t ASOCR
Definition: pdma_reg.h:283
DSCT_T
Definition: pdma_reg.h:27
PDMA_T::REQSEL4_7
__IO uint32_t REQSEL4_7
Definition: pdma_reg.h:1241