| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
PDMA_T Struct Reference
Control Register

`#include <pdma_reg.h>`

## Data Fields
DSCT_T | DSCT [16]
__I uint32_t | CURSCAT [16]
__IO uint32_t | CHCTL
__O uint32_t | PAUSE
__O uint32_t | SWREQ
__I uint32_t | TRGSTS
__IO uint32_t | PRISET
__O uint32_t | PRICLR
__IO uint32_t | INTEN
__IO uint32_t | INTSTS
__IO uint32_t | ABTSTS
__IO uint32_t | TDSTS
__IO uint32_t | ALIGN
__I uint32_t | TACTSTS
__IO uint32_t | TOUTPSC
__IO uint32_t | TOUTEN
__IO uint32_t | TOUTIEN
__IO uint32_t | SCATBA
__IO uint32_t | TOC0_1
__IO uint32_t | CHRST
__IO uint32_t | REQSEL0_3
__IO uint32_t | REQSEL4_7
__IO uint32_t | REQSEL8_11
__IO uint32_t | REQSEL12_15
STRIDE_T | STRIDE [6]
REPEAT_T | REPEAT [2]

## Detailed Description

Definition at line 336 of file pdma_reg.h.

## Field Documentation

## ◆ ABTSTS

PDMA_T::ABTSTS

[0x0420] PDMA Channel Read/Write Target Abort Flag Register

ABTSTS

Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register

Bits | Field | Descriptions
[15:0] | ABTIFn | PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. 0 = No AHB bus ERROR response received when channel n transfer. 1 = AHB bus ERROR response received when channel n transfer.

Definition at line 1224 of file pdma_reg.h.

## ◆ ALIGN

PDMA_T::ALIGN

[0x0428] PDMA Transfer Alignment Status Register

ALIGN

Offset: 0x428 PDMA Transfer Alignment Status Register

Bits | Field | Descriptions
[15:0] | ALIGNn | Transfer Alignment Flag Register 0 = PDMA channel source address and destination address both follow transfer width setting. 1 = PDMA channel source address or destination address is not follow transfer width setting.

Definition at line 1226 of file pdma_reg.h.

## ◆ CHCTL

PDMA_T::CHCTL

[0x0400] PDMA Channel Control Register

CHCTL

Offset: 0x400 PDMA Channel Control Register

Bits | Field | Descriptions
[15:0] | CHENn | PDMA Channel Enable Bit Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. 0 = PDMA channel [n] Disabled. 1 = PDMA channel [n] Enabled. Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.

Definition at line 1216 of file pdma_reg.h.

## ◆ CHRST

PDMA_T::CHRST

[0x0460] PDMA Channel Reset Register

CHRST

Offset: 0x460 PDMA Channel Reset Register

Bits | Field | Descriptions
[15:0] | CHnRST | Channel N Reset 0 = corresponding channel n not reset. 1 = corresponding channel n is reset.

Definition at line 1236 of file pdma_reg.h.

## ◆ CURSCAT

PDMA_T::CURSCAT

[0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n

CURSCAT

Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n

Bits | Field | Descriptions
[31:0] | CURADDR | PDMA Current Description Address Register (Read Only) This field indicates a 32-bit current external description address of PDMA controller. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.

Definition at line 1212 of file pdma_reg.h.

## ◆ DSCT

DSCT_T PDMA_T::DSCT[16]

Definition at line 1211 of file pdma_reg.h.

## ◆ INTEN

PDMA_T::INTEN

[0x0418] PDMA Interrupt Enable Register

INTEN

Offset: 0x418 PDMA Interrupt Enable Register

Bits | Field | Descriptions
[15:0] | INTENn | PDMA Interrupt Enable Register This field is used for enabling PDMA channel[n] interrupt. 0 = PDMA channel n interrupt Disabled. 1 = PDMA channel n interrupt Enabled.

Definition at line 1222 of file pdma_reg.h.

## ◆ INTSTS

PDMA_T::INTSTS

[0x041c] PDMA Interrupt Status Register

INTSTS

Offset: 0x41C PDMA Interrupt Status Register

Bits | Field | Descriptions
[0] | ABTIF | PDMA Read/Write Target Abort Interrupt Flag (Read-only) This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. 0 = No AHB bus ERROR response received. 1 = AHB bus ERROR response received.
[1] | TDIF | Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. 0 = Not finished yet. 1 = PDMA channel has finished transmission.
[2] | ALIGNF | Transfer Alignment Interrupt Flag (Read Only) 0 = PDMA channel source address and destination address both follow transfer width setting. 1 = PDMA channel source address or destination address is not follow transfer width setting.
[8] | REQTOF0 | Request Time-out Flag for Channel 0 This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. 0 = No request time-out. 1 = Peripheral request time-out.
[9] | REQTOF1 | Request Time-out Flag for Channel 1 This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. 0 = No request time-out. 1 = Peripheral request time-out.

Definition at line 1223 of file pdma_reg.h.

## ◆ PAUSE

PDMA_T::PAUSE

[0x0404] PDMA Transfer Pause Control Register

PAUSE

Offset: 0x404 PDMA Transfer Stop Control Register

Bits | Field | Descriptions
[15:0] | PAUSEn | PDMA Transfer Pause Control Register (Write Only) User can set PAUSEn bit field to pause the PDMA transfer When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag If re-enable the paused channel again, the remaining transfers will be processed. 0 = No effect. 1 = Pause PDMA channel n transfer.

Definition at line 1217 of file pdma_reg.h.

## ◆ PRICLR

PDMA_T::PRICLR

[0x0414] PDMA Fixed Priority Clear Register

PRICLR

Offset: 0x414 PDMA Fixed Priority Clear Register

Bits | Field | Descriptions
[15:0] | FPRICLRn | PDMA Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level. 0 = No effect. 1 = Clear PDMA channel [n] fixed priority setting. Note: User can read PDMA_PRISET register to know the channel priority.

Definition at line 1221 of file pdma_reg.h.

## ◆ PRISET

PDMA_T::PRISET

[0x0410] PDMA Fixed Priority Setting Register

PRISET

Offset: 0x410 PDMA Fixed Priority Setting Register

Bits | Field | Descriptions
[15:0] | FPRISETn | PDMA Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level. Write Operation: 0 = No effect. 1 = Set PDMA channel [n] to fixed priority channel. Read Operation: 0 = Corresponding PDMA channel is round-robin priority. 1 = Corresponding PDMA channel is fixed priority. Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.

Definition at line 1220 of file pdma_reg.h.

## ◆ REPEAT

REPEAT_T PDMA_T::REPEAT[2]

Definition at line 1251 of file pdma_reg.h.

## ◆ REQSEL0_3

PDMA_T::REQSEL0_3

[0x0480] PDMA Request Source Select Register 0

REQSEL0_3

Offset: 0x480 PDMA Request Source Select Register 0

Bits | Field | Descriptions
[6:0] | REQSRC0 | Channel 0 Request Source Selection This filed defines which peripheral is connected to PDMA channel 0 User can configure the peripheral by setting REQSRC0. 0 = Disable PDMA peripheral request. 1 = Reserved. 2 = Channel connects to USB_TX. 3 = Channel connects to USB_RX. 4 = Channel connects to UART0_TX. 5 = Channel connects to UART0_RX. 6 = Channel connects to UART1_TX. 7 = Channel connects to UART1_RX. 8 = Channel connects to UART2_TX. 9 = Channel connects to UART2_RX. 10=Channel connects to UART3_TX. 11 = Channel connects to UART3_RX. 12 = Channel connects to UART4_TX. 13 = Channel connects to UART4_RX. 14 = Channel connects to UART5_TX. 15 = Channel connects to UART5_RX. 16 = Channel connects to USCI0_TX. 17 = Channel connects to USCI0_RX. 18 = Channel connects to USCI1_TX. 19 = Channel connects to USCI1_RX. 20 = Channel connects to QSPI0_TX. 21 = Channel connects to QSPI0_RX. 22 = Channel connects to SPI0_TX. 23 = Channel connects to SPI0_RX. 24 = Channel connects to SPI1_TX. 25 = Channel connects to SPI1_RX. 26 = Channel connects to SPI2_TX. 27 = Channel connects to SPI2_RX. 28 = Channel connects to SPI3_TX. 29 = Channel connects to SPI3_RX. 30 = Reserved. 31 = Reserved. 32 = Channel connects to EPWM0_P1_RX. 33 = Channel connects to EPWM0_P2_RX. 34 = Channel connects to EPWM0_P3_RX. 35 = Channel connects to EPWM1_P1_RX. 36 = Channel connects to EPWM1_P2_RX. 37 = Channel connects to EPWM1_P3_RX. 38 = Channel connects to I2C0_TX. 39 = Channel connects to I2C0_RX. 40 = Channel connects to I2C1_TX. 41 = Channel connects to I2C1_RX. 42 = Channel connects to I2C2_TX. 43 = Channel connects to I2C2_RX. 44 = Channel connects to I2S0_TX. 45 = Channel connects to I2S0_RX. 46 = Channel connects to TMR0. 47 = Channel connects to TMR1. 48 = Channel connects to TMR2. 49 = Channel connects to TMR3. 50 = Channel connects to ADC_RX. 51 = Channel connects to DAC0_TX. 52 = Channel connects to DAC1_TX. 53 = Channel connects to EPWM0_CH0_TX. 54 = Channel connects to EPWM0_CH1_TX. 55 = Channel connects to EPWM0_CH2_TX. 56 = Channel connects to EPWM0_CH3_TX. 57 = Channel connects to EPWM0_CH4_TX. 58 = Channel connects to EPWM0_CH5_TX. 59 = Channel connects to EPWM1_CH0_TX. 60 = Channel connects to EPWM1_CH1_TX. 61 = Channel connects to EPWM1_CH2_TX. 62 = Channel connects to EPWM1_CH3_TX. 63 = Channel connects to EPWM1_CH4_TX. 64 = Channel connects to EPWM1_CH5_TX. 65 = Channel connects to ETMC_RX. Others = Reserved. Note 1: A peripheral can't assign to two channels at the same time. Note 2: This field is useless when transfer between memory and memory.
[14:8] | REQSRC1 | Channel 1 Request Source Selection This filed defines which peripheral is connected to PDMA channel 1 User can configure the peripheral setting by REQSRC1. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[22:16] | REQSRC2 | Channel 2 Request Source Selection This filed defines which peripheral is connected to PDMA channel 2 User can configure the peripheral setting by REQSRC2. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[30:24] | REQSRC3 | Channel 3 Request Source Selection This filed defines which peripheral is connected to PDMA channel 3 User can configure the peripheral setting by REQSRC3. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.

Definition at line 1240 of file pdma_reg.h.

## ◆ REQSEL12_15

PDMA_T::REQSEL12_15

[0x048c] PDMA Request Source Select Register 3

REQSEL12_15

Offset: 0x48C PDMA Request Source Select Register 3

Bits | Field | Descriptions
[6:0] | REQSRC12 | Channel 12 Request Source Selection This filed defines which peripheral is connected to PDMA channel 12 User can configure the peripheral setting by REQSRC12. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[14:8] | REQSRC13 | Channel 13 Request Source Selection This filed defines which peripheral is connected to PDMA channel 13 User can configure the peripheral setting by REQSRC13. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[22:16] | REQSRC14 | Channel 14 Request Source Selection This filed defines which peripheral is connected to PDMA channel 14 User can configure the peripheral setting by REQSRC14. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[30:24] | REQSRC15 | Channel 15 Request Source Selection This filed defines which peripheral is connected to PDMA channel 15 User can configure the peripheral setting by REQSRC15. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.

Definition at line 1243 of file pdma_reg.h.

## ◆ REQSEL4_7

PDMA_T::REQSEL4_7

[0x0484] PDMA Request Source Select Register 1

REQSEL4_7

Offset: 0x484 PDMA Request Source Select Register 1

Bits | Field | Descriptions
[6:0] | REQSRC4 | Channel 4 Request Source Selection This filed defines which peripheral is connected to PDMA channel 4 User can configure the peripheral setting by REQSRC4. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[14:8] | REQSRC5 | Channel 5 Request Source Selection This filed defines which peripheral is connected to PDMA channel 5 User can configure the peripheral setting by REQSRC5. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[22:16] | REQSRC6 | Channel 6 Request Source Selection This filed defines which peripheral is connected to PDMA channel 6 User can configure the peripheral setting by REQSRC6. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[30:24] | REQSRC7 | Channel 7 Request Source Selection This filed defines which peripheral is connected to PDMA channel 7 User can configure the peripheral setting by REQSRC7. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.

Definition at line 1241 of file pdma_reg.h.

## ◆ REQSEL8_11

PDMA_T::REQSEL8_11

[0x0488] PDMA Request Source Select Register 2

REQSEL8_11

Offset: 0x488 PDMA Request Source Select Register 2

Bits | Field | Descriptions
[6:0] | REQSRC8 | Channel 8 Request Source Selection This filed defines which peripheral is connected to PDMA channel 8 User can configure the peripheral setting by REQSRC8. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[14:8] | REQSRC9 | Channel 9 Request Source Selection This filed defines which peripheral is connected to PDMA channel 9 User can configure the peripheral setting by REQSRC9. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[22:16] | REQSRC10 | Channel 10 Request Source Selection This filed defines which peripheral is connected to PDMA channel 10 User can configure the peripheral setting by REQSRC10. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.
[30:24] | REQSRC11 | Channel 11 Request Source Selection This filed defines which peripheral is connected to PDMA channel 11 User can configure the peripheral setting by REQSRC11. Note: The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0.

Definition at line 1242 of file pdma_reg.h.

## ◆ SCATBA

PDMA_T::SCATBA

[0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register

SCATBA

Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register

Bits | Field | Descriptions
[31:16] | SCATBA | PDMA Scatter-gather Descriptor Table Address Register In Scatter-Gather mode, this is the base address for calculating the next link - list address The next link address equation is Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. Note: Only useful in Scatter-Gather mode.

Definition at line 1231 of file pdma_reg.h.

## ◆ STRIDE

STRIDE_T PDMA_T::STRIDE[6]

Definition at line 1247 of file pdma_reg.h.

## ◆ SWREQ

PDMA_T::SWREQ

[0x0408] PDMA Software Request Register

SWREQ

Offset: 0x408 PDMA Software Request Register

Bits | Field | Descriptions
[15:0] | SWREQn | PDMA Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA [n]. 0 = No effect. 1 = Generate a software request. Note1: User can read PDMA_TRGSTS register to know which channel is on active Active flag may be triggered by software request or peripheral request. Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.

Definition at line 1218 of file pdma_reg.h.

## ◆ TACTSTS

PDMA_T::TACTSTS

[0x042c] PDMA Transfer Active Flag Register

TACTSTS

Offset: 0x42C PDMA Transfer Active Flag Register

Bits | Field | Descriptions
[15:0] | TXACTFn | Transfer on Active Flag Register (Read Only) This bit indicates which PDMA channel is in active. 0 = PDMA channel is not finished. 1 = PDMA channel is active.

Definition at line 1227 of file pdma_reg.h.

## ◆ TDSTS

PDMA_T::TDSTS

[0x0424] PDMA Channel Transfer Done Flag Register

TDSTS

Offset: 0x424 PDMA Channel Transfer Done Flag Register

Bits | Field | Descriptions
[15:0] | TDIFn | Transfer Done Flag Register This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 0 = PDMA channel transfer has not finished. 1 = PDMA channel has finished transmission.

Definition at line 1225 of file pdma_reg.h.

## ◆ TOC0_1

PDMA_T::TOC0_1

[0x0440] PDMA Time-out Counter Ch1 and Ch0 Register

TOC0_1

Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register

Bits | Field | Descriptions
[15:0] | TOC0 | Time-out Counter for Channel 0 This controls the period of time-out function for channel 0 The calculation unit is based on 10 kHz clock.
[31:16] | TOC1 | Time-out Counter for Channel 1 This controls the period of time-out function for channel 1 The calculation unit is based on 10 kHz clock.

Definition at line 1232 of file pdma_reg.h.

## ◆ TOUTEN

PDMA_T::TOUTEN

[0x0434] PDMA Time-out Enable Register

TOUTEN

Offset: 0x434 PDMA Time-out Enable Register

Bits | Field | Descriptions
[1:0] | TOUTENn | PDMA Time-out Enable Bits 0 = PDMA Channel n time-out function Disable. 1 = PDMA Channel n time-out function Enable.

Definition at line 1229 of file pdma_reg.h.

## ◆ TOUTIEN

PDMA_T::TOUTIEN

[0x0438] PDMA Time-out Interrupt Enable Register

TOUTIEN

Offset: 0x438 PDMA Time-out Interrupt Enable Register

Bits | Field | Descriptions
[1:0] | TOUTIENn | PDMA Time-out Interrupt Enable Bits 0 = PDMA Channel n time-out interrupt Disable. 1 = PDMA Channel n time-out interrupt Enable.

Definition at line 1230 of file pdma_reg.h.

## ◆ TOUTPSC

PDMA_T::TOUTPSC

[0x0430] PDMA Time-out Prescaler Register

TOUTPSC

Offset: 0x430 PDMA Time-out Prescaler Register

Bits | Field | Descriptions
[2:0] | TOUTPSC0 | PDMA Channel 0 Time-out Clock Source Prescaler Bits 000 = PDMA channel 0 time-out clock source is HCLK/28. 001 = PDMA channel 0 time-out clock source is HCLK/29. 010 = PDMA channel 0 time-out clock source is HCLK/210. 011 = PDMA channel 0 time-out clock source is HCLK/211. 100 = PDMA channel 0 time-out clock source is HCLK/212. 101 = PDMA channel 0 time-out clock source is HCLK/213. 110 = PDMA channel 0 time-out clock source is HCLK/214. 111 = PDMA channel 0 time-out clock source is HCLK/215.
[6:4] | TOUTPSC1 | PDMA Channel 1 Time-out Clock Source Prescaler Bits 000 = PDMA channel 1 time-out clock source is HCLK/28. 001 = PDMA channel 1 time-out clock source is HCLK/29. 010 = PDMA channel 1 time-out clock source is HCLK/210. 011 = PDMA channel 1 time-out clock source is HCLK/211. 100 = PDMA channel 1 time-out clock source is HCLK/212. 101 = PDMA channel 1 time-out clock source is HCLK/213. 110 = PDMA channel 1 time-out clock source is HCLK/214. 111 = PDMA channel 1 time-out clock source is HCLK/215.

Definition at line 1228 of file pdma_reg.h.

## ◆ TRGSTS

PDMA_T::TRGSTS

[0x040c] PDMA Channel Request Status Register

TRGSTS

Offset: 0x40C PDMA Channel Request Status Register

Bits | Field | Descriptions
[15:0] | REQSTSn | PDMA Channel Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral When PDMA controller finishes channel transfer, this bit will be cleared automatically. 0 = PDMA Channel n has no request. 1 = PDMA Channel n has a request. Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.

Definition at line 1219 of file pdma_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/pdma_reg.h