| M480 BSP V3.05.001 The Board Support Package for M480 Series

spim.h
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1 /**************************************************************************/
9 #ifndef __SPIM_H__
10 #define __SPIM_H__
11
12 /*---------------------------------------------------------------------------------------------------------*/
13 /* Include related headers */
14 /*---------------------------------------------------------------------------------------------------------*/
15
16 #ifdef __cplusplus
17 extern "C"
18 {
19 #endif
20
21
35 #define SPIM_DMM_MAP_ADDR 0x8000000UL
36 #define SPIM_DMM_SIZE 0x2000000UL
37 #define SPIM_CCM_ADDR 0x20020000UL
38 #define SPIM_CCM_SIZE 0x8000UL
40 /*---------------------------------------------------------------------------------------------------------*/
41 /* SPIM_CTL0 constant definitions */
42 /*---------------------------------------------------------------------------------------------------------*/
43 #define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos))
44 #define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos)
45 #define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos)
46 #define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos)
47 #define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos)
48 #define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos)
49 #define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos)
50 #define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos)
52 #define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos)
53 #define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos)
54 #define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos)
55 #define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos)
56 #define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos)
58 #define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos)
59 #define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos)
60 #define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos)
61 #define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos)
62 #define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos)
63 #define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos)
64 #define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos)
65 #define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos)
69 typedef enum
70 {
71 MFGID_UNKNOW = 0x00U,
72 MFGID_SPANSION = 0x01U,
73 MFGID_EON = 0x1CU,
74 MFGID_ISSI = 0x7FU,
75 MFGID_MXIC = 0xC2U,
76 MFGID_WINBOND = 0xEFU
77 }
78 E_MFGID;
79
80 /* Flash opcodes. */
81 #define OPCODE_WREN 0x06U /* Write enable */
82 #define OPCODE_RDSR 0x05U /* Read status register #1*/
83 #define OPCODE_WRSR 0x01U /* Write status register #1 */
84 #define OPCODE_RDSR2 0x35U /* Read status register #2*/
85 #define OPCODE_WRSR2 0x31U /* Write status register #2 */
86 #define OPCODE_RDSR3 0x15U /* Read status register #3*/
87 #define OPCODE_WRSR3 0x11U /* Write status register #3 */
88 #define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */
89 #define OPCODE_SE_4K 0x20U /* Erase 4KB sector */
90 #define OPCODE_BE_32K 0x52U /* Erase 32KB block */
91 #define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */
92 #define OPCODE_BE_64K 0xd8U /* Erase 64KB block */
93 #define OPCODE_READ_ID 0x90U /* Read ID */
94 #define OPCODE_RDID 0x9fU /* Read JEDEC ID */
95 #define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */
96 #define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */
97 #define OPCODE_NORM_READ 0x03U /* Read data bytes */
98 #define OPCODE_FAST_READ 0x0bU /* Read data bytes */
99 #define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */
100 #define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */
101
102 /* Used for SST flashes only. */
103 #define OPCODE_BP 0x02U /* Byte program */
104 #define OPCODE_WRDI 0x04U /* Write disable */
105 #define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */
106
107 /* Used for Macronix flashes only. */
108 #define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */
109 #define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */
110
111 #define OPCODE_RDSCUR 0x2bU
112 #define OPCODE_WRSCUR 0x2fU
113
114 #define OPCODE_RSTEN 0x66U
115 #define OPCODE_RST 0x99U
116
117 #define OPCODE_ENQPI 0x38U
118 #define OPCODE_EXQPI 0xFFU
119
120 /* Status Register bits. */
121 #define SR_WIP 0x1U /* Write in progress */
122 #define SR_WEL 0x2U /* Write enable latch */
123 #define SR_QE 0x40U /* Quad Enable for MXIC */
124 /* Status Register #2 bits. */
125 #define SR2_QE 0x2U /* Quad Enable for Winbond */
126 /* meaning of other SR_* bits may differ between vendors */
127 #define SR_BP0 0x4U /* Block protect 0 */
128 #define SR_BP1 0x8U /* Block protect 1 */
129 #define SR_BP2 0x10U /* Block protect 2 */
130 #define SR_SRWD 0x80U /* SR write protect */
131 #define SR3_ADR 0x01U /* 4-byte u32Address mode */
132
133 #define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */
134
137 /* end of group SPIM_EXPORTED_CONSTANTS */
138
139
145 /*---------------------------------------------------------------------------------------------------------*/
146 /* Define Macros and functions */
147 /*---------------------------------------------------------------------------------------------------------*/
148
153 #define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk)
154
159 #define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk)
160
165 #define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk)
166
171 #define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk)
172
177 #define SPIM_SET_4BYTE_ADDR_EN(x) \
178 do { \
179 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \
180 } while (0)
181
186 #define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk)
187
192 #define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk)
193
198 #define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL)
199
204 #define SPIM_CLR_INT() \
205 do { \
206 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \
207 } while (0)
208
213 #define SPIM_SET_DATA_WIDTH(x) \
214 do { \
215 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \
216 } while (0)
217
222 #define SPIM_GET_DATA_WIDTH() \
223 (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U)
224
229 #define SPIM_SET_DATA_NUM(x) \
230 do { \
231 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \
232 } while (0)
233
238 #define SPIM_GET_DATA_NUM() \
239 (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U)
240
245 #define SPIM_ENABLE_SING_INPUT_MODE() \
246 do { \
247 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \
248 } while (0)
249
254 #define SPIM_ENABLE_SING_OUTPUT_MODE() \
255 do { \
256 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \
257 } while (0)
258
263 #define SPIM_ENABLE_DUAL_INPUT_MODE() \
264 do { \
265 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \
266 } while (0)
267
272 #define SPIM_ENABLE_DUAL_OUTPUT_MODE() \
273 do { \
274 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \
275 } while (0)
276
281 #define SPIM_ENABLE_QUAD_INPUT_MODE() \
282 do { \
283 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \
284 } while (0)
285
290 #define SPIM_ENABLE_QUAD_OUTPUT_MODE() \
291 do { \
292 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \
293 } while (0)
294
299 #define SPIM_SET_SUSP_INTVL(x) \
300 do { \
301 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \
302 } while (0)
303
308 #define SPIM_GET_SUSP_INTVL() \
309 ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos)
310
315 #define SPIM_SET_OPMODE(x) \
316 do { \
317 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \
318 } while (0)
319
324 #define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk)
325
330 #define SPIM_SET_SPIM_MODE(x) \
331 do { \
332 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \
333 } while (0)
334
339 #define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk)
340
345 #define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk)
346
351 #define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk)
352
357 #define SPIM_WAIT_FREE() \
358 do { \
359 while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \
360 } while (0)
361
366 #define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk)
367
372 #define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk)
373
378 #define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1)
379
384 #define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk)
385
390 #define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk)
391
396 #define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos)
397
402 #define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk)
403
408 #define SPIM_SET_SS_EN(x) \
409 do { \
410 (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \
411 } while (0)
412
417 #define SPIM_GET_SS_EN() \
418 (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk))
419
424 #define SPIM_SET_SS_ACTLVL(x) \
425 do { \
426 (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \
427 } while (0)
428
433 #define SPIM_SET_IDL_INTVL(x) \
434 do { \
435 SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \
436 } while (0)
437
442 #define SPIM_GET_IDL_INTVL() \
443 ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos)
444
449 #define SPIM_SET_CLOCK_DIVIDER(x) \
450 do { \
451 SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \
452 } while (0)
453
458 #define SPIM_GET_CLOCK_DIVIDER() \
459 ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos)
460
465 #define SPIM_SET_RXCLKDLY_DWDELSEL(x) \
466 do { \
467 (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \
468 } while (0)
469
474 #define SPIM_GET_RXCLKDLY_DWDELSEL() \
475 ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos)
476
481 #define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \
482 do { \
483 (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \
484 } while (0)
485
490 #define SPIM_GET_RXCLKDLY_RDDLYSEL() \
491 ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos)
492
497 #define SPIM_SET_RXCLKDLY_RDEDGE() \
498 (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \
499
500
504 #define SPIM_CLR_RXCLKDLY_RDEDGE() \
505 (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk)
506
511 #define SPIM_SET_DMMCTL_CRMDAT(x) \
512 do { \
513 (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \
514 } while (0)
515
520 #define SPIM_GET_DMMCTL_CRMDAT() \
521 ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos)
522
527 #define SPIM_DMM_SET_DESELTIM(x) \
528 do { \
529 SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \
530 } while (0)
531
536 #define SPIM_DMM_GET_DESELTIM() \
537 ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos)
538
543 #define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk)
544
549 #define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk)
550
555 #define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk)
556
561 #define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk)
562
567 #define SPIM_DMM_SET_ACTSCLKT(x) \
568 do { \
569 SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \
570 } while (0)
571
576 #define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk)
577
582 #define SPIM_SET_DCNUM(x) \
583 do { \
584 SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \
585 } while (0)
586
591 #define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk)
592
593
594
595 /*---------------------------------------------------------------------------------------------------------*/
596 /* Define Function Prototypes */
597 /*---------------------------------------------------------------------------------------------------------*/
598
599
600 int SPIM_InitFlash(int clrWP);
601 uint32_t SPIM_GetSClkFreq(void);
602 void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit);
603 int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit);
604 int SPIM_Is4ByteModeEnable(uint32_t u32NBit);
605
606 void SPIM_ChipErase(uint32_t u32NBit, int isSync);
607 void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync);
608
609 void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat);
610 void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy);
611
612 void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd);
613 void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync);
614
615 void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl);
616 void SPIM_ExitDirectMapMode(void);
617
618 void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit);
619
620 void SPIM_WinbondUnlock(uint32_t u32NBit);
621 /* end of group SPIM_EXPORTED_FUNCTIONS */
623 /* end of group SPIM_Driver */
625 /* end of group Standard_Driver */
627
628 #ifdef __cplusplus
629 }
630 #endif
631
632 #endif /* __SPIM_H__ */
633
634 /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
SPIM_EnterDirectMapMode
void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl)
Enter Direct Map mode.
Definition: spim.c:1284
SPIM_IO_Write
void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat)
Write data to SPI Flash by sending commands manually (I/O mode).
Definition: spim.c:1104
SPIM_ExitDirectMapMode
void SPIM_ExitDirectMapMode(void)
Exit Direct Map mode.
Definition: spim.c:1296
SPIM_InitFlash
int SPIM_InitFlash(int clrWP)
Initialize SPIM flash.
Definition: spim.c:492
SPIM_Is4ByteModeEnable
int SPIM_Is4ByteModeEnable(uint32_t u32NBit)
SPIM_Enable_4Bytes_Mode
int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit)
Enter/Exit 4-byte address mode.
Definition: spim.c:832
SPIM_DMA_Write
void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd)
Write data to SPI Flash by Page Write mode.
Definition: spim.c:1210
SPIM_SetQuadEnable
void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit)
Set Quad Enable/disable.
Definition: spim.c:650
SPIM_ChipErase
void SPIM_ChipErase(uint32_t u32NBit, int isSync)
Erase whole chip.
Definition: spim.c:926
SPIM_DMA_Read
void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync)
Read data from SPI Flash by Page Read mode.
Definition: spim.c:1259
SPIM_IO_Read
void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy)
Read data from SPI Flash by sending commands manually (I/O mode).
Definition: spim.c:1157
SPIM_EraseBlock
void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync)
Erase one block.
Definition: spim.c:953
SPIM_GetSClkFreq
uint32_t SPIM_GetSClkFreq(void)
Get SPIM serial clock.
Definition: spim.c:479
SPIM_WinbondUnlock
void SPIM_WinbondUnlock(uint32_t u32NBit)
Definition: spim.c:893
SPIM_ReadJedecId
void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit)
Issue JEDEC ID command.
Definition: spim.c:566