| M480 BSP V3.05.001 The Board Support Package for M480 Series

uart.c
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1 /**************************************************************************/
10 #include <stdio.h>
11 #include "NuMicro.h"
12
41 void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag)
42 {
43
44 if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
45 {
46 uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk;
47 uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
48 }
49
50 if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */
51 {
52 uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
53 }
54 else
55 {
56 }
57
58 if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
59 {
60 uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
61 }
62
63 if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */
64 {
65 uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk |
66 UART_WKSTS_RFRTWKF_Msk |UART_WKSTS_RS485WKF_Msk |
67 UART_WKSTS_TOUTWKF_Msk;
68 }
69
70 if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */
71 {
72 uart->INTSTS = UART_INTSTS_LINIF_Msk;
73 uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk |
74 UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
75 UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ;
76 }
77 }
78
79
89 void UART_Close(UART_T* uart)
90 {
91 uart->INTEN = 0ul;
92 }
93
94
104 void UART_DisableFlowCtrl(UART_T* uart)
105 {
106 uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
107 }
108
109
128 void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)
129 {
130 /* Disable UART specified interrupt */
131 UART_DISABLE_INT(uart, u32InterruptFlag);
132 }
133
134
144 void UART_EnableFlowCtrl(UART_T* uart)
145 {
146 /* Set RTS pin output is low level active */
147 uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
148
149 /* Set CTS pin input is low level active */
150 uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
151
152 /* Set RTS and CTS auto flow control enable */
153 uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
154 }
155
156
175 void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)
176 {
177 /* Enable UART specified interrupt */
178 UART_ENABLE_INT(uart, u32InterruptFlag);
179 }
180
181
192 void UART_Open(UART_T* uart, uint32_t u32baudrate)
193 {
194 uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
195 uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC};
196 uint32_t u32Baud_Div = 0ul;
197
198
199 if(uart==(UART_T*)UART0)
200 {
201 /* Get UART clock source selection */
202 u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
203 /* Get UART clock divider number */
204 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
205 }
206 else if(uart==(UART_T*)UART1)
207 {
208 /* Get UART clock source selection */
209 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
210 /* Get UART clock divider number */
211 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
212 }
213 else if(uart==(UART_T*)UART2)
214 {
215 /* Get UART clock source selection */
216 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
217 /* Get UART clock divider number */
218 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
219 }
220 else if(uart==(UART_T*)UART3)
221 {
222 /* Get UART clock source selection */
223 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
224 /* Get UART clock divider number */
225 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
226 }
227 else if(uart==(UART_T*)UART4)
228 {
229 /* Get UART clock source selection */
230 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
231 /* Get UART clock divider number */
232 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
233 }
234 else if(uart==(UART_T*)UART5)
235 {
236 /* Get UART clock source selection */
237 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
238 /* Get UART clock divider number */
239 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
240 }
241
242 /* Select UART function */
243 uart->FUNCSEL = UART_FUNCSEL_UART;
244
245 /* Set UART line configuration */
246 uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
247
248 /* Set UART Rx and RTS trigger level */
249 uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
250
251 /* Get PLL clock frequency if UART clock source selection is PLL */
252 if(u32UartClkSrcSel == 1ul)
253 {
254 u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
255 }
256
257 /* Set UART baud rate */
258 if(u32baudrate != 0ul)
259 {
260 u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
261
262 if(u32Baud_Div > 0xFFFFul)
263 {
264 uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
265 }
266 else
267 {
268 uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
269 }
270 }
271 }
272
273
285 uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
286 {
287 uint32_t u32Count, u32delayno;
288 uint32_t u32Exit = 0ul;
289
290 for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
291 {
292 u32delayno = 0ul;
293
294 while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
295 {
296 u32delayno++;
297 if(u32delayno >= 0x40000000ul)
298 {
299 u32Exit = 1ul;
300 break;
301 }
302 else
303 {
304 }
305 }
306
307 if(u32Exit == 1ul)
308 {
309 break;
310 }
311 else
312 {
313 pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */
314 }
315 }
316
317 return u32Count;
318
319 }
320
321
348 void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
349 {
350 uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
351 uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
352 uint32_t u32Baud_Div = 0ul;
353
354
355 if(uart==(UART_T*)UART0)
356 {
357 /* Get UART clock source selection */
358 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
359 /* Get UART clock divider number */
360 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
361 }
362 else if(uart==(UART_T*)UART1)
363 {
364 /* Get UART clock source selection */
365 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
366 /* Get UART clock divider number */
367 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
368 }
369 else if(uart==(UART_T*)UART2)
370 {
371 /* Get UART clock source selection */
372 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
373 /* Get UART clock divider number */
374 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
375 }
376 else if(uart==(UART_T*)UART3)
377 {
378 /* Get UART clock source selection */
379 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
380 /* Get UART clock divider number */
381 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
382 }
383 else if(uart==(UART_T*)UART4)
384 {
385 /* Get UART clock source selection */
386 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
387 /* Get UART clock divider number */
388 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
389 }
390 else if(uart==(UART_T*)UART5)
391 {
392 /* Get UART clock source selection */
393 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
394 /* Get UART clock divider number */
395 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
396 }
397
398 /* Get PLL clock frequency if UART clock source selection is PLL */
399 if(u32UartClkSrcSel == 1ul)
400 {
401 u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
402 }
403 else
404 {
405 }
406
407 /* Set UART baud rate */
408 if(u32baudrate != 0ul)
409 {
410 u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
411
412 if(u32Baud_Div > 0xFFFFul)
413 {
414 uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
415 }
416 else
417 {
418 uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
419 }
420 }
421
422 /* Set UART line configuration */
423 uart->LINE = u32data_width | u32parity | u32stop_bits;
424 }
425
426
437 void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
438 {
439 /* Set time-out interrupt comparator */
440 uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
441
442 /* Set time-out counter enable */
443 uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
444 }
445
446
460 void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
461 {
462 uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul;
463 uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC};
464 uint32_t u32Baud_Div;
465
466 /* Select IrDA function mode */
467 uart->FUNCSEL = UART_FUNCSEL_IrDA;
468
469
470 if(uart==UART0)
471 {
472 /* Get UART clock source selection */
473 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
474 /* Get UART clock divider number */
475 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
476 }
477 else if(uart==UART1)
478 {
479 /* Get UART clock source selection */
480 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
481 /* Get UART clock divider number */
482 u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
483 }
484 else if(uart==UART2)
485 {
486 /* Get UART clock source selection */
487 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
488 /* Get UART clock divider number */
489 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
490 }
491 else if(uart==UART3)
492 {
493 /* Get UART clock source selection */
494 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos;
495 /* Get UART clock divider number */
496 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos;
497 }
498 else if(uart==UART4)
499 {
500 /* Get UART clock source selection */
501 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos;
502 /* Get UART clock divider number */
503 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos;
504 }
505 else if(uart==UART5)
506 {
507 /* Get UART clock source selection */
508 u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos;
509 /* Get UART clock divider number */
510 u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos;
511 }
512
513
514 /* Get PLL clock frequency if UART clock source selection is PLL */
515 if(u32UartClkSrcSel == 1ul)
516 {
517 u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
518 }
519 else
520 {
521 }
522
523 /* Set UART IrDA baud rate in mode 0 */
524 if(u32Buadrate != 0ul)
525 {
526 u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
527
528 if(u32Baud_Div < 0xFFFFul)
529 {
530 uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
531 }
532 else
533 {
534 }
535 }
536
537 /* Configure IrDA relative settings */
538 if(u32Direction == UART_IRDA_RXEN)
539 {
540 uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/
541 uart->IRDA &= ~UART_IRDA_TXEN_Msk;
542 }
543 else
544 {
545 uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/
546 uart->IRDA |= UART_IRDA_TXEN_Msk;
547 }
548
549 }
550
551
566 void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
567 {
568 /* Select UART RS485 function mode */
569 uart->FUNCSEL = UART_FUNCSEL_RS485;
570
571 /* Set RS585 configuration */
572 uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
573 uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
574 }
575
576
590 void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
591 {
592 /* Select LIN function mode */
593 uart->FUNCSEL = UART_FUNCSEL_LIN;
594
595 /* Select LIN function setting : Tx enable, Rx enable and break field length */
596 uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
597 uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
598 }
599
600
612 uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
613 {
614 uint32_t u32Count, u32delayno;
615 uint32_t u32Exit = 0ul;
616
617 for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
618 {
619 u32delayno = 0ul;
620 while(uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Check Tx Full */
621 {
622 u32delayno++;
623 if(u32delayno >= 0x40000000ul)
624 {
625 u32Exit = 1ul;
626 break;
627 }
628 else
629 {
630 }
631 }
632
633 if(u32Exit == 1ul)
634 {
635 break;
636 }
637 else
638 {
639 uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
640 }
641 }
642
643 return u32Count;
644 }
645
646 /* end of group UART_EXPORTED_FUNCTIONS */
648 /* end of group UART_Driver */
650 /* end of group Standard_Driver */
652
653 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
654
655
656
UART_WKSTS_RS485WKF_Msk
#define UART_WKSTS_RS485WKF_Msk
Definition: uart_reg.h:2249
UART_WORD_LEN_8
#define UART_WORD_LEN_8
Definition: uart.h:62
UART_T::ALTCTL
__IO uint32_t ALTCTL
Definition: uart_reg.h:1833
UART_ALTCTL_BRKFL_Msk
#define UART_ALTCTL_BRKFL_Msk
Definition: uart_reg.h:2120
UART_INTSTS_RLSINT_Msk
#define UART_INTSTS_RLSINT_Msk
Definition: uart_reg.h:2042
CLK_CLKSEL1_UART1SEL_Msk
#define CLK_CLKSEL1_UART1SEL_Msk
Definition: clk_reg.h:2544
UART_IRDA_RXINV_Msk
#define UART_IRDA_RXINV_Msk
Definition: uart_reg.h:2117
UART_FIFO_RTSTRGLV_Msk
#define UART_FIFO_RTSTRGLV_Msk
Definition: uart_reg.h:1913
UART_ALTCTL_ADDRMV_Pos
#define UART_ALTCTL_ADDRMV_Pos
Definition: uart_reg.h:2149
UART_FIFOSTS_RXOVIF_Msk
#define UART_FIFOSTS_RXOVIF_Msk
Definition: uart_reg.h:1961
CLK
#define CLK
Definition: M480.h:368
UART_FIFOSTS_TXOVIF_Msk
#define UART_FIFOSTS_TXOVIF_Msk
Definition: uart_reg.h:2000
UART_EnableFlowCtrl
void UART_EnableFlowCtrl(UART_T *uart)
Enable UART auto flow control function.
Definition: uart.c:144
CLK_CLKDIV4_UART4DIV_Msk
#define CLK_CLKDIV4_UART4DIV_Msk
Definition: clk_reg.h:2667
CLK_CLKDIV0_UART0DIV_Pos
#define CLK_CLKDIV0_UART0DIV_Pos
Definition: clk_reg.h:2621
CLK_CLKSEL3_UART2SEL_Pos
#define CLK_CLKSEL3_UART2SEL_Pos
Definition: clk_reg.h:2603
UART_ALTCTL_BRKFL_Pos
#define UART_ALTCTL_BRKFL_Pos
Definition: uart_reg.h:2119
CLK_CLKSEL3_UART4SEL_Pos
#define CLK_CLKSEL3_UART4SEL_Pos
Definition: clk_reg.h:2609
UART4
#define UART4
Definition: M480.h:433
UART_BAUD_MODE2_DIVIDER
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate)
Calculate UART baudrate mode2 divider.
Definition: uart.h:149
CLK_CLKSEL3_UART5SEL_Msk
#define CLK_CLKSEL3_UART5SEL_Msk
Definition: clk_reg.h:2613
UART_TOUT_TOIC_Msk
#define UART_TOUT_TOIC_Msk
Definition: uart_reg.h:2093
UART_INTEN_ATORTSEN_Msk
#define UART_INTEN_ATORTSEN_Msk
Definition: uart_reg.h:1883
UART_ENABLE_INT
#define UART_ENABLE_INT(uart, u32eIntSel)
Enable specified UART interrupt.
Definition: uart.h:325
CLK_CLKDIV0_UART0DIV_Msk
#define CLK_CLKDIV0_UART0DIV_Msk
Definition: clk_reg.h:2622
UART_T::MODEMSTS
__IO uint32_t MODEMSTS
Definition: uart_reg.h:1827
UART3
#define UART3
Definition: M480.h:432
UART_ALTCTL_RS485AUD_Msk
#define UART_ALTCTL_RS485AUD_Msk
Definition: uart_reg.h:2135
UART_FUNCSEL_UART
#define UART_FUNCSEL_UART
Definition: uart.h:92
UART_T::IRDA
__IO uint32_t IRDA
Definition: uart_reg.h:1832
UART_IRDA_TXINV_Msk
#define UART_IRDA_TXINV_Msk
Definition: uart_reg.h:2114
CLK_CLKSEL1_UART0SEL_Msk
#define CLK_CLKSEL1_UART0SEL_Msk
Definition: clk_reg.h:2541
UART_WKSTS_CTSWKF_Msk
#define UART_WKSTS_CTSWKF_Msk
Definition: uart_reg.h:2240
UART_T::LINSTS
__IO uint32_t LINSTS
Definition: uart_reg.h:1836
UART_DisableFlowCtrl
void UART_DisableFlowCtrl(UART_T *uart)
Disable UART auto flow control function.
Definition: uart.c:104
UART_MODEMSTS_CTSACTLV_Msk
#define UART_MODEMSTS_CTSACTLV_Msk
Definition: uart_reg.h:1958
UART_MODEM_RTSACTLV_Msk
#define UART_MODEM_RTSACTLV_Msk
Definition: uart_reg.h:1946
UART_LINSTS_SLVIDPEF_Msk
#define UART_LINSTS_SLVIDPEF_Msk
Definition: uart_reg.h:2207
UART_INTSTS_WKINT_Msk
#define UART_INTSTS_WKINT_Msk
Definition: uart_reg.h:2054
CLK_CLKDIV4_UART3DIV_Msk
#define CLK_CLKDIV4_UART3DIV_Msk
Definition: clk_reg.h:2664
UART_FIFO_RFITL_Msk
#define UART_FIFO_RFITL_Msk
Definition: uart_reg.h:1907
UART_LINSTS_SLVHDETF_Msk
#define UART_LINSTS_SLVHDETF_Msk
Definition: uart_reg.h:2201
UART_LINSTS_BITEF_Msk
#define UART_LINSTS_BITEF_Msk
Definition: uart_reg.h:2216
NuMicro.h
NuMicro peripheral access layer header file.
UART_WKSTS_TOUTWKF_Msk
#define UART_WKSTS_TOUTWKF_Msk
Definition: uart_reg.h:2252
UART_BAUD_MODE0
#define UART_BAUD_MODE0
Definition: uart.h:112
UART_BAUD_MODE0_DIVIDER
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate)
Calculate UART baudrate mode0 divider.
Definition: uart.h:135
UART_ALTCTL_LINRXEN_Msk
#define UART_ALTCTL_LINRXEN_Msk
Definition: uart_reg.h:2123
UART_FIFOSTS_FEF_Msk
#define UART_FIFOSTS_FEF_Msk
Definition: uart_reg.h:1976
UART_T::INTEN
__IO uint32_t INTEN
Definition: uart_reg.h:1823
UART_ALTCTL_RS485AAD_Msk
#define UART_ALTCTL_RS485AAD_Msk
Definition: uart_reg.h:2132
UART_IRDA_RXEN
#define UART_IRDA_RXEN
Definition: uart.h:86
UART_INTEN_TOCNTEN_Msk
#define UART_INTEN_TOCNTEN_Msk
Definition: uart_reg.h:1880
CLK_CLKDIV4_UART4DIV_Pos
#define CLK_CLKDIV4_UART4DIV_Pos
Definition: clk_reg.h:2666
UART_DisableInt
void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag)
Disable UART specified interrupt.
Definition: uart.c:128
UART_SelectIrDAMode
void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction)
Select and configure IrDA function.
Definition: uart.c:460
UART_STOP_BIT_1
#define UART_STOP_BIT_1
Definition: uart.h:70
UART_WKSTS_DATWKF_Msk
#define UART_WKSTS_DATWKF_Msk
Definition: uart_reg.h:2243
UART_FIFOSTS_PEF_Msk
#define UART_FIFOSTS_PEF_Msk
Definition: uart_reg.h:1973
UART_FIFOSTS_BIF_Msk
#define UART_FIFOSTS_BIF_Msk
Definition: uart_reg.h:1979
UART_INTSTS_LINIF_Msk
#define UART_INTSTS_LINIF_Msk
Definition: uart_reg.h:2033
UART_INTSTS_MODEMINT_Msk
#define UART_INTSTS_MODEMINT_Msk
Definition: uart_reg.h:2045
CLK_CLKDIV0_UART1DIV_Pos
#define CLK_CLKDIV0_UART1DIV_Pos
Definition: clk_reg.h:2624
UART1
#define UART1
Definition: M480.h:430
UART_SelectLINMode
void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength)
Select and configure LIN function.
Definition: uart.c:590
UART_SetLineConfig
void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
Set UART line configuration.
Definition: uart.c:348
UART_T::BAUD
__IO uint32_t BAUD
Definition: uart_reg.h:1831
UART_DISABLE_INT
#define UART_DISABLE_INT(uart, u32eIntSel)
Disable specified UART interrupt.
Definition: uart.h:348
UART5
#define UART5
Definition: M480.h:434
UART_LINSTS_SLVSYNCF_Msk
#define UART_LINSTS_SLVSYNCF_Msk
Definition: uart_reg.h:2210
UART_T::DAT
__IO uint32_t DAT
Definition: uart_reg.h:1822
UART_FIFOSTS_ADDRDETF_Msk
#define UART_FIFOSTS_ADDRDETF_Msk
Definition: uart_reg.h:1970
UART_ALTCTL_RS485NMM_Msk
#define UART_ALTCTL_RS485NMM_Msk
Definition: uart_reg.h:2129
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1188
UART_T::INTSTS
__IO uint32_t INTSTS
Definition: uart_reg.h:1829
UART_IRDA_TXEN_Msk
#define UART_IRDA_TXEN_Msk
Definition: uart_reg.h:2111
CLK_CLKSEL3_UART3SEL_Msk
#define CLK_CLKSEL3_UART3SEL_Msk
Definition: clk_reg.h:2607
UART_PARITY_NONE
#define UART_PARITY_NONE
Definition: uart.h:64
UART_FUNCSEL_LIN
#define UART_FUNCSEL_LIN
Definition: uart.h:93
UART_SelectRS485Mode
void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr)
Select and configure RS485 function.
Definition: uart.c:566
UART_Close
void UART_Close(UART_T *uart)
Disable UART interrupt.
Definition: uart.c:89
UART0
#define UART0
Definition: M480.h:429
UART_WKSTS_RFRTWKF_Msk
#define UART_WKSTS_RFRTWKF_Msk
Definition: uart_reg.h:2246
UART_INTEN_ATOCTSEN_Msk
#define UART_INTEN_ATOCTSEN_Msk
Definition: uart_reg.h:1886
UART_MODEMSTS_CTSDETF_Msk
#define UART_MODEMSTS_CTSDETF_Msk
Definition: uart_reg.h:1952
CLK_CLKSEL3_UART5SEL_Pos
#define CLK_CLKSEL3_UART5SEL_Pos
Definition: clk_reg.h:2612
UART_LINSTS_BRKDETF_Msk
#define UART_LINSTS_BRKDETF_Msk
Definition: uart_reg.h:2213
UART_Write
uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
Write UART data.
Definition: uart.c:612
UART_FUNCSEL_IrDA
#define UART_FUNCSEL_IrDA
Definition: uart.h:94
UART_BAUD_MODE2
#define UART_BAUD_MODE2
Definition: uart.h:113
UART_T::TOUT
__IO uint32_t TOUT
Definition: uart_reg.h:1830
CLK_CLKDIV4_UART3DIV_Pos
#define CLK_CLKDIV4_UART3DIV_Pos
Definition: clk_reg.h:2663
UART_T::LINE
__IO uint32_t LINE
Definition: uart_reg.h:1825
CLK_CLKDIV0_UART1DIV_Msk
#define CLK_CLKDIV0_UART1DIV_Msk
Definition: clk_reg.h:2625
UART_LINSTS_SLVHEF_Msk
#define UART_LINSTS_SLVHEF_Msk
Definition: uart_reg.h:2204
UART_FUNCSEL_RS485
#define UART_FUNCSEL_RS485
Definition: uart.h:95
CLK_CLKDIV4_UART5DIV_Msk
#define CLK_CLKDIV4_UART5DIV_Msk
Definition: clk_reg.h:2670
CLK_CLKDIV4_UART2DIV_Msk
#define CLK_CLKDIV4_UART2DIV_Msk
Definition: clk_reg.h:2661
CLK_CLKDIV4_UART5DIV_Pos
#define CLK_CLKDIV4_UART5DIV_Pos
Definition: clk_reg.h:2669
CLK_CLKSEL3_UART3SEL_Pos
#define CLK_CLKSEL3_UART3SEL_Pos
Definition: clk_reg.h:2606
UART_FIFOSTS_RXEMPTY_Msk
#define UART_FIFOSTS_RXEMPTY_Msk
Definition: uart_reg.h:1985
UART_ALTCTL_LINTXEN_Msk
#define UART_ALTCTL_LINTXEN_Msk
Definition: uart_reg.h:2126
__LXT
#define __LXT
Definition: system_M480.h:33
__HIRC
#define __HIRC
Definition: system_M480.h:36
CLK_CLKSEL1_UART1SEL_Pos
#define CLK_CLKSEL1_UART1SEL_Pos
Definition: clk_reg.h:2543
UART_INTSTS_LININT_Msk
#define UART_INTSTS_LININT_Msk
Definition: uart_reg.h:2057
UART_Open
void UART_Open(UART_T *uart, uint32_t u32baudrate)
Open and set UART function.
Definition: uart.c:192
UART_INTSTS_BUFERRINT_Msk
#define UART_INTSTS_BUFERRINT_Msk
Definition: uart_reg.h:2051
UART_T
Definition: uart_reg.h:26
UART_ALTCTL_ADDRMV_Msk
#define UART_ALTCTL_ADDRMV_Msk
Definition: uart_reg.h:2150
CLK_CLKSEL1_UART0SEL_Pos
#define CLK_CLKSEL1_UART0SEL_Pos
Definition: clk_reg.h:2540
UART_T::FUNCSEL
__IO uint32_t FUNCSEL
Definition: uart_reg.h:1834
UART_T::MODEM
__IO uint32_t MODEM
Definition: uart_reg.h:1826
UART_EnableInt
void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag)
The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
Definition: uart.c:175
CLK_CLKSEL3_UART4SEL_Msk
#define CLK_CLKSEL3_UART4SEL_Msk
Definition: clk_reg.h:2610
UART_ClearIntFlag
void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag)
Clear UART specified interrupt flag.
Definition: uart.c:41
UART_T::FIFOSTS
__IO uint32_t FIFOSTS
Definition: uart_reg.h:1828
UART2
#define UART2
Definition: M480.h:431
CLK_CLKSEL3_UART2SEL_Msk
#define CLK_CLKSEL3_UART2SEL_Msk
Definition: clk_reg.h:2604
UART_Read
uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
Read UART data.
Definition: uart.c:285
UART_SetTimeoutCnt
void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC)
Set Rx timeout count.
Definition: uart.c:437
__HXT
#define __HXT
Definition: system_M480.h:29
UART_T::FIFO
__IO uint32_t FIFO
Definition: uart_reg.h:1824
CLK_CLKDIV4_UART2DIV_Pos
#define CLK_CLKDIV4_UART2DIV_Pos
Definition: clk_reg.h:2660
UART_FIFOSTS_TXFULL_Msk
#define UART_FIFOSTS_TXFULL_Msk
Definition: uart_reg.h:1997
UART_T::WKSTS
__IO uint32_t WKSTS
Definition: uart_reg.h:1839