| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
CAN_T Struct Reference
Control Register

`#include <can_reg.h>`

## Data Fields
__IO uint32_t | CON
__IO uint32_t | STATUS
__I uint32_t | ERR
__IO uint32_t | BTIME
__I uint32_t | IIDR
__IO uint32_t | TEST
__IO uint32_t | BRPE
__IO CAN_IF_T | IF [2]
__I uint32_t | TXREQ1
__I uint32_t | TXREQ2
__I uint32_t | NDAT1
__I uint32_t | NDAT2
__I uint32_t | IPND1
__I uint32_t | IPND2
__I uint32_t | MVLD1
__I uint32_t | MVLD2
__IO uint32_t | WU_EN
__IO uint32_t | WU_STATUS

## Detailed Description

Definition at line 550 of file can_reg.h.

## Field Documentation

## ◆ BRPE

CAN_T::BRPE

[0x0018] Baud Rate Prescaler Extension Register

BRPE

Offset: 0x18 Baud Rate Prescaler Extension Register

Bits | Field | Descriptions
[3:0] | BRPE | BRPE: Baud Rate Prescaler Extension 0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023 The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.

Definition at line 1087 of file can_reg.h.

## ◆ BTIME

CAN_T::BTIME

[0x000c] Bit Timing Register

BTIME

Offset: 0x0C Bit Timing Register

Bits | Field | Descriptions
[5:0] | BRP | Baud Rate Prescaler 0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta The bit time is built up from a multiple of this quanta Valid values for the Baud Rate Prescaler are [0...63] The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
[7:6] | SJW | (Re)Synchronization Jump Width 0x0-0x3: Valid programmed values are [0...3] The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
[11:8] | TSeg1 | Time Segment Before the Sample Point Minus Sync_Seg 0x01-0x0F: valid values for TSeg1 are [1...15] The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
[14:12] | TSeg2 | Time Segment After Sample Point 0x0-0x7: Valid values for TSeg2 are [0...7] The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Definition at line 1084 of file can_reg.h.

## ◆ CON

CAN_T::CON

[0x0000] Control Register

CON

Offset: 0x00 Control Register

Bits | Field | Descriptions
[0] | Init | Init Initialization 0 = Normal Operation. 1 = Initialization is started.
[1] | IE | Module Interrupt Enable Bit 0 = Function interrupt is Disabled. 1 = Function interrupt is Enabled.
[2] | SIE | Status Change Interrupt Enable Bit 0 = Disabled - No Status Change Interrupt will be generated. 1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
[3] | EIE | Error Interrupt Enable Bit 0 = Disabled - No Error Status Interrupt will be generated. 1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
[5] | DAR | Automatic Re-transmission Disable Bit 0 = Automatic Retransmission of disturbed messages Enabled. 1 = Automatic Retransmission Disabled.
[6] | CCE | Configuration Change Enable Bit 0 = No write access to the Bit Timing Register. 1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
[7] | Test | Test Mode Enable Bit 0 = Normal Operation. 1 = Test Mode.

Definition at line 1081 of file can_reg.h.

## ◆ ERR

CAN_T::ERR

[0x0008] Error Counter Register

ERR

Offset: 0x08 Error Counter Register

Bits | Field | Descriptions
[7:0] | TEC | Transmit Error Counter Actual state of the Transmit Error Counter. Values between 0 and 255.
[14:8] | REC | Receive Error Counter Actual state of the Receive Error Counter. Values between 0 and 127.
[15] | RP | Receive Error Passive 0 = The Receive Error Counter is below the error passive level. 1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.

Definition at line 1083 of file can_reg.h.

## ◆ IF

__IO CAN_IF_T CAN_T::IF[2]

Definition at line 1091 of file can_reg.h.

## ◆ IIDR

CAN_T::IIDR

[0x0010] Interrupt Identifier Register

IIDR

Offset: 0x10 Interrupt Identifier Register

Bits | Field | Descriptions
[15:0] | IntId | Interrupt Identifier (Indicates the Source of the Interrupt) If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order An interrupt remains pending until the application software has cleared it If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. The Status Interrupt has the highest priority Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]) The Status Interrupt is cleared by reading the Status Register.

Definition at line 1085 of file can_reg.h.

## ◆ IPND1

CAN_T::IPND1

[0x0140] Interrupt Pending Register 1

IPND1

Offset: 0x140 Interrupt Pending Register 1

Bits | Field | Descriptions
[15:0] | IntPnd16_1 | Interrupt Pending Bits 16-1 (of All Message Objects) 0 = This message object is not the source of an interrupt. 1 = This message object is the source of an interrupt.

Definition at line 1105 of file can_reg.h.

## ◆ IPND2

CAN_T::IPND2

[0x0144] Interrupt Pending Register 2

IPND2

Offset: 0x144 Interrupt Pending Register 2

Bits | Field | Descriptions
[15:0] | IntPnd32_17 | Interrupt Pending Bits 32-17 (of All Message Objects) 0 = This message object is not the source of an interrupt. 1 = This message object is the source of an interrupt.

Definition at line 1106 of file can_reg.h.

## ◆ MVLD1

CAN_T::MVLD1

[0x0160] Message Valid Register 1

MVLD1

Offset: 0x160 Message Valid Register 1

Bits | Field | Descriptions
[15:0] | MsgVal16_1 | Message Valid Bits 16-1 (of All Message Objects) (Read Only) 0 = This Message Object is ignored by the Message Handler. 1 = This Message Object is configured and should be considered by the Message Handler. Ex CAN_MVLD1[0] means Message object No.1 is valid or not If CAN_MVLD1[0] is set, message object No.1 is configured.

Definition at line 1110 of file can_reg.h.

## ◆ MVLD2

CAN_T::MVLD2

[0x0164] Message Valid Register 2

MVLD2

Offset: 0x164 Message Valid Register 2

Bits | Field | Descriptions
[15:0] | MsgVal32_17 | Message Valid Bits 32-17 (of All Message Objects) (Read Only) 0 = This Message Object is ignored by the Message Handler. 1 = This Message Object is configured and should be considered by the Message Handler. Ex.CAN_MVLD2[15] means Message object No.32 is valid or not If CAN_MVLD2[15] is set, message object No.32 is configured.

Definition at line 1111 of file can_reg.h.

## ◆ NDAT1

CAN_T::NDAT1

[0x0120] New Data Register 1

NDAT1

Offset: 0x120 New Data Register 1

Bits | Field | Descriptions
[15:0] | NewData16_1 | New Data Bits 16-1 (of All Message Objects) 0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. 1 = The Message Handler or the application software has written new data into the data portion of this Message Object.

Definition at line 1100 of file can_reg.h.

## ◆ NDAT2

CAN_T::NDAT2

[0x0124] New Data Register 2

NDAT2

Offset: 0x124 New Data Register 2

Bits | Field | Descriptions
[15:0] | NewData32_17 | New Data Bits 32-17 (of All Message Objects) 0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. 1 = The Message Handler or the application software has written new data into the data portion of this Message Object.

Definition at line 1101 of file can_reg.h.

## ◆ STATUS

CAN_T::STATUS

[0x0004] Status Register

STATUS

Offset: 0x04 Status Register

Bits | Field | Descriptions
[2:0] | LEC | Last Error Code (Type of the Last Error to Occur on the CAN Bus) The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus This field will be cleared to '0' when a message has been transferred (reception or transmission) without error The unused code '7' may be written by the CPU to check for updates The Error! Reference source not found describes the error code.
[3] | TxOK | Transmitted a Message Successfully 0 = Since this bit was reset by the CPU, no message has been successfully transmitted This bit is never reset by the CAN Core. 1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
[4] | RxOK | Received a Message Successfully 0 = No message has been successfully received since this bit was last reset by the CPU This bit is never reset by the CAN Core. 1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
[5] | EPass | Error Passive (Read Only) 0 = The CAN Core is error active. 1 = The CAN Core is in the error passive state as defined in the CAN Specification.
[6] | EWarn | Error Warning Status (Read Only) 0 = Both error counters are below the error warning limit of 96. 1 = At least one of the error counters in the EML has reached the error warning limit of 96.
[7] | BOff | Bus-off Status (Read Only) 0 = The CAN module is not in bus-off state. 1 = The CAN module is in bus-off state.

Definition at line 1082 of file can_reg.h.

## ◆ TEST

CAN_T::TEST

[0x0014] Test Register

TEST

Offset: 0x14 Test Register

Bits | Field | Descriptions
[2] | Basic | Basic Mode 0 = Basic Mode Disabled. 1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
[3] | Silent | Silent Mode 0 = Normal operation. 1 = The module is in Silent Mode.
[4] | LBack | Loop Back Mode Enable Bit 0 = Loop Back Mode is Disabled. 1 = Loop Back Mode is Enabled.
[6:5] | Tx | Tx[1:0]: Control of CAN_TX Pin 00 = Reset value, CAN_TX pin is controlled by the CAN Core. 01 = Sample Point can be monitored at CAN_TX pin. 10 = CAN_TX pin drives a dominant ('0') value. 11 = CAN_TX pin drives a recessive ('1') value.
[7] | Rx | Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) 0 = The CAN bus is dominant (CAN_RX = '0'). 1 = The CAN bus is recessive (CAN_RX = '1').

Definition at line 1086 of file can_reg.h.

## ◆ TXREQ1

CAN_T::TXREQ1

[0x0100] Transmission Request Register 1

TXREQ1

Offset: 0x100 Transmission Request Register 1

Bits | Field | Descriptions
[15:0] | TxRqst16_1 | Transmission Request Bits 16-1 (of All Message Objects) 0 = This Message Object is not waiting for transmission. 1 = The transmission of this Message Object is requested and is not yet done. These bits are read only.

Definition at line 1095 of file can_reg.h.

## ◆ TXREQ2

CAN_T::TXREQ2

[0x0104] Transmission Request Register 2

TXREQ2

Offset: 0x104 Transmission Request Register 2

Bits | Field | Descriptions
[15:0] | TxRqst32_17 | Transmission Request Bits 32-17 (of All Message Objects) 0 = This Message Object is not waiting for transmission. 1 = The transmission of this Message Object is requested and is not yet done. These bits are read only.

Definition at line 1096 of file can_reg.h.

## ◆ WU_EN

CAN_T::WU_EN

[0x0168] Wake-up Enable Control Register

WU_EN

Offset: 0x168 Wake-up Enable Control Register

Bits | Field | Descriptions
[0] | WAKUP_EN | Wake-up Enable Bit 0 = The wake-up function Disabled. 1 = The wake-up function Enabled. Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.

Definition at line 1112 of file can_reg.h.

## ◆ WU_STATUS

CAN_T::WU_STATUS

[0x016c] Wake-up Status Register

WU_STATUS

Offset: 0x16C Wake-up Status Register

Bits | Field | Descriptions
[0] | WAKUP_STS | Wake-up Status 0 = No wake-up event occurred. 1 = Wake-up event occurred. Note: This bit can be cleared by writing '0'.

Definition at line 1113 of file can_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/can_reg.h