| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
USPI_T Struct Reference
Control Register

`#include <uspi_reg.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | INTEN
__IO uint32_t | BRGEN
__IO uint32_t | DATIN0
__IO uint32_t | CTLIN0
__IO uint32_t | CLKIN
__IO uint32_t | LINECTL
__O uint32_t | TXDAT
__I uint32_t | RXDAT
__IO uint32_t | BUFCTL
__IO uint32_t | BUFSTS
__IO uint32_t | PDMACTL
__IO uint32_t | WKCTL
__IO uint32_t | WKSTS
__IO uint32_t | PROTCTL
__IO uint32_t | PROTIEN
__IO uint32_t | PROTSTS

## Detailed Description

    @addtogroup USPI SPI Mode of USCI Controller(USPI)
    Memory Mapped Structure for USPI Controller

Definition at line 26 of file uspi_reg.h.

## Field Documentation

## ◆ BRGEN

USPI_T::BRGEN

[0x0008] USCI Baud Rate Generator Register

BRGEN

Offset: 0x08 USCI Baud Rate Generator Register

Bits | Field | Descriptions
[0] | RCLKSEL | Reference Clock Source Selection This bit selects the source of reference clock (fREF_CLK). 0 = Peripheral device clock fPCLK. 1 = Reserved.
[1] | PTCLKSEL | Protocol Clock Source Selection This bit selects the source of protocol clock (fPROT_CLK). 0 = Reference clock fREF_CLK. 1 = fREF_CLK2 (its frequency is half of fREF_CLK).
[3:2] | SPCLKSEL | Sample Clock Source Selection This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 00 = fDIV_CLK. 01 = fPROT_CLK. 10 = fSCLK. 11 = fREF_CLK.
[4] | TMCNTEN | Time Measurement Counter Enable Bit This bit enables the 10-bit timing measurement counter. 0 = Time measurement counter is Disabled. 1 = Time measurement counter is Enabled.
[5] | TMCNTSRC | Time Measurement Counter Clock Source Selection 0 = Time measurement counter with fPROT_CLK. 1 = Time measurement counter with fDIV_CLK.
[25:16] | CLKDIV | Clock Divider This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled The revised value is the average bit time between bit 5 and bit 6 The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.

Definition at line 946 of file uspi_reg.h.

## ◆ BUFCTL

USPI_T::BUFCTL

[0x0038] USCI Transmit/Receive Buffer Control Register

BUFCTL

Offset: 0x38 USCI Transmit/Receive Buffer Control Register

Bits | Field | Descriptions
[6] | TXUDRIEN | Slave Transmit Under Run Interrupt Enable Bit 0 = Transmit under-run interrupt Disabled. 1 = Transmit under-run interrupt Enabled.
[7] | TXCLR | Clear Transmit Buffer 0 = No effect. 1 = The transmit buffer is cleared Should only be used while the buffer is not taking part in data traffic. Note: It is cleared automatically after one PCLK cycle.
[14] | RXOVIEN | Receive Buffer Overrun Interrupt Enable Bit 0 = Receive overrun interrupt Disabled. 1 = Receive overrun interrupt Enabled.
[15] | RXCLR | Clear Receive Buffer 0 = No effect. 1 = The receive buffer is cleared Should only be used while the buffer is not taking part in data traffic. Note: It is cleared automatically after one PCLK cycle.
[16] | TXRST | Transmit Reset 0 = No effect. 1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. Note: It is cleared automatically after one PCLK cycle.
[17] | RXRST | Receive Reset 0 = No effect. 1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. Note: It is cleared automatically after one PCLK cycle.

Definition at line 962 of file uspi_reg.h.

## ◆ BUFSTS

USPI_T::BUFSTS

[0x003c] USCI Transmit/Receive Buffer Status Register

BUFSTS

Offset: 0x3C USCI Transmit/Receive Buffer Status Register

Bits | Field | Descriptions
[0] | RXEMPTY | Receive Buffer Empty Indicator 0 = Receive buffer is not empty. 1 = Receive buffer is empty.
[1] | RXFULL | Receive Buffer Full Indicator 0 = Receive buffer is not full. 1 = Receive buffer is full.
[3] | RXOVIF | Receive Buffer Over-run Interrupt Status This bit indicates that a receive buffer overrun event has been detected If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated It is cleared by software writes 1 to this bit. 0 = A receive buffer overrun event has not been detected. 1 = A receive buffer overrun event has been detected.
[8] | TXEMPTY | Transmit Buffer Empty Indicator 0 = Transmit buffer is not empty. 1 = Transmit buffer is empty and available for the next transmission datum.
[9] | TXFULL | Transmit Buffer Full Indicator 0 = Transmit buffer is not full. 1 = Transmit buffer is full.
[11] | TXUDRIF | Transmit Buffer Under-run Interrupt Status This bit indicates that a transmit buffer under-run event has been detected If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated It is cleared by software writes 1 to this bit 0 = A transmit buffer under-run event has not been detected. 1 = A transmit buffer under-run event has been detected.

Definition at line 963 of file uspi_reg.h.

## ◆ CLKIN

USPI_T::CLKIN

[0x0028] USCI Input Clock Signal Configuration Register

CLKIN

Offset: 0x28 USCI Input Clock Signal Configuration Register

Bits | Field | Descriptions
[0] | SYNCSEL | Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 = The un-synchronized signal can be taken as input for the data shift unit. 1 = The synchronized signal can be taken as input for the data shift unit. Note: In SPI protocol, we suggest this bit should be set as 0.

Definition at line 958 of file uspi_reg.h.

## ◆ CTL

USPI_T::CTL

[0x0000] USCI Control Register

CTL

Offset: 0x00 USCI Control Register

Bits | Field | Descriptions
[2:0] | FUNMODE | Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols, the USCI has to be disabled before selecting a new protocol Simultaneously, the USCI will be reset when user write 000 to FUNMODE. 000 = The USCI is disabled. All protocol related state machines are set to idle state. 001 = The SPI protocol is selected. 010 = The UART protocol is selected. 100 = The I2C protocol is selected. Note: Other bit combinations are reserved.

Definition at line 944 of file uspi_reg.h.

## ◆ CTLIN0

USPI_T::CTLIN0

[0x0020] USCI Input Control Signal Configuration Register 0

CTLIN0

Offset: 0x20 USCI Input Control Signal Configuration Register 0

Bits | Field | Descriptions
[0] | SYNCSEL | Input Synchronization Signal Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 = The un-synchronized signal can be taken as input for the data shift unit. 1 = The synchronized signal can be taken as input for the data shift unit. Note: In SPI protocol, we suggest this bit should be set as 0.
[2] | ININV | Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 0 = The un-synchronized input signal will not be inverted. 1 = The un-synchronized input signal will be inverted.

Definition at line 954 of file uspi_reg.h.

## ◆ DATIN0

USPI_T::DATIN0

[0x0010] USCI Input Data Signal Configuration Register 0

DATIN0

Offset: 0x10 USCI Input Data Signal Configuration Register 0

Bits | Field | Descriptions
[0] | SYNCSEL | Input Signal Synchronization Selection This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 = The un-synchronized signal can be taken as input for the data shift unit. 1 = The synchronized signal can be taken as input for the data shift unit. Note: In SPI protocol, we suggest this bit should be set as 0.
[2] | ININV | Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. 0 = The un-synchronized input signal will not be inverted. 1 = The un-synchronized input signal will be inverted. Note: In SPI protocol, we suggest this bit should be set as 0.

Definition at line 950 of file uspi_reg.h.

## ◆ INTEN

USPI_T::INTEN

[0x0004] USCI Interrupt Enable Register

INTEN

Offset: 0x04 USCI Interrupt Enable Register

Bits | Field | Descriptions
[1] | TXSTIEN | Transmit Start Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit start event. 0 = The transmit start interrupt is disabled. 1 = The transmit start interrupt is enabled.
[2] | TXENDIEN | Transmit End Interrupt Enable Bit This bit enables the interrupt generation in case of a transmit finish event. 0 = The transmit finish interrupt is disabled. 1 = The transmit finish interrupt is enabled.
[3] | RXSTIEN | Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event. 0 = The receive start interrupt is disabled. 1 = The receive start interrupt is enabled.
[4] | RXENDIEN | Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. 0 = The receive end interrupt is disabled. 1 = The receive end interrupt is enabled.

Definition at line 945 of file uspi_reg.h.

## ◆ LINECTL

USPI_T::LINECTL

[0x002c] USCI Line Control Register

LINECTL

Offset: 0x2C USCI Line Control Register

Bits | Field | Descriptions
[0] | LSB | LSB First Transmission Selection 0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
[5] | DATOINV | Data Output Inverse Selection This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 0 = Data output level is not inverted. 1 = Data output level is inverted.
[7] | CTLOINV | Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control signal. 0 = No effect. 1 = The control signal will be inverted before its output. Note: The control signal has different definitions in different protocol In SPI protocol, the control signal means slave select signal
[11:8] | DWIDTH | Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission The data word is always right-aligned in the data buffer USCI support word length from 4 to 16 bits. 0x0: The data word contains 16 bits located at bit positions [15:0]. 0x1: Reserved. 0x2: Reserved. 0x3: Reserved. 0x4: The data word contains 4 bits located at bit positions [3:0]. 0x5: The data word contains 5 bits located at bit positions [4:0]. ... 0xF: The data word contains 15 bits located at bit positions [14:0].

Definition at line 959 of file uspi_reg.h.

## ◆ PDMACTL

USPI_T::PDMACTL

[0x0040] USCI PDMA Control Register

PDMACTL

Offset: 0x40 USCI PDMA Control Register

Bits | Field | Descriptions
[0] | PDMARST | PDMA Reset 0 = No effect. 1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
[1] | TXPDMAEN | PDMA Transmit Channel Available 0 = Transmit PDMA function Disabled. 1 = Transmit PDMA function Enabled.
[2] | RXPDMAEN | PDMA Receive Channel Available 0 = Receive PDMA function Disabled. 1 = Receive PDMA function Enabled.
[3] | PDMAEN | PDMA Mode Enable Bit 0 = PDMA function Disabled. 1 = PDMA function Enabled. Notice: The I2C is not supporting PDMA function.

Definition at line 964 of file uspi_reg.h.

## ◆ PROTCTL

USPI_T::PROTCTL

[0x005c] USCI Protocol Control Register

PROTCTL

Offset: 0x5C USCI Protocol Control Register

Bits | Field | Descriptions
[0] | SLAVE | Slave Mode Selection 0 = Master mode. 1 = Slave mode.
[1] | SLV3WIRE | Slave 3-wire Mode Selection (Slave Only) The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 0 = 4-wire bi-direction interface. 1 = 3-wire bi-direction interface.
[2] | SS | Slave Select Control (Master Only) If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. Note: In SPI protocol, the internal slave select signal is active high.
[3] | AUTOSS | Automatic Slave Select Function Enable (Master Only) 0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. 1 = Slave select signal will be generated automatically The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
[7:6] | SCLKMODE | Serial Bus Clock Mode This bit field defines the SCLK idle status, data transmit, and data receive edge. MODE0 = The idle state of SPI clock is low level Data is transmitted with falling edge and received with rising edge. MODE1 = The idle state of SPI clock is low level Data is transmitted with rising edge and received with falling edge. MODE2 = The idle state of SPI clock is high level Data is transmitted with rising edge and received with falling edge. MODE3 = The idle state of SPI clock is high level Data is transmitted with falling edge and received with rising edge.
[11:8] | SUSPITV | Suspend Interval (Master Only) This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word The default value is 0x3 The period of the suspend interval is obtained according to the following equation. (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle Example: SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. ..... SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
[14:12] | TSMSEL | Transmit Data Mode Selection This bit field describes how receive and transmit data is shifted in and out. TSMSEL = 000b: Full-duplex SPI. TSMSEL = 100b: Half-duplex SPI. Other values are reserved. Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
[25:16] | SLVTOCNT | Slave Mode Time-out Period (Slave Only) In Slave mode, this bit field is used for Slave time-out period This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event Writing 0x0 into this bit field will disable the Slave time-out function. Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
[28] | TXUDRPOL | Transmit Under-run Data Polarity (for Slave) This bit defines the transmitting data level when no data is available for transferring. 0 = The output data level is 0 if TX under run event occurs. 1 = The output data level is 1 if TX under run event occurs.
[31] | PROTEN | SPI Protocol Enable Bit 0 = SPI Protocol Disabled. 1 = SPI Protocol Enabled.

Definition at line 970 of file uspi_reg.h.

## ◆ PROTIEN

USPI_T::PROTIEN

[0x0060] USCI Protocol Interrupt Enable Register

PROTIEN

Offset: 0x60 USCI Protocol Interrupt Enable Register

Bits | Field | Descriptions
[0] | SSINAIEN | Slave Select Inactive Interrupt Enable Control This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 = Slave select inactive interrupt generation Disabled. 1 = Slave select inactive interrupt generation Enabled.
[1] | SSACTIEN | Slave Select Active Interrupt Enable Control This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 0 = Slave select active interrupt generation Disabled. 1 = Slave select active interrupt generation Enabled.
[2] | SLVTOIEN | Slave Time-out Interrupt Enable Control In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 0 = The Slave time-out interrupt Disabled. 1 = The Slave time-out interrupt Enabled.
[3] | SLVBEIEN | Slave Mode Bit Count Error Interrupt Enable Control If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) Bit count error event occurs. 0 = The Slave mode bit count error interrupt Disabled. 1 = The Slave mode bit count error interrupt Enabled.

Definition at line 971 of file uspi_reg.h.

## ◆ PROTSTS

USPI_T::PROTSTS

[0x0064] USCI Protocol Status Register

PROTSTS

Offset: 0x64 USCI Protocol Status Register

Bits | Field | Descriptions
[1] | TXSTIF | Transmit Start Interrupt Flag 0 = Transmit start event does not occur. 1 = Transmit start event occurs. Note: It is cleared by software writes 1 to this bit
[2] | TXENDIF | Transmit End Interrupt Flag 0 = Transmit end event does not occur. 1 = Transmit end event occurs. Note: It is cleared by software writes 1 to this bit
[3] | RXSTIF | Receive Start Interrupt Flag 0 = Receive start event does not occur. 1 = Receive start event occurs. Note: It is cleared by software writes 1 to this bit
[4] | RXENDIF | Receive End Interrupt Flag 0 = Receive end event does not occur. 1 = Receive end event occurs. Note: It is cleared by software writes 1 to this bit
[5] | SLVTOIF | Slave Time-out Interrupt Flag (for Slave Only) 0 = Slave time-out event does not occur. 1 = Slave time-out event occurs. Note: It is cleared by software writes 1 to this bit
[6] | SLVBEIF | Slave Bit Count Error Interrupt Flag (for Slave Only) 0 = Slave bit count error event does not occur. 1 = Slave bit count error event occurs. Note: It is cleared by software writes 1 to this bit.
[8] | SSINAIF | Slave Select Inactive Interrupt Flag (for Slave Only) This bit indicates that the internal slave select signal has changed to inactive It is cleared by software writes 1 to this bit 0 = The slave select signal has not changed to inactive. 1 = The slave select signal has changed to inactive. Note: The internal slave select signal is active high.
[9] | SSACTIF | Slave Select Active Interrupt Flag (for Slave Only) This bit indicates that the internal slave select signal has changed to active It is cleared by software writes one to this bit 0 = The slave select signal has not changed to active. 1 = The slave select signal has changed to active. Note: The internal slave select signal is active high.
[16] | SSLINE | Slave Select Line Bus Status (Read Only) This bit is only available in Slave mode It used to monitor the current status of the input slave select signal on the bus. 0 = The slave select line status is 0. 1 = The slave select line status is 1.
[17] | BUSY | Busy Status (Read Only) 0 = SPI is in idle state. 1 = SPI is in busy state. The following listing are the bus busy conditions: a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
[18] | SLVUDR | Slave Mode Transmit Under-run Status (Read Only) In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 0 = Slave transmit under-run event does not occur. 1 = Slave transmit under-run event occurs.

Definition at line 972 of file uspi_reg.h.

## ◆ RXDAT

USPI_T::RXDAT

[0x0034] USCI Receive Data Register

RXDAT

Offset: 0x34 USCI Receive Data Register

Bits | Field | Descriptions
[15:0] | RXDAT | Received Data This bit field monitors the received data which stored in receive data buffer.

Definition at line 961 of file uspi_reg.h.

## ◆ TXDAT

USPI_T::TXDAT

[0x0030] USCI Transmit Data Register

TXDAT

Offset: 0x30 USCI Transmit Data Register

Bits | Field | Descriptions
[15:0] | TXDAT | Transmit Data Software can use this bit field to write 16-bit transmit data for transmission In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
[16] | PORTDIR | Port Direction Control This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer It is used to define the direction of the data port pin When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. 0 = The data pin is configured as output mode. 1 = The data pin is configured as input mode.

Definition at line 960 of file uspi_reg.h.

## ◆ WKCTL

USPI_T::WKCTL

[0x0054] USCI Wake-up Control Register

WKCTL

Offset: 0x54 USCI Wake-up Control Register

Bits | Field | Descriptions
[0] | WKEN | Wake-up Enable Bit 0 = Wake-up function Disabled. 1 = Wake-up function Enabled.
[1] | WKADDREN | Wake-up Address Match Enable Bit 0 = The chip is woken up according data toggle. 1 = The chip is woken up according address match.
[2] | PDBOPT | Power Down Blocking Option 0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. 1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.

Definition at line 968 of file uspi_reg.h.

## ◆ WKSTS

USPI_T::WKSTS

[0x0058] USCI Wake-up Status Register

WKSTS

Offset: 0x58 USCI Wake-up Status Register

Bits | Field | Descriptions
[0] | WKF | Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1 Software can write 1 to clear this bit.

Definition at line 969 of file uspi_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/uspi_reg.h