| M480 BSP V3.05.001 The Board Support Package for M480 Series

M480.h
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1 /**************************************************************************/
50 #ifndef __M480_H__
51 #define __M480_H__
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56
57 /******************************************************************************/
58 /* Processor and Core Peripherals */
59 /******************************************************************************/
68 typedef enum IRQn
69 {
70 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
71 NonMaskableInt_IRQn = -14,
72 MemoryManagement_IRQn = -12,
73 BusFault_IRQn = -11,
74 UsageFault_IRQn = -10,
75 SVCall_IRQn = -5,
76 DebugMonitor_IRQn = -4,
77 PendSV_IRQn = -2,
78 SysTick_IRQn = -1,
80 /****** M480 Specific Interrupt Numbers ********************************************************/
81
82 BOD_IRQn = 0,
83 IRC_IRQn = 1,
84 PWRWU_IRQn = 2,
85 RAMPE_IRQn = 3,
86 CKFAIL_IRQn = 4,
87 RTC_IRQn = 6,
88 TAMPER_IRQn = 7,
89 WDT_IRQn = 8,
90 WWDT_IRQn = 9,
91 EINT0_IRQn = 10,
92 EINT1_IRQn = 11,
93 EINT2_IRQn = 12,
94 EINT3_IRQn = 13,
95 EINT4_IRQn = 14,
96 EINT5_IRQn = 15,
97 GPA_IRQn = 16,
98 GPB_IRQn = 17,
99 GPC_IRQn = 18,
100 GPD_IRQn = 19,
101 GPE_IRQn = 20,
102 GPF_IRQn = 21,
103 QSPI0_IRQn = 22,
104 SPI0_IRQn = 23,
105 BRAKE0_IRQn = 24,
106 EPWM0P0_IRQn = 25,
107 EPWM0P1_IRQn = 26,
108 EPWM0P2_IRQn = 27,
109 BRAKE1_IRQn = 28,
110 EPWM1P0_IRQn = 29,
111 EPWM1P1_IRQn = 30,
112 EPWM1P2_IRQn = 31,
113 TMR0_IRQn = 32,
114 TMR1_IRQn = 33,
115 TMR2_IRQn = 34,
116 TMR3_IRQn = 35,
117 UART0_IRQn = 36,
118 UART1_IRQn = 37,
119 I2C0_IRQn = 38,
120 I2C1_IRQn = 39,
121 PDMA_IRQn = 40,
122 DAC_IRQn = 41,
123 EADC00_IRQn = 42,
124 EADC01_IRQn = 43,
125 ACMP01_IRQn = 44,
126 EADC02_IRQn = 46,
127 EADC03_IRQn = 47,
128 UART2_IRQn = 48,
129 UART3_IRQn = 49,
130 QSPI1_IRQn = 50,
131 SPI1_IRQn = 51,
132 SPI2_IRQn = 52,
133 USBD_IRQn = 53,
134 USBH_IRQn = 54,
135 USBOTG_IRQn = 55,
136 CAN0_IRQn = 56,
137 CAN1_IRQn = 57,
138 SC0_IRQn = 58,
139 SC1_IRQn = 59,
140 SC2_IRQn = 60,
141 SPI3_IRQn = 62,
142 EMAC_TX_IRQn = 66,
143 EMAC_RX_IRQn = 67,
144 SDH0_IRQn = 64,
145 USBD20_IRQn = 65,
146 I2S0_IRQn = 68,
147 OPA_IRQn = 70,
148 CRPT_IRQn = 71,
149 GPG_IRQn = 72,
150 EINT6_IRQn = 73,
151 UART4_IRQn = 74,
152 UART5_IRQn = 75,
153 USCI0_IRQn = 76,
154 USCI1_IRQn = 77,
155 BPWM0_IRQn = 78,
156 BPWM1_IRQn = 79,
157 SPIM_IRQn = 80,
158 CCAP_IRQn = 81,
159 I2C2_IRQn = 82,
160 QEI0_IRQn = 84,
161 QEI1_IRQn = 85,
162 ECAP0_IRQn = 86,
163 ECAP1_IRQn = 87,
164 GPH_IRQn = 88,
165 EINT7_IRQn = 89,
166 SDH1_IRQn = 90,
167 HSUSBH_IRQn = 92,
168 USBOTG20_IRQn = 93,
169 TRNG_IRQn = 101,
170 UART6_IRQn = 102,
171 UART7_IRQn = 103,
172 EADC10_IRQn = 104,
173 EADC11_IRQn = 105,
174 EADC12_IRQn = 106,
175 EADC13_IRQn = 107,
176 CAN2_IRQn = 108,
177 }
178 IRQn_Type;
179
180
181 /*
182 * ==========================================================================
183 * ----------- Processor and Core Peripheral Section ------------------------
184 * ==========================================================================
185 */
186
187 /* Configuration of the Cortex-M4 Processor and Core Peripherals */
188 #define __CM4_REV 0x0201UL
189 #define __NVIC_PRIO_BITS 4UL
190 #define __Vendor_SysTickConfig 0UL
191 #define __MPU_PRESENT 1UL
192 #ifdef __FPU_PRESENT
193 #undef __FPU_PRESENT
194 #define __FPU_PRESENT 1UL
195 #else
196 #define __FPU_PRESENT 1UL
197 #endif
198 /* end of group CMSIS_Device */
200
201
202 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
203 #include "system_M480.h" /* System include file */
204 #include <stdint.h>
205
206
207
208 #if defined ( __CC_ARM )
209 #pragma anon_unions
210 #endif
211
212 /******************************************************************************/
213 /* Register definitions */
214 /******************************************************************************/
215
216 #include "sys_reg.h"
217 #include "clk_reg.h"
218 #include "fmc_reg.h"
219 #include "gpio_reg.h"
220 #include "pdma_reg.h"
221 #include "timer_reg.h"
222 #include "wdt_reg.h"
223 #include "wwdt_reg.h"
224 #include "rtc_reg.h"
225 #include "epwm_reg.h"
226 #include "bpwm_reg.h"
227 #include "qei_reg.h"
228 #include "ecap_reg.h"
229 #include "uart_reg.h"
230 #include "emac_reg.h"
231 #include "sc_reg.h"
232 #include "i2s_reg.h"
233 #include "spi_reg.h"
234 #include "qspi_reg.h"
235 #include "spim_reg.h"
236 #include "i2c_reg.h"
237 #include "uuart_reg.h"
238 #include "uspi_reg.h"
239 #include "ui2c_reg.h"
240 #include "can_reg.h"
241 #include "sdh_reg.h"
242 #include "ebi_reg.h"
243 #include "usbd_reg.h"
244 #include "hsusbd_reg.h"
245 #include "usbh_reg.h"
246 #include "hsusbh_reg.h"
247 #include "otg_reg.h"
248 #include "hsotg_reg.h"
249 #include "crc_reg.h"
250 #include "crypto_reg.h"
251 #include "trng_reg.h"
252 #include "eadc_reg.h"
253 #include "dac_reg.h"
254 #include "acmp_reg.h"
255 #include "opa_reg.h"
256 #include "ccap_reg.h"
257
258
263 /* Peripheral and SRAM base address */
264 #define FLASH_BASE ((uint32_t)0x00000000)
265 #define SRAM_BASE ((uint32_t)0x20000000)
266 #define PERIPH_BASE ((uint32_t)0x40000000)
267 #define AHBPERIPH_BASE PERIPH_BASE
268 #define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000)
271 #define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
272 #define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
273 #define NMI_BASE (AHBPERIPH_BASE + 0x00300UL)
274 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
275 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
276 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
277 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
278 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
279 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
280 #define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
281 #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
282 #define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL)
283 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
284 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
285 #define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
286 #define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
287 #define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL)
288 #define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL)
289 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
290 #define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
291 #define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
292 #define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
293 #define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL)
294 #define CCAP_BASE (AHBPERIPH_BASE + 0x30000UL)
295 #define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
296 #define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL)
297
299 #define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
300 #define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
301 #define OPA_BASE (APBPERIPH_BASE + 0x06000UL)
302 #define I2S_BASE (APBPERIPH_BASE + 0x08000UL)
303 #define EADC1_BASE (APBPERIPH_BASE + 0x0B000UL)
304 #define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL)
305 #define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL)
306 #define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
307 #define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
308 #define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
309 #define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
310 #define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
311 #define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
312 #define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
313 #define UART4_BASE (APBPERIPH_BASE + 0x34000UL)
314 #define UART6_BASE (APBPERIPH_BASE + 0x36000UL)
315 #define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
316 #define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
317 #define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
318 #define CAN2_BASE (APBPERIPH_BASE + 0x62000UL)
319 #define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
320 #define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
321 #define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
322
323
325 #define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
326 #define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
327 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
328 #define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
329 #define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
330 #define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
331 #define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
332 #define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
333 #define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
334 #define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
335 #define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
336 #define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
337 #define QSPI1_BASE (APBPERIPH_BASE + 0x29000UL)
338 #define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
339 #define UART3_BASE (APBPERIPH_BASE + 0x33000UL)
340 #define UART5_BASE (APBPERIPH_BASE + 0x35000UL)
341 #define UART7_BASE (APBPERIPH_BASE + 0x37000UL)
342 #define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
343 #define CAN1_BASE (APBPERIPH_BASE + 0x61000UL)
344 #define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
345 #define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
346 #define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
347 #define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
348 #define CRPT_BASE (0x50080000UL)
349 #define SPIM_BASE (0x40007000UL)
350
351 #define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
352 #define SC1_BASE (APBPERIPH_BASE + 0x51000UL)
353 #define SC2_BASE (APBPERIPH_BASE + 0x52000UL)
354 #define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
355 #define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
356 #define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL)
357 #define OPA0_BASE (APBPERIPH_BASE + 0x06000UL)
358 /* end of group PERIPHERAL_MEM_MAP */
360
361
367 #define SYS ((SYS_T *) SYS_BASE)
368 #define CLK ((CLK_T *) CLK_BASE)
369 #define NMI ((NMI_T *) NMI_BASE)
370 #define PA ((GPIO_T *) GPIOA_BASE)
371 #define PB ((GPIO_T *) GPIOB_BASE)
372 #define PC ((GPIO_T *) GPIOC_BASE)
373 #define PD ((GPIO_T *) GPIOD_BASE)
374 #define PE ((GPIO_T *) GPIOE_BASE)
375 #define PF ((GPIO_T *) GPIOF_BASE)
376 #define PG ((GPIO_T *) GPIOG_BASE)
377 #define PH ((GPIO_T *) GPIOH_BASE)
378 #define GPA ((GPIO_T *) GPIOA_BASE)
379 #define GPB ((GPIO_T *) GPIOB_BASE)
380 #define GPC ((GPIO_T *) GPIOC_BASE)
381 #define GPD ((GPIO_T *) GPIOD_BASE)
382 #define GPE ((GPIO_T *) GPIOE_BASE)
383 #define GPF ((GPIO_T *) GPIOF_BASE)
384 #define GPG ((GPIO_T *) GPIOG_BASE)
385 #define GPH ((GPIO_T *) GPIOH_BASE)
386 #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
387 #define PDMA ((PDMA_T *) PDMA_BASE)
388 #define USBH ((USBH_T *) USBH_BASE)
389 #define HSUSBH ((HSUSBH_T *) HSUSBH_BASE)
390 #define EMAC ((EMAC_T *) EMAC_BASE)
391 #define FMC ((FMC_T *) FMC_BASE)
392 #define SDH0 ((SDH_T *) SDH0_BASE)
393 #define SDH1 ((SDH_T *) SDH1_BASE)
394 #define EBI ((EBI_T *) EBI_BASE)
395 #define CRC ((CRC_T *) CRC_BASE)
396 #define TAMPER ((TAMPER_T *) TAMPER_BASE)
397
398 #define WDT ((WDT_T *) WDT_BASE)
399 #define WWDT ((WWDT_T *) WWDT_BASE)
400 #define RTC ((RTC_T *) RTC_BASE)
401 #define EADC ((EADC_T *) EADC_BASE)
402 #define EADC0 ((EADC_T *) EADC_BASE)
403 #define EADC1 ((EADC_T *) EADC1_BASE)
404 #define ACMP01 ((ACMP_T *) ACMP01_BASE)
405
406 #define I2S0 ((I2S_T *) I2S_BASE)
407 #define USBD ((USBD_T *) USBD_BASE)
408 #define OTG ((OTG_T *) OTG_BASE)
409 #define HSUSBD ((HSUSBD_T *)HSUSBD_BASE)
410 #define HSOTG ((HSOTG_T *) HSOTG_BASE)
411 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
412 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
413 #define TIMER2 ((TIMER_T *) TIMER2_BASE)
414 #define TIMER3 ((TIMER_T *) TIMER3_BASE)
415 #define EPWM0 ((EPWM_T *) EPWM0_BASE)
416 #define EPWM1 ((EPWM_T *) EPWM1_BASE)
417 #define BPWM0 ((BPWM_T *) BPWM0_BASE)
418 #define BPWM1 ((BPWM_T *) BPWM1_BASE)
419 #define ECAP0 ((ECAP_T *) ECAP0_BASE)
420 #define ECAP1 ((ECAP_T *) ECAP1_BASE)
421 #define QEI0 ((QEI_T *) QEI0_BASE)
422 #define QEI1 ((QEI_T *) QEI1_BASE)
423 #define QSPI0 ((QSPI_T *) QSPI0_BASE)
424 #define QSPI1 ((QSPI_T *) QSPI1_BASE)
425 #define SPI0 ((SPI_T *) SPI0_BASE)
426 #define SPI1 ((SPI_T *) SPI1_BASE)
427 #define SPI2 ((SPI_T *) SPI2_BASE)
428 #define SPI3 ((SPI_T *) SPI3_BASE)
429 #define UART0 ((UART_T *) UART0_BASE)
430 #define UART1 ((UART_T *) UART1_BASE)
431 #define UART2 ((UART_T *) UART2_BASE)
432 #define UART3 ((UART_T *) UART3_BASE)
433 #define UART4 ((UART_T *) UART4_BASE)
434 #define UART5 ((UART_T *) UART5_BASE)
435 #define UART6 ((UART_T *) UART6_BASE)
436 #define UART7 ((UART_T *) UART7_BASE)
437 #define I2C0 ((I2C_T *) I2C0_BASE)
438 #define I2C1 ((I2C_T *) I2C1_BASE)
439 #define I2C2 ((I2C_T *) I2C2_BASE)
440 #define SC0 ((SC_T *) SC0_BASE)
441 #define SC1 ((SC_T *) SC1_BASE)
442 #define SC2 ((SC_T *) SC2_BASE)
443 #define CAN0 ((CAN_T *) CAN0_BASE)
444 #define CAN1 ((CAN_T *) CAN1_BASE)
445 #define CAN2 ((CAN_T *) CAN2_BASE)
446 #define CRPT ((CRPT_T *) CRPT_BASE)
447 #define TRNG ((TRNG_T *) TRNG_BASE)
448 #define SPIM ((volatile SPIM_T *) SPIM_BASE)
449 #define DAC0 ((DAC_T *) DAC0_BASE)
450 #define DAC1 ((DAC_T *) DAC1_BASE)
451 #define USPI0 ((USPI_T *) USCI0_BASE)
452 #define USPI1 ((USPI_T *) USCI1_BASE)
453 #define OPA ((OPA_T *) OPA_BASE)
454 #define UI2C0 ((UI2C_T *) USCI0_BASE)
455 #define UI2C1 ((UI2C_T *) USCI1_BASE)
456 #define UUART0 ((UUART_T *) USCI0_BASE)
457 #define UUART1 ((UUART_T *) USCI1_BASE)
458 #define CCAP ((CCAP_T *) CCAP_BASE)
459 /* end of group ERIPHERAL_DECLARATION */
461
467 typedef volatile unsigned char vu8;
468 typedef volatile unsigned short vu16;
469 typedef volatile unsigned long vu32;
470
476 #define M8(addr) (*((vu8 *) (addr)))
477
484 #define M16(addr) (*((vu16 *) (addr)))
485
492 #define M32(addr) (*((vu32 *) (addr)))
493
501 #define outpw(port,value) *((volatile unsigned int *)(port)) = (value)
502
509 #define inpw(port) (*((volatile unsigned int *)(port)))
510
518 #define outps(port,value) *((volatile unsigned short *)(port)) = (value)
519
526 #define inps(port) (*((volatile unsigned short *)(port)))
527
534 #define outpb(port,value) *((volatile unsigned char *)(port)) = (value)
535
541 #define inpb(port) (*((volatile unsigned char *)(port)))
542
550 #define outp32(port,value) *((volatile unsigned int *)(port)) = (value)
551
558 #define inp32(port) (*((volatile unsigned int *)(port)))
559
567 #define outp16(port,value) *((volatile unsigned short *)(port)) = (value)
568
575 #define inp16(port) (*((volatile unsigned short *)(port)))
576
583 #define outp8(port,value) *((volatile unsigned char *)(port)) = (value)
584
590 #define inp8(port) (*((volatile unsigned char *)(port)))
591
592 /* end of group IO_ROUTINE */
594
595 /******************************************************************************/
596 /* Legacy Constants */
597 /******************************************************************************/
603 #ifndef NULL
604 #define NULL (0)
605 #endif
606
607 #define TRUE (1UL)
608 #define FALSE (0UL)
609
610 #define ENABLE (1UL)
611 #define DISABLE (0UL)
612
613 /* Define one bit mask */
614 #define BIT0 (0x00000001UL)
615 #define BIT1 (0x00000002UL)
616 #define BIT2 (0x00000004UL)
617 #define BIT3 (0x00000008UL)
618 #define BIT4 (0x00000010UL)
619 #define BIT5 (0x00000020UL)
620 #define BIT6 (0x00000040UL)
621 #define BIT7 (0x00000080UL)
622 #define BIT8 (0x00000100UL)
623 #define BIT9 (0x00000200UL)
624 #define BIT10 (0x00000400UL)
625 #define BIT11 (0x00000800UL)
626 #define BIT12 (0x00001000UL)
627 #define BIT13 (0x00002000UL)
628 #define BIT14 (0x00004000UL)
629 #define BIT15 (0x00008000UL)
630 #define BIT16 (0x00010000UL)
631 #define BIT17 (0x00020000UL)
632 #define BIT18 (0x00040000UL)
633 #define BIT19 (0x00080000UL)
634 #define BIT20 (0x00100000UL)
635 #define BIT21 (0x00200000UL)
636 #define BIT22 (0x00400000UL)
637 #define BIT23 (0x00800000UL)
638 #define BIT24 (0x01000000UL)
639 #define BIT25 (0x02000000UL)
640 #define BIT26 (0x04000000UL)
641 #define BIT27 (0x08000000UL)
642 #define BIT28 (0x10000000UL)
643 #define BIT29 (0x20000000UL)
644 #define BIT30 (0x40000000UL)
645 #define BIT31 (0x80000000UL)
646
647 /* Byte Mask Definitions */
648 #define BYTE0_Msk (0x000000FFUL)
649 #define BYTE1_Msk (0x0000FF00UL)
650 #define BYTE2_Msk (0x00FF0000UL)
651 #define BYTE3_Msk (0xFF000000UL)
652
653 #define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) )
654 #define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8)
655 #define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16)
656 #define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24)
658 /* end of group Legacy_Constants */
659
660
661 /******************************************************************************/
662 /* Peripheral header files */
663 /******************************************************************************/
664 #include "sys.h"
665 #include "clk.h"
666
667 #include "acmp.h"
668 #include "dac.h"
669 #include "emac.h"
670 #include "uart.h"
671 #include "usci_spi.h"
672 #include "gpio.h"
673 #include "ccap.h"
674 #include "ecap.h"
675 #include "qei.h"
676 #include "timer.h"
677 #include "timer_pwm.h"
678 #include "pdma.h"
679 #include "crypto.h"
680 #include "trng.h"
681 #include "fmc.h"
682 #include "spim.h"
683 #include "i2c.h"
684 #include "i2s.h"
685 #include "epwm.h"
686 #include "eadc.h"
687 #include "bpwm.h"
688 #include "wdt.h"
689 #include "wwdt.h"
690 #include "opa.h"
691 #include "crc.h"
692 #include "ebi.h"
693 #include "usci_i2c.h"
694 #include "scuart.h"
695 #include "sc.h"
696 #include "spi.h"
697 #include "qspi.h"
698 #include "can.h"
699 #include "rtc.h"
700 #include "usci_uart.h"
701 #include "sdh.h"
702 #include "usbd.h"
703 #include "hsusbd.h"
704 #include "otg.h"
705 #include "hsotg.h"
706
707
708 #ifdef __cplusplus
709 }
710 #endif
711
712 #endif /* __M480_H__ */
713
UART4_IRQn
Definition: M480.h:151
SC0_IRQn
Definition: M480.h:138
EADC12_IRQn
Definition: M480.h:174
I2S0_IRQn
Definition: M480.h:146
rtc.h
M480 series RTC driver header file.
uart.h
M480 series UART driver header file.
ecap_reg.h
ECAP register definition header file.
epwm_reg.h
EPWM register definition header file.
fmc_reg.h
FMC register definition header file.
ebi_reg.h
EBI register definition header file.
sdh.h
M480 SDH driver header file.
bpwm.h
M480 series PWM driver header file.
UART2_IRQn
Definition: M480.h:128
UsageFault_IRQn
Definition: M480.h:74
clk_reg.h
CLK register definition header file.
acmp.h
M480 Series ACMP Driver Header File.
hsotg_reg.h
HSOTG register definition header file.
ccap.h
M480 Series CCAP Driver Header File.
gpio_reg.h
GPIO register definition header file.
i2s_reg.h
I2S register definition header file.
IRQn_Type
enum IRQn IRQn_Type
CAN0_IRQn
Definition: M480.h:136
GPF_IRQn
Definition: M480.h:102
SysTick_IRQn
Definition: M480.h:78
hsusbd.h
M480 HSUSBD driver header file.
SDH0_IRQn
Definition: M480.h:144
eadc.h
M480 series EADC driver header file.
EADC01_IRQn
Definition: M480.h:124
otg_reg.h
OTG register definition header file.
wwdt.h
M480 series WWDT driver header file.
SDH1_IRQn
Definition: M480.h:166
TRNG_IRQn
Definition: M480.h:169
sc_reg.h
SC register definition header file.
PendSV_IRQn
Definition: M480.h:77
SPI0_IRQn
Definition: M480.h:104
EINT7_IRQn
Definition: M480.h:165
CKFAIL_IRQn
Definition: M480.h:86
gpio.h
M480 series GPIO driver header file.
i2c_reg.h
I2C register definition header file.
EADC10_IRQn
Definition: M480.h:172
crypto.h
Cryptographic Accelerator driver header file.
TMR1_IRQn
Definition: M480.h:114
WWDT_IRQn
Definition: M480.h:90
USCI0_IRQn
Definition: M480.h:153
qei.h
Quadrature Encoder Interface (QEI) driver header file.
ECAP1_IRQn
Definition: M480.h:163
I2C1_IRQn
Definition: M480.h:120
otg.h
M480 Series OTG Driver Header File.
ACMP01_IRQn
Definition: M480.h:125
IRQn
IRQn
Definition: M480.h:68
system_M480.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480.
GPH_IRQn
Definition: M480.h:164
BOD_IRQn
Definition: M480.h:82
ui2c_reg.h
UI2C register definition header file.
CRPT_IRQn
Definition: M480.h:148
can_reg.h
CAN register definition header file.
GPD_IRQn
Definition: M480.h:100
WDT_IRQn
Definition: M480.h:89
EPWM0P0_IRQn
Definition: M480.h:106
sys.h
M480 Series SYS Driver Header File.
TAMPER_IRQn
Definition: M480.h:88
EADC03_IRQn
Definition: M480.h:127
qei_reg.h
QEI register definition header file.
CAN1_IRQn
Definition: M480.h:137
SC1_IRQn
Definition: M480.h:139
pdma_reg.h
PDMA register definition header file.
sys_reg.h
SYS register definition header file.
crc.h
M480 series CRC driver header file.
PWRWU_IRQn
Definition: M480.h:84
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: M480.h:469
pdma.h
M480 series PDMA driver header file.
usci_i2c.h
M480 series USCI I2C(UI2C) driver header file.
sc.h
M480 Smartcard (SC) driver header file.
uuart_reg.h
UUART register definition header file.
DAC_IRQn
Definition: M480.h:122
timer.h
M480 series Timer Controller(Timer) driver header file.
USBD20_IRQn
Definition: M480.h:145
GPA_IRQn
Definition: M480.h:97
acmp_reg.h
ACMP register definition header file.
GPE_IRQn
Definition: M480.h:101
SPI1_IRQn
Definition: M480.h:131
wdt.h
M480 series WDT driver header file.
TMR0_IRQn
Definition: M480.h:113
spi.h
M480 series SPI driver header file.
dac_reg.h
DAC register definition header file.
USBOTG20_IRQn
Definition: M480.h:168
EADC02_IRQn
Definition: M480.h:126
I2C2_IRQn
Definition: M480.h:159
UART7_IRQn
Definition: M480.h:171
BRAKE0_IRQn
Definition: M480.h:105
GPB_IRQn
Definition: M480.h:98
EPWM1P0_IRQn
Definition: M480.h:110
UART5_IRQn
Definition: M480.h:152
scuart.h
M480 Smartcard UART mode (SCUART) driver header file.
QEI0_IRQn
Definition: M480.h:160
HSUSBH_IRQn
Definition: M480.h:167
EADC13_IRQn
Definition: M480.h:175
fmc.h
M480 Series Flash Memory Controller Driver Header File.
SPI2_IRQn
Definition: M480.h:132
spim_reg.h
SPIM register definition header file.
I2C0_IRQn
Definition: M480.h:119
EADC00_IRQn
Definition: M480.h:123
usbd_reg.h
USBD register definition header file.
usbh_reg.h
USBH register definition header file.
timer_pwm.h
M480 series Timer PWM Controller(Timer PWM) driver header file.
clk.h
M480 Series CLK Driver Header File.
QSPI0_IRQn
Definition: M480.h:103
DebugMonitor_IRQn
Definition: M480.h:76
usci_uart.h
M480 series USCI UART (UUART) driver header file.
crypto_reg.h
CRYPTO register definition header file.
EPWM1P1_IRQn
Definition: M480.h:111
USBD_IRQn
Definition: M480.h:133
EINT3_IRQn
Definition: M480.h:94
uspi_reg.h
USPI register definition header file.
EINT0_IRQn
Definition: M480.h:91
SPIM_IRQn
Definition: M480.h:157
i2s.h
M480 I2S driver header file.
PDMA_IRQn
Definition: M480.h:121
QEI1_IRQn
Definition: M480.h:161
timer_reg.h
TIMER register definition header file.
EINT4_IRQn
Definition: M480.h:95
IRC_IRQn
Definition: M480.h:83
BusFault_IRQn
Definition: M480.h:73
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: M480.h:467
USBH_IRQn
Definition: M480.h:134
BPWM1_IRQn
Definition: M480.h:156
SC2_IRQn
Definition: M480.h:140
emac_reg.h
EMAC register definition header file.
EINT5_IRQn
Definition: M480.h:96
RAMPE_IRQn
Definition: M480.h:85
rtc_reg.h
RTC register definition header file.
emac.h
M480 EMAC driver header file.
SPI3_IRQn
Definition: M480.h:141
crc_reg.h
CRC register definition header file.
sdh_reg.h
SDH register definition header file.
GPG_IRQn
Definition: M480.h:149
BPWM0_IRQn
Definition: M480.h:155
EINT2_IRQn
Definition: M480.h:93
wwdt_reg.h
WWDT register definition header file.
ecap.h
EnHanced Input Capture Timer(ECAP) driver header file.
MemoryManagement_IRQn
Definition: M480.h:72
QSPI1_IRQn
Definition: M480.h:130
bpwm_reg.h
BPWM register definition header file.
dac.h
M480 series DAC driver header file.
UART3_IRQn
Definition: M480.h:129
spim.h
M480 series SPIM driver header file.
ECAP0_IRQn
Definition: M480.h:162
wdt_reg.h
WDT register definition header file.
qspi.h
M480 series QSPI driver header file.
epwm.h
M480 series EPWM driver header file.
CAN2_IRQn
Definition: M480.h:176
trng.h
TRNG driver header file.
EMAC_RX_IRQn
Definition: M480.h:143
hsotg.h
M480 Series HSOTG Driver Header File.
spi_reg.h
SPI register definition header file.
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: M480.h:468
EMAC_TX_IRQn
Definition: M480.h:142
qspi_reg.h
QSPI register definition header file.
uart_reg.h
UART register definition header file.
USCI1_IRQn
Definition: M480.h:154
ebi.h
M480 series External Bus Interface(EBI) driver header file.
TMR2_IRQn
Definition: M480.h:115
opa_reg.h
OPA register definition header file.
EPWM0P1_IRQn
Definition: M480.h:107
EPWM1P2_IRQn
Definition: M480.h:112
GPC_IRQn
Definition: M480.h:99
BRAKE1_IRQn
Definition: M480.h:109
EPWM0P2_IRQn
Definition: M480.h:108
NonMaskableInt_IRQn
Definition: M480.h:71
hsusbd_reg.h
HSUSBD register definition header file.
RTC_IRQn
Definition: M480.h:87
SVCall_IRQn
Definition: M480.h:75
eadc_reg.h
EADC register definition header file.
USBOTG_IRQn
Definition: M480.h:135
can.h
M480 Series CAN Driver Header File.
UART1_IRQn
Definition: M480.h:118
EINT1_IRQn
Definition: M480.h:92
TMR3_IRQn
Definition: M480.h:116
EINT6_IRQn
Definition: M480.h:150
ccap_reg.h
CCAP register definition header file.
trng_reg.h
TRNG register definition header file.
hsusbh_reg.h
HSUSBH register definition header file.
EADC11_IRQn
Definition: M480.h:173
usci_spi.h
M480 series USCI_SPI driver header file.
OPA_IRQn
Definition: M480.h:147
usbd.h
M480 series USB driver header file.
opa.h
M480 series OPA driver header file.
UART0_IRQn
Definition: M480.h:117
i2c.h
M480 series I2C driver header file.
CCAP_IRQn
Definition: M480.h:158
UART6_IRQn
Definition: M480.h:170