| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
STRIDE_T Struct Reference
Control Register

`#include <pdma_reg.h>`

## Data Fields
__IO uint32_t | STCR
__IO uint32_t | ASOCR

## Detailed Description

Definition at line 236 of file pdma_reg.h.

## Field Documentation

## ◆ ASOCR

STRIDE_T::ASOCR

[0x0504] Address Stride Offset Register of PDMA Channel 0

ASOCR

Offset: 0x504 Address Stride Offset Register of PDMA Channel n

Bits | Field | Descriptions
[15:0] | SASOL | VDMA Source Address Stride Offset Length The 16-bit register defines the source address stride transfer offset count of each row.
[31:16] | DASOL | VDMA Destination Address Stride Offset Length The 16-bit register defines the destination address stride transfer offset count of each row.

Definition at line 283 of file pdma_reg.h.

## ◆ STCR

STRIDE_T::STCR

[0x0500] Stride Transfer Count Register of PDMA Channel 0

STCR

Offset: 0x500 Stride Transfer Count Register of PDMA Channel n

Bits | Field | Descriptions
[15:0] | STC | PDMA Stride Transfer Count The 16-bit register defines the stride transfer count of each row.

Definition at line 282 of file pdma_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/pdma_reg.h