| M480 BSP V3.05.001 The Board Support Package for M480 Series

i2s.c
Go to the documentation of this file.
1 /**************************************************************************/
10 #include <stdio.h>
11 #include "NuMicro.h"
12
25 static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s);
26
32 static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
33 {
34 uint32_t u32Freq, u32ClkSrcSel;
35
36 /* get I2S selection clock source */
37 u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk;
38
39 switch (u32ClkSrcSel)
40 {
41 case CLK_CLKSEL3_I2S0SEL_HXT:
42 u32Freq = __HXT;
43 break;
44
45 case CLK_CLKSEL3_I2S0SEL_PLL:
46 u32Freq = CLK_GetPLLClockFreq();
47 break;
48
49 case CLK_CLKSEL3_I2S0SEL_HIRC:
50 u32Freq = __HIRC;
51 break;
52
53 case CLK_CLKSEL3_I2S0SEL_PCLK0:
54 u32Freq = (uint32_t)CLK_GetPCLK0Freq();
55 break;
56
57 default:
58 u32Freq = __HIRC;
59 break;
60 }
61
62 return u32Freq;
63 }
64
91 uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat)
92 {
93 uint16_t u16Divider;
94 uint32_t u32BitRate, u32SrcClk;
95
96 SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;
97 SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;
98
99 i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat;
100 i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8;
101
102 u32SrcClk = I2S_GetSourceClockFreq(i2s);
103
104 u32BitRate = u32SampleRate * (((u32WordWidth>>4U) & 0x3U) + 1U) * 16U;
105 //u16Divider = (uint16_t)((u32SrcClk/u32BitRate) >> 1U) - 1U;
106 u16Divider = (uint16_t)((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U;
107 i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U);
108
109 /* calculate real sample rate */
110 u32BitRate = u32SrcClk / (2U*((uint32_t)u16Divider+1U));
111 u32SampleRate = u32BitRate / ((((u32WordWidth>>4U) & 0x3U) + 1U) * 16U);
112
113 i2s->CTL0 |= I2S_CTL0_I2SEN_Msk;
114
115 return u32SampleRate;
116 }
117
123 void I2S_Close(I2S_T *i2s)
124 {
125 i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk;
126 }
127
135 void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
136 {
137 i2s->IEN |= u32Mask;
138 }
139
147 void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
148 {
149 i2s->IEN &= ~u32Mask;
150 }
151
158 uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
159 {
160 uint8_t u8Divider;
161 uint32_t u32SrcClk, u32Reg, u32Clock;
162
163 u32SrcClk = I2S_GetSourceClockFreq(i2s);
164 if (u32BusClock == u32SrcClk)
165 {
166 u8Divider = 0U;
167 }
168 else
169 {
170 u8Divider = (uint8_t)(u32SrcClk/u32BusClock) >> 1U;
171 }
172
173 i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;
174
175 i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk;
176
177 u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;
178
179 if (u32Reg == 0U)
180 {
181 u32Clock = u32SrcClk;
182 }
183 else
184 {
185 u32Clock = ((u32SrcClk >> 1U) / u32Reg);
186 }
187
188 return u32Clock;
189 }
190
196 void I2S_DisableMCLK(I2S_T *i2s)
197 {
198 i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk;
199 }
200
209 void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
210 {
211 i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) |
212 (u32TxThreshold << I2S_CTL1_TXTH_Pos) |
213 (u32RxThreshold << I2S_CTL1_RXTH_Pos));
214 }
215
216
236 void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
237 {
238 i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) |
239 (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) |
240 (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) |
241 (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos));
242 }
243 /* end of group I2S_EXPORTED_FUNCTIONS */
245 /* end of group I2S_Driver */
247 /* end of group Standard_Driver */
249
250 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
I2S_CLKDIV_BCLKDIV_Msk
#define I2S_CLKDIV_BCLKDIV_Msk
Definition: i2s_reg.h:1065
CLK
#define CLK
Definition: M480.h:368
CLK_CLKSEL3_I2S0SEL_PCLK0
#define CLK_CLKSEL3_I2S0SEL_PCLK0
Definition: clk.h:215
I2S_FIFO_RX_LEVEL_WORD_8
#define I2S_FIFO_RX_LEVEL_WORD_8
Definition: i2s.h:94
CLK_CLKSEL3_I2S0SEL_HIRC
#define CLK_CLKSEL3_I2S0SEL_HIRC
Definition: clk.h:214
I2S_T::CTL1
__IO uint32_t CTL1
Definition: i2s_reg.h:997
I2S_CTL0_CHWIDTH_Pos
#define I2S_CTL0_CHWIDTH_Pos
Definition: i2s_reg.h:1055
I2S_EnableInt
void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
This function enables the interrupt according to the mask parameter.
Definition: i2s.c:135
I2S_DisableInt
void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
This function disables the interrupt according to the mask parameter.
Definition: i2s.c:147
I2S_EnableMCLK
uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
Enable MCLK .
Definition: i2s.c:158
NuMicro.h
NuMicro peripheral access layer header file.
I2S_CTL1_RXTH_Msk
#define I2S_CTL1_RXTH_Msk
Definition: i2s_reg.h:1188
SYS
#define SYS
Definition: M480.h:367
CLK_CLKSEL3_I2S0SEL_HXT
#define CLK_CLKSEL3_I2S0SEL_HXT
Definition: clk.h:212
SYS_IPRST1_I2S0RST_Msk
#define SYS_IPRST1_I2S0RST_Msk
Definition: sys_reg.h:4972
I2S_CTL0_PCMSYNC_Pos
#define I2S_CTL0_PCMSYNC_Pos
Definition: i2s_reg.h:1052
I2S_CLKDIV_MCLKDIV_Msk
#define I2S_CLKDIV_MCLKDIV_Msk
Definition: i2s_reg.h:1062
CLK_GetPCLK0Freq
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:164
I2S_FIFO_TX_LEVEL_WORD_8
#define I2S_FIFO_TX_LEVEL_WORD_8
Definition: i2s.h:78
I2S_T
Definition: i2s_reg.h:26
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1188
I2S_CTL0_TDMCHNUM_Pos
#define I2S_CTL0_TDMCHNUM_Pos
Definition: i2s_reg.h:1058
I2S_CTL0_MCLKEN_Msk
#define I2S_CTL0_MCLKEN_Msk
Definition: i2s_reg.h:1032
I2S_T::CLKDIV
__IO uint32_t CLKDIV
Definition: i2s_reg.h:989
I2S_CTL0_I2SEN_Msk
#define I2S_CTL0_I2SEN_Msk
Definition: i2s_reg.h:1008
I2S_CTL1_TXTH_Msk
#define I2S_CTL1_TXTH_Msk
Definition: i2s_reg.h:1185
I2S_CTL1_TXTH_Pos
#define I2S_CTL1_TXTH_Pos
Definition: i2s_reg.h:1184
I2S_ConfigureTDM
void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width.
Definition: i2s.c:236
I2S_Open
uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat)
This function configures some parameters of I2S interface for general purpose use....
Definition: i2s.c:91
__HIRC
#define __HIRC
Definition: system_M480.h:36
CLK_CLKSEL3_I2S0SEL_Msk
#define CLK_CLKSEL3_I2S0SEL_Msk
Definition: clk_reg.h:2595
I2S_CTL1_RXTH_Pos
#define I2S_CTL1_RXTH_Pos
Definition: i2s_reg.h:1187
I2S_Close
void I2S_Close(I2S_T *i2s)
Disable I2S function and I2S clock.
Definition: i2s.c:123
I2S_DisableMCLK
void I2S_DisableMCLK(I2S_T *i2s)
Disable MCLK .
Definition: i2s.c:196
I2S_T::CTL0
__IO uint32_t CTL0
Definition: i2s_reg.h:988
CLK_CLKSEL3_I2S0SEL_PLL
#define CLK_CLKSEL3_I2S0SEL_PLL
Definition: clk.h:213
I2S_CTL0_CHWIDTH_Msk
#define I2S_CTL0_CHWIDTH_Msk
Definition: i2s_reg.h:1056
I2S_SetFIFO
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
Definition: i2s.c:209
__HXT
#define __HXT
Definition: system_M480.h:29
I2S_GetSourceClockFreq
static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
This function is used to get I2S source clock frequency.
Definition: i2s.c:32
I2S_T::IEN
__IO uint32_t IEN
Definition: i2s_reg.h:990
I2S_CTL0_PCMSYNC_Msk
#define I2S_CTL0_PCMSYNC_Msk
Definition: i2s_reg.h:1053
I2S_CTL0_TDMCHNUM_Msk
#define I2S_CTL0_TDMCHNUM_Msk
Definition: i2s_reg.h:1059