| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Structures
i2s_reg.h File Reference

I2S register definition header file. More...

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## Data Structures
struct | I2S_T

## Macros
#define | I2S_CTL0_I2SEN_Pos (0)
#define | I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos)
#define | I2S_CTL0_TXEN_Pos (1)
#define | I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos)
#define | I2S_CTL0_RXEN_Pos (2)
#define | I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos)
#define | I2S_CTL0_MUTE_Pos (3)
#define | I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos)
#define | I2S_CTL0_DATWIDTH_Pos (4)
#define | I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos)
#define | I2S_CTL0_MONO_Pos (6)
#define | I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos)
#define | I2S_CTL0_ORDER_Pos (7)
#define | I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos)
#define | I2S_CTL0_SLAVE_Pos (8)
#define | I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos)
#define | I2S_CTL0_MCLKEN_Pos (15)
#define | I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos)
#define | I2S_CTL0_TXFBCLR_Pos (18)
#define | I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos)
#define | I2S_CTL0_RXFBCLR_Pos (19)
#define | I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos)
#define | I2S_CTL0_TXPDMAEN_Pos (20)
#define | I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos)
#define | I2S_CTL0_RXPDMAEN_Pos (21)
#define | I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos)
#define | I2S_CTL0_RXLCH_Pos (23)
#define | I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos)
#define | I2S_CTL0_FORMAT_Pos (24)
#define | I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos)
#define | I2S_CTL0_PCMSYNC_Pos (27)
#define | I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos)
#define | I2S_CTL0_CHWIDTH_Pos (28)
#define | I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos)
#define | I2S_CTL0_TDMCHNUM_Pos (30)
#define | I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos)
#define | I2S_CLKDIV_MCLKDIV_Pos (0)
#define | I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos)
#define | I2S_CLKDIV_BCLKDIV_Pos (8)
#define | I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos)
#define | I2S_IEN_RXUDFIEN_Pos (0)
#define | I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos)
#define | I2S_IEN_RXOVFIEN_Pos (1)
#define | I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos)
#define | I2S_IEN_RXTHIEN_Pos (2)
#define | I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos)
#define | I2S_IEN_TXUDFIEN_Pos (8)
#define | I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos)
#define | I2S_IEN_TXOVFIEN_Pos (9)
#define | I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos)
#define | I2S_IEN_TXTHIEN_Pos (10)
#define | I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos)
#define | I2S_IEN_CH0ZCIEN_Pos (16)
#define | I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos)
#define | I2S_IEN_CH1ZCIEN_Pos (17)
#define | I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos)
#define | I2S_IEN_CH2ZCIEN_Pos (18)
#define | I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos)
#define | I2S_IEN_CH3ZCIEN_Pos (19)
#define | I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos)
#define | I2S_IEN_CH4ZCIEN_Pos (20)
#define | I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos)
#define | I2S_IEN_CH5ZCIEN_Pos (21)
#define | I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos)
#define | I2S_IEN_CH6ZCIEN_Pos (22)
#define | I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos)
#define | I2S_IEN_CH7ZCIEN_Pos (23)
#define | I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos)
#define | I2S_STATUS0_I2SINT_Pos (0)
#define | I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos)
#define | I2S_STATUS0_I2SRXINT_Pos (1)
#define | I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos)
#define | I2S_STATUS0_I2STXINT_Pos (2)
#define | I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos)
#define | I2S_STATUS0_DATACH_Pos (3)
#define | I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos)
#define | I2S_STATUS0_RXUDIF_Pos (8)
#define | I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos)
#define | I2S_STATUS0_RXOVIF_Pos (9)
#define | I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos)
#define | I2S_STATUS0_RXTHIF_Pos (10)
#define | I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos)
#define | I2S_STATUS0_RXFULL_Pos (11)
#define | I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos)
#define | I2S_STATUS0_RXEMPTY_Pos (12)
#define | I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos)
#define | I2S_STATUS0_TXUDIF_Pos (16)
#define | I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos)
#define | I2S_STATUS0_TXOVIF_Pos (17)
#define | I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos)
#define | I2S_STATUS0_TXTHIF_Pos (18)
#define | I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos)
#define | I2S_STATUS0_TXFULL_Pos (19)
#define | I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos)
#define | I2S_STATUS0_TXEMPTY_Pos (20)
#define | I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos)
#define | I2S_STATUS0_TXBUSY_Pos (21)
#define | I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos)
#define | I2S_TXFIFO_TXFIFO_Pos (0)
#define | I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos)
#define | I2S_RXFIFO_RXFIFO_Pos (0)
#define | I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos)
#define | I2S_CTL1_CH0ZCEN_Pos (0)
#define | I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos)
#define | I2S_CTL1_CH1ZCEN_Pos (1)
#define | I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos)
#define | I2S_CTL1_CH2ZCEN_Pos (2)
#define | I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos)
#define | I2S_CTL1_CH3ZCEN_Pos (3)
#define | I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos)
#define | I2S_CTL1_CH4ZCEN_Pos (4)
#define | I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos)
#define | I2S_CTL1_CH5ZCEN_Pos (5)
#define | I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos)
#define | I2S_CTL1_CH6ZCEN_Pos (6)
#define | I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos)
#define | I2S_CTL1_CH7ZCEN_Pos (7)
#define | I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos)
#define | I2S_CTL1_TXTH_Pos (8)
#define | I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos)
#define | I2S_CTL1_RXTH_Pos (16)
#define | I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos)
#define | I2S_CTL1_PBWIDTH_Pos (24)
#define | I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos)
#define | I2S_CTL1_PB16ORD_Pos (25)
#define | I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos)
#define | I2S_STATUS1_CH0ZCIF_Pos (0)
#define | I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos)
#define | I2S_STATUS1_CH1ZCIF_Pos (1)
#define | I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos)
#define | I2S_STATUS1_CH2ZCIF_Pos (2)
#define | I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos)
#define | I2S_STATUS1_CH3ZCIF_Pos (3)
#define | I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos)
#define | I2S_STATUS1_CH4ZCIF_Pos (4)
#define | I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos)
#define | I2S_STATUS1_CH5ZCIF_Pos (5)
#define | I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos)
#define | I2S_STATUS1_CH6ZCIF_Pos (6)
#define | I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos)
#define | I2S_STATUS1_CH7ZCIF_Pos (7)
#define | I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos)
#define | I2S_STATUS1_TXCNT_Pos (8)
#define | I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos)
#define | I2S_STATUS1_RXCNT_Pos (16)
#define | I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos)

## Detailed Description

I2S register definition header file.

Version
  V1.00 SPDX-License-Identifier: Apache-2.0

Copyright
  (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.

Definition in file i2s_reg.h.