| M480 BSP V3.05.001 The Board Support Package for M480 Series

qspi.h
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1 /**************************************************************************/
9 #ifndef __QSPI_H__
10 #define __QSPI_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
30 #define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk)
31 #define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk)
32 #define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk)
33 #define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk)
35 #define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk)
36 #define QSPI_MASTER (0x0U)
38 #define QSPI_SS (QSPI_SSCTL_SS_Msk)
39 #define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk)
40 #define QSPI_SS_ACTIVE_LOW (0x0U)
42 /* QSPI Interrupt Mask */
43 #define QSPI_UNIT_INT_MASK (0x001U)
44 #define QSPI_SSACT_INT_MASK (0x002U)
45 #define QSPI_SSINACT_INT_MASK (0x004U)
46 #define QSPI_SLVUR_INT_MASK (0x008U)
47 #define QSPI_SLVBE_INT_MASK (0x010U)
48 #define QSPI_TXUF_INT_MASK (0x040U)
49 #define QSPI_FIFO_TXTH_INT_MASK (0x080U)
50 #define QSPI_FIFO_RXTH_INT_MASK (0x100U)
51 #define QSPI_FIFO_RXOV_INT_MASK (0x200U)
52 #define QSPI_FIFO_RXTO_INT_MASK (0x400U)
54 /* QSPI Status Mask */
55 #define QSPI_BUSY_MASK (0x01U)
56 #define QSPI_RX_EMPTY_MASK (0x02U)
57 #define QSPI_RX_FULL_MASK (0x04U)
58 #define QSPI_TX_EMPTY_MASK (0x08U)
59 #define QSPI_TX_FULL_MASK (0x10U)
60 #define QSPI_TXRX_RESET_MASK (0x20U)
61 #define QSPI_QSPIEN_STS_MASK (0x40U)
62 #define QSPI_SSLINE_STS_MASK (0x80U)
64 /* end of group QSPI_EXPORTED_CONSTANTS */
65
66
78 #define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk)
79
87 #define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk)
88
96 #define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk)
97
105 #define QSPI_TRIGGER_TX_RX_PDMA(qspi) ((qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk))
106
114 #define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk )
115
123 #define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
124
132 #define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) )
133
141 #define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos)
142
151 #define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos)
152
161 #define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos)
162
171 #define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos)
172
180 #define QSPI_READ_RX(qspi) ((qspi)->RX)
181
190 #define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData))
191
199 #define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))
200
208 #define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk)
209
217 #define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk)
218
226 #define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk)
227
237 #define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos))
238
246 #define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk)
247
255 #define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk)
256
265 #define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos))
266
275 #define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos )
276
284 #define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk)
285
293 #define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk)
294
301 #define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
302
309 #define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk )
310
317 #define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk )
318
325 #define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
326
333 #define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk )
334
341 #define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk )
342
343
344
345
346 /* Function prototype declaration */
347 uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
348 void QSPI_Close(QSPI_T *qspi);
349 void QSPI_ClearRxFIFO(QSPI_T *qspi);
350 void QSPI_ClearTxFIFO(QSPI_T *qspi);
351 void QSPI_DisableAutoSS(QSPI_T *qspi);
352 void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
353 uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock);
354 void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
355 uint32_t QSPI_GetBusClock(QSPI_T *qspi);
356 void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask);
357 void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask);
358 uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask);
359 void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask);
360 uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask);
361
362 /* end of group QSPI_EXPORTED_FUNCTIONS */
364 /* end of group QSPI_Driver */
366 /* end of group Standard_Driver */
368
369 #ifdef __cplusplus
370 }
371 #endif
372
373 #endif
374
375 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
QSPI_EnableInt
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
Enable interrupt function.
Definition: qspi.c:463
QSPI_GetIntFlag
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
Get interrupt flag.
Definition: qspi.c:629
QSPI_SetFIFO
void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
Definition: qspi.c:376
QSPI_ClearRxFIFO
void QSPI_ClearRxFIFO(QSPI_T *qspi)
Clear RX FIFO buffer.
Definition: qspi.c:213
QSPI_DisableInt
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
Disable interrupt function.
Definition: qspi.c:546
QSPI_GetStatus
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
Get QSPI status.
Definition: qspi.c:785
QSPI_ClearIntFlag
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
Clear interrupt flag.
Definition: qspi.c:724
QSPI_T
Definition: qspi_reg.h:26
QSPI_Open
uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make QSPI module be ready to transfer.
Definition: qspi.c:43
QSPI_Close
void QSPI_Close(QSPI_T *qspi)
Disable QSPI controller.
Definition: qspi.c:192
QSPI_ClearTxFIFO
void QSPI_ClearTxFIFO(QSPI_T *qspi)
Clear TX FIFO buffer.
Definition: qspi.c:225
QSPI_EnableAutoSS
void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave selection function.
Definition: qspi.c:250
QSPI_SetBusClock
uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
Set the QSPI bus clock.
Definition: qspi.c:267
QSPI_GetBusClock
uint32_t QSPI_GetBusClock(QSPI_T *qspi)
Get the actual frequency of QSPI bus clock. Only available in Master mode.
Definition: qspi.c:389
QSPI_DisableAutoSS
void QSPI_DisableAutoSS(QSPI_T *qspi)
Disable the automatic slave selection function.
Definition: qspi.c:236