| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
REPEAT_T Struct Reference
Control Register

`#include <pdma_reg.h>`

## Data Fields
__IO uint32_t | AICTL
__IO uint32_t | RCNT

## Detailed Description

Definition at line 286 of file pdma_reg.h.

## Field Documentation

## ◆ AICTL

REPEAT_T::AICTL

[0x0600] Address Interval Control Register of PDMA Channel 0

AICTL

Offset: 0x600 Address Interval Control Register of PDMA Channel n

Bits | Field | Descriptions
[15:0] | SAICNT | PDMA Source Address Interval Count The 16-bit register defines the source address interval count of each row.
[31:16] | DAICNT | PDMA Destination Address Interval Count The 16-bit register defines the destination address interval count of each row.

Definition at line 332 of file pdma_reg.h.

## ◆ RCNT

REPEAT_T::RCNT

[0x0604] Repeat Count Register of PDMA Channel 0

RCNT

Offset: 0x604 Repeat Count Register of PDMA Channe n

Bits | Field | Descriptions
[15:0] | RCNT | PDMA Repeat Count The 16-bit register defines the repeat times of block transfer.

Definition at line 333 of file pdma_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/pdma_reg.h