| M480 BSP V3.05.001 The Board Support Package for M480 Series

Data Fields
HSUSBD_T Struct Reference
Control Register

`#include <hsusbd_reg.h>`

## Data Fields
__I uint32_t | GINTSTS
__IO uint32_t | GINTEN
__IO uint32_t | BUSINTSTS
__IO uint32_t | BUSINTEN
__IO uint32_t | OPER
__I uint32_t | FRAMECNT
__IO uint32_t | FADDR
__IO uint32_t | TEST
union {
__IO uint32_t CEPDAT
__IO uint8_t CEPDAT_BYTE
}; |
__IO uint32_t | CEPCTL
__IO uint32_t | CEPINTEN
__IO uint32_t | CEPINTSTS
__IO uint32_t | CEPTXCNT
__I uint32_t | CEPRXCNT
__I uint32_t | CEPDATCNT
__I uint32_t | SETUP1_0
__I uint32_t | SETUP3_2
__I uint32_t | SETUP5_4
__I uint32_t | SETUP7_6
__IO uint32_t | CEPBUFST
__IO uint32_t | CEPBUFEND
__IO uint32_t | DMACTL
__IO uint32_t | DMACNT
HSUSBD_EP_T | EP [12]
__IO uint32_t | DMAADDR
__IO uint32_t | PHYCTL

## Detailed Description

Definition at line 624 of file hsusbd_reg.h.

## Field Documentation

## ◆ @3

union { ... }

[0x0028] Control-Endpoint Data Buffer

## ◆ BUSINTEN

HSUSBD_T::BUSINTEN

[0x0014] USB Bus Interrupt Enable Register

BUSINTEN

Offset: 0x14 USB Bus Interrupt Enable Register

Bits | Field | Descriptions
[0] | SOFIEN | SOF Interrupt This bit enables the SOF interrupt. 0 = SOF interrupt Disabled. 1 = SOF interrupt Enabled.
[1] | RSTIEN | Reset Status This bit enables the USB-Reset interrupt. 0 = USB-Reset interrupt Disabled. 1 = USB-Reset interrupt Enabled.
[2] | RESUMEIEN | Resume This bit enables the Resume interrupt. 0 = Resume interrupt Disabled. 1 = Resume interrupt Enabled.
[3] | SUSPENDIEN | Suspend Request This bit enables the Suspend interrupt. 0 = Suspend interrupt Disabled. 1 = Suspend interrupt Enabled.
[4] | HISPDIEN | High-speed Settle This bit enables the high-speed settle interrupt. 0 = High-speed settle interrupt Disabled. 1 = High-speed settle interrupt Enabled.
[5] | DMADONEIEN | DMA Completion Interrupt This bit enables the DMA completion interrupt 0 = DMA completion interrupt Disabled. 1 = DMA completion interrupt Enabled.
[6] | PHYCLKVLDIEN | Usable Clock Interrupt This bit enables the usable clock interrupt. 0 = Usable clock interrupt Disabled. 1 = Usable clock interrupt Enabled.
[8] | VBUSDETIEN | VBUS Detection Interrupt Enable Bit This bit enables the VBUS floating detection interrupt. 0 = VBUS floating detection interrupt Disabled. 1 = VBUS floating detection interrupt Enabled.

Definition at line 1954 of file hsusbd_reg.h.

## ◆ BUSINTSTS

HSUSBD_T::BUSINTSTS

[0x0010] USB Bus Interrupt Status Register

BUSINTSTS

Offset: 0x10 USB Bus Interrupt Status Register

Bits | Field | Descriptions
[0] | SOFIF | SOF Receive Control This bit indicates when a start-of-frame packet has been received. 0 = No start-of-frame packet has been received. 1 = Start-of-frame packet has been received. Note: Write 1 to clear this bit to 0.
[1] | RSTIF | Reset Status When set, this bit indicates that either the USB root port reset is end. 0 = No USB root port reset is end. 1 = USB root port reset is end. Note: Write 1 to clear this bit to 0.
[2] | RESUMEIF | Resume When set, this bit indicates that a device resume has occurred. 0 = No device resume has occurred. 1 = Device resume has occurred. Note: Write 1 to clear this bit to 0.
[3] | SUSPENDIF | Suspend Request This bit is set as default and it has to be cleared by writing '1' before the USB reset This bit is also set when a USB Suspend request is detected from the host. 0 = No USB Suspend request is detected from the host. 1= USB Suspend request is detected from the host. Note: Write 1 to clear this bit to 0.
[4] | HISPDIF | High-speed Settle 0 = No valid high-speed reset protocol is detected. 1 = Valid high-speed reset protocol is over and the device has settled in high-speed. Note: Write 1 to clear this bit to 0.
[5] | DMADONEIF | DMA Completion Interrupt 0 = No DMA transfer over. 1 = DMA transfer is over. Note: Write 1 to clear this bit to 0.
[6] | PHYCLKVLDIF | Usable Clock Interrupt 0 = Usable clock is not available. 1 = Usable clock is available from the transceiver. Note: Write 1 to clear this bit to 0.
[8] | VBUSDETIF | VBUS Detection Interrupt Status 0 = No VBUS is plug-in. 1 = VBUS is plug-in. Note: Write 1 to clear this bit to 0.

Definition at line 1953 of file hsusbd_reg.h.

## ◆ CEPBUFEND

HSUSBD_T::CEPBUFEND

[0x0058] Control Endpoint RAM End Address Register

CEPBUFEND

Offset: 0x58 Control Endpoint RAM End Address Register

Bits | Field | Descriptions
[11:0] | EADDR | Control-endpoint End Address This is the end-address of the RAM space allocated for the control-endpoint.

Definition at line 1978 of file hsusbd_reg.h.

## ◆ CEPBUFST

HSUSBD_T::CEPBUFST

[0x0054] Control Endpoint RAM Start Address Register

CEPBUFST

Offset: 0x54 Control Endpoint RAM Start Address Register

Bits | Field | Descriptions
[11:0] | SADDR | Control-endpoint Start Address This is the start-address of the RAM space allocated for the control-endpoint.

Definition at line 1977 of file hsusbd_reg.h.

## ◆ CEPCTL

HSUSBD_T::CEPCTL

[0x002c] Control-Endpoint Control Register

CEPCTL

Offset: 0x2C Control-Endpoint Control Register

Bits | Field | Descriptions
[0] | NAKCLR | No Acknowledge Control This bit plays a crucial role in any control transfer. 0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. 1 = This bit is set to one by the USB device controller, whenever a setup token is received The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
[1] | STALLEN | Stall Enable Bit When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter This is typically used for response to invalid/unsupported requests When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL It is automatically cleared on receipt of a next setup-token So, the local CPU need not write again to clear this bit. 0 = No sends a stall handshake in response to any in or out token thereafter. 1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
[2] | ZEROLEN | Zero Packet Length This bit is valid for Auto Validation mode only. 0 = No zero length packet to the host during Data stage to an IN token. 1 = USB device controller can send a zero length packet to the host during Data stage to an IN token This bit gets cleared once the zero length data packet is sent So, the local CPU need not write again to clear this bit.
[3] | FLUSH | CEP-flush Bit 0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. 1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared This bit is self-cleaning.

Definition at line 1967 of file hsusbd_reg.h.

## ◆ CEPDAT

HSUSBD_T::CEPDAT

CEPDAT

Offset: 0x28 Control-Endpoint Data Buffer

Bits | Field | Descriptions
[31:0] | DAT | Control-endpoint Data Buffer Control endpoint data buffer for the buffer transaction (read or write). Note: Only word access is supported.

Definition at line 1962 of file hsusbd_reg.h.

## ◆ CEPDAT_BYTE

HSUSBD_T::CEPDAT_BYTE

CEPDAT_BYTE

Offset: 0x28 Control-Endpoint Data Buffer

Bits | Field | Descriptions
[7:0] | DAT | Control-endpoint Data Buffer Control endpoint data buffer for the buffer transaction (read or write). Note: Only byte access is supported.

Definition at line 1963 of file hsusbd_reg.h.

## ◆ CEPDATCNT

HSUSBD_T::CEPDATCNT

[0x0040] Control-Endpoint data count

CEPDATCNT

Offset: 0x40 Control-Endpoint data count

Bits | Field | Descriptions
[15:0] | DATCNT | Control-endpoint Data Count The USB device controller maintains the count of the data of control-endpoint.

Definition at line 1972 of file hsusbd_reg.h.

## ◆ CEPINTEN

HSUSBD_T::CEPINTEN

[0x0030] Control-Endpoint Interrupt Enable

CEPINTEN

Offset: 0x30 Control-Endpoint Interrupt Enable

Bits | Field | Descriptions
[0] | SETUPTKIEN | Setup Token Interrupt Enable Bit 0 = The SETUP token interrupt in Control Endpoint Disabled. 1 = The SETUP token interrupt in Control Endpoint Enabled.
[1] | SETUPPKIEN | Setup Packet Interrupt 0 = The SETUP packet interrupt in Control Endpoint Disabled. 1 = The SETUP packet interrupt in Control Endpoint Enabled.
[2] | OUTTKIEN | Out Token Interrupt 0 = The OUT token interrupt in Control Endpoint Disabled. 1 = The OUT token interrupt in Control Endpoint Enabled.
[3] | INTKIEN | In Token Interrupt 0 = The IN token interrupt in Control Endpoint Disabled. 1 = The IN token interrupt in Control Endpoint Enabled.
[4] | PINGIEN | Ping Token Interrupt 0 = The ping token interrupt in Control Endpoint Disabled. 1 = The ping token interrupt Control Endpoint Enabled.
[5] | TXPKIEN | Data Packet Transmitted Interrupt 0 = The data packet transmitted interrupt in Control Endpoint Disabled. 1 = The data packet transmitted interrupt in Control Endpoint Enabled.
[6] | RXPKIEN | Data Packet Received Interrupt 0 = The data received interrupt in Control Endpoint Disabled. 1 = The data received interrupt in Control Endpoint Enabled.
[7] | NAKIEN | NAK Sent Interrupt 0 = The NAK sent interrupt in Control Endpoint Disabled. 1 = The NAK sent interrupt in Control Endpoint Enabled.
[8] | STALLIEN | STALL Sent Interrupt 0 = The STALL sent interrupt in Control Endpoint Disabled. 1 = The STALL sent interrupt in Control Endpoint Enabled.
[9] | ERRIEN | USB Error Interrupt 0 = The USB Error interrupt in Control Endpoint Disabled. 1 = The USB Error interrupt in Control Endpoint Enabled.
[10] | STSDONEIEN | Status Completion Interrupt 0 = The Status Completion interrupt in Control Endpoint Disabled. 1 = The Status Completion interrupt in Control Endpoint Enabled.
[11] | BUFFULLIEN | Buffer Full Interrupt 0 = The buffer full interrupt in Control Endpoint Disabled. 1 = The buffer full interrupt in Control Endpoint Enabled.
[12] | BUFEMPTYIEN | Buffer Empty Interrupt 0 = The buffer empty interrupt in Control Endpoint Disabled. 1= The buffer empty interrupt in Control Endpoint Enabled.

Definition at line 1968 of file hsusbd_reg.h.

## ◆ CEPINTSTS

HSUSBD_T::CEPINTSTS

[0x0034] Control-Endpoint Interrupt Status

CEPINTSTS

Offset: 0x34 Control-Endpoint Interrupt Status

Bits | Field | Descriptions
[0] | SETUPTKIF | Setup Token Interrupt 0 = Not a Setup token is received. 1 = A Setup token is received. Writing 1 clears this status bit Note: Write 1 to clear this bit to 0.
[1] | SETUPPKIF | Setup Packet Interrupt This bit must be cleared (by writing 1) before the next setup packet can be received If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. 0 = Not a Setup packet has been received from the host. 1 = A Setup packet has been received from the host. Note: Write 1 to clear this bit to 0.
[2] | OUTTKIF | Out Token Interrupt 0 = The control-endpoint does not received an OUT token from the host. 1 = The control-endpoint receives an OUT token from the host. Note: Write 1 to clear this bit to 0.
[3] | INTKIF | in Token Interrupt 0 = The control-endpoint does not received an IN token from the host. 1 = The control-endpoint receives an IN token from the host. Note: Write 1 to clear this bit to 0.
[4] | PINGIF | Ping Token Interrupt 0 = The control-endpoint does not received a ping token from the host. 1 = The control-endpoint receives a ping token from the host. Note: Write 1 to clear this bit to 0.
[5] | TXPKIF | Data Packet Transmitted Interrupt 0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. 1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. Note: Write 1 to clear this bit to 0.
[6] | RXPKIF | Data Packet Received Interrupt 0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. 1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. Note: Write 1 to clear this bit to 0.
[7] | NAKIF | NAK Sent Interrupt 0 = Not a NAK-token is sent in response to an IN/OUT token. 1 = A NAK-token is sent in response to an IN/OUT token. Note: Write 1 to clear this bit to 0.
[8] | STALLIF | STALL Sent Interrupt 0 = Not a stall-token is sent in response to an IN/OUT token. 1 = A stall-token is sent in response to an IN/OUT token. Note: Write 1 to clear this bit to 0.
[9] | ERRIF | USB Error Interrupt 0 = No error had occurred during the transaction. 1 = An error had occurred during the transaction. Note: Write 1 to clear this bit to 0.
[10] | STSDONEIF | Status Completion Interrupt 0 = Not a USB transaction has completed successfully. 1 = The status stage of a USB transaction has completed successfully. Note: Write 1 to clear this bit to 0.
[11] | BUFFULLIF | Buffer Full Interrupt 0 = The control-endpoint buffer is not full. 1 = The control-endpoint buffer is full. Note: Write 1 to clear this bit to 0.
[12] | BUFEMPTYIF | Buffer Empty Interrupt 0 = The control-endpoint buffer is not empty. 1 = The control-endpoint buffer is empty. Note: Write 1 to clear this bit to 0.

Definition at line 1969 of file hsusbd_reg.h.

## ◆ CEPRXCNT

HSUSBD_T::CEPRXCNT

[0x003c] Control-Endpoint Out-transfer Data Count

CEPRXCNT

Offset: 0x3C Control-Endpoint Out-transfer Data Count

Bits | Field | Descriptions
[7:0] | RXCNT | Out-transfer Data Count The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.

Definition at line 1971 of file hsusbd_reg.h.

## ◆ CEPTXCNT

HSUSBD_T::CEPTXCNT

[0x0038] Control-Endpoint In-transfer Data Count

CEPTXCNT

Offset: 0x38 Control-Endpoint In-transfer Data Count

Bits | Field | Descriptions
[7:0] | TXCNT | In-transfer Data Count There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register When zero is written into this field, a zero length packet is sent to the host When the count written in the register is more than the MPS, the data sent will be of only MPS.

Definition at line 1970 of file hsusbd_reg.h.

## ◆ DMAADDR

HSUSBD_T::DMAADDR

[0x0700] AHB DMA Address Register

DMAADDR

Offset: 0x700 AHB DMA Address Register

Bits | Field | Descriptions
[31:0] | DMAADDR | DMAADDR The register specifies the address from which the DMA has to read / write The address must WORD (32-bit) aligned.

Definition at line 1987 of file hsusbd_reg.h.

## ◆ DMACNT

HSUSBD_T::DMACNT

[0x0060] DMA Count Register

DMACNT

Offset: 0x60 DMA Count Register

Bits | Field | Descriptions
[19:0] | DMACNT | DMA Transfer Count The transfer count of the DMA operation to be performed is written to this register.

Definition at line 1980 of file hsusbd_reg.h.

## ◆ DMACTL

HSUSBD_T::DMACTL

[0x005c] DMA Control Status Register

DMACTL

Offset: 0x5C DMA Control Status Register

Bits | Field | Descriptions
[3:0] | EPNUM | DMA Endpoint Address Bits Used to define the Endpoint Address
[4] | DMARD | DMA Operation 0 : The operation is a DMA write (read from USB buffer) DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation. 1 : The operation is a DMA read (write to USB buffer).
[5] | DMAEN | DMA Enable Bit 0 : DMA function Disabled. 1 : DMA function Enabled.
[6] | SGEN | Scatter Gather Function Enable Bit 0 : Scatter gather function Disabled. 1 : Scatter gather function Enabled.
[7] | DMARST | Reset DMA State Machine 0 : No reset the DMA state machine. 1 : Reset the DMA state machine.
[8] | SVINEP | Serve IN Endpoint This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint. 0: DMA serves OUT endpoint 1: DMA serves IN endpoint

Definition at line 1979 of file hsusbd_reg.h.

## ◆ EP

HSUSBD_EP_T HSUSBD_T::EP[12]

Definition at line 1982 of file hsusbd_reg.h.

## ◆ FADDR

HSUSBD_T::FADDR

[0x0020] USB Function Address Register

FADDR

Offset: 0x20 USB Function Address Register

Bits | Field | Descriptions
[6:0] | FADDR | USB Function Address This field contains the current USB address of the device This field is cleared when a root port reset is detected

Definition at line 1957 of file hsusbd_reg.h.

## ◆ FRAMECNT

HSUSBD_T::FRAMECNT

[0x001c] USB Frame Count Register

FRAMECNT

Offset: 0x1C USB Frame Count Register

Bits | Field | Descriptions
[2:0] | MFRAMECNT | Micro-frame Counter This field contains the micro-frame number for the frame number in the frame counter field.
[13:3] | FRAMECNT | Frame Counter This field contains the frame count from the most recent start-of-frame packet.

Definition at line 1956 of file hsusbd_reg.h.

## ◆ GINTEN

HSUSBD_T::GINTEN

[0x0008] Global Interrupt Enable Register

GINTEN

Offset: 0x08 Global Interrupt Enable Register

Bits | Field | Descriptions
[0] | USBIEN | USB Interrupt Enable Bit When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[1] | CEPIEN | Control Endpoint Interrupt Enable Bit When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[2] | EPAIEN | Interrupt Enable Control for Endpoint a When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[3] | EPBIEN | Interrupt Enable Control for Endpoint B When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[4] | EPCIEN | Interrupt Enable Control for Endpoint C When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[5] | EPDIEN | Interrupt Enable Control for Endpoint D When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[6] | EPEIEN | Interrupt Enable Control for Endpoint E When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[7] | EPFIEN | Interrupt Enable Control for Endpoint F When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[8] | EPGIEN | Interrupt Enable Control for Endpoint G When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[9] | EPHIEN | Interrupt Enable Control for Endpoint H When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[10] | EPIIEN | Interrupt Enable Control for Endpoint I When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[11] | EPJIEN | Interrupt Enable Control for Endpoint J When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[12] | EPKIEN | Interrupt Enable Control for Endpoint K When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.
[13] | EPLIEN | Interrupt Enable Control for Endpoint L When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L 0 = The related interrupt Disabled. 1 = The related interrupt Enabled.

Definition at line 1949 of file hsusbd_reg.h.

## ◆ GINTSTS

HSUSBD_T::GINTSTS

[0x0000] Global Interrupt Status Register

GINTSTS

Offset: 0x00 Global Interrupt Status Register

Bits | Field | Descriptions
[0] | USBIF | USB Interrupt This bit conveys the interrupt status for USB specific events endpoint When set, USB interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[1] | CEPIF | Control Endpoint Interrupt This bit conveys the interrupt status for control endpoint When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[2] | EPAIF | Endpoint a Interrupt When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[3] | EPBIF | Endpoint B Interrupt When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[4] | EPCIF | Endpoint C Interrupt When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[5] | EPDIF | Endpoint D Interrupt When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[6] | EPEIF | Endpoint E Interrupt When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[7] | EPFIF | Endpoint F Interrupt When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[8] | EPGIF | Endpoint G Interrupt When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[9] | EPHIF | Endpoint H Interrupt When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[10] | EPIIF | Endpoint I Interrupt When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[11] | EPJIF | Endpoint J Interrupt When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[12] | EPKIF | Endpoint K Interrupt When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.
[13] | EPLIF | Endpoint L Interrupt When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. 0 = No interrupt event occurred. 1 = The related interrupt event is occurred.

Definition at line 1945 of file hsusbd_reg.h.

## ◆ OPER

HSUSBD_T::OPER

[0x0018] USB Operational Register

OPER

Offset: 0x18 USB Operational Register

Bits | Field | Descriptions
[0] | RESUMEEN | Generate Resume 0 = No Resume sequence to be initiated to the host. 1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled This bit is self-clearing.
[1] | HISPDEN | USB High-speed 0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. 1 = The USB device controller to initiate a chirp-sequence during reset protocol.
[2] | CURSPD | USB Current Speed 0 = The device has settled in Full Speed. 1 = The USB device controller has settled in High-speed.

Definition at line 1955 of file hsusbd_reg.h.

## ◆ PHYCTL

HSUSBD_T::PHYCTL

[0x0704] USB PHY Control Register

PHYCTL

Offset: 0x704 USB PHY Control Register

Bits | Field | Descriptions
[8] | DPPUEN | DP Pull-up 0 = Pull-up resistor on D+ Disabled. 1 = Pull-up resistor on D+ Enabled.
[9] | PHYEN | PHY Suspend Enable Bit 0 = The USB PHY is suspend. 1 = The USB PHY is not suspend.
[24] | WKEN | Wake-up Enable Bit 0 = The wake-up function Disabled. 1 = The wake-up function Enabled.
[31] | VBUSDET | VBUS Status 0 = The VBUS is not detected yet. 1 = The VBUS is detected.

Definition at line 1988 of file hsusbd_reg.h.

## ◆ SETUP1_0

HSUSBD_T::SETUP1_0

[0x0044] Setup1 & Setup0 bytes

SETUP1_0

Offset: 0x44 Setup1 & Setup0 bytes

Bits | Field | Descriptions
[7:0] | SETUP0 | Setup Byte 0[7:0] This register provides byte 0 of the last setup packet received For a Standard Device Request, the following bmRequestType information is returned. Bit 7(Direction): 0: Host to device 1: Device to host Bit 6-5 (Type): 00: Standard 01: Class 10: Vendor 11: Reserved Bit 4-0 (Recipient) 00000: Device 00001: Interface 00010: Endpoint 00011: Other Others: Reserved
[15:8] | SETUP1 | Setup Byte 1[15:8] This register provides byte 1 of the last setup packet received For a Standard Device Request, the following bRequest Code information is returned. 00000000 = Get Status. 00000001 = Clear Feature. 00000010 = Reserved. 00000011 = Set Feature. 00000100 = Reserved. 00000101 = Set Address. 00000110 = Get Descriptor. 00000111 = Set Descriptor. 00001000 = Get Configuration. 00001001 = Set Configuration. 00001010 = Get Interface. 00001011 = Set Interface. 00001100 = Sync Frame.

Definition at line 1973 of file hsusbd_reg.h.

## ◆ SETUP3_2

HSUSBD_T::SETUP3_2

[0x0048] Setup3 & Setup2 Bytes

SETUP3_2

Offset: 0x48 Setup3 & Setup2 Bytes

Bits | Field | Descriptions
[7:0] | SETUP2 | Setup Byte 2 [7:0] This register provides byte 2 of the last setup packet received For a Standard Device Request, the least significant byte of the wValue field is returned
[15:8] | SETUP3 | Setup Byte 3 [15:8] This register provides byte 3 of the last setup packet received For a Standard Device Request, the most significant byte of the wValue field is returned.

Definition at line 1974 of file hsusbd_reg.h.

## ◆ SETUP5_4

HSUSBD_T::SETUP5_4

[0x004c] Setup5 & Setup4 Bytes

SETUP5_4

Offset: 0x4C Setup5 & Setup4 Bytes

Bits | Field | Descriptions
[7:0] | SETUP4 | Setup Byte 4[7:0] This register provides byte 4 of the last setup packet received For a Standard Device Request, the least significant byte of the wIndex is returned.
[15:8] | SETUP5 | Setup Byte 5[15:8] This register provides byte 5 of the last setup packet received For a Standard Device Request, the most significant byte of the wIndex field is returned.

Definition at line 1975 of file hsusbd_reg.h.

## ◆ SETUP7_6

HSUSBD_T::SETUP7_6

[0x0050] Setup7 & Setup6 Bytes

SETUP7_6

Offset: 0x50 Setup7 & Setup6 Bytes

Bits | Field | Descriptions
[7:0] | SETUP6 | Setup Byte 6[7:0] This register provides byte 6 of the last setup packet received For a Standard Device Request, the least significant byte of the wLength field is returned.
[15:8] | SETUP7 | Setup Byte 7[15:8] This register provides byte 7 of the last setup packet received For a Standard Device Request, the most significant byte of the wLength field is returned.

Definition at line 1976 of file hsusbd_reg.h.

## ◆ TEST

HSUSBD_T::TEST

[0x0024] USB Test Mode Register

TEST

Offset: 0x24 USB Test Mode Register

Bits | Field | Descriptions
[2:0] | TESTMODE | Test Mode Selection 000 = Normal Operation. 001 = Test_J. 010 = Test_K. 011 = Test_SE0_NAK. 100 = Test_Packet. 101 = Test_Force_Enable. 110 = Reserved. 111 = Reserved. Note: This field is cleared when root port reset is detected.

Definition at line 1958 of file hsusbd_reg.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/M480/Include/hsusbd_reg.h